From nobody Thu Oct 2 09:16:52 2025 Received: from pegase2.c-s.fr (pegase2.c-s.fr [93.17.235.10]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2C26E253950; Thu, 18 Sep 2025 16:51:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=93.17.235.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758214269; cv=none; b=F1HOoVVcUieUrxU+fbCStT2rH2aIG0WxR30FN0eC/M/0n+wxxq+kOcC1sGC/dc2M7oj9Cz8tn/I2cPgQ5uukak8Wl4P8RKIeWLiWe+bPxZBeaXElJ5ojcKNqPoOMtxPxds7t/iXUzwmnWRb5clfmbLb3NbFR0kTWSOU/TEkRkQw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758214269; c=relaxed/simple; bh=G7scsgL+yrYA4D+2n/22/LhhZgPYYRLFCIoU4FAox1M=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=u4xwa1em9DqzA6W3LQLDkgTGnUQdl27L+2N4mxFPnQMwH12oyuI4NIhdoziq+TnD3dRMNLpZQRcZerkibT+sqrKhm8QbxHzcdhW6cpnO65ACgT2lxiTTPe/yWjGWIqZ5D3ZRUWe9Ip8c5LQbsCCz2fJN1Gx9HZ2x/mBHih7lxfg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=csgroup.eu; spf=pass smtp.mailfrom=csgroup.eu; arc=none smtp.client-ip=93.17.235.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=csgroup.eu Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=csgroup.eu Received: from localhost (mailhub4.si.c-s.fr [172.26.127.67]) by localhost (Postfix) with ESMTP id 4cSLY20nLBz9sfk; Thu, 18 Sep 2025 18:23:34 +0200 (CEST) X-Virus-Scanned: amavisd-new at c-s.fr Received: from pegase2.c-s.fr ([172.26.127.65]) by localhost (pegase2.c-s.fr [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id DC6pAqwuh5tc; Thu, 18 Sep 2025 18:23:34 +0200 (CEST) Received: from messagerie.si.c-s.fr (messagerie.si.c-s.fr [192.168.25.192]) by pegase2.c-s.fr (Postfix) with ESMTP id 4cSLY160R7z9sfj; Thu, 18 Sep 2025 18:23:33 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by messagerie.si.c-s.fr (Postfix) with ESMTP id BBD638B776; Thu, 18 Sep 2025 18:23:33 +0200 (CEST) X-Virus-Scanned: amavisd-new at c-s.fr Received: from messagerie.si.c-s.fr ([127.0.0.1]) by localhost (messagerie.si.c-s.fr [127.0.0.1]) (amavisd-new, port 10023) with ESMTP id DYqBu_E8srgz; Thu, 18 Sep 2025 18:23:33 +0200 (CEST) Received: from PO20335.idsi0.si.c-s.fr (unknown [192.168.235.99]) by messagerie.si.c-s.fr (Postfix) with ESMTP id D63CA8B767; Thu, 18 Sep 2025 18:23:32 +0200 (CEST) From: Christophe Leroy To: Qiang Zhao , Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Christophe Leroy , linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 1/7] soc: fsl: qe: Add an interrupt controller for QUICC Engine Ports Date: Thu, 18 Sep 2025 18:23:21 +0200 Message-ID: <74d4a911a6d17eae7b94a8f30a4d24498a217e71.1758212309.git.christophe.leroy@csgroup.eu> X-Mailer: git-send-email 2.49.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758212605; l=5183; i=christophe.leroy@csgroup.eu; s=20211009; h=from:subject:message-id; bh=G7scsgL+yrYA4D+2n/22/LhhZgPYYRLFCIoU4FAox1M=; b=65/ofNRoICaFrDJaLuae+CUguGjCMPj2TeU/+DM/ipRDBymnjuE1lMxVfJbnOEbS/w0Z3PfLY NrutJyTMFh2AgW1ounjp+1wosQbl9Iczz5pisy0QH7GbqYcL+KNjGY2 X-Developer-Key: i=christophe.leroy@csgroup.eu; a=ed25519; pk=HIzTzUj91asvincQGOFx6+ZF5AoUuP9GdOtQChs7Mm0= Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The QUICC Engine provides interrupts for a few I/O ports. This is handled via a separate interrupt ID and managed via a triplet of dedicated registers hosted by the SoC. Implement an interrupt driver for it for that those IRQs can then be linked to the related GPIOs. The number of ports for which interrupts are supported depends on the microcontroller: - mpc8323 has 10 interrupts - mpc8360 has 28 interrupts - mpc8568 has 18 interrupts So add this information as data of the compatible. Signed-off-by: Christophe Leroy --- drivers/soc/fsl/qe/Makefile | 2 +- drivers/soc/fsl/qe/qe_ports_ic.c | 156 +++++++++++++++++++++++++++++++ 2 files changed, 157 insertions(+), 1 deletion(-) create mode 100644 drivers/soc/fsl/qe/qe_ports_ic.c diff --git a/drivers/soc/fsl/qe/Makefile b/drivers/soc/fsl/qe/Makefile index ec8506e13113..901a9c40d5eb 100644 --- a/drivers/soc/fsl/qe/Makefile +++ b/drivers/soc/fsl/qe/Makefile @@ -11,4 +11,4 @@ obj-$(CONFIG_UCC_SLOW) +=3D ucc_slow.o obj-$(CONFIG_UCC_FAST) +=3D ucc_fast.o obj-$(CONFIG_QE_TDM) +=3D qe_tdm.o obj-$(CONFIG_QE_USB) +=3D usb.o -obj-$(CONFIG_QE_GPIO) +=3D gpio.o +obj-$(CONFIG_QE_GPIO) +=3D gpio.o qe_ports_ic.o diff --git a/drivers/soc/fsl/qe/qe_ports_ic.c b/drivers/soc/fsl/qe/qe_ports= _ic.c new file mode 100644 index 000000000000..9715643d36a6 --- /dev/null +++ b/drivers/soc/fsl/qe/qe_ports_ic.c @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * QUICC ENGINE I/O Ports Interrupt Controller + * + * Copyright (c) 2025 Christophe Leroy CS GROUP France (christophe.leroy@c= sgroup.eu) + */ + +#include +#include +#include + +/* QE IC registers offset */ +#define CEPIER 0x0c +#define CEPIMR 0x10 +#define CEPICR 0x14 + +struct qepic_data { + void __iomem *reg; + struct irq_domain *host; +}; + +static void qepic_mask(struct irq_data *d) +{ + struct qepic_data *data =3D irq_data_get_irq_chip_data(d); + + clrbits32(data->reg + CEPIMR, 1 << (31 - irqd_to_hwirq(d))); +} + +static void qepic_unmask(struct irq_data *d) +{ + struct qepic_data *data =3D irq_data_get_irq_chip_data(d); + + setbits32(data->reg + CEPIMR, 1 << (31 - irqd_to_hwirq(d))); +} + +static void qepic_end(struct irq_data *d) +{ + struct qepic_data *data =3D irq_data_get_irq_chip_data(d); + + out_be32(data->reg + CEPIER, 1 << (31 - irqd_to_hwirq(d))); +} + +static int qepic_set_type(struct irq_data *d, unsigned int flow_type) +{ + struct qepic_data *data =3D irq_data_get_irq_chip_data(d); + unsigned int vec =3D (unsigned int)irqd_to_hwirq(d); + + switch (flow_type & IRQ_TYPE_SENSE_MASK) { + case IRQ_TYPE_EDGE_FALLING: + setbits32(data->reg + CEPICR, 1 << (31 - vec)); + return 0; + case IRQ_TYPE_EDGE_BOTH: + case IRQ_TYPE_NONE: + clrbits32(data->reg + CEPICR, 1 << (31 - vec)); + return 0; + } + return -EINVAL; +} + +static struct irq_chip qepic =3D { + .name =3D "QEPIC", + .irq_mask =3D qepic_mask, + .irq_unmask =3D qepic_unmask, + .irq_eoi =3D qepic_end, + .irq_set_type =3D qepic_set_type, +}; + +static int qepic_get_irq(struct irq_desc *desc) +{ + struct qepic_data *data =3D irq_desc_get_handler_data(desc); + u32 event =3D in_be32(data->reg + CEPIER); + + if (!event) + return -1; + + return irq_find_mapping(data->host, 32 - ffs(event)); +} + +static void qepic_cascade(struct irq_desc *desc) +{ + generic_handle_irq(qepic_get_irq(desc)); +} + +static int qepic_host_map(struct irq_domain *h, unsigned int virq, irq_hw_= number_t hw) +{ + irq_set_chip_data(virq, h->host_data); + irq_set_chip_and_handler(virq, &qepic, handle_fasteoi_irq); + return 0; +} + +static const struct irq_domain_ops qepic_host_ops =3D { + .map =3D qepic_host_map, +}; + +static int qepic_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct qepic_data *data; + unsigned long nb; + int irq; + + nb =3D (unsigned long)of_device_get_match_data(dev); + if (nb < 1 || nb > 32) + return -EINVAL; + + data =3D devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->reg =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(data->reg)) + return PTR_ERR(data->reg); + + irq =3D platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + data->host =3D irq_domain_add_linear(dev->of_node, nb, &qepic_host_ops, d= ata); + if (!data->host) + return -ENODEV; + + irq_set_handler_data(irq, data); + irq_set_chained_handler(irq, qepic_cascade); + + return 0; +} + +static const struct of_device_id qepic_match[] =3D { + { + .compatible =3D "fsl,mpc8323-qe-ports-ic", + .data =3D (void *)10, + }, + { + .compatible =3D "fsl,mpc8360-qe-ports-ic", + .data =3D (void *)28, + }, + { + .compatible =3D "fsl,mpc8568-qe-ports-ic", + .data =3D (void *)18, + }, + {}, +}; + +static struct platform_driver qepic_driver =3D { + .driver =3D { + .name =3D "qe_ports_ic", + .of_match_table =3D qepic_match, + }, + .probe =3D qepic_probe, +}; + +static int __init qepic_init(void) +{ + return platform_driver_register(&qepic_driver); +} +arch_initcall(qepic_init); --=20 2.49.0 From nobody Thu Oct 2 09:16:52 2025 Received: from pegase2.c-s.fr (pegase2.c-s.fr [93.17.235.10]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C53682505AA; Thu, 18 Sep 2025 16:50:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=93.17.235.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758214259; cv=none; b=TF5WtBbkubR9OUAk2pLqtVUdq+MspheBGe2CmWofYNjWXnmRU6sf16Sn/jDKfLKDeDGb5yrzDkDmPd90dQFxDy1/kZHhB4YZXzLrSTghce5RSCJacQ67o/qsrGgKu7zSUEusoHgJNRltiYfB8huZ4hEnDQ98dKvAzMDDMxPLlK8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758214259; c=relaxed/simple; bh=JPKAv81IjiGNw3TMzw+WVRovmT/FOWbfetWem9cmBzI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=E7wcOjkqtaxPrrP0sGkt0Y/KZKeIO2+0HBvuk3QjuH8RCq9+/nQtzufdGzbcwIfBzYNcKPB47ovV2xe62d1X2AdkzdBMOLov9KMGFt1fT2CnlvNwm8iVUtn46CE0lKy8vISL+C/9TZKWkO6xoyi35roYw2/XCYWjFM9njpuBHOc= ARC-Authentication-Results: i=1; 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Thu, 18 Sep 2025 18:23:34 +0200 (CEST) X-Virus-Scanned: amavisd-new at c-s.fr Received: from messagerie.si.c-s.fr ([127.0.0.1]) by localhost (messagerie.si.c-s.fr [127.0.0.1]) (amavisd-new, port 10023) with ESMTP id pGYRopBfxKG1; Thu, 18 Sep 2025 18:23:34 +0200 (CEST) Received: from PO20335.idsi0.si.c-s.fr (unknown [192.168.235.99]) by messagerie.si.c-s.fr (Postfix) with ESMTP id BBF8E8B778; Thu, 18 Sep 2025 18:23:33 +0200 (CEST) From: Christophe Leroy To: Qiang Zhao , Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Christophe Leroy , linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, Bartosz Golaszewski Subject: [PATCH v6 2/7] soc: fsl: qe: Change GPIO driver to a proper platform driver Date: Thu, 18 Sep 2025 18:23:22 +0200 Message-ID: X-Mailer: git-send-email 2.49.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758212605; l=4799; i=christophe.leroy@csgroup.eu; s=20211009; h=from:subject:message-id; bh=JPKAv81IjiGNw3TMzw+WVRovmT/FOWbfetWem9cmBzI=; b=9qbHdo/P81nMONTzCCSudErSniguq5Eb0y1BmQthiMKsaulHldEoExoiWx59usw/R3X7sDvgV mWeQfQrbtI0BRJXNaXw2Tw2/sa8eumjtQasowcu8pCmIwSkJuFC/ou1 X-Developer-Key: i=christophe.leroy@csgroup.eu; a=ed25519; pk=HIzTzUj91asvincQGOFx6+ZF5AoUuP9GdOtQChs7Mm0= Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In order to be able to add interrupts to the GPIOs, first change the QE GPIO driver to the proper platform driver in order to allow initialisation to be done in the right order, otherwise the GPIOs get added before the interrupts are registered. Remove linux/of.h and linux/property.h which are unused. And to improve readability and reduce risk of errors, add a macro to transform a pin number into the mask that matches the associated bit in registers. Reviewed-by: Bartosz Golaszewski Signed-off-by: Christophe Leroy --- drivers/soc/fsl/qe/gpio.c | 98 +++++++++++++++++++++------------------ 1 file changed, 53 insertions(+), 45 deletions(-) diff --git a/drivers/soc/fsl/qe/gpio.c b/drivers/soc/fsl/qe/gpio.c index 8df1e8fa86a5..04b44fc2bb58 100644 --- a/drivers/soc/fsl/qe/gpio.c +++ b/drivers/soc/fsl/qe/gpio.c @@ -12,16 +12,17 @@ #include #include #include -#include #include #include #include #include #include -#include +#include =20 #include =20 +#define PIN_MASK(gpio) (1UL << (QE_PIO_PINS - 1 - (gpio))) + struct qe_gpio_chip { struct of_mm_gpio_chip mm_gc; spinlock_t lock; @@ -52,7 +53,7 @@ static int qe_gpio_get(struct gpio_chip *gc, unsigned int= gpio) { struct of_mm_gpio_chip *mm_gc =3D to_of_mm_gpio_chip(gc); struct qe_pio_regs __iomem *regs =3D mm_gc->regs; - u32 pin_mask =3D 1 << (QE_PIO_PINS - 1 - gpio); + u32 pin_mask =3D PIN_MASK(gpio); =20 return !!(ioread32be(®s->cpdata) & pin_mask); } @@ -63,7 +64,7 @@ static int qe_gpio_set(struct gpio_chip *gc, unsigned int= gpio, int val) struct qe_gpio_chip *qe_gc =3D gpiochip_get_data(gc); struct qe_pio_regs __iomem *regs =3D mm_gc->regs; unsigned long flags; - u32 pin_mask =3D 1 << (QE_PIO_PINS - 1 - gpio); + u32 pin_mask =3D PIN_MASK(gpio); =20 spin_lock_irqsave(&qe_gc->lock, flags); =20 @@ -95,9 +96,9 @@ static int qe_gpio_set_multiple(struct gpio_chip *gc, break; if (__test_and_clear_bit(i, mask)) { if (test_bit(i, bits)) - qe_gc->cpdata |=3D (1U << (QE_PIO_PINS - 1 - i)); + qe_gc->cpdata |=3D PIN_MASK(i); else - qe_gc->cpdata &=3D ~(1U << (QE_PIO_PINS - 1 - i)); + qe_gc->cpdata &=3D ~PIN_MASK(i); } } =20 @@ -295,45 +296,52 @@ void qe_pin_set_gpio(struct qe_pin *qe_pin) } EXPORT_SYMBOL(qe_pin_set_gpio); =20 -static int __init qe_add_gpiochips(void) +static int qe_gpio_probe(struct platform_device *ofdev) { - struct device_node *np; - - for_each_compatible_node(np, NULL, "fsl,mpc8323-qe-pario-bank") { - int ret; - struct qe_gpio_chip *qe_gc; - struct of_mm_gpio_chip *mm_gc; - struct gpio_chip *gc; - - qe_gc =3D kzalloc(sizeof(*qe_gc), GFP_KERNEL); - if (!qe_gc) { - ret =3D -ENOMEM; - goto err; - } + struct device *dev =3D &ofdev->dev; + struct device_node *np =3D dev->of_node; + struct qe_gpio_chip *qe_gc; + struct of_mm_gpio_chip *mm_gc; + struct gpio_chip *gc; =20 - spin_lock_init(&qe_gc->lock); - - mm_gc =3D &qe_gc->mm_gc; - gc =3D &mm_gc->gc; - - mm_gc->save_regs =3D qe_gpio_save_regs; - gc->ngpio =3D QE_PIO_PINS; - gc->direction_input =3D qe_gpio_dir_in; - gc->direction_output =3D qe_gpio_dir_out; - gc->get =3D qe_gpio_get; - gc->set =3D qe_gpio_set; - gc->set_multiple =3D qe_gpio_set_multiple; - - ret =3D of_mm_gpiochip_add_data(np, mm_gc, qe_gc); - if (ret) - goto err; - continue; -err: - pr_err("%pOF: registration failed with status %d\n", - np, ret); - kfree(qe_gc); - /* try others anyway */ - } - return 0; + qe_gc =3D devm_kzalloc(dev, sizeof(*qe_gc), GFP_KERNEL); + if (!qe_gc) + return -ENOMEM; + + spin_lock_init(&qe_gc->lock); + + mm_gc =3D &qe_gc->mm_gc; + gc =3D &mm_gc->gc; + + mm_gc->save_regs =3D qe_gpio_save_regs; + gc->ngpio =3D QE_PIO_PINS; + gc->direction_input =3D qe_gpio_dir_in; + gc->direction_output =3D qe_gpio_dir_out; + gc->get =3D qe_gpio_get; + gc->set =3D qe_gpio_set; + gc->set_multiple =3D qe_gpio_set_multiple; + + return of_mm_gpiochip_add_data(np, mm_gc, qe_gc); +} + +static const struct of_device_id qe_gpio_match[] =3D { + { + .compatible =3D "fsl,mpc8323-qe-pario-bank", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, qe_gpio_match); + +static struct platform_driver qe_gpio_driver =3D { + .probe =3D qe_gpio_probe, + .driver =3D { + .name =3D "qe-gpio", + .of_match_table =3D qe_gpio_match, + }, +}; + +static int __init qe_gpio_init(void) +{ + return platform_driver_register(&qe_gpio_driver); } -arch_initcall(qe_add_gpiochips); +arch_initcall(qe_gpio_init); --=20 2.49.0 From nobody Thu Oct 2 09:16:52 2025 Received: from pegase2.c-s.fr (pegase2.c-s.fr [93.17.235.10]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 94081252910; Thu, 18 Sep 2025 16:51:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=93.17.235.10 ARC-Seal: i=1; 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Thu, 18 Sep 2025 18:23:34 +0200 (CEST) From: Christophe Leroy To: Qiang Zhao , Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Christophe Leroy , linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, Bartosz Golaszewski Subject: [PATCH v6 3/7] soc: fsl: qe: Drop legacy-of-mm-gpiochip.h header from GPIO driver Date: Thu, 18 Sep 2025 18:23:23 +0200 Message-ID: X-Mailer: git-send-email 2.49.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758212605; l=7404; i=christophe.leroy@csgroup.eu; s=20211009; h=from:subject:message-id; bh=e9P1hoN+HY9Rxao1ca5iWYSEWhtfCo2AeUitPGnj+o0=; b=40eCMf78XLHsXYk4sfOhPuF/a2MMGNJ13kM+yPseBa57hDBf+LS8nBb+aAsa6qU4fAVSs/2S3 ZjE4I04MM9FCKkvZoYp6QKbRQKplpN+E8HYXLirIzvA7az12O7hZx01 X-Developer-Key: i=christophe.leroy@csgroup.eu; a=ed25519; pk=HIzTzUj91asvincQGOFx6+ZF5AoUuP9GdOtQChs7Mm0= Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Remove legacy-of-mm-gpiochip.h header file. The above mentioned file provides an OF API that's deprecated. There is no agnostic alternatives to it and we have to open code the logic which was hidden behind of_mm_gpiochip_add_data(). Note, most of the GPIO drivers are using their own labeling schemas and resource retrieval that only a few may gain of the code deduplication, so whenever alternative is appear we can move drivers again to use that one. As a side effect this change fixes a potential memory leak on an error path, if of_mm_gpiochip_add_data() fails. [Text copied from commit 34064c8267a6 ("powerpc/8xx: Drop legacy-of-mm-gpiochip.h header")] Suggested-by: Bartosz Golaszewski Reviewed-by: Bartosz Golaszewski Signed-off-by: Christophe Leroy --- arch/powerpc/platforms/Kconfig | 1 - drivers/soc/fsl/qe/gpio.c | 51 ++++++++++++++++++---------------- 2 files changed, 27 insertions(+), 25 deletions(-) diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig index fea3766eac0f..5b689bd3ddf4 100644 --- a/arch/powerpc/platforms/Kconfig +++ b/arch/powerpc/platforms/Kconfig @@ -232,7 +232,6 @@ config QE_GPIO bool "QE GPIO support" depends on QUICC_ENGINE select GPIOLIB - select OF_GPIO_MM_GPIOCHIP help Say Y here if you're going to use hardware that connects to the QE GPIOs. diff --git a/drivers/soc/fsl/qe/gpio.c b/drivers/soc/fsl/qe/gpio.c index 04b44fc2bb58..c54154b404df 100644 --- a/drivers/soc/fsl/qe/gpio.c +++ b/drivers/soc/fsl/qe/gpio.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include #include @@ -24,7 +23,8 @@ #define PIN_MASK(gpio) (1UL << (QE_PIO_PINS - 1 - (gpio))) =20 struct qe_gpio_chip { - struct of_mm_gpio_chip mm_gc; + struct gpio_chip gc; + void __iomem *regs; spinlock_t lock; =20 /* shadowed data register to clear/set bits safely */ @@ -34,11 +34,9 @@ struct qe_gpio_chip { struct qe_pio_regs saved_regs; }; =20 -static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_gc) +static void qe_gpio_save_regs(struct qe_gpio_chip *qe_gc) { - struct qe_gpio_chip *qe_gc =3D - container_of(mm_gc, struct qe_gpio_chip, mm_gc); - struct qe_pio_regs __iomem *regs =3D mm_gc->regs; + struct qe_pio_regs __iomem *regs =3D qe_gc->regs; =20 qe_gc->cpdata =3D ioread32be(®s->cpdata); qe_gc->saved_regs.cpdata =3D qe_gc->cpdata; @@ -51,8 +49,8 @@ static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_= gc) =20 static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio) { - struct of_mm_gpio_chip *mm_gc =3D to_of_mm_gpio_chip(gc); - struct qe_pio_regs __iomem *regs =3D mm_gc->regs; + struct qe_gpio_chip *qe_gc =3D gpiochip_get_data(gc); + struct qe_pio_regs __iomem *regs =3D qe_gc->regs; u32 pin_mask =3D PIN_MASK(gpio); =20 return !!(ioread32be(®s->cpdata) & pin_mask); @@ -60,9 +58,8 @@ static int qe_gpio_get(struct gpio_chip *gc, unsigned int= gpio) =20 static int qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) { - struct of_mm_gpio_chip *mm_gc =3D to_of_mm_gpio_chip(gc); struct qe_gpio_chip *qe_gc =3D gpiochip_get_data(gc); - struct qe_pio_regs __iomem *regs =3D mm_gc->regs; + struct qe_pio_regs __iomem *regs =3D qe_gc->regs; unsigned long flags; u32 pin_mask =3D PIN_MASK(gpio); =20 @@ -83,9 +80,8 @@ static int qe_gpio_set(struct gpio_chip *gc, unsigned int= gpio, int val) static int qe_gpio_set_multiple(struct gpio_chip *gc, unsigned long *mask, unsigned long *bits) { - struct of_mm_gpio_chip *mm_gc =3D to_of_mm_gpio_chip(gc); struct qe_gpio_chip *qe_gc =3D gpiochip_get_data(gc); - struct qe_pio_regs __iomem *regs =3D mm_gc->regs; + struct qe_pio_regs __iomem *regs =3D qe_gc->regs; unsigned long flags; int i; =20 @@ -111,13 +107,12 @@ static int qe_gpio_set_multiple(struct gpio_chip *gc, =20 static int qe_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio) { - struct of_mm_gpio_chip *mm_gc =3D to_of_mm_gpio_chip(gc); struct qe_gpio_chip *qe_gc =3D gpiochip_get_data(gc); unsigned long flags; =20 spin_lock_irqsave(&qe_gc->lock, flags); =20 - __par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_IN, 0, 0, 0); + __par_io_config_pin(qe_gc->regs, gpio, QE_PIO_DIR_IN, 0, 0, 0); =20 spin_unlock_irqrestore(&qe_gc->lock, flags); =20 @@ -126,7 +121,6 @@ static int qe_gpio_dir_in(struct gpio_chip *gc, unsigne= d int gpio) =20 static int qe_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int va= l) { - struct of_mm_gpio_chip *mm_gc =3D to_of_mm_gpio_chip(gc); struct qe_gpio_chip *qe_gc =3D gpiochip_get_data(gc); unsigned long flags; =20 @@ -134,7 +128,7 @@ static int qe_gpio_dir_out(struct gpio_chip *gc, unsign= ed int gpio, int val) =20 spin_lock_irqsave(&qe_gc->lock, flags); =20 - __par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_OUT, 0, 0, 0); + __par_io_config_pin(qe_gc->regs, gpio, QE_PIO_DIR_OUT, 0, 0, 0); =20 spin_unlock_irqrestore(&qe_gc->lock, flags); =20 @@ -240,7 +234,7 @@ EXPORT_SYMBOL(qe_pin_free); void qe_pin_set_dedicated(struct qe_pin *qe_pin) { struct qe_gpio_chip *qe_gc =3D qe_pin->controller; - struct qe_pio_regs __iomem *regs =3D qe_gc->mm_gc.regs; + struct qe_pio_regs __iomem *regs =3D qe_gc->regs; struct qe_pio_regs *sregs =3D &qe_gc->saved_regs; int pin =3D qe_pin->num; u32 mask1 =3D 1 << (QE_PIO_PINS - (pin + 1)); @@ -269,7 +263,6 @@ void qe_pin_set_dedicated(struct qe_pin *qe_pin) =20 iowrite32be(qe_gc->cpdata, ®s->cpdata); qe_clrsetbits_be32(®s->cpodr, mask1, sregs->cpodr & mask1); - spin_unlock_irqrestore(&qe_gc->lock, flags); } EXPORT_SYMBOL(qe_pin_set_dedicated); @@ -284,7 +277,7 @@ EXPORT_SYMBOL(qe_pin_set_dedicated); void qe_pin_set_gpio(struct qe_pin *qe_pin) { struct qe_gpio_chip *qe_gc =3D qe_pin->controller; - struct qe_pio_regs __iomem *regs =3D qe_gc->mm_gc.regs; + struct qe_pio_regs __iomem *regs =3D qe_gc->regs; unsigned long flags; =20 spin_lock_irqsave(&qe_gc->lock, flags); @@ -301,7 +294,6 @@ static int qe_gpio_probe(struct platform_device *ofdev) struct device *dev =3D &ofdev->dev; struct device_node *np =3D dev->of_node; struct qe_gpio_chip *qe_gc; - struct of_mm_gpio_chip *mm_gc; struct gpio_chip *gc; =20 qe_gc =3D devm_kzalloc(dev, sizeof(*qe_gc), GFP_KERNEL); @@ -310,18 +302,29 @@ static int qe_gpio_probe(struct platform_device *ofde= v) =20 spin_lock_init(&qe_gc->lock); =20 - mm_gc =3D &qe_gc->mm_gc; - gc =3D &mm_gc->gc; + gc =3D &qe_gc->gc; =20 - mm_gc->save_regs =3D qe_gpio_save_regs; + gc->base =3D -1; gc->ngpio =3D QE_PIO_PINS; gc->direction_input =3D qe_gpio_dir_in; gc->direction_output =3D qe_gpio_dir_out; gc->get =3D qe_gpio_get; gc->set =3D qe_gpio_set; gc->set_multiple =3D qe_gpio_set_multiple; + gc->parent =3D dev; + gc->owner =3D THIS_MODULE; + + gc->label =3D devm_kasprintf(dev, GFP_KERNEL, "%pOF", np); + if (!gc->label) + return -ENOMEM; + + qe_gc->regs =3D devm_of_iomap(dev, np, 0, NULL); + if (IS_ERR(qe_gc->regs)) + return PTR_ERR(qe_gc->regs); + + qe_gpio_save_regs(qe_gc); =20 - return of_mm_gpiochip_add_data(np, mm_gc, qe_gc); + return devm_gpiochip_add_data(dev, gc, qe_gc); } =20 static const struct of_device_id qe_gpio_match[] =3D { --=20 2.49.0 From nobody Thu Oct 2 09:16:52 2025 Received: from pegase2.c-s.fr (pegase2.c-s.fr [93.17.235.10]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D26CF259C9A; Thu, 18 Sep 2025 16:50:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=93.17.235.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758214254; cv=none; b=a2xhKZffolOwjHM31p4mlJhj/qA1uhkXf4K0uAVIKsrMSUG65o6T+LSRwV5fLx1jHM793nFICu8P1pHrh8Z45LA5ZLXZEGPfEQsSNIpgSoQ1uOt5oXnzgUESgsT26AUMQNh+HADIQ3IwWcCeYTRkciWSRvoFjf5RwBTJ37NZG/g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758214254; c=relaxed/simple; bh=ECnVefXmhNl1JmdZzgG8I7sGGtwU4E9wPX7lONyQWKg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=hXOQI9NDbyRvawc/iljAbTVL5iDa0q0Px4/nP68in7qrisFvWQR0/oiRD9Gwf8AsApaHz3rOPZqQvbNrRuhTWh76urA/7oTzf9ABD7+oBtp2bB5ER5S3t6n/4+r94ZhIHujuCmrlS+qj+ahYUX6NXTQZQRXy8EGoxeOdPSI18kE= ARC-Authentication-Results: i=1; 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Thu, 18 Sep 2025 18:23:35 +0200 (CEST) X-Virus-Scanned: amavisd-new at c-s.fr Received: from messagerie.si.c-s.fr ([127.0.0.1]) by localhost (messagerie.si.c-s.fr [127.0.0.1]) (amavisd-new, port 10023) with ESMTP id 4GRJcVK8mL3E; Thu, 18 Sep 2025 18:23:35 +0200 (CEST) Received: from PO20335.idsi0.si.c-s.fr (unknown [192.168.235.99]) by messagerie.si.c-s.fr (Postfix) with ESMTP id 3A2A18B767; Thu, 18 Sep 2025 18:23:35 +0200 (CEST) From: Christophe Leroy To: Qiang Zhao , Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Christophe Leroy , linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, Bartosz Golaszewski Subject: [PATCH v6 4/7] soc: fsl: qe: Add support of IRQ in QE GPIO Date: Thu, 18 Sep 2025 18:23:24 +0200 Message-ID: <9a4d8bc1145f708a5ee6dde24fe2bd85cff006e2.1758212309.git.christophe.leroy@csgroup.eu> X-Mailer: git-send-email 2.49.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758212605; l=6045; i=christophe.leroy@csgroup.eu; s=20211009; h=from:subject:message-id; bh=ECnVefXmhNl1JmdZzgG8I7sGGtwU4E9wPX7lONyQWKg=; b=BCYsDj1HWoo7ACd1jnIWD1gvVC+4kIJPnu4mQAebHTYtdnONQI8aBWW2ByUbOLumzvmOVOvo5 7M0NqjAB6jlCtOfaAQF5rhWMlJ2Q2LShqj9FcaDbvVkQV0AVwpz/yil X-Developer-Key: i=christophe.leroy@csgroup.eu; a=ed25519; pk=HIzTzUj91asvincQGOFx6+ZF5AoUuP9GdOtQChs7Mm0= Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In the QE, a few GPIOs have an associated IRQ to notify changes. Add IRQ support to QE GPIO. As not all GPIOs have an associated IRQ, the driver needs to know to which GPIO corresponds each provided IRQ. This is provided via multiple compatible properties: compatible =3D "fsl,mpc8323-qe-pario-bank-a" compatible =3D "fsl,mpc8323-qe-pario-bank-b" compatible =3D "fsl,mpc8323-qe-pario-bank-c" compatible =3D "fsl,mpc8360-qe-pario-bank-a" compatible =3D "fsl,mpc8360-qe-pario-bank-b" compatible =3D "fsl,mpc8360-qe-pario-bank-c" compatible =3D "fsl,mpc8360-qe-pario-bank-d" compatible =3D "fsl,mpc8360-qe-pario-bank-e" compatible =3D "fsl,mpc8360-qe-pario-bank-f" compatible =3D "fsl,mpc8360-qe-pario-bank-g" compatible =3D "fsl,mpc8568-qe-pario-bank-a" compatible =3D "fsl,mpc8568-qe-pario-bank-b" compatible =3D "fsl,mpc8568-qe-pario-bank-c" compatible =3D "fsl,mpc8568-qe-pario-bank-d" compatible =3D "fsl,mpc8568-qe-pario-bank-e" compatible =3D "fsl,mpc8568-qe-pario-bank-f" When not using IRQ and for banks having no IRQ (like bank D on mpc8323) the origin compatible =3D "fsl,mpc8323-qe-pario-bank" is sufficient. Here is an exemple for port B of mpc8323 which has IRQs for GPIOs PB7, PB9, PB25 and PB27. qe_pio_b: gpio-controller@1418 { compatible =3D "fsl,mpc8323-qe-pario-bank-b"; reg =3D <0x1418 0x18>; interrupts =3D <4 5 6 7>; interrupt-parent =3D <&qepic>; gpio-controller; #gpio-cells =3D <2>; }; Reviewed-by: Bartosz Golaszewski Signed-off-by: Christophe Leroy --- v6: Changed mask local var to unsigned long instead of u32 to avoid build f= ailure on 64 bits --- drivers/soc/fsl/qe/gpio.c | 72 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/drivers/soc/fsl/qe/gpio.c b/drivers/soc/fsl/qe/gpio.c index c54154b404df..7a23eb220217 100644 --- a/drivers/soc/fsl/qe/gpio.c +++ b/drivers/soc/fsl/qe/gpio.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -32,6 +33,8 @@ struct qe_gpio_chip { =20 /* saved_regs used to restore dedicated functions */ struct qe_pio_regs saved_regs; + + int irq[QE_PIO_PINS]; }; =20 static void qe_gpio_save_regs(struct qe_gpio_chip *qe_gc) @@ -135,6 +138,13 @@ static int qe_gpio_dir_out(struct gpio_chip *gc, unsig= ned int gpio, int val) return 0; } =20 +static int qe_gpio_to_irq(struct gpio_chip *gc, unsigned int gpio) +{ + struct qe_gpio_chip *qe_gc =3D gpiochip_get_data(gc); + + return qe_gc->irq[gpio] ? : -ENXIO; +} + struct qe_pin { /* * The qe_gpio_chip name is unfortunate, we should change that to @@ -295,6 +305,7 @@ static int qe_gpio_probe(struct platform_device *ofdev) struct device_node *np =3D dev->of_node; struct qe_gpio_chip *qe_gc; struct gpio_chip *gc; + unsigned long mask; =20 qe_gc =3D devm_kzalloc(dev, sizeof(*qe_gc), GFP_KERNEL); if (!qe_gc) @@ -302,6 +313,15 @@ static int qe_gpio_probe(struct platform_device *ofdev) =20 spin_lock_init(&qe_gc->lock); =20 + mask =3D (unsigned long)of_device_get_match_data(dev); + if (mask) { + int i, j; + + for (i =3D 0, j =3D 0; i < ARRAY_SIZE(qe_gc->irq); i++) + if (mask & PIN_MASK(i)) + qe_gc->irq[i] =3D irq_of_parse_and_map(np, j++); + } + gc =3D &qe_gc->gc; =20 gc->base =3D -1; @@ -311,6 +331,7 @@ static int qe_gpio_probe(struct platform_device *ofdev) gc->get =3D qe_gpio_get; gc->set =3D qe_gpio_set; gc->set_multiple =3D qe_gpio_set_multiple; + gc->to_irq =3D qe_gpio_to_irq; gc->parent =3D dev; gc->owner =3D THIS_MODULE; =20 @@ -330,6 +351,57 @@ static int qe_gpio_probe(struct platform_device *ofdev) static const struct of_device_id qe_gpio_match[] =3D { { .compatible =3D "fsl,mpc8323-qe-pario-bank", + }, { + .compatible =3D "fsl,mpc8323-qe-pario-bank-a", + .data =3D (void *)(PIN_MASK(8) | PIN_MASK(10) | PIN_MASK(26) | PIN_MASK(= 28)), + }, { + .compatible =3D "fsl,mpc8323-qe-pario-bank-b", + .data =3D (void *)(PIN_MASK(7) | PIN_MASK(9) | PIN_MASK(25) | PIN_MASK(2= 7)), + }, { + .compatible =3D "fsl,mpc8323-qe-pario-bank-c", + .data =3D (void *)(PIN_MASK(24) | PIN_MASK(29)), + }, { + .compatible =3D "fsl,mpc8360-qe-pario-bank-a", + .data =3D (void *)(PIN_MASK(15) | PIN_MASK(16) | PIN_MASK(29) | PIN_MASK= (30)), + }, { + .compatible =3D "fsl,mpc8360-qe-pario-bank-b", + .data =3D (void *)(PIN_MASK(3) | PIN_MASK(5) | PIN_MASK(12) | PIN_MASK(1= 3) | + PIN_MASK(26) | PIN_MASK(27)), + }, { + .compatible =3D "fsl,mpc8360-qe-pario-bank-c", + .data =3D (void *)(PIN_MASK(27) | PIN_MASK(28) | PIN_MASK(29)), + }, { + .compatible =3D "fsl,mpc8360-qe-pario-bank-d", + .data =3D (void *)(PIN_MASK(12) | PIN_MASK(13) | PIN_MASK(16) | PIN_MASK= (17) | + PIN_MASK(26) | PIN_MASK(27)), + }, { + .compatible =3D "fsl,mpc8360-qe-pario-bank-e", + .data =3D (void *)(PIN_MASK(12) | PIN_MASK(13) | PIN_MASK(24) | PIN_MASK= (25) | + PIN_MASK(26) | PIN_MASK(27) | PIN_MASK(31)), + }, { + .compatible =3D "fsl,mpc8360-qe-pario-bank-f", + .data =3D (void *)(PIN_MASK(20)), + }, { + .compatible =3D "fsl,mpc8360-qe-pario-bank-g", + .data =3D (void *)(PIN_MASK(31)), + }, { + .compatible =3D "fsl,mpc8568-qe-pario-bank-a", + .data =3D (void *)(PIN_MASK(22) | PIN_MASK(23)), + }, { + .compatible =3D "fsl,mpc8568-qe-pario-bank-b", + .data =3D (void *)(PIN_MASK(12) | PIN_MASK(13) | PIN_MASK(28) | PIN_MASK= (29)), + }, { + .compatible =3D "fsl,mpc8568-qe-pario-bank-c", + .data =3D (void *)(PIN_MASK(16) | PIN_MASK(17) | PIN_MASK(25) | PIN_MASK= (26)), + }, { + .compatible =3D "fsl,mpc8568-qe-pario-bank-d", + .data =3D (void *)(PIN_MASK(18) | PIN_MASK(19)), + }, { + .compatible =3D "fsl,mpc8568-qe-pario-bank-e", + .data =3D (void *)(PIN_MASK(12) | PIN_MASK(16) | PIN_MASK(30)), + }, { + .compatible =3D "fsl,mpc8568-qe-pario-bank-f", + .data =3D (void *)(PIN_MASK(12) | PIN_MASK(16) | PIN_MASK(30)), }, {}, }; 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Thu, 18 Sep 2025 18:23:36 +0200 (CEST) X-Virus-Scanned: amavisd-new at c-s.fr Received: from messagerie.si.c-s.fr ([127.0.0.1]) by localhost (messagerie.si.c-s.fr [127.0.0.1]) (amavisd-new, port 10023) with ESMTP id cycSslAEFx8u; Thu, 18 Sep 2025 18:23:36 +0200 (CEST) Received: from PO20335.idsi0.si.c-s.fr (unknown [192.168.235.99]) by messagerie.si.c-s.fr (Postfix) with ESMTP id EC5308B776; Thu, 18 Sep 2025 18:23:35 +0200 (CEST) From: Christophe Leroy To: Qiang Zhao , Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Christophe Leroy , linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, Conor Dooley Subject: [PATCH v6 5/7] dt-bindings: soc: fsl: qe: Add an interrupt controller for QUICC Engine Ports Date: Thu, 18 Sep 2025 18:23:25 +0200 Message-ID: <67987bbf42344398709949cb53e3e8415260ec09.1758212309.git.christophe.leroy@csgroup.eu> X-Mailer: git-send-email 2.49.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758212605; l=2384; i=christophe.leroy@csgroup.eu; s=20211009; h=from:subject:message-id; bh=LLw9e41r3Nu4RX42WVov9+WnfXYO1+RpidnMUsA7kyA=; b=YDDPEKiP3Ihfi8Pm7o7zYRnNRvlYkYvxNfNQKaJ78/6tLwk/gZeiVWgFd34JlEKpPkQz5YuNm 7q+0fY29QL+CIgPgMa30z7I7M2Y68WpSf6wgo9LrLQ1Iy4lQ7igZ528 X-Developer-Key: i=christophe.leroy@csgroup.eu; a=ed25519; pk=HIzTzUj91asvincQGOFx6+ZF5AoUuP9GdOtQChs7Mm0= Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The QUICC Engine provides interrupts for a few I/O ports. This is handled via a separate interrupt ID and managed via a triplet of dedicated registers hosted by the SoC. Implement an interrupt driver for it for that those IRQs can then be linked to the related GPIOs. Acked-by: Conor Dooley Signed-off-by: Christophe Leroy --- .../soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe= -ports-ic.yaml diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-= ic.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-ic.= yaml new file mode 100644 index 000000000000..a356ad8b13f5 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale QUICC Engine I/O Ports Interrupt Controller + +maintainers: + - Christophe Leroy + +description: + Interrupt controller for the QUICC Engine I/O ports found on some Freesc= ale/NXP PowerQUICC and QorIQ SoCs. + +properties: + compatible: + enum: + - fsl,mpc8323-qe-ports-ic + - fsl,mpc8360-qe-ports-ic + - fsl,mpc8568-qe-ports-ic + + reg: + maxItems: 1 + description: Base address and size of the QE I/O Ports Interrupt Contr= oller registers. + + interrupt-controller: true + + '#address-cells': + const: 0 + + '#interrupt-cells': + const: 1 + + interrupts: + maxItems: 1 + description: Interrupt line to which the QE I/O Ports controller is co= nnected. + +required: + - compatible + - reg + - interrupt-controller + - '#address-cells' + - '#interrupt-cells' + - interrupts + +additionalProperties: false + +examples: + - | + interrupt-controller@c00 { + compatible =3D "fsl,mpc8323-qe-ports-ic"; + reg =3D <0xc00 0x18>; + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + interrupts =3D <74 0x8>; + interrupt-parent =3D <&ipic>; + }; --=20 2.49.0 From nobody Thu Oct 2 09:16:52 2025 Received: from pegase2.c-s.fr (pegase2.c-s.fr [93.17.235.10]) by smtp.subspace.kernel.org (Postfix) with ESMTP id BB86D221F29; Thu, 18 Sep 2025 16:50:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=93.17.235.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758214242; cv=none; b=j11H9edmHXgbTAMdEYoREqjFYOJ/N2AiP8dPIAEspHtnFHPluZtZtQ489kMHiEmCs31kGwyjFvdHazL4Iau9GsElJA4uIqSDTJxuRv8HMoDr4oNrlWDtBU1/yK5aERUfuyM6NwaQeHWjpihCg5B9H+6P488lH6ltZvU81loob5E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758214242; c=relaxed/simple; bh=Dvuwwh8MSNUgRklML1mjdeLSnlO6YfBO8ze0l2VRvwk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=W58dyZfUXyfi3JKVg7QOeAzBR4PpRK3HWXApE0UgK6MG58dyfyrnYIHEYMfcz74vIPUljFU8RI2afKeasRVyVYpLq9KmIH+gN3G3chWpO4ebmXx5de/EsC3DYlMOxVdArt3enmSS7OqqKnDvXFzwhSPU86JYN6U2Vgy7uy+g9xk= ARC-Authentication-Results: i=1; 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Thu, 18 Sep 2025 18:23:37 +0200 (CEST) X-Virus-Scanned: amavisd-new at c-s.fr Received: from messagerie.si.c-s.fr ([127.0.0.1]) by localhost (messagerie.si.c-s.fr [127.0.0.1]) (amavisd-new, port 10023) with ESMTP id MPO8j3rwFKzz; Thu, 18 Sep 2025 18:23:37 +0200 (CEST) Received: from PO20335.idsi0.si.c-s.fr (unknown [192.168.235.99]) by messagerie.si.c-s.fr (Postfix) with ESMTP id B88608B776; Thu, 18 Sep 2025 18:23:36 +0200 (CEST) From: Christophe Leroy To: Qiang Zhao , Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Christophe Leroy , linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 6/7] dt-bindings: soc: fsl: qe: Convert QE GPIO to DT schema Date: Thu, 18 Sep 2025 18:23:26 +0200 Message-ID: <5c4f831404857dd6eeefebe2ecdf2bb8ad503538.1758212309.git.christophe.leroy@csgroup.eu> X-Mailer: git-send-email 2.49.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758212606; l=3281; i=christophe.leroy@csgroup.eu; s=20211009; h=from:subject:message-id; bh=Dvuwwh8MSNUgRklML1mjdeLSnlO6YfBO8ze0l2VRvwk=; b=772HlsH6h7UbPeuqAuXNjZe1qUDYjxe+koslvNmvWWXiaDk343uXnAoM6Ktsbnm/d8eLZYDLB GfJSIX1NDfkAW8rn07MXW6bSNkPxrqaok3BYmgU4ZotlEFyuJ2gkImU X-Developer-Key: i=christophe.leroy@csgroup.eu; a=ed25519; pk=HIzTzUj91asvincQGOFx6+ZF5AoUuP9GdOtQChs7Mm0= Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Convert QE QPIO devicetree binding to DT schema. Signed-off-by: Christophe Leroy --- v6: Comments from Rob taken into account except the comment on fsl,-q= e-pario-bank becoming fsl,chip-qe-pario-bank as I don't know what to do. --- .../gpio/fsl,mpc8323-qe-pario-bank.yaml | 49 +++++++++++++++++++ .../bindings/soc/fsl/cpm_qe/qe/par_io.txt | 26 +--------- 2 files changed, 50 insertions(+), 25 deletions(-) create mode 100644 Documentation/devicetree/bindings/gpio/fsl,mpc8323-qe-p= ario-bank.yaml diff --git a/Documentation/devicetree/bindings/gpio/fsl,mpc8323-qe-pario-ba= nk.yaml b/Documentation/devicetree/bindings/gpio/fsl,mpc8323-qe-pario-bank.= yaml new file mode 100644 index 000000000000..0dd9c0e6ca39 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/fsl,mpc8323-qe-pario-bank.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,mpc8323-qe-pario-ban= k.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale QUICC Engine Parallel I/O (QE PARIO) GPIO Bank + +maintainers: + - Christophe Leroy + +properties: + compatible: + items: + - enum: + - fsl,chip-qe-pario-bank + - const: fsl,mpc8323-qe-pario-bank + + reg: + maxItems: 1 + + gpio-controller: true + + '#gpio-cells': + const: 2 + +required: + - compatible + - reg + - gpio-controller + - '#gpio-cells' + +additionalProperties: false + +examples: + - | + gpio-controller@1400 { + compatible =3D "fsl,mpc8360-qe-pario-bank", "fsl,mpc8323-qe-pario-= bank"; + reg =3D <0x1400 0x18>; + gpio-controller; + #gpio-cells =3D <2>; + }; + + gpio-controller@1460 { + compatible =3D "fsl,mpc8360-qe-pario-bank", "fsl,mpc8323-qe-pario-= bank"; + reg =3D <0x1460 0x18>; + gpio-controller; + #gpio-cells =3D <2>; + }; diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/par_io.txt= b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/par_io.txt index 09b1b05fa677..782699c14567 100644 --- a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/par_io.txt +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/par_io.txt @@ -24,28 +24,4 @@ par_io@1400 { =20 Note that "par_io" nodes are obsolete, and should not be used for the new device trees. Instead, each Par I/O bank should be represented -via its own gpio-controller node: - -Required properties: -- #gpio-cells : should be "2". -- compatible : should be "fsl,-qe-pario-bank", - "fsl,mpc8323-qe-pario-bank". -- reg : offset to the register set and its length. -- gpio-controller : node to identify gpio controllers. - -Example: - qe_pio_a: gpio-controller@1400 { - #gpio-cells =3D <2>; - compatible =3D "fsl,mpc8360-qe-pario-bank", - "fsl,mpc8323-qe-pario-bank"; - reg =3D <0x1400 0x18>; - gpio-controller; - }; - - qe_pio_e: gpio-controller@1460 { - #gpio-cells =3D <2>; - compatible =3D "fsl,mpc8360-qe-pario-bank", - "fsl,mpc8323-qe-pario-bank"; - reg =3D <0x1460 0x18>; - gpio-controller; - }; +via its own gpio-controller node. --=20 2.49.0 From nobody Thu Oct 2 09:16:52 2025 Received: from pegase2.c-s.fr (pegase2.c-s.fr [93.17.235.10]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 9AAA5221F29; Thu, 18 Sep 2025 16:50:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=93.17.235.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758214237; cv=none; b=HhSkN27VcfT7J0dod+F1XK4d76bpz/GZN4HpRYf02oadZTDgx9hCFEV4k0n2o1OHPbvg8gk91EKECKVx04P5qFcZLGXFFHLWzbmIrQUaOmlSDXWNjb583oGit7ggEwH1SJJLlQoMP21DNLB9yUkBp3Sb1GWm72mb2RENROPW4VQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758214237; c=relaxed/simple; bh=k3Y6MBNnl6dECpR6PnRX0K8qXjVVH4SDYF4pnM6U+5g=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=lLQ/afSkHbTZ9GQNIU5i5wiRUO25KQ+4RJJBVGxLww4gIE0fkVBaDM70Anoyec/J8wywXDl5e6ThlbwUPk2ysWPJQtfQoESEUCe1ulqXD3p/9f0F7k0NzZor+PeX1S2FgJyGb/WbD4RZRF3pnzdIawno2Ggu43PlkG/86RD16YQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=csgroup.eu; spf=pass smtp.mailfrom=csgroup.eu; arc=none smtp.client-ip=93.17.235.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=csgroup.eu Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=csgroup.eu Received: from localhost (mailhub4.si.c-s.fr [172.26.127.67]) by localhost (Postfix) with ESMTP id 4cSLY82NTDz9sg9; Thu, 18 Sep 2025 18:23:40 +0200 (CEST) X-Virus-Scanned: amavisd-new at c-s.fr Received: from pegase2.c-s.fr ([172.26.127.65]) by localhost (pegase2.c-s.fr [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id sEG83xOg8Ef7; Thu, 18 Sep 2025 18:23:40 +0200 (CEST) Received: from messagerie.si.c-s.fr (messagerie.si.c-s.fr [192.168.25.192]) by pegase2.c-s.fr (Postfix) with ESMTP id 4cSLY624WMz9sfq; Thu, 18 Sep 2025 18:23:38 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by messagerie.si.c-s.fr (Postfix) with ESMTP id 361D48B767; Thu, 18 Sep 2025 18:23:38 +0200 (CEST) X-Virus-Scanned: amavisd-new at c-s.fr Received: from messagerie.si.c-s.fr ([127.0.0.1]) by localhost (messagerie.si.c-s.fr [127.0.0.1]) (amavisd-new, port 10023) with ESMTP id mscD6JiKuvkZ; Thu, 18 Sep 2025 18:23:38 +0200 (CEST) Received: from PO20335.idsi0.si.c-s.fr (unknown [192.168.235.99]) by messagerie.si.c-s.fr (Postfix) with ESMTP id 79A2C8B778; Thu, 18 Sep 2025 18:23:37 +0200 (CEST) From: Christophe Leroy To: Qiang Zhao , Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Christophe Leroy , linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 7/7] dt-bindings: soc: fsl: qe: Add support of IRQ in QE GPIO Date: Thu, 18 Sep 2025 18:23:27 +0200 Message-ID: <7269082e90d20cf2cb4c11ceb61e24f0520d0154.1758212309.git.christophe.leroy@csgroup.eu> X-Mailer: git-send-email 2.49.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758212606; l=3549; i=christophe.leroy@csgroup.eu; s=20211009; h=from:subject:message-id; bh=k3Y6MBNnl6dECpR6PnRX0K8qXjVVH4SDYF4pnM6U+5g=; b=3OSUaeiNXCSwzLz+tUKTqJNBGf6B7Ioh5bO/V4rphHE6/+9Er+qUOqScWnM/rlK+XLEXiwf1o glInwdidngzCUT7dAGGwouPmY/73WQuRgFgH5vsf+hc8S21egdBPaJM X-Developer-Key: i=christophe.leroy@csgroup.eu; a=ed25519; pk=HIzTzUj91asvincQGOFx6+ZF5AoUuP9GdOtQChs7Mm0= Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In the QE, a few GPIOs have an associated IRQ to notify changes. Add IRQ support to QE GPIO. As not all GPIOs have an associated IRQ, the driver needs to know to which GPIO corresponds each provided IRQ. This is provided via multiple compatible properties: compatible =3D "fsl,mpc8323-qe-pario-bank-a" compatible =3D "fsl,mpc8323-qe-pario-bank-b" compatible =3D "fsl,mpc8323-qe-pario-bank-c" compatible =3D "fsl,mpc8360-qe-pario-bank-a" compatible =3D "fsl,mpc8360-qe-pario-bank-b" compatible =3D "fsl,mpc8360-qe-pario-bank-c" compatible =3D "fsl,mpc8360-qe-pario-bank-d" compatible =3D "fsl,mpc8360-qe-pario-bank-e" compatible =3D "fsl,mpc8360-qe-pario-bank-f" compatible =3D "fsl,mpc8360-qe-pario-bank-g" compatible =3D "fsl,mpc8568-qe-pario-bank-a" compatible =3D "fsl,mpc8568-qe-pario-bank-b" compatible =3D "fsl,mpc8568-qe-pario-bank-c" compatible =3D "fsl,mpc8568-qe-pario-bank-d" compatible =3D "fsl,mpc8568-qe-pario-bank-e" compatible =3D "fsl,mpc8568-qe-pario-bank-f" When not using IRQ and for banks having no IRQ (like bank D on mpc8323) the origin compatible =3D "fsl,mpc8323-qe-pario-bank" is still valid. Signed-off-by: Christophe Leroy --- .../gpio/fsl,mpc8323-qe-pario-bank.yaml | 27 +++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/gpio/fsl,mpc8323-qe-pario-ba= nk.yaml b/Documentation/devicetree/bindings/gpio/fsl,mpc8323-qe-pario-bank.= yaml index 0dd9c0e6ca39..c34aeea119e0 100644 --- a/Documentation/devicetree/bindings/gpio/fsl,mpc8323-qe-pario-bank.yaml +++ b/Documentation/devicetree/bindings/gpio/fsl,mpc8323-qe-pario-bank.yaml @@ -14,6 +14,22 @@ properties: items: - enum: - fsl,chip-qe-pario-bank + - fsl,mpc8323-qe-pario-bank-a + - fsl,mpc8323-qe-pario-bank-b + - fsl,mpc8323-qe-pario-bank-c + - fsl,mpc8360-qe-pario-bank-a + - fsl,mpc8360-qe-pario-bank-b + - fsl,mpc8360-qe-pario-bank-c + - fsl,mpc8360-qe-pario-bank-d + - fsl,mpc8360-qe-pario-bank-e + - fsl,mpc8360-qe-pario-bank-f + - fsl,mpc8360-qe-pario-bank-g + - fsl,mpc8568-qe-pario-bank-a + - fsl,mpc8568-qe-pario-bank-b + - fsl,mpc8568-qe-pario-bank-c + - fsl,mpc8568-qe-pario-bank-d + - fsl,mpc8568-qe-pario-bank-e + - fsl,mpc8568-qe-pario-bank-f - const: fsl,mpc8323-qe-pario-bank =20 reg: @@ -24,6 +40,9 @@ properties: '#gpio-cells': const: 2 =20 + interrupts: + description: List of interrupts for lines of the port that trigger int= errupts on change. + required: - compatible - reg @@ -35,15 +54,19 @@ additionalProperties: false examples: - | gpio-controller@1400 { - compatible =3D "fsl,mpc8360-qe-pario-bank", "fsl,mpc8323-qe-pario-= bank"; + compatible =3D "fsl,mpc8360-qe-pario-bank-a", "fsl,mpc8323-qe-pari= o-bank"; reg =3D <0x1400 0x18>; gpio-controller; #gpio-cells =3D <2>; + interrupts =3D <0 1 2 3>; + interrupt-parent =3D <&qepic>; }; =20 gpio-controller@1460 { - compatible =3D "fsl,mpc8360-qe-pario-bank", "fsl,mpc8323-qe-pario-= bank"; + compatible =3D "fsl,mpc8360-qe-pario-bank-e", "fsl,mpc8323-qe-pari= o-bank"; reg =3D <0x1460 0x18>; gpio-controller; #gpio-cells =3D <2>; + interrupts =3D <19 20 21 22 23 24 25>; + interrupt-parent =3D <&qepic>; }; --=20 2.49.0