From nobody Thu Oct 2 13:00:54 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8A6CD27E7DA; Tue, 16 Sep 2025 19:50:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758052251; cv=none; b=b/B75pJlfsJy+Idvn+/4mKT0Jy7I85UApjQ20hn9T2/6IJZXYStKorNXpsIAA6tNDn/PPf2I1lk/6GicmpANRi/1mVhW/FaoID5zaO9ROwzONeVw4m7oaNGa9N0TIidB+9XqUf4PCPrPWeTUZ/jVmqbynxt78mbeHyupUK5O8Og= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758052251; c=relaxed/simple; bh=WYEakKaGIgOHZEwp+8RyHz2DG4XYM1t05a+iyML1wAk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=tJ2+IFra9Pu/6TrcpjplfhBBjOoozEWGNOAw1Op3p73hj42u/xeR4Dxwe0dSDyVa1TKYMxyg8vwEjzQWR/Hbrtg/PIrHSpth+RF1IxOUoWM5sdejTn2YMshv4ruWN+hN+8tfbF3Sy4c2RwGIymTUWYhKg+zFvqNknmioTOgubc0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=hdsKg0tz; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="hdsKg0tz" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1758052249; x=1789588249; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=WYEakKaGIgOHZEwp+8RyHz2DG4XYM1t05a+iyML1wAk=; b=hdsKg0tzOJrBKc4m+gI2ZY3DKJWtYVe/oBQ7RgTpXVt3hWem8Z6QD3Ql CZ7IH8rkaqwgMgJPreQO2mf0OGLjBuszOtp+gVUxdC3ioQyCDnpfxzkFu JzHNfAvgGhmxvR7NfwUKJySgazRVU7TPhFlN2o3EU6MEkPcgxkLC0K/uZ fUDQfn382NU4k+af03nebySX57Xq5KY9AvgLX/Ax3S2+VhJjw09ZBaWS/ lu1XnLbl5Sjq/S8ip+Dr59RFPKKVx9c32Sf7visEo7/Ly9uVgPa4xO7eW jYi28nLfP21a5mTLLCHwAijYE/PD4Tn5cAKN+n7kIesZhbKNTDp7kJKEB w==; X-CSE-ConnectionGUID: OpVEzCAsSoaW6AVT1s3wKQ== X-CSE-MsgGUID: +kdF4wBhR8+O8zYogwmtAg== X-IronPort-AV: E=Sophos;i="6.18,269,1751266800"; d="scan'208";a="47129845" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 16 Sep 2025 12:50:48 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Tue, 16 Sep 2025 12:50:17 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 16 Sep 2025 12:50:17 -0700 From: To: , , , , , , , CC: , , , , Varshini Rajendran Subject: [PATCH v2 1/3] dt-bindings: power: reset: atmel,sama5d2-shdwc: add lpm binding Date: Tue, 16 Sep 2025 12:50:30 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Varshini Rajendran Add microchip,lpm-connection binding which allows to specify the devices the SHDWC's Low Power Mode pin is connected to. Signed-off-by: Varshini Rajendran [ryan.wanner@microchip.com: Add sam9x7-shdwc SoC to properties check] Signed-off-by: Ryan Wanner --- .../power/reset/atmel,sama5d2-shdwc.yaml | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-sh= dwc.yaml b/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdw= c.yaml index 9c34249b2d6d..668b541eb44c 100644 --- a/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml +++ b/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml @@ -56,6 +56,13 @@ properties: description: enable real-time timer wake-up type: boolean =20 + microchip,lpm-connection: + description: + List of phandles to devices which are connected to SHDWC's Low Power= Mode Pin. + The LPM pin is used to idicate to an external power supply or device= to enter + or exit a special powering state. + $ref: /schemas/types.yaml#/definitions/phandle-array + patternProperties: "^input@[0-15]$": description: @@ -96,6 +103,18 @@ allOf: properties: atmel,wakeup-rtt-timer: false =20 + - if: + properties: + compatible: + contains: + enum: + - atmel,sama5d2-shdwc + - microchip,sam9x60-shdwc + - microchip,sam9x7-shdwc + then: + properties: + microchip,lpm-connection: false + additionalProperties: false =20 examples: --=20 2.43.0 From nobody Thu Oct 2 13:00:54 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 894072C11F5; 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charset="utf-8" From: Claudiu Beznea The LPM shutdown controller output could signal the transition to PM state for different devices connected on board. On different boards LPM could be connected to different devices (e.g. on SAMA7G5-EK REV4 the LPM is connected to on main crystal oscillator, KSZ8081 PHY and to MCP16502 PMIC). Toggling LPM on BSR PM mode is done unconditionally and it helps PMIC to transition to a power saving mode. Toggling LPM on ULP0 and ULP1 should be done conditionally based on user defined wakeup sources, available wakeup source for PM mode and connections to SHDWC's LPM pin. On ULP0 any device could act as wakeup sources. On ULP1 only some of the on SoC controllers could act as wakeup sources. For this the architecture specific PM code parses board specific LPM devices, check them against possible wakeup source (in case of ULP1) and tells assembly code to act properly on SHDWC's LPM pin. Signed-off-by: Claudiu Beznea [ryan.wanner@microchip.com: Fixed conflicts when applying.] Signed-off-by: Ryan Wanner Reviewed-by: Claudiu Beznea --- arch/arm/mach-at91/pm.c | 96 +++++++++++++++++++++++++++- arch/arm/mach-at91/pm.h | 1 + arch/arm/mach-at91/pm_data-offsets.c | 1 + arch/arm/mach-at91/pm_suspend.S | 48 ++++++++++++-- 4 files changed, 138 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 35058b99069c..40052b06d979 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -116,6 +116,7 @@ struct at91_pm_quirks { * @config_shdwc_ws: wakeup sources configuration function for SHDWC * @config_pmc_ws: wakeup srouces configuration function for PMC * @ws_ids: wakup sources of_device_id array + * @shdwc_np: pointer to shdwc node * @bu: backup unit mapped data (for backup mode) * @quirks: PM quirks * @data: PM data to be used on last phase of suspend @@ -126,6 +127,7 @@ struct at91_soc_pm { int (*config_shdwc_ws)(void __iomem *shdwc, u32 *mode, u32 *polarity); int (*config_pmc_ws)(void __iomem *pmc, u32 mode, u32 polarity); const struct of_device_id *ws_ids; + struct device_node *shdwc_np; struct at91_pm_bu *bu; struct at91_pm_quirks quirks; struct at91_pm_data data; @@ -243,6 +245,82 @@ static const struct of_device_id sam9x7_ws_ids[] =3D { { /* sentinel */ } }; =20 +static bool at91_pm_device_in_list(const struct platform_device *pdev, + const struct of_device_id *ids) +{ + struct platform_device *local_pdev; + const struct of_device_id *match; + struct device_node *np; + int in_list =3D 0; + + for_each_matching_node_and_match(np, ids, &match) { + local_pdev =3D of_find_device_by_node(np); + if (!local_pdev) + continue; + + put_device(&local_pdev->dev); + if (pdev =3D=3D local_pdev) + return true; + } + + return false; +} + +static int at91_pm_prepare_lpm(unsigned int pm_mode) +{ + struct platform_device *pdev; + int ndevices, i, ret; + struct of_phandle_args lpmspec; + + if ((pm_mode !=3D AT91_PM_ULP0 && pm_mode !=3D AT91_PM_ULP1) || + !soc_pm.shdwc_np) + return 0; + + ndevices =3D of_count_phandle_with_args(soc_pm.shdwc_np, + "microchip,lpm-connection", NULL); + if (ndevices < 0) + return 0; + + soc_pm.data.lpm =3D 1; + for (i =3D 0; i < ndevices; i++) { + ret =3D of_parse_phandle_with_args(soc_pm.shdwc_np, + "microchip,lpm-connection", + NULL, i, &lpmspec); + if (ret < 0) { + if (ret =3D=3D -ENOENT) { + continue; + } else { + soc_pm.data.lpm =3D 0; + return ret; + } + } + + pdev =3D of_find_device_by_node(lpmspec.np); + of_node_put(lpmspec.np); + if (!pdev) + continue; + + if (device_may_wakeup(&pdev->dev)) { + if (pm_mode =3D=3D AT91_PM_ULP1) { + /* + * ULP1 wake-up sources are limited. Ignore it if not + * in soc_pm.ws_ids. + */ + if (at91_pm_device_in_list(pdev, soc_pm.ws_ids)) + soc_pm.data.lpm =3D 0; + } else { + soc_pm.data.lpm =3D 0; + } + } + + put_device(&pdev->dev); + if (!soc_pm.data.lpm) + break; + } + + return 0; +} + static int at91_pm_config_ws(unsigned int pm_mode, bool set) { const struct wakeup_source_info *wsi; @@ -481,10 +559,17 @@ static int at91_pm_begin(suspend_state_t state) soc_pm.data.mode =3D -1; } =20 - ret =3D at91_pm_config_ws(soc_pm.data.mode, true); + ret =3D at91_pm_prepare_lpm(soc_pm.data.mode); if (ret) return ret; =20 + ret =3D at91_pm_config_ws(soc_pm.data.mode, true); + if (ret) { + /* Revert LPM if any. */ + soc_pm.data.lpm =3D 0; + return ret; + } + if (soc_pm.data.mode =3D=3D AT91_PM_BACKUP) soc_pm.bu->suspended =3D 1; else if (soc_pm.bu) @@ -1266,7 +1351,11 @@ static void __init at91_pm_modes_init(const u32 *map= s, int len) AT91_PM_REPLACE_MODES(maps, SHDWC); } else { soc_pm.data.shdwc =3D of_iomap(np, 0); - of_node_put(np); + /* + * np is used further on suspend/resume path so we skip the + * of_node_put(np) here. + */ + soc_pm.shdwc_np =3D np; } } =20 @@ -1669,7 +1758,8 @@ void __init sama7_pm_init(void) AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP1, AT91_PM_BACKUP, }; static const u32 iomaps[] __initconst =3D { - [AT91_PM_ULP0] =3D AT91_PM_IOMAP(SFRBU), + [AT91_PM_ULP0] =3D AT91_PM_IOMAP(SFRBU) | + AT91_PM_IOMAP(SHDWC), [AT91_PM_ULP1] =3D AT91_PM_IOMAP(SFRBU) | AT91_PM_IOMAP(SHDWC) | AT91_PM_IOMAP(ETHC), diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h index 50c3a425d140..5707ff6ff444 100644 --- a/arch/arm/mach-at91/pm.h +++ b/arch/arm/mach-at91/pm.h @@ -40,6 +40,7 @@ struct at91_pm_data { unsigned int pmc_mckr_offset; unsigned int pmc_version; unsigned int pmc_mcks; + unsigned int lpm; }; #endif =20 diff --git a/arch/arm/mach-at91/pm_data-offsets.c b/arch/arm/mach-at91/pm_d= ata-offsets.c index 0ca5da66dc26..fb9651abdfdf 100644 --- a/arch/arm/mach-at91/pm_data-offsets.c +++ b/arch/arm/mach-at91/pm_data-offsets.c @@ -20,6 +20,7 @@ int main(void) pmc_version)); DEFINE(PM_DATA_PMC_MCKS, offsetof(struct at91_pm_data, pmc_mcks)); + DEFINE(PM_DATA_LPM, offsetof(struct at91_pm_data, lpm)); =20 return 0; } diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspen= d.S index 2e639f9ed648..b9b4208ff732 100644 --- a/arch/arm/mach-at91/pm_suspend.S +++ b/arch/arm/mach-at91/pm_suspend.S @@ -87,9 +87,30 @@ tmp3 .req r6 =20 .endm =20 - .macro at91_backup_set_lpm reg +/* + * Set LPM + * @ena: 0 - disable LPM + * 1 - enable LPM + * + * Side effects: overwrites r7, r8, r9 + */ + .macro at91_set_lpm ena #ifdef CONFIG_SOC_SAMA7 - orr \reg, \reg, #0x200000 + ldr r7, .lpm + cmp r7, #1 + bne 21f + ldr r7, .shdwc + cmp r7, #0 + beq 21f + mov r8, #0xA5000000 + add r8, #0x200000 + mov r9, #\ena + cmp r9, #1 + beq 20f + add r8, #0x200000 +20: + str r8, [r7] +21: #endif .endm =20 @@ -479,7 +500,7 @@ sr_dis_exit: ldr tmp1, [pmc, #AT91_PMC_SR] str tmp1, .saved_osc_status tst tmp1, #AT91_PMC_MOSCRCS - bne 1f + bne 7f =20 /* Turn off RC oscillator */ ldr tmp1, [pmc, #AT91_CKGR_MOR] @@ -493,6 +514,9 @@ sr_dis_exit: tst tmp1, #AT91_PMC_MOSCRCS bne 2b =20 + /* Enable LPM. */ +7: at91_set_lpm 1 + /* Wait for interrupt */ 1: at91_cpu_idle =20 @@ -510,7 +534,9 @@ sr_dis_exit: wait_mckrdy tmp3 b 6f =20 -5: /* Restore RC oscillator state */ +5: at91_set_lpm 0 + + /* Restore RC oscillator state */ ldr tmp1, .saved_osc_status tst tmp1, #AT91_PMC_MOSCRCS beq 4f @@ -588,6 +614,9 @@ sr_dis_exit: =20 wait_mckrdy tmp3 =20 + /* Enable LPM */ + at91_set_lpm 1 + /* Enter the ULP1 mode by set WAITMODE bit in CKGR_MOR */ ldr tmp1, [pmc, #AT91_CKGR_MOR] orr tmp1, tmp1, #AT91_PMC_WAITMODE @@ -601,6 +630,9 @@ sr_dis_exit: =20 wait_mckrdy tmp3 =20 + /* Disable LPM. */ + at91_set_lpm 0 + /* Enable the crystal oscillator */ ldr tmp1, [pmc, #AT91_CKGR_MOR] orr tmp1, tmp1, #AT91_PMC_MOSCEN @@ -1054,7 +1086,9 @@ ulp_exit: ldr r0, .shdwc mov tmp1, #0xA5000000 add tmp1, tmp1, #0x1 - at91_backup_set_lpm tmp1 +#ifdef CONFIG_SOC_SAMA7 + orr tmp1, tmp1, #0x200000 +#endif str tmp1, [r0, #0] .endm =20 @@ -1088,6 +1122,8 @@ ENTRY(at91_pm_suspend_in_sram) #ifdef CONFIG_SOC_SAMA7 ldr tmp1, [r0, #PM_DATA_PMC_MCKS] str tmp1, .mcks + ldr tmp1, [r0, #PM_DATA_LPM] + str tmp1, .lpm #endif =20 /* @@ -1179,6 +1215,8 @@ ENDPROC(at91_pm_suspend_in_sram) #ifdef CONFIG_SOC_SAMA7 .mcks: .word 0 +.lpm: + .word 0 #endif .saved_mckr: .word 0 --=20 2.43.0 From nobody Thu Oct 2 13:00:54 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1057A2E54BB; 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X-CSE-ConnectionGUID: OpVEzCAsSoaW6AVT1s3wKQ== X-CSE-MsgGUID: iEhMxX1lQ0qgWColzJt/pQ== X-IronPort-AV: E=Sophos;i="6.18,269,1751266800"; d="scan'208";a="47129849" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 16 Sep 2025 12:50:49 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Tue, 16 Sep 2025 12:50:17 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 16 Sep 2025 12:50:17 -0700 From: To: , , , , , , , CC: , , , , Claudiu Beznea Subject: [PATCH v2 3/3] ARM: dts: at91: sama7g5ek: add microchip,lpm-connection on shdwc node Date: Tue, 16 Sep 2025 12:50:32 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Add microchip,lpm-connection binding to shdwc node. On SAMA7G5-EK REV4 LPM is connected to GMAC1's PHY, 24MHz oscillator and PMIC. On board PMIC is not listed here as it is only treated on BSR mode uncoditionally. Signed-off-by: Claudiu Beznea Signed-off-by: Ryan Wanner --- arch/arm/boot/dts/microchip/at91-sama7g5ek.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/microchip/at91-sama7g5ek.dts b/arch/arm/boot= /dts/microchip/at91-sama7g5ek.dts index 3924f62ff0fb..50e9a5a5732a 100644 --- a/arch/arm/boot/dts/microchip/at91-sama7g5ek.dts +++ b/arch/arm/boot/dts/microchip/at91-sama7g5ek.dts @@ -872,6 +872,7 @@ &sdmmc2 { =20 &shdwc { debounce-delay-us =3D <976>; + microchip,lpm-connection =3D <&gmac1 &main_xtal>; status =3D "okay"; =20 input@0 { --=20 2.43.0