From nobody Wed Sep 10 23:25:52 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 98268335BCC; Wed, 10 Sep 2025 16:22:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757521359; cv=none; b=cE+CoubnNaxXee4Q0x82fB9zV+NEm1sstIv8N5IjXFFlwQV9MHuyGgHeYY5aOE/GUSQC/lxtpxVJe6qlWyvbHWpn+AEWVbxWrChzz3gL/yWnI1hc4/3VtvdL1TmpS/GR7vJBCVU+rkbSZdcy8Q7EA+vS5X29T+TeDujTMX4pzkA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757521359; c=relaxed/simple; bh=scNnRW/xaf/hHxWjoSyQk47lXv/bg4g6PJeBtBDImSg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=l3Zi1A70RelZjz5LRH37AkYlC3LCG1DNQHLjNUSFc2j7j9BU7xzzG2y8o2G6HlHAcImyU5fTXB/gJEOVk1WdqoCAwq2k3zhwOgQAmY4pHxIfuTf88mIO4T2BCwe/rU3M0XmBqoy8DD4w6QZ2IAEx2yr2pmuPd4vqTlMLut9rhpM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=NyWFEwzt; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="NyWFEwzt" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1757521357; x=1789057357; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=scNnRW/xaf/hHxWjoSyQk47lXv/bg4g6PJeBtBDImSg=; b=NyWFEwztc0pffGYRUZCeWZHga6AYxtWkY+sidc9Pe5air/a2Diaonkre SgdNrAKUN7C85//78ED4N5KJcwQpWfmm3/UGjrHl06fRUgIG8Nu3aY7IL s0DotAV/14ax4dOVOiPDTVzb0vnx7OzHNqviL6Ivus0ww29P2qj2tESDg E8GvsUcigeHQu+51FKRjHIiT7E+kalsHbfKxE6doEogwsLTisuw7OIGZG 3u4A7HDnePUNdA2FMOYYKMQZPw/hqMxAJvARS416xvM4DWDBuWIQZIoH0 yxjp4SziKgEp+YnyyPv4U/01UKfKV8v8sRz282GPALJQMsuOpT85oPJ/C g==; X-CSE-ConnectionGUID: yOp9HMF6QSeW0ZytE26RNg== X-CSE-MsgGUID: iiaFCm9vSaC9R8K+buWEdQ== X-IronPort-AV: E=Sophos;i="6.18,254,1751266800"; d="scan'208";a="46875548" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 10 Sep 2025 09:22:36 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Wed, 10 Sep 2025 09:22:10 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Wed, 10 Sep 2025 09:22:10 -0700 From: To: , , , , , , , CC: , , , , Varshini Rajendran Subject: [PATCH 1/4] dt-bindings: power: reset: atmel,sama5d2-shdwc: add lpm binding Date: Wed, 10 Sep 2025 09:20:36 -0700 Message-ID: <71c7d25f64612ca9571aa544be8f2651be8fe33e.1757519351.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Varshini Rajendran Add microchip,lpm-connection binding which allows to specify the devices the SHDWC's LPM pin is connected. Signed-off-by: Varshini Rajendran [ryan.wanner@microchip.com: Add sam9x7-shdwc SoC to properties check] Signed-off-by: Ryan Wanner --- .../power/reset/atmel,sama5d2-shdwc.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-sh= dwc.yaml b/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdw= c.yaml index 9c34249b2d6d..b1a8ccd0873d 100644 --- a/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml +++ b/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml @@ -56,6 +56,10 @@ properties: description: enable real-time timer wake-up type: boolean =20 + microchip,lpm-connection: + description: list of phandles to devices which are connected to SHDWC'= s LPM pin + $ref: /schemas/types.yaml#/definitions/phandle + patternProperties: "^input@[0-15]$": description: @@ -96,6 +100,18 @@ allOf: properties: atmel,wakeup-rtt-timer: false =20 + - if: + properties: + compatible: + contains: + enum: + - atmel,sama5d2-shdwc + - microchip,sam9x60-shdwc + - microchip,sam9x7-shdwc + then: + properties: + microchip,lpm-connection: false + additionalProperties: false =20 examples: --=20 2.43.0 From nobody Wed Sep 10 23:25:52 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2FDA43375C2; Wed, 10 Sep 2025 16:22:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757521360; cv=none; b=IGNUYf0pkA0EDkRv8vI5faAKsvREAcZ8grjL6NWNHNO+99NZNlo7Tvr+f9ow6Tz1saTujWRRk3ontaKw8Gbn5hmMF9IUaX+uIkhumHpNNfVnJWMFdWs0PTXGn1swKX1T7of4CRKjKM0gPBVlLztQr88J9+sszXmxHTNcYhytWdU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757521360; c=relaxed/simple; bh=HRy4Y8fxp59EvUPRyo1sN5bM58I22ICctqiwhIZ2ORo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ENastNHdadt9guoz8w8xcp8IQ96G5XskXp+iR/DQL4gsrYN2eFDHlIdDRyykWoJcZ+ss8UvKxMrT5S3/rp63U6S10EtB1uCdzGbVBVDYINxwCrq2AbFD8LduvYexMfv62Q+Pui+eqFlPSwKueBrfnEWXEoMd2z/P5/PuLfRs/a4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=0Sd45sD0; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="0Sd45sD0" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1757521358; x=1789057358; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=HRy4Y8fxp59EvUPRyo1sN5bM58I22ICctqiwhIZ2ORo=; b=0Sd45sD04OCGXzfGzA3aiSO5JTTEFAV15neFa2GcDDFtE55jQT/JY5bt UFBBOBlQmT+38O07VRyY9NZTl2Ek7vfti56N6cvwc/uM9ZcaCLAx8Jjfk jCRIbpBi1vISyMXRL7VUYYsh0yaCPdPUHNGUwbn/BU1I+52Gk/XfsUf1M 7c+Hn4a4qq0NVAcc17ASMCzTODWg5QnDv1uY6ckfXt3XUpl4oESOxiHHF KdgEyn7Jo+pMjG88+ClCHxDuE1g6V1f/o/PdObP39cpg7TvQMrkbx7j5B Hq7Nnujnkdj0REpX65/cxz4tv+8ebs3V8ePgs7cayOyOxx83LDIIMxrYw w==; X-CSE-ConnectionGUID: yOp9HMF6QSeW0ZytE26RNg== X-CSE-MsgGUID: ELQo421uRx6cAqZp9KSB4g== X-IronPort-AV: E=Sophos;i="6.18,254,1751266800"; d="scan'208";a="46875550" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 10 Sep 2025 09:22:36 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Wed, 10 Sep 2025 09:22:10 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Wed, 10 Sep 2025 09:22:10 -0700 From: To: , , , , , , , CC: , , , Subject: [PATCH 2/4] ARM: at91: PM: implement selection of LPM Date: Wed, 10 Sep 2025 09:20:37 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The LPM shutdown controller output could signal the transition to PM state for different devices connected on board. On different boards LPM could be connected to different devices (e.g. on SAMA7G5-EK REV4 the LPM is connected to on main crystal oscillator, KSZ8081 PHY and to MCP16502 PMIC). Toggling LPM on BSR PM mode is done unconditionally and it helps PMIC to transition to a power saving mode. Toggling LPM on ULP0 and ULP1 should be done conditionally based on user defined wakeup sources, available wakeup source for PM mode and connections to SHDWC's LPM pin. On ULP0 any device could act as wakeup sources. On ULP1 only some of the on SoC controllers could act as wakeup sources. For this the architecture specific PM code parses board specific LPM devices, check them against possible wakeup source (in case of ULP1) and tells assembly code to act properly on SHDWC's LPM pin. Signed-off-by: Claudiu Beznea [ryan.wanner@microchip.com: Fixed conflicts when applying.] Signed-off-by: Ryan Wanner --- arch/arm/mach-at91/pm.c | 98 +++++++++++++++++++++++++++- arch/arm/mach-at91/pm.h | 1 + arch/arm/mach-at91/pm_data-offsets.c | 1 + arch/arm/mach-at91/pm_suspend.S | 50 ++++++++++++-- 4 files changed, 141 insertions(+), 9 deletions(-) diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 35058b99069c..29348d6c852b 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -116,6 +116,7 @@ struct at91_pm_quirks { * @config_shdwc_ws: wakeup sources configuration function for SHDWC * @config_pmc_ws: wakeup srouces configuration function for PMC * @ws_ids: wakup sources of_device_id array + * @shdwc_np: pointer to shdwc node * @bu: backup unit mapped data (for backup mode) * @quirks: PM quirks * @data: PM data to be used on last phase of suspend @@ -126,6 +127,7 @@ struct at91_soc_pm { int (*config_shdwc_ws)(void __iomem *shdwc, u32 *mode, u32 *polarity); int (*config_pmc_ws)(void __iomem *pmc, u32 mode, u32 polarity); const struct of_device_id *ws_ids; + struct device_node *shdwc_np; struct at91_pm_bu *bu; struct at91_pm_quirks quirks; struct at91_pm_data data; @@ -243,6 +245,84 @@ static const struct of_device_id sam9x7_ws_ids[] =3D { { /* sentinel */ } }; =20 +static int at91_pm_device_in_list(const struct platform_device *pdev, + const struct of_device_id *ids) +{ + struct platform_device *local_pdev; + const struct of_device_id *match; + struct device_node *np; + int in_list =3D 0; + + for_each_matching_node_and_match(np, ids, &match) { + local_pdev =3D of_find_device_by_node(np); + if (!local_pdev) + continue; + + if (pdev =3D=3D local_pdev) + in_list =3D 1; + + put_device(&local_pdev->dev); + if (in_list) + return in_list; + } + + return in_list; +} + +static int at91_pm_prepare_lpm(unsigned int pm_mode) +{ + struct platform_device *pdev; + int ndevices, i, ret; + struct of_phandle_args lpmspec; + + if ((pm_mode !=3D AT91_PM_ULP0 && pm_mode !=3D AT91_PM_ULP1) || + !soc_pm.shdwc_np) + return 0; + + ndevices =3D of_count_phandle_with_args(soc_pm.shdwc_np, + "microchip,lpm-connection", 0); + if (ndevices < 0) + return 0; + + soc_pm.data.lpm =3D 1; + for (i =3D 0; i < ndevices; i++) { + ret =3D of_parse_phandle_with_args(soc_pm.shdwc_np, + "microchip,lpm-connection", + NULL, i, &lpmspec); + if (ret < 0) { + if (ret =3D=3D -ENOENT) { + continue; + } else { + soc_pm.data.lpm =3D 0; + return ret; + } + } + + pdev =3D of_find_device_by_node(lpmspec.np); + if (!pdev) + continue; + + if (device_may_wakeup(&pdev->dev)) { + if (pm_mode =3D=3D AT91_PM_ULP1) { + /* + * ULP1 wake-up sources are limited. Ignore it if not + * in soc_pm.ws_ids. + */ + if (at91_pm_device_in_list(pdev, soc_pm.ws_ids)) + soc_pm.data.lpm =3D 0; + } else { + soc_pm.data.lpm =3D 0; + } + } + + put_device(&pdev->dev); + if (!soc_pm.data.lpm) + break; + } + + return 0; +} + static int at91_pm_config_ws(unsigned int pm_mode, bool set) { const struct wakeup_source_info *wsi; @@ -481,10 +561,17 @@ static int at91_pm_begin(suspend_state_t state) soc_pm.data.mode =3D -1; } =20 - ret =3D at91_pm_config_ws(soc_pm.data.mode, true); + ret =3D at91_pm_prepare_lpm(soc_pm.data.mode); if (ret) return ret; =20 + ret =3D at91_pm_config_ws(soc_pm.data.mode, true); + if (ret) { + /* Revert LPM if any. */ + soc_pm.data.lpm =3D 0; + return ret; + } + if (soc_pm.data.mode =3D=3D AT91_PM_BACKUP) soc_pm.bu->suspended =3D 1; else if (soc_pm.bu) @@ -1266,7 +1353,11 @@ static void __init at91_pm_modes_init(const u32 *map= s, int len) AT91_PM_REPLACE_MODES(maps, SHDWC); } else { soc_pm.data.shdwc =3D of_iomap(np, 0); - of_node_put(np); + /* + * np is used further on suspend/resume path so we skip the + * of_node_put(np) here. + */ + soc_pm.shdwc_np =3D np; } } =20 @@ -1669,7 +1760,8 @@ void __init sama7_pm_init(void) AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP1, AT91_PM_BACKUP, }; static const u32 iomaps[] __initconst =3D { - [AT91_PM_ULP0] =3D AT91_PM_IOMAP(SFRBU), + [AT91_PM_ULP0] =3D AT91_PM_IOMAP(SFRBU) | + AT91_PM_IOMAP(SHDWC), [AT91_PM_ULP1] =3D AT91_PM_IOMAP(SFRBU) | AT91_PM_IOMAP(SHDWC) | AT91_PM_IOMAP(ETHC), diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h index 50c3a425d140..5707ff6ff444 100644 --- a/arch/arm/mach-at91/pm.h +++ b/arch/arm/mach-at91/pm.h @@ -40,6 +40,7 @@ struct at91_pm_data { unsigned int pmc_mckr_offset; unsigned int pmc_version; unsigned int pmc_mcks; + unsigned int lpm; }; #endif =20 diff --git a/arch/arm/mach-at91/pm_data-offsets.c b/arch/arm/mach-at91/pm_d= ata-offsets.c index 0ca5da66dc26..fb9651abdfdf 100644 --- a/arch/arm/mach-at91/pm_data-offsets.c +++ b/arch/arm/mach-at91/pm_data-offsets.c @@ -20,6 +20,7 @@ int main(void) pmc_version)); DEFINE(PM_DATA_PMC_MCKS, offsetof(struct at91_pm_data, pmc_mcks)); + DEFINE(PM_DATA_LPM, offsetof(struct at91_pm_data, lpm)); =20 return 0; } diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspen= d.S index aad53ec9e957..198236bdbbb3 100644 --- a/arch/arm/mach-at91/pm_suspend.S +++ b/arch/arm/mach-at91/pm_suspend.S @@ -110,9 +110,30 @@ lp_done_\ena: #endif .endm =20 - .macro at91_backup_set_lpm reg +/* + * Set LPM + * @ena: 0 - disable LPM + * 1 - enable LPM + * + * Side effects: overwrites r7, r8, r9 + */ + .macro at91_set_lpm ena #ifdef CONFIG_SOC_SAMA7 - orr \reg, \reg, #0x200000 + ldr r7, .lpm + cmp r7, #1 + bne 21f + ldr r7, .shdwc + cmp r7, #0 + beq 21f + mov r8, #0xA5000000 + add r8, #0x200000 + mov r9, #\ena + cmp r9, #1 + beq 20f + add r8, #0x200000 +20: + str r8, [r7] +21: #endif .endm =20 @@ -502,7 +523,7 @@ sr_dis_exit: ldr tmp1, [pmc, #AT91_PMC_SR] str tmp1, .saved_osc_status tst tmp1, #AT91_PMC_MOSCRCS - bne 1f + bne 7f =20 /* Turn off RC oscillator */ ldr tmp1, [pmc, #AT91_CKGR_MOR] @@ -516,6 +537,9 @@ sr_dis_exit: tst tmp1, #AT91_PMC_MOSCRCS bne 2b =20 + /* Enable LPM. */ +7: at91_set_lpm 1 + /* Wait for interrupt */ 1: at91_cpu_idle =20 @@ -533,8 +557,10 @@ sr_dis_exit: wait_mckrdy tmp3 b 6f =20 -5: /* Restore RC oscillator state */ - ldr tmp1, .saved_osc_status +5: at91_set_lpm 0 + + /* Restore RC oscillator state */ +8: ldr tmp1, .saved_osc_status tst tmp1, #AT91_PMC_MOSCRCS beq 4f =20 @@ -611,6 +637,9 @@ sr_dis_exit: =20 wait_mckrdy tmp3 =20 + /* Enable LPM */ + at91_set_lpm 1 + /* Enter the ULP1 mode by set WAITMODE bit in CKGR_MOR */ ldr tmp1, [pmc, #AT91_CKGR_MOR] orr tmp1, tmp1, #AT91_PMC_WAITMODE @@ -624,6 +653,9 @@ sr_dis_exit: =20 wait_mckrdy tmp3 =20 + /* Disable LPM. */ + at91_set_lpm 0 + /* Enable the crystal oscillator */ ldr tmp1, [pmc, #AT91_CKGR_MOR] orr tmp1, tmp1, #AT91_PMC_MOSCEN @@ -1083,7 +1115,9 @@ ulp_exit: ldr r0, .shdwc mov tmp1, #0xA5000000 add tmp1, tmp1, #0x1 - at91_backup_set_lpm tmp1 +#ifdef CONFIG_SOC_SAMA7 + orr tmp1, tmp1, #0x200000 +#endif str tmp1, [r0, #0] .endm =20 @@ -1117,6 +1151,8 @@ ENTRY(at91_pm_suspend_in_sram) #ifdef CONFIG_SOC_SAMA7 ldr tmp1, [r0, #PM_DATA_PMC_MCKS] str tmp1, .mcks + ldr tmp1, [r0, #PM_DATA_LPM] + str tmp1, .lpm #endif =20 /* @@ -1208,6 +1244,8 @@ ENDPROC(at91_pm_suspend_in_sram) #ifdef CONFIG_SOC_SAMA7 .mcks: .word 0 +.lpm: + .word 0 #endif .saved_mckr: .word 0 --=20 2.43.0 From nobody Wed Sep 10 23:25:52 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 169B420E030; Wed, 10 Sep 2025 16:22:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757521354; cv=none; b=uauihxhhW36QvcIbEtAnlc0jYDpnk5ivexI0zI/ttP7h5HOzXrijfLj4QftF+npgIcMm8oahJ2KLf1VQLrDnMEVppyjhN8WPKhYy4Qa5kSCov6OZ1AEAuvedL7IXlCejG/mytxH62509PcBYa5YR4e96MVvulxeBOPdvAxZG4Ec= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757521354; c=relaxed/simple; bh=OA697MSbwYFaga1yasvj23HlhhxErDH/zxQeYPOWGmE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=b+x8VbauVob4ll4+LtbX87Hout0QN8/PCu32rXaiU39CdH6Ed1+BEjeB4yzSSg4+fQ4HDqkAgAKBs0mfW/BMVvEUUJtDJkxX9wcArPYz7jAvcnXvielSiwJHtcnjGfU+e/OsBBHVzJvHW+AF9H/mPi8I+/7T8IHNtalh+3UsOdY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=nETLaO+O; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="nETLaO+O" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1757521352; x=1789057352; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=OA697MSbwYFaga1yasvj23HlhhxErDH/zxQeYPOWGmE=; b=nETLaO+Of0l/+cWjZWUDkqcViJLV2y09vFw4cF/4xKmaLqdXkosVviOq I6gOVKkrE8hcZf9C0IDKpvyFg7VaN81gj2JuhREo+szgtXJV3tY3nXVCu Hcf1dEIqg/o38i8GWGjSr3URLUQvc61gL3VK6oRRRmb3Lr5GGSAN9bfMU aIDAFkukDGrtfvzuEccjm8LYvMsetJDW9n3c92VtYdy4+dM4PAuRJMB3W oAhqNtsi3HP5HslRCo4ISBU3NMGZK+ITOBwY2v0edinAaqkTdkzPGFW5G /BKEAoNDFV0qkI1VWo8fgA3cmgX5MTkD7wq1dzbpa8S0c5XfSFtqGmaJ0 g==; X-CSE-ConnectionGUID: tPE+SbpaSyCyxVMbhLqdoA== X-CSE-MsgGUID: +YSUaQIrRSOq/S/Erz+hxg== X-IronPort-AV: E=Sophos;i="6.18,254,1751266800"; d="scan'208";a="213715732" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 10 Sep 2025 09:22:25 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Wed, 10 Sep 2025 09:22:11 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Wed, 10 Sep 2025 09:22:11 -0700 From: To: , , , , , , , CC: , , , , "Ryan Wanner" Subject: [PATCH 3/4] ARM: at91: pm: Remove 2.5V regulator Date: Wed, 10 Sep 2025 09:20:38 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Ryan Wanner Remove 2.5V regulator since enabling and disabling this regulator is no longer supported. Signed-off-by: Ryan Wanner --- arch/arm/mach-at91/pm_suspend.S | 29 ----------------------------- include/soc/at91/sama7-sfrbu.h | 7 ------- 2 files changed, 36 deletions(-) diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspen= d.S index 198236bdbbb3..36cae7b1a490 100644 --- a/arch/arm/mach-at91/pm_suspend.S +++ b/arch/arm/mach-at91/pm_suspend.S @@ -87,29 +87,6 @@ tmp3 .req r6 =20 .endm =20 -/** - * Set state for 2.5V low power regulator - * @ena: 0 - disable regulator - * 1 - enable regulator - * - * Side effects: overwrites r7, r8, r9, r10 - */ - .macro at91_2_5V_reg_set_low_power ena -#ifdef CONFIG_SOC_SAMA7 - ldr r7, .sfrbu - mov r8, #\ena - ldr r9, [r7, #AT91_SFRBU_25LDOCR] - orr r9, r9, #AT91_SFRBU_25LDOCR_LP - cmp r8, #1 - beq lp_done_\ena - bic r9, r9, #AT91_SFRBU_25LDOCR_LP -lp_done_\ena: - ldr r10, =3DAT91_SFRBU_25LDOCR_LDOANAKEY - orr r9, r9, r10 - str r9, [r7, #AT91_SFRBU_25LDOCR] -#endif - .endm - /* * Set LPM * @ena: 0 - disable LPM @@ -1055,9 +1032,6 @@ save_mck: =20 at91_plla_disable =20 - /* Enable low power mode for 2.5V regulator. */ - at91_2_5V_reg_set_low_power 1 - ldr tmp3, .pm_mode cmp tmp3, #AT91_PM_ULP1 beq ulp1_mode @@ -1070,9 +1044,6 @@ ulp1_mode: b ulp_exit =20 ulp_exit: - /* Disable low power mode for 2.5V regulator. */ - at91_2_5V_reg_set_low_power 0 - ldr pmc, .pmc_base =20 at91_plla_enable diff --git a/include/soc/at91/sama7-sfrbu.h b/include/soc/at91/sama7-sfrbu.h index 76b740810d34..8cee48d1ae2c 100644 --- a/include/soc/at91/sama7-sfrbu.h +++ b/include/soc/at91/sama7-sfrbu.h @@ -18,13 +18,6 @@ #define AT91_SFRBU_PSWBU_SOFTSWITCH (1 << 1) /* Power switch BU source se= lection */ #define AT91_SFRBU_PSWBU_CTRL (1 << 0) /* Power switch BU control */ =20 -#define AT91_SFRBU_25LDOCR (0x0C) /* SFRBU 2.5V LDO Control Register */ -#define AT91_SFRBU_25LDOCR_LDOANAKEY (0x3B6E18 << 8) /* Specific value ma= ndatory to allow writing of other register bits. */ -#define AT91_SFRBU_25LDOCR_STATE (1 << 3) /* LDOANA Switch On/Off Control= */ -#define AT91_SFRBU_25LDOCR_LP (1 << 2) /* LDOANA Low-Power Mode Control = */ -#define AT91_SFRBU_PD_VALUE_MSK (0x3) -#define AT91_SFRBU_25LDOCR_PD_VALUE(v) ((v) & AT91_SFRBU_PD_VALUE_MSK) /*= LDOANA Pull-down value */ - #define AT91_FRBU_DDRPWR (0x10) /* SFRBU DDR Power Control Register */ #define AT91_FRBU_DDRPWR_STATE (1 << 0) /* DDR Power Mode State */ =20 --=20 2.43.0 From nobody Wed Sep 10 23:25:52 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D865A327A04; Wed, 10 Sep 2025 16:22:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757521356; cv=none; b=OgMJFGIz6JTLxP8HWQ4jE8Ks1k6YX/EO9wLGpKJ80dzSykG9iA/CiOkMLwhlZWDyCK09B4PYKETjvBkoi5NBAsyKwYBf9r+2GtR2WP8hFFx6JTcmLWaHJt9nxy88UwACWg5q7l5tqW2tB4vH5gOLu6JR9OWMQR06vGbp63lJFLE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757521356; c=relaxed/simple; bh=5pieibsRPJo/V0RuJcEOBHWPfpUwqYwCzxf8IMfkT2k=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=m7QBkOxQzR25mMl8hx6KnuPXN8OtMyOOQYhS5DULtvUmZ+OineMsT//bssqR+jVTaUkUpkGN9Jr0qeBrGaSHTFIzXisAoBocQAsY8CKg+K4gkXoz7FWx+M7pkeN8uP6t77zrDp6bIUfFaU3GftnNm0jXLWskD2j0/2BSAbxPT0M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=XpsrgZLw; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="XpsrgZLw" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1757521354; x=1789057354; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5pieibsRPJo/V0RuJcEOBHWPfpUwqYwCzxf8IMfkT2k=; b=XpsrgZLw63C06QJN+AIdW4Sje2XsuVahjVn46u2dw4xwzRAjg0FUcSWj RDfNhgDfhRdzSKl+KvyOGkdDv4SGR/95j0/Axq5NLzzDuzjhPWQMXRrmA BkGi1OZ6b86AUqK8m4qHgfSTczUIXu0vOiOiux3WjTLCR98DwbrAdNQSn z8mxLvhPhcQWVwPvnNcQI+In1tV3JlzKwvposEdYBzOy1xKlhthyNFgsb cttBOgBvFxoJNosB2rHnjK+g4cNQ5uo7wWx9lv5HntvW+R4kMfS6hQGwr hZB87I1T9x/m0nmo9JbssGD3X+bOCUkY1ugDJgZuu5B5OWW9AvBUHZySu g==; X-CSE-ConnectionGUID: tPE+SbpaSyCyxVMbhLqdoA== X-CSE-MsgGUID: f2/xiDzdRj6Lx1CeFsmEmQ== X-IronPort-AV: E=Sophos;i="6.18,254,1751266800"; d="scan'208";a="213715733" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 10 Sep 2025 09:22:25 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Wed, 10 Sep 2025 09:22:11 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Wed, 10 Sep 2025 09:22:11 -0700 From: To: , , , , , , , CC: , , , Subject: [PATCH 4/4] ARM: dts: at91: sama7g5ek: add microchip,lpm-connection on shdwc node Date: Wed, 10 Sep 2025 09:20:39 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Add microchip,lpm-connection binding to shdwc node. On SAMA7G5-EK REV4 LPM is connected to GMAC1's PHY, 24MHz oscillator and PMIC. On board PMIC is not listed here as it is only treated on BSR mode uncoditionally. Signed-off-by: Claudiu Beznea Signed-off-by: Ryan Wanner --- arch/arm/boot/dts/microchip/at91-sama7g5ek.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/microchip/at91-sama7g5ek.dts b/arch/arm/boot= /dts/microchip/at91-sama7g5ek.dts index 3924f62ff0fb..50e9a5a5732a 100644 --- a/arch/arm/boot/dts/microchip/at91-sama7g5ek.dts +++ b/arch/arm/boot/dts/microchip/at91-sama7g5ek.dts @@ -872,6 +872,7 @@ &sdmmc2 { =20 &shdwc { debounce-delay-us =3D <976>; + microchip,lpm-connection =3D <&gmac1 &main_xtal>; status =3D "okay"; =20 input@0 { --=20 2.43.0