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Mon, 8 Sep 2025 16:28:38 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , Subject: [PATCH rfcv2 1/8] iommu/arm-smmu-v3: Clear cmds->num after arm_smmu_cmdq_batch_submit Date: Mon, 8 Sep 2025 16:26:55 -0700 Message-ID: <2f7f5fff38d43221fd60139323d23b258e34cf8d.1757373449.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001F0:EE_|IA0PR12MB8326:EE_ X-MS-Office365-Filtering-Correlation-Id: d895f002-254a-4f7f-56cc-08ddef2f79f3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|7416014|376014|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?xuD3n/T+8YjoMawAHqV71YvmFrWvG+hGNpZZqVfNsZQ2dZKLkAjKKmLzzl/8?= =?us-ascii?Q?CQMc3wQZKjvhPBJvC8vFg0uHgbjcFquMWpIVNROVrykM1VSHEhtUTgYBD96K?= =?us-ascii?Q?ICPl7QERMb5Zv6CIjeuRNPeKmC2Ox7P5XzsuL3Oj99gfm+f/v2PtmRcD0nm9?= =?us-ascii?Q?gAVTaWD7qe8HUl33pdJd3d/PrqB05C1YXcMTSrgKIsUnTrfSNBOFJQSWpoxs?= =?us-ascii?Q?ps+aWMx6Pg/FN19CVqn6PubBl3GN1oOKKQdstzIHHbLgi0w16wY80zJ9sGKN?= =?us-ascii?Q?BR4CtNt6IVNU0mLlnVSCCEi3dnJNize7rBIgDhj4ID1D4y6dPDFGiXxejkTe?= =?us-ascii?Q?g8x+j+74bT6gfefh51jxurS3eQH9XG1k0UkwpBctzBX4WUe/Lbgurdwxt3eZ?= =?us-ascii?Q?er2G2+Bjr6sRqLmRHPgukNreVrKzQgPHG00LYv0UcxIM5QFe1vMU3Tjh5AcG?= =?us-ascii?Q?OC/BnDypZlwtlwm2EamhvB0EIbsb80BwIY5ezcnv/2aW8oOt1+Ybe1bjkWDk?= =?us-ascii?Q?Z2Wfpwrvd+K9vw9k8/bTUgx/lq+eP3dxE5T28VRKEdawQEu2HlC4Q/JFComC?= =?us-ascii?Q?Dd9reUZBNeW6oNNsA5TGrtK295VtkVKJMADkmteaEkagODBJ9QEs1hPoGZwL?= =?us-ascii?Q?aVoCp/5A09OLX57iuBnlxME0vzxxztgZ4KqzRXPB9QCB0meyNLpaPrO5iQCX?= =?us-ascii?Q?jPa25zL6ayvuaKtjlrgNVbOlzrsM0PsrYs3JMg46ogJoPUAxjpzwuJCgVabY?= =?us-ascii?Q?vPeKMMM9WEequSaKTYrG1ILn2r5neBjs5ZyDXQI4ENcDrK+S349bmlqfkWdU?= =?us-ascii?Q?9IpSpg6RXbmglLjo5iCYV7P5q5brsG1Y8qWjNbh9BRP1Q4w4+iS6ryA6weFm?= =?us-ascii?Q?u0eyuxa62wMZsHUyNCkaAQt3K2ER0WvzetyTMs2sLojQQNoc5m4fzZnFiGBv?= =?us-ascii?Q?QUNz0MRdW8/yIg3GSHx4JrKs5rfcqQzvfMIFQVBOZAy79anVFZ+sx3ynWPV8?= =?us-ascii?Q?7PbU6nB+p1q+AYu22NtV9EsZReSUsz/tEzBvjEuq7J0sP+pyN9Eu5T8BTr6U?= =?us-ascii?Q?xZl34P8GYOG+NgxjYJljaz1PArw686PBXucOWwwJmvSaI9N1W5gZQ7nYRp0o?= =?us-ascii?Q?3jfd2f1ACVLSZDyO1C+RHrDtQ2vzU+I3BW/PkK2JUF1r094F1EEA5ZRFFf+W?= =?us-ascii?Q?l21AmJa5qPY9kbwbIMy6o6GgfmpB9AVzzI69VMqYytIPzLKESjE2XkHEBvkK?= =?us-ascii?Q?rq5EsvjnFV2/cfxWdcJnvRneGiPHopfBwF04aZMV2fftUqlzPCwtMmQF7E0O?= =?us-ascii?Q?BSO8mk+Ap38lckMVMKHQWbW6Sx28av4vJ/K5ZUqyh7/YMdlxUi6/z+0TXMRc?= =?us-ascii?Q?XPCllBZO2B3oa0ogaBsSs4e4hIyX2gzXQCkN3rXMkxJfB+G1dRi+11knP7gA?= =?us-ascii?Q?Ig0XMAofPX/5ODT+6TfOpymXHUzFz7j6s818gl8OMfI1dWy3RV1erxfskm15?= =?us-ascii?Q?ng0624jvvvTXuolShOZDjcwUNzKFOv08OVj4?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(7416014)(376014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Sep 2025 23:28:54.4695 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d895f002-254a-4f7f-56cc-08ddef2f79f3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F0.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8326 Content-Type: text/plain; charset="utf-8" None of the callers of arm_smmu_cmdq_batch_submit() cares about the batch after a submission. So, it'll be certainly safe to nuke the cmds->num, at least upon a successful one. This will ease a bit a wrapper function, for the new arm_smmu_invs structure. Signed-off-by: Nicolin Chen Acked-by: Balbir Singh --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 2a8b46b948f05..cccf8f52ee0d5 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -974,11 +974,17 @@ static void arm_smmu_cmdq_batch_add(struct arm_smmu_d= evice *smmu, cmds->num++; } =20 +/* Clears cmds->num after a successful submission */ static int arm_smmu_cmdq_batch_submit(struct arm_smmu_device *smmu, struct arm_smmu_cmdq_batch *cmds) { - return arm_smmu_cmdq_issue_cmdlist(smmu, cmds->cmdq, cmds->cmds, - cmds->num, true); + int ret; + + ret =3D arm_smmu_cmdq_issue_cmdlist(smmu, cmds->cmdq, cmds->cmds, + cmds->num, true); + if (!ret) + cmds->num =3D 0; + return ret; } =20 static void arm_smmu_page_response(struct device *dev, struct iopf_fault *= unused, --=20 2.43.0 From nobody Wed Sep 10 01:53:18 2025 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2079.outbound.protection.outlook.com [40.107.220.79]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0D73C2F9C32 for ; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Sep 2025 23:28:54.9084 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e8924a8f-4e61-42a3-0e62-08ddef2f7a41 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000FCC1.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4374 Content-Type: text/plain; charset="utf-8" Both the ARM_SMMU_DOMAIN_S1 case and the SVA case use ASID, requiring ASID based invalidation commands to flush the TLB. Define an ARM_SMMU_DOMAIN_SVA to make the SVA case clear to share the same path with the ARM_SMMU_DOMAIN_S1 case, which will be a part of the routine to build a new per-domain invalidation array. There is no function change. Suggested-by: Jason Gunthorpe Signed-off-by: Nicolin Chen Acked-by: Balbir Singh --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 + drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 1 + drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 3 +++ 3 files changed, 5 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index ae23aacc38402..5c0b38595d209 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -858,6 +858,7 @@ struct arm_smmu_master { enum arm_smmu_domain_stage { ARM_SMMU_DOMAIN_S1 =3D 0, ARM_SMMU_DOMAIN_S2, + ARM_SMMU_DOMAIN_SVA, }; =20 struct arm_smmu_domain { diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iomm= u/arm/arm-smmu-v3/arm-smmu-v3-sva.c index 59a480974d80f..6097f1f540d87 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c @@ -346,6 +346,7 @@ struct iommu_domain *arm_smmu_sva_domain_alloc(struct d= evice *dev, * ARM_SMMU_FEAT_RANGE_INV is present */ smmu_domain->domain.pgsize_bitmap =3D PAGE_SIZE; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Sep 2025 23:28:56.0165 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e43cfac9-3310-4b49-237a-08ddef2f7aea X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000FCC3.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB9160 Content-Type: text/plain; charset="utf-8" There will be a bit more things to free than smmu_domain itself. So keep a simple inline function in the header to share aross files. Suggested-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 5 +++++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 2 +- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 4 ++-- 3 files changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 5c0b38595d209..96a23ca633cb6 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -954,6 +954,11 @@ extern struct mutex arm_smmu_asid_lock; =20 struct arm_smmu_domain *arm_smmu_domain_alloc(void); =20 +static inline void arm_smmu_domain_free(struct arm_smmu_domain *smmu_domai= n) +{ + kfree(smmu_domain); +} + void arm_smmu_clear_cd(struct arm_smmu_master *master, ioasid_t ssid); struct arm_smmu_cd *arm_smmu_get_cd_ptr(struct arm_smmu_master *master, u32 ssid); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iomm= u/arm/arm-smmu-v3/arm-smmu-v3-sva.c index 6097f1f540d87..fc601b494e0af 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c @@ -365,6 +365,6 @@ struct iommu_domain *arm_smmu_sva_domain_alloc(struct d= evice *dev, err_asid: xa_erase(&arm_smmu_asid_xa, smmu_domain->cd.asid); err_free: - kfree(smmu_domain); + arm_smmu_domain_free(smmu_domain); return ERR_PTR(ret); } diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 0016ec699acfe..08af5f2d1235a 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2498,7 +2498,7 @@ static void arm_smmu_domain_free_paging(struct iommu_= domain *domain) ida_free(&smmu->vmid_map, cfg->vmid); } =20 - kfree(smmu_domain); + arm_smmu_domain_free(smmu_domain); } =20 static int arm_smmu_domain_finalise_s1(struct arm_smmu_device *smmu, @@ -3359,7 +3359,7 @@ arm_smmu_domain_alloc_paging_flags(struct device *dev= , u32 flags, return &smmu_domain->domain; =20 err_free: - kfree(smmu_domain); + arm_smmu_domain_free(smmu_domain); return ERR_PTR(ret); } =20 --=20 2.43.0 From nobody Wed Sep 10 01:53:18 2025 Received: from NAM04-MW2-obe.outbound.protection.outlook.com (mail-mw2nam04on2040.outbound.protection.outlook.com [40.107.101.40]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 438DE30DD0C for ; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Sep 2025 23:28:56.6105 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0e6e64cf-5ba2-4468-96ec-08ddef2f7b46 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000FCC4.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN5PR12MB9512 Content-Type: text/plain; charset="utf-8" From: Jason Gunthorpe Create a new data structure to hold an array of invalidations that need to be performed for the domain based on what masters are attached, to replace the single smmu pointer and linked list of masters in the current design. Each array entry holds one of the invalidation actions - S1_ASID, S2_VMID, ATS or their variant with information to feed invalidation commands to HW. It is structured so that multiple SMMUs can participate in the same array, removing one key limitation of the current system. To maximize performance, a sorted array is used as the data structure. It allows grouping SYNCs together to parallelize invalidations. For instance, it will group all the ATS entries after the ASID/VMID entry, so they will all be pushed to the PCI devices in parallel with one SYNC. To minimize the locking cost on the invalidation fast path (reader of the invalidation array), the array is managed with RCU. Provide a set of APIs to add/delete entries to/from an array, which cover cannot-fail attach cases, e.g. attaching to arm_smmu_blocked_domain. Also add kunit coverage for those APIs. Signed-off-by: Jason Gunthorpe Co-developed-by: Nicolin Chen Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 79 +++++++ .../iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c | 93 ++++++++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 212 ++++++++++++++++++ 3 files changed, 384 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 96a23ca633cb6..34fcc1a930e6a 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -649,6 +649,82 @@ struct arm_smmu_cmdq_batch { int num; }; =20 +/* + * The order here also determines the sequence in which commands are sent = to the + * command queue. E.g. TLBI must be done before ATC_INV. + */ +enum arm_smmu_inv_type { + INV_TYPE_S1_ASID, + INV_TYPE_S2_VMID, + INV_TYPE_S2_VMID_S1_CLEAR, + INV_TYPE_ATS, + INV_TYPE_ATS_FULL, +}; + +struct arm_smmu_inv { + struct arm_smmu_device *smmu; + u8 type; + u8 size_opcode; + u8 nsize_opcode; + u32 id; /* ASID or VMID or SID */ + union { + size_t pgsize; /* ARM_SMMU_FEAT_RANGE_INV */ + u32 ssid; /* INV_TYPE_ATS */ + }; + + refcount_t users; /* users=3D0 to mark as a trash to be purged */ +}; + +/** + * struct arm_smmu_invs - Per-domain invalidation array + * @num_invs: number of invalidations in the flexible array + * @rcu: rcu head for kfree_rcu() + * @inv: flexible invalidation array + * + * The arm_smmu_invs is an RCU data structure. During a ->attach_dev callb= ack, + * arm_smmu_invs_merge(), arm_smmu_invs_unref() and arm_smmu_invs_purge() = will + * be used to allocate a new copy of an old array for addition and deletio= n in + * the old domain's and new domain's invs arrays. + * + * The arm_smmu_invs_unref() mutates a given array, by internally reducing= the + * users counts of some given entries. This exists to support a no-fail ro= utine + * like attaching to an IOMMU_DOMAIN_BLOCKED. And it could pair with a fol= lowup + * arm_smmu_invs_purge() call to generate a new clean array. + * + * Concurrent invalidation thread will push every invalidation described i= n the + * array into the command queue for each invalidation event. It is designe= d like + * this to optimize the invalidation fast path by avoiding locks. + * + * A domain can be shared across SMMU instances. When an instance gets rem= oved, + * it would delete all the entries that belong to that SMMU instance. Then= , a + * synchronize_rcu() would have to be called to sync the array, to prevent= any + * concurrent invalidation thread accessing the old array from issuing com= mands + * to the command queue of a removed SMMU instance. + */ +struct arm_smmu_invs { + size_t num_invs; + struct rcu_head rcu; + struct arm_smmu_inv inv[]; +}; + +static inline struct arm_smmu_invs *arm_smmu_invs_alloc(size_t num_invs) +{ + struct arm_smmu_invs *new_invs; + + new_invs =3D kzalloc(struct_size(new_invs, inv, num_invs), GFP_KERNEL); + if (!new_invs) + return ERR_PTR(-ENOMEM); + new_invs->num_invs =3D num_invs; + return new_invs; +} + +struct arm_smmu_invs *arm_smmu_invs_merge(struct arm_smmu_invs *invs, + struct arm_smmu_invs *to_merge); +size_t arm_smmu_invs_unref(struct arm_smmu_invs *invs, + struct arm_smmu_invs *to_unref); +struct arm_smmu_invs *arm_smmu_invs_purge(struct arm_smmu_invs *invs, + size_t num_dels); + struct arm_smmu_evtq { struct arm_smmu_queue q; struct iopf_queue *iopf; @@ -875,6 +951,8 @@ struct arm_smmu_domain { =20 struct iommu_domain domain; =20 + struct arm_smmu_invs __rcu *invs; + /* List of struct arm_smmu_master_domain */ struct list_head devices; spinlock_t devices_lock; @@ -956,6 +1034,7 @@ struct arm_smmu_domain *arm_smmu_domain_alloc(void); =20 static inline void arm_smmu_domain_free(struct arm_smmu_domain *smmu_domai= n) { + kfree_rcu(smmu_domain->invs, rcu); kfree(smmu_domain); } =20 diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c b/drivers/iom= mu/arm/arm-smmu-v3/arm-smmu-v3-test.c index d2671bfd37981..417a2b5ea2024 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c @@ -567,6 +567,98 @@ static void arm_smmu_v3_write_cd_test_sva_release(stru= ct kunit *test) NUM_EXPECTED_SYNCS(2)); } =20 +static void arm_smmu_v3_invs_test_verify(struct kunit *test, + struct arm_smmu_invs *invs, int num, + const int *ids, const int *users) +{ + KUNIT_EXPECT_EQ(test, invs->num_invs, num); + while (num--) { + KUNIT_EXPECT_EQ(test, invs->inv[num].id, ids[num]); + KUNIT_EXPECT_EQ(test, refcount_read(&invs->inv[num].users), + users[num]); + } +} + +static struct arm_smmu_invs invs1 =3D { + .num_invs =3D 3, + .inv =3D { { .type =3D INV_TYPE_S2_VMID, .id =3D 1, }, + { .type =3D INV_TYPE_S2_VMID, .id =3D 2, }, + { .type =3D INV_TYPE_S2_VMID, .id =3D 3, }, }, +}; + +static struct arm_smmu_invs invs2 =3D { + .num_invs =3D 3, + .inv =3D { { .type =3D INV_TYPE_S2_VMID, .id =3D 1, }, /* duplicated */ + { .type =3D INV_TYPE_ATS, .id =3D 4, }, + { .type =3D INV_TYPE_ATS, .id =3D 5, }, }, +}; + +static struct arm_smmu_invs invs3 =3D { + .num_invs =3D 3, + .inv =3D { { .type =3D INV_TYPE_S2_VMID, .id =3D 1, }, /* duplicated */ + { .type =3D INV_TYPE_ATS, .id =3D 5, }, /* recover a trash */ + { .type =3D INV_TYPE_ATS, .id =3D 6, }, }, +}; + +static void arm_smmu_v3_invs_test(struct kunit *test) +{ + const int results1[2][3] =3D { { 1, 2, 3, }, { 1, 1, 1, }, }; + const int results2[2][5] =3D { { 1, 2, 3, 4, 5, }, { 2, 1, 1, 1, 1, }, }; + const int results3[2][5] =3D { { 1, 2, 3, 4, 5, }, { 1, 1, 1, 0, 0, }, }; + const int results4[2][5] =3D { { 1, 2, 3, 5, 6, }, { 2, 1, 1, 1, 1, }, }; + const int results5[2][5] =3D { { 1, 2, 3, 5, 6, }, { 1, 0, 0, 1, 1, }, }; + const int results6[2][5] =3D { { 1, 2, 3, 5, 6, }, { 0, 0, 0, 0, 0, }, }; + struct arm_smmu_invs *test_a, *test_b; + size_t num_dels; + + /* New array */ + test_a =3D arm_smmu_invs_alloc(0); + KUNIT_EXPECT_EQ(test, test_a->num_invs, 0); + + /* Test1: merge invs1 (new array) */ + test_b =3D arm_smmu_invs_merge(test_a, &invs1); + kfree(test_a); + arm_smmu_v3_invs_test_verify(test, test_b, ARRAY_SIZE(results1[0]), + results1[0], results1[1]); + + /* Test2: merge invs2 (new array) */ + test_a =3D arm_smmu_invs_merge(test_b, &invs2); + kfree(test_b); + arm_smmu_v3_invs_test_verify(test, test_a, ARRAY_SIZE(results2[0]), + results2[0], results2[1]); + + /* Test3: unref invs2 (same array) */ + num_dels =3D arm_smmu_invs_unref(test_a, &invs2); + arm_smmu_v3_invs_test_verify(test, test_a, ARRAY_SIZE(results3[0]), + results3[0], results3[1]); + KUNIT_EXPECT_EQ(test, num_dels, 2); + + /* Test4: merge invs3 (new array) */ + test_b =3D arm_smmu_invs_merge(test_a, &invs3); + kfree(test_a); + arm_smmu_v3_invs_test_verify(test, test_b, ARRAY_SIZE(results4[0]), + results4[0], results4[1]); + + /* Test5: unref invs1 (same array) */ + num_dels =3D arm_smmu_invs_unref(test_b, &invs1); + arm_smmu_v3_invs_test_verify(test, test_b, ARRAY_SIZE(results5[0]), + results5[0], results5[1]); + KUNIT_EXPECT_EQ(test, num_dels, 2); + + /* Test6: unref invs3 (same array) */ + num_dels =3D arm_smmu_invs_unref(test_b, &invs3); + arm_smmu_v3_invs_test_verify(test, test_b, ARRAY_SIZE(results6[0]), + results6[0], results6[1]); + KUNIT_EXPECT_EQ(test, num_dels, 5); + + /* Test7: purge test_b (new array) */ + test_a =3D arm_smmu_invs_purge(test_b, num_dels); + kfree(test_b); + KUNIT_EXPECT_EQ(test, test_a->num_invs, 0); + + kfree(test_a); +} + static struct kunit_case arm_smmu_v3_test_cases[] =3D { KUNIT_CASE(arm_smmu_v3_write_ste_test_bypass_to_abort), KUNIT_CASE(arm_smmu_v3_write_ste_test_abort_to_bypass), @@ -590,6 +682,7 @@ static struct kunit_case arm_smmu_v3_test_cases[] =3D { KUNIT_CASE(arm_smmu_v3_write_ste_test_s2_to_s1_stall), KUNIT_CASE(arm_smmu_v3_write_cd_test_sva_clear), KUNIT_CASE(arm_smmu_v3_write_cd_test_sva_release), + KUNIT_CASE(arm_smmu_v3_invs_test), {}, }; =20 diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 08af5f2d1235a..83d842bd88817 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -1033,6 +1034,209 @@ void arm_smmu_tlb_inv_asid(struct arm_smmu_device *= smmu, u16 asid) arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); } =20 +static int arm_smmu_invs_cmp(const void *_l, const void *_r) +{ + const struct arm_smmu_inv *l =3D _l; + const struct arm_smmu_inv *r =3D _r; + + if (l->smmu !=3D r->smmu) + return cmp_int((uintptr_t)l->smmu, (uintptr_t)r->smmu); + if (l->type !=3D r->type) + return cmp_int(l->type, r->type); + return cmp_int(l->id, r->id); +} + +/* + * Merge compare of two sorted arrays items. If one side is past the end o= f the + * array, return the other side to let it run out the iteration. + */ +static inline int +arm_smmu_invs_merge_cmp(const struct arm_smmu_invs *l, size_t l_idx, + const struct arm_smmu_invs *r, size_t r_idx) +{ + if (l_idx !=3D l->num_invs && r_idx !=3D r->num_invs) + return arm_smmu_invs_cmp(&l->inv[l_idx], &r->inv[r_idx]); + if (l_idx !=3D l->num_invs) + return -1; + return 1; +} + +/** + * arm_smmu_invs_merge() - Merge @to_merge into @invs and generate a new a= rray + * @invs: the base invalidation array + * @to_merge: an array of invlidations to merge + * + * Return: a newly allocated array on success, or ERR_PTR + * + * This function must be locked and serialized with arm_smmu_invs_unref() = and + * arm_smmu_invs_purge(), but do not lockdep on any lock for KUNIT test. + * + * Either @invs or @to_merge must be sorted itself. This ensures the retur= ned + * array will be sorted as well. + * + * Caller is resposible for freeing the @invs and the returned new one. + * + * Entries marked as trash will be purged in the returned array. + */ +VISIBLE_IF_KUNIT +struct arm_smmu_invs *arm_smmu_invs_merge(struct arm_smmu_invs *invs, + struct arm_smmu_invs *to_merge) +{ + struct arm_smmu_invs *new_invs; + struct arm_smmu_inv *new; + size_t num_adds =3D 0; + size_t num_dels =3D 0; + size_t i, j; + + for (i =3D j =3D 0; i !=3D invs->num_invs || j !=3D to_merge->num_invs;) { + int cmp =3D arm_smmu_invs_merge_cmp(invs, i, to_merge, j); + + if (cmp < 0) { + /* no found in to_merge, leave alone but delete trash */ + if (!refcount_read(&invs->inv[i].users)) + num_dels++; + i++; + } else if (cmp =3D=3D 0) { + /* same item */ + i++; + j++; + } else { + /* unique to to_merge */ + num_adds++; + j++; + } + } + + new_invs =3D arm_smmu_invs_alloc(invs->num_invs - num_dels + num_adds); + if (IS_ERR(new_invs)) + return new_invs; + + new =3D new_invs->inv; + for (i =3D j =3D 0; i !=3D invs->num_invs || j !=3D to_merge->num_invs;) { + int cmp =3D arm_smmu_invs_merge_cmp(invs, i, to_merge, j); + + if (cmp <=3D 0 && !refcount_read(&invs->inv[i].users)) { + i++; + continue; + } + + if (cmp < 0) { + *new =3D invs->inv[i]; + i++; + } else if (cmp =3D=3D 0) { + *new =3D invs->inv[i]; + refcount_inc(&new->users); + i++; + j++; + } else { + *new =3D to_merge->inv[j]; + refcount_set(&new->users, 1); + j++; + } + new++; + } + + WARN_ON(new !=3D new_invs->inv + new_invs->num_invs); + + return new_invs; +} +EXPORT_SYMBOL_IF_KUNIT(arm_smmu_invs_merge); + +/** + * arm_smmu_invs_unref() - Find in @invs for all entries in @to_unref, dec= rease + * the user counts without deletions + * @invs: the base invalidation array + * @to_unref: an array of invlidations to decrease their user counts + * + * Return: the number of trash entries in the array, for arm_smmu_invs_pur= ge() + * + * This function will not fail. Any entry with users=3D0 will be marked as= trash. + * All trash entries will remain in the @invs until being completely delet= ed by + * the next arm_smmu_invs_merge() or an arm_smmu_invs_purge() function cal= l. + * + * This function must be locked and serialized with arm_smmu_invs_merge() = and + * arm_smmu_invs_purge(), but do not lockdep on any lock for KUNIT test. + * + * Note that the @invs->num_invs will not be updated, even if the actual n= umber + * of invalidations are decreased. Readers should take the read lock to it= erate + * each entry and check its users counter until @inv->num_invs. + */ +VISIBLE_IF_KUNIT +size_t arm_smmu_invs_unref(struct arm_smmu_invs *invs, + struct arm_smmu_invs *to_unref) +{ + size_t num_dels =3D 0; + size_t i, j; + + for (i =3D j =3D 0; i !=3D invs->num_invs || j !=3D to_unref->num_invs;) { + int cmp; + + if (!refcount_read(&invs->inv[i].users)) { + num_dels++; + i++; + continue; + } + + cmp =3D arm_smmu_invs_merge_cmp(invs, i, to_unref, j); + if (cmp < 0) { + /* not found in to_unref, leave alone */ + i++; + } else if (cmp =3D=3D 0) { + /* same item */ + if (refcount_dec_and_test(&invs->inv[i].users)) + num_dels++; + i++; + j++; + } else { + /* item in to_unref is not in invs or already a trash */ + WARN_ON(true); + j++; + } + } + return num_dels; +} +EXPORT_SYMBOL_IF_KUNIT(arm_smmu_invs_unref); + +/** + * arm_smmu_invs_purge() - Purge all the trash entries in the @invs + * @invs: the base invalidation array + * @num_dels: expected number of trash entries, typically the return value= from + * a prior arm_smmu_invs_unref() call + * + * Return: a newly allocated array on success removing all the trash entri= es, or + * NULL on failure + * + * This function must be locked and serialized with arm_smmu_invs_merge() = and + * arm_smmu_invs_unref(), but do not lockdep on any lock for KUNIT test. + * + * Caller is resposible for freeing the @invs and the returned new one. + */ +VISIBLE_IF_KUNIT +struct arm_smmu_invs *arm_smmu_invs_purge(struct arm_smmu_invs *invs, + size_t num_dels) +{ + struct arm_smmu_invs *new_invs; + size_t i, j; + + if (WARN_ON(invs->num_invs < num_dels)) + return NULL; + + new_invs =3D arm_smmu_invs_alloc(invs->num_invs - num_dels); + if (IS_ERR(new_invs)) + return NULL; + + for (i =3D j =3D 0; i !=3D invs->num_invs; i++) { + if (!refcount_read(&invs->inv[i].users)) + continue; + new_invs->inv[j] =3D invs->inv[i]; + j++; + } + + WARN_ON(j !=3D new_invs->num_invs); + return new_invs; +} +EXPORT_SYMBOL_IF_KUNIT(arm_smmu_invs_purge); + /* * Based on the value of ent report which bits of the STE the HW will acce= ss. It * would be nice if this was complete according to the spec, but minimally= it @@ -2468,13 +2672,21 @@ static bool arm_smmu_enforce_cache_coherency(struct= iommu_domain *domain) struct arm_smmu_domain *arm_smmu_domain_alloc(void) { struct arm_smmu_domain *smmu_domain; + struct arm_smmu_invs *new_invs; =20 smmu_domain =3D kzalloc(sizeof(*smmu_domain), GFP_KERNEL); if (!smmu_domain) return ERR_PTR(-ENOMEM); =20 + new_invs =3D arm_smmu_invs_alloc(0); + if (IS_ERR(new_invs)) { + kfree(smmu_domain); + return ERR_CAST(new_invs); + } + INIT_LIST_HEAD(&smmu_domain->devices); spin_lock_init(&smmu_domain->devices_lock); + rcu_assign_pointer(smmu_domain->invs, new_invs); =20 return smmu_domain; } --=20 2.43.0 From nobody Wed Sep 10 01:53:18 2025 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2073.outbound.protection.outlook.com [40.107.223.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A6F33002C1 for ; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Sep 2025 23:28:57.2008 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b9ba50bc-eb57-4a8f-3ef0-08ddef2f7ba1 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000FCC3.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6001 Content-Type: text/plain; charset="utf-8" When a master is attached from an old domain to a new domain, it needs to build an invalidation array to delete and add the array entries from/onto the invalidation arrays of those two domains, passed via the to_merge and to_unref arguments into arm_smmu_invs_merge/unref() respectively. Since the master->num_streams might differ across masters, a memory would have to be allocated when building an to_merge/to_unref array which might fail with -ENOMEM. On the other hand, an attachment to arm_smmu_blocked_domain must not fail so it's the best to avoid any memory allocation in that path. Pre-allocate a fixed size invalidation array for every master. This array will be used as a scratch to fill dynamically when building a to_merge or to_unref invs array. Co-developed-by: Jason Gunthorpe Signed-off-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 8 +++++++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 26 +++++++++++++++++++++ 2 files changed, 34 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 34fcc1a930e6a..246c6d84de3ab 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -919,6 +919,14 @@ struct arm_smmu_master { struct arm_smmu_device *smmu; struct device *dev; struct arm_smmu_stream *streams; + /* + * Scratch memory for a to_merge or to_unref array to build a per-domain + * invalidation array. It'll be pre-allocated with enough enries for all + * possible build scenarios. It can be used by only one caller at a time + * until the arm_smmu_invs_merge/unref() finishes. Must be locked by the + * iommu_group mutex. + */ + struct arm_smmu_invs *build_invs; struct arm_smmu_vmaster *vmaster; /* use smmu->streams_mutex */ /* Locked by the iommu core using the group mutex */ struct arm_smmu_ctx_desc_cfg cd_table; diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 83d842bd88817..4e69c81f5a28b 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3663,12 +3663,22 @@ static int arm_smmu_init_sid_strtab(struct arm_smmu= _device *smmu, u32 sid) return 0; } =20 +static int arm_smmu_ids_cmp(const void *_l, const void *_r) +{ + const typeof_member(struct iommu_fwspec, ids[0]) *l =3D _l; + const typeof_member(struct iommu_fwspec, ids[0]) *r =3D _r; + + return cmp_int(*l, *r); +} + static int arm_smmu_insert_master(struct arm_smmu_device *smmu, struct arm_smmu_master *master) { int i; int ret =3D 0; struct iommu_fwspec *fwspec =3D dev_iommu_fwspec_get(master->dev); + bool ats_supported =3D dev_is_pci(master->dev) && + pci_ats_supported(to_pci_dev(master->dev)); =20 master->streams =3D kcalloc(fwspec->num_ids, sizeof(*master->streams), GFP_KERNEL); @@ -3676,6 +3686,20 @@ static int arm_smmu_insert_master(struct arm_smmu_de= vice *smmu, return -ENOMEM; master->num_streams =3D fwspec->num_ids; =20 + /* Base case has 1 ASID or 1~2 VMIDs. ATS case adds num_ids */ + if (!ats_supported) + master->build_invs =3D arm_smmu_invs_alloc(2); + else + master->build_invs =3D arm_smmu_invs_alloc(2 + fwspec->num_ids); + if (IS_ERR(master->build_invs)) { + kfree(master->streams); + return PTR_ERR(master->build_invs); + } + + /* Put the ids into order for a sorted to_merge or to_unref array */ + sort_nonatomic(fwspec->ids, fwspec->num_ids, sizeof(fwspec->ids[0]), + arm_smmu_ids_cmp, NULL); + mutex_lock(&smmu->streams_mutex); for (i =3D 0; i < fwspec->num_ids; i++) { struct arm_smmu_stream *new_stream =3D &master->streams[i]; @@ -3713,6 +3737,7 @@ static int arm_smmu_insert_master(struct arm_smmu_dev= ice *smmu, for (i--; i >=3D 0; i--) rb_erase(&master->streams[i].node, &smmu->streams); kfree(master->streams); + kfree(master->build_invs); } mutex_unlock(&smmu->streams_mutex); =20 @@ -3734,6 +3759,7 @@ static void arm_smmu_remove_master(struct arm_smmu_ma= ster *master) mutex_unlock(&smmu->streams_mutex); =20 kfree(master->streams); + kfree(master->build_invs); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Sep 2025 23:28:56.7378 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 69261b6a-eba4-48b3-9c13-08ddef2f7b4d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F2.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6329 Content-Type: text/plain; charset="utf-8" Update the invs array with the invalidations required by each domain type during attachment operations. Only an SVA domain or a paging domain will have an invs array: a. SVA domain will add an INV_TYPE_S1_ASID per SMMU and an INV_TYPE_ATS per SID b. Non-nesting-parent paging domain with no ATS-enabled master will add a single INV_TYPE_S1_ASID or INV_TYPE_S2_VMID per SMMU c. Non-nesting-parent paging domain with ATS-enabled master(s) will do (b) and add an INV_TYPE_ATS per SID d. Nesting-parent paging domain will add an INV_TYPE_S2_VMID followed by an INV_TYPE_S2_VMID_S1_CLEAR per vSMMU. For an ATS-enabled master, it will add an INV_TYPE_ATS_FULL per SID The per-domain invalidation is not needed, until the domain is attached to a master, i.e. a possible translation request. Giving this clears a way to allowing the domain to be attached to many SMMUs, and avoids any pointless invalidation overheads during a teardown if there are no STE/CDs referring to the domain. This also means, when the last device is detached, the old domain must flush its ASID or VMID because any iommu_unmap() call after it wouldn't initiate any invalidation given an empty domain invs array. Introduce some arm_smmu_invs helper functions for building scratch arrays, preparing and installing old/new domain's invalidation arrays. Co-developed-by: Jason Gunthorpe Signed-off-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 22 ++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 312 +++++++++++++++++++- 2 files changed, 332 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 246c6d84de3ab..e4e0e066108cc 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -678,6 +678,8 @@ struct arm_smmu_inv { /** * struct arm_smmu_invs - Per-domain invalidation array * @num_invs: number of invalidations in the flexible array + * @old: flag to synchronize with reader + * @rwlock: optional rwlock to fench ATS operations * @rcu: rcu head for kfree_rcu() * @inv: flexible invalidation array * @@ -703,6 +705,8 @@ struct arm_smmu_inv { */ struct arm_smmu_invs { size_t num_invs; + rwlock_t rwlock; + u8 old; struct rcu_head rcu; struct arm_smmu_inv inv[]; }; @@ -714,6 +718,7 @@ static inline struct arm_smmu_invs *arm_smmu_invs_alloc= (size_t num_invs) new_invs =3D kzalloc(struct_size(new_invs, inv, num_invs), GFP_KERNEL); if (!new_invs) return ERR_PTR(-ENOMEM); + rwlock_init(&new_invs->rwlock); new_invs->num_invs =3D num_invs; return new_invs; } @@ -1082,6 +1087,21 @@ static inline bool arm_smmu_master_canwbs(struct arm= _smmu_master *master) IOMMU_FWSPEC_PCI_RC_CANWBS; } =20 +/** + * struct arm_smmu_inv_state - Per-domain invalidation array state + * @invs_ptr: points to the domain->invs (unwinding nesting/etc.) or is NU= LL if + * no change should be made + * @old_invs: the original invs array + * @new_invs: for new domain, this is the new invs array to update domin->= invs; + * for old domain, this is the master->build_invs to pass in as= the + * to_unref argument to an arm_smmu_invs_unref() call + */ +struct arm_smmu_inv_state { + struct arm_smmu_invs **invs_ptr; + struct arm_smmu_invs *old_invs; + struct arm_smmu_invs *new_invs; +}; + struct arm_smmu_attach_state { /* Inputs */ struct iommu_domain *old_domain; @@ -1091,6 +1111,8 @@ struct arm_smmu_attach_state { ioasid_t ssid; /* Resulting state */ struct arm_smmu_vmaster *vmaster; + struct arm_smmu_inv_state old_domain_invst; + struct arm_smmu_inv_state new_domain_invst; bool ats_enabled; }; =20 diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 4e69c81f5a28b..ee779df1d78fb 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1183,8 +1183,11 @@ size_t arm_smmu_invs_unref(struct arm_smmu_invs *inv= s, i++; } else if (cmp =3D=3D 0) { /* same item */ - if (refcount_dec_and_test(&invs->inv[i].users)) + if (refcount_dec_and_test(&invs->inv[i].users)) { + /* Notify the caller about this deletion */ + refcount_set(&to_unref->inv[j].users, 1); num_dels++; + } i++; j++; } else { @@ -3028,6 +3031,97 @@ static void arm_smmu_disable_iopf(struct arm_smmu_ma= ster *master, iopf_queue_remove_device(master->smmu->evtq.iopf, master->dev); } =20 +/* + * Use the preallocated scratch array at master->build_invs, to build a to= _merge + * or to_unref array, to pass into a following arm_smmu_invs_merge/unref()= call. + * + * Do not free the returned invs array. It is reused, and will be overwrit= ten by + * the next arm_smmu_master_build_invs() call. + */ +static struct arm_smmu_invs * +arm_smmu_master_build_invs(struct arm_smmu_master *master, bool ats_enable= d, + ioasid_t ssid, struct arm_smmu_domain *smmu_domain) +{ + const bool e2h =3D master->smmu->features & ARM_SMMU_FEAT_E2H; + struct arm_smmu_invs *build_invs =3D master->build_invs; + const bool nesting =3D smmu_domain->nest_parent; + struct arm_smmu_inv *cur; + + iommu_group_mutex_assert(master->dev); + + cur =3D build_invs->inv; + + switch (smmu_domain->stage) { + case ARM_SMMU_DOMAIN_SVA: + case ARM_SMMU_DOMAIN_S1: + *cur =3D (struct arm_smmu_inv){ + .smmu =3D master->smmu, + .type =3D INV_TYPE_S1_ASID, + .id =3D smmu_domain->cd.asid, + .size_opcode =3D e2h ? CMDQ_OP_TLBI_EL2_VA : + CMDQ_OP_TLBI_NH_VA, + .nsize_opcode =3D e2h ? CMDQ_OP_TLBI_EL2_ASID : + CMDQ_OP_TLBI_NH_ASID + }; + break; + case ARM_SMMU_DOMAIN_S2: + *cur =3D (struct arm_smmu_inv){ + .smmu =3D master->smmu, + .type =3D INV_TYPE_S2_VMID, + .id =3D smmu_domain->s2_cfg.vmid, + .size_opcode =3D CMDQ_OP_TLBI_S2_IPA, + .nsize_opcode =3D CMDQ_OP_TLBI_S12_VMALL, + }; + break; + default: + WARN_ON(true); + return NULL; + } + + /* Range-based invalidation requires the leaf pgsize for calculation */ + if (master->smmu->features & ARM_SMMU_FEAT_RANGE_INV) + cur->pgsize =3D __ffs(smmu_domain->domain.pgsize_bitmap); + cur++; + + /* All the nested S1 ASIDs have to be flushed when S2 parent changes */ + if (nesting) { + *cur =3D (struct arm_smmu_inv){ + .smmu =3D master->smmu, + .type =3D INV_TYPE_S2_VMID_S1_CLEAR, + .id =3D smmu_domain->s2_cfg.vmid, + .size_opcode =3D CMDQ_OP_TLBI_NH_ALL, + .nsize_opcode =3D CMDQ_OP_TLBI_NH_ALL, + }; + cur++; + } + + if (ats_enabled) { + size_t i; + + for (i =3D 0; i < master->num_streams; i++) { + /* + * If an S2 used as a nesting parent is changed we have + * no option but to completely flush the ATC. + */ + *cur =3D (struct arm_smmu_inv){ + .smmu =3D master->smmu, + .type =3D nesting ? INV_TYPE_ATS_FULL : + INV_TYPE_ATS, + .id =3D master->streams[i].id, + .ssid =3D ssid, + .size_opcode =3D CMDQ_OP_ATC_INV, + .nsize_opcode =3D CMDQ_OP_ATC_INV, + }; + cur++; + } + } + + /* Note this build_invs must have been sorted */ + + build_invs->num_invs =3D cur - build_invs->inv; + return build_invs; +} + static void arm_smmu_remove_master_domain(struct arm_smmu_master *master, struct iommu_domain *domain, ioasid_t ssid) @@ -3057,6 +3151,211 @@ static void arm_smmu_remove_master_domain(struct ar= m_smmu_master *master, kfree(master_domain); } =20 +static inline void arm_smmu_invs_dbg(struct arm_smmu_master *master, + struct arm_smmu_domain *smmu_domain, + struct arm_smmu_invs *invs, char *name) +{ + size_t i; + + dev_dbg(master->dev, "domain (type: %x), invs: %s, num_invs: %ld\n", + smmu_domain->domain.type, name, invs->num_invs); + for (i =3D 0; i < invs->num_invs; i++) { + struct arm_smmu_inv *cur =3D &invs->inv[i]; + + dev_dbg(master->dev, + " entry: inv[%ld], type: %u, id: %u, users: %u\n", i, + cur->type, cur->id, refcount_read(&cur->users)); + } +} + +/* + * During attachment, the updates of the two domain->invs arrays are seque= nced: + * 1. new domain updates its invs array, merging master->build_invs + * 2. new domain starts to include the master during its invalidation + * 3. master updates its STE switching from the old domain to the new dom= ain + * 4. old domain still includes the master during its invalidation + * 5. old domain updates its invs array, unreferencing master->build_invs + * + * For 1 and 5, prepare the two updated arrays in advance, handling any ch= anges + * that can possibly failure. So the actual update of either 1 or 5 won't = fail. + * arm_smmu_asid_lock ensures that the old invs in the domains are intact = while + * we are sequencing to update them. + */ +static int arm_smmu_attach_prepare_invs(struct arm_smmu_attach_state *stat= e, + struct arm_smmu_domain *new_smmu_domain) +{ + struct arm_smmu_domain *old_smmu_domain =3D + to_smmu_domain_devices(state->old_domain); + struct arm_smmu_master *master =3D state->master; + ioasid_t ssid =3D state->ssid; + + /* A re-attach case doesn't need to update invs array */ + if (new_smmu_domain =3D=3D old_smmu_domain) + return 0; + + /* + * At this point a NULL domain indicates the domain doesn't use the + * IOTLB, see to_smmu_domain_devices(). + */ + if (new_smmu_domain) { + struct arm_smmu_inv_state *invst =3D &state->new_domain_invst; + struct arm_smmu_invs *build_invs; + + invst->invs_ptr =3D &new_smmu_domain->invs; + invst->old_invs =3D rcu_dereference_protected( + new_smmu_domain->invs, + lockdep_is_held(&arm_smmu_asid_lock)); + build_invs =3D arm_smmu_master_build_invs( + master, state->ats_enabled, ssid, new_smmu_domain); + if (!build_invs) + return -EINVAL; + + invst->new_invs =3D + arm_smmu_invs_merge(invst->old_invs, build_invs); + if (IS_ERR(invst->new_invs)) + return PTR_ERR(invst->new_invs); + + arm_smmu_invs_dbg(master, new_smmu_domain, invst->old_invs, + "new domain's old invs"); + arm_smmu_invs_dbg(master, new_smmu_domain, build_invs, "merge"); + arm_smmu_invs_dbg(master, new_smmu_domain, invst->new_invs, + "new domain's new invs"); + } + + if (old_smmu_domain) { + struct arm_smmu_inv_state *invst =3D &state->old_domain_invst; + + invst->invs_ptr =3D &old_smmu_domain->invs; + invst->old_invs =3D rcu_dereference_protected( + old_smmu_domain->invs, + lockdep_is_held(&arm_smmu_asid_lock)); + /* For old_smmu_domain, new_invs points to master->build_invs */ + invst->new_invs =3D arm_smmu_master_build_invs( + master, master->ats_enabled, ssid, old_smmu_domain); + } + + return 0; +} + +/* Must be installed before arm_smmu_install_ste_for_dev() */ +static void +arm_smmu_install_new_domain_invs(struct arm_smmu_attach_state *state) +{ + struct arm_smmu_inv_state *invst =3D &state->new_domain_invst; + + if (!invst->invs_ptr) + return; + + rcu_assign_pointer(*invst->invs_ptr, invst->new_invs); + /* + * Committed to updating the STE, using the new invalidation array, and + * acquiring any racing IOPTE updates. + */ + smp_mb(); + kfree_rcu(invst->old_invs, rcu); +} + +/* + * When an array entry's users count reaches zero, it means the ASID/VMID = is no + * longer being invalidated by map/unmap and must be cleaned. The rule is = that + * all ASIDs/VMIDs not in an invalidation array are left cleared in the IO= TLB. + */ +static void arm_smmu_invs_flush_iotlb_tags(struct arm_smmu_invs *invs) +{ + size_t i; + + for (i =3D 0; i !=3D invs->num_invs; i++) { + struct arm_smmu_inv *inv =3D &invs->inv[i]; + struct arm_smmu_cmdq_ent cmd =3D {}; + + /* arm_smmu_invs_unref() sets users if it was the last user */ + if (!refcount_read(&inv->users)) + continue; + + switch (inv->type) { + case INV_TYPE_S1_ASID: + cmd.tlbi.asid =3D inv->id; + break; + case INV_TYPE_S2_VMID: + /* S2_VMID using nsize_opcode covers S2_VMID_S1_CLEAR */ + cmd.tlbi.vmid =3D inv->id; + break; + default: + continue; + } + + cmd.opcode =3D inv->nsize_opcode; + arm_smmu_cmdq_issue_cmd_with_sync(inv->smmu, &cmd); + } +} + +/* Should be installed after arm_smmu_install_ste_for_dev() */ +static void +arm_smmu_install_old_domain_invs(struct arm_smmu_attach_state *state) +{ + struct arm_smmu_inv_state *invst =3D &state->old_domain_invst; + struct arm_smmu_domain *old_smmu_domain =3D + to_smmu_domain_devices(state->old_domain); + struct arm_smmu_invs *old_invs =3D invst->old_invs; + struct arm_smmu_master *master =3D state->master; + struct arm_smmu_invs *new_invs; + unsigned long flags; + size_t num_dels; + + lockdep_assert_held(&arm_smmu_asid_lock); + + if (!invst->invs_ptr) + return; + + arm_smmu_invs_dbg(master, old_smmu_domain, old_invs, + "old domain's old invs"); + arm_smmu_invs_dbg(master, old_smmu_domain, invst->new_invs, "unref"); + num_dels =3D arm_smmu_invs_unref(old_invs, invst->new_invs); + if (!num_dels) { + arm_smmu_invs_dbg(master, old_smmu_domain, old_invs, + "old domain's new invs"); + return; + } + + arm_smmu_invs_flush_iotlb_tags(invst->new_invs); + + new_invs =3D arm_smmu_invs_purge(old_invs, num_dels); + if (!new_invs) { + size_t new_num =3D old_invs->num_invs; + + /* + * OOM. Couldn't make a copy. Leave the array unoptimized. But + * trim its size if some tailing entries are marked as trash. + */ + while (new_num !=3D 0) { + if (refcount_read(&old_invs->inv[new_num - 1].users)) + break; + new_num--; + } + + arm_smmu_invs_dbg(master, old_smmu_domain, old_invs, + "old domain's new invs"); + + /* The lock is required to fence concurrent ATS operations. */ + write_lock_irqsave(&old_invs->rwlock, flags); + WRITE_ONCE(old_invs->num_invs, new_num); + write_unlock_irqrestore(&old_invs->rwlock, flags); + return; + } + + arm_smmu_invs_dbg(master, old_smmu_domain, new_invs, + "old domain's new invs"); + + /* new_invs is a copy, do the copy update part of RCU */ + rcu_assign_pointer(*invst->invs_ptr, new_invs); + /* Notify any concurrent invalidation to read the updated invs */ + write_lock_irqsave(&old_invs->rwlock, flags); + WRITE_ONCE(old_invs->old, true); + write_unlock_irqrestore(&old_invs->rwlock, flags); + + kfree_rcu(old_invs, rcu); +} + /* * Start the sequence to attach a domain to a master. The sequence contain= s three * steps: @@ -3114,12 +3413,16 @@ int arm_smmu_attach_prepare(struct arm_smmu_attach_= state *state, arm_smmu_ats_supported(master); } =20 + ret =3D arm_smmu_attach_prepare_invs(state, smmu_domain); + if (ret) + return ret; + if (smmu_domain) { if (new_domain->type =3D=3D IOMMU_DOMAIN_NESTED) { ret =3D arm_smmu_attach_prepare_vmaster( state, to_smmu_nested_domain(new_domain)); if (ret) - return ret; + goto err_unprepare_invs; } =20 master_domain =3D kzalloc(sizeof(*master_domain), GFP_KERNEL); @@ -3167,6 +3470,8 @@ int arm_smmu_attach_prepare(struct arm_smmu_attach_st= ate *state, atomic_inc(&smmu_domain->nr_ats_masters); list_add(&master_domain->devices_elm, &smmu_domain->devices); spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); + + arm_smmu_install_new_domain_invs(state); } =20 if (!state->ats_enabled && master->ats_enabled) { @@ -3186,6 +3491,8 @@ int arm_smmu_attach_prepare(struct arm_smmu_attach_st= ate *state, kfree(master_domain); err_free_vmaster: kfree(state->vmaster); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Sep 2025 23:28:59.1436 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 05395b6d-d05a-4b9d-05f5-08ddef2f7cc7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000FCC3.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6072 Content-Type: text/plain; charset="utf-8" Now, each smmu_domain is built with an invs array that keeps all the IDs (ASID/VMID) and its attached device SIDs, following the exact pattern of all the existing invalidation functions. Introduce a new arm_smmu_domain_inv helper iterating smmu_domain->invs, to convert the invalidation array to commands. Any invalidation request with no size specified means an entire flush over a range based one. ATC invalidations must be in sync with an attachment, espeically when it is an IOMMU_DOMAIN_BLOCKED that is used by the core for a device reset. Add a has_ats flag in the invs structure and hold the read lock if it is set, in which way a concurrent attachment will be blocked until any ATC invalidation being sent to the in the command queue is finished. Co-developed-by: Jason Gunthorpe Signed-off-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 16 ++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 225 ++++++++++++++++++-- 2 files changed, 228 insertions(+), 13 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index e4e0e066108cc..c73a94514c6d6 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -675,9 +675,15 @@ struct arm_smmu_inv { refcount_t users; /* users=3D0 to mark as a trash to be purged */ }; =20 +static inline bool arm_smmu_inv_is_ats(struct arm_smmu_inv *inv) +{ + return inv->type =3D=3D INV_TYPE_ATS || inv->type =3D=3D INV_TYPE_ATS_FUL= L; +} + /** * struct arm_smmu_invs - Per-domain invalidation array * @num_invs: number of invalidations in the flexible array + * @has_ats: flag if the array contains an INV_TYPE_ATS or INV_TYPE_ATS_FU= LL * @old: flag to synchronize with reader * @rwlock: optional rwlock to fench ATS operations * @rcu: rcu head for kfree_rcu() @@ -706,6 +712,7 @@ struct arm_smmu_inv { struct arm_smmu_invs { size_t num_invs; rwlock_t rwlock; + u8 has_ats; u8 old; struct rcu_head rcu; struct arm_smmu_inv inv[]; @@ -1072,6 +1079,15 @@ void arm_smmu_tlb_inv_range_asid(unsigned long iova,= size_t size, int asid, int arm_smmu_atc_inv_domain(struct arm_smmu_domain *smmu_domain, unsigned long iova, size_t size); =20 +void arm_smmu_domain_inv_range(struct arm_smmu_domain *smmu_domain, + unsigned long iova, size_t size, + unsigned int granule, bool leaf); + +static inline void arm_smmu_domain_inv(struct arm_smmu_domain *smmu_domain) +{ + arm_smmu_domain_inv_range(smmu_domain, 0, 0, 0, false); +} + void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, struct arm_smmu_cmdq *cmdq); int arm_smmu_init_one_queue(struct arm_smmu_device *smmu, diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index ee779df1d78fb..c06d2dd893c11 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2479,23 +2479,19 @@ static void arm_smmu_tlb_inv_context(void *cookie) arm_smmu_atc_inv_domain(smmu_domain, 0, 0); } =20 -static void __arm_smmu_tlb_inv_range(struct arm_smmu_cmdq_ent *cmd, - unsigned long iova, size_t size, - size_t granule, - struct arm_smmu_domain *smmu_domain) +static void arm_smmu_cmdq_batch_add_range(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq_batch *cmds, + struct arm_smmu_cmdq_ent *cmd, + unsigned long iova, size_t size, + size_t granule, size_t pgsize) { - struct arm_smmu_device *smmu =3D smmu_domain->smmu; - unsigned long end =3D iova + size, num_pages =3D 0, tg =3D 0; + unsigned long end =3D iova + size, num_pages =3D 0, tg =3D pgsize; size_t inv_range =3D granule; - struct arm_smmu_cmdq_batch cmds; =20 if (!size) return; =20 if (smmu->features & ARM_SMMU_FEAT_RANGE_INV) { - /* Get the leaf page size */ - tg =3D __ffs(smmu_domain->domain.pgsize_bitmap); - num_pages =3D size >> tg; =20 /* Convert page size of 12,14,16 (log2) to 1,2,3 */ @@ -2515,8 +2511,6 @@ static void __arm_smmu_tlb_inv_range(struct arm_smmu_= cmdq_ent *cmd, num_pages++; } =20 - arm_smmu_cmdq_batch_init(smmu, &cmds, cmd); - while (iova < end) { if (smmu->features & ARM_SMMU_FEAT_RANGE_INV) { /* @@ -2544,9 +2538,26 @@ static void __arm_smmu_tlb_inv_range(struct arm_smmu= _cmdq_ent *cmd, } =20 cmd->tlbi.addr =3D iova; - arm_smmu_cmdq_batch_add(smmu, &cmds, cmd); + arm_smmu_cmdq_batch_add(smmu, cmds, cmd); iova +=3D inv_range; } +} + +static void __arm_smmu_tlb_inv_range(struct arm_smmu_cmdq_ent *cmd, + unsigned long iova, size_t size, + size_t granule, + struct arm_smmu_domain *smmu_domain) +{ + struct arm_smmu_device *smmu =3D smmu_domain->smmu; + struct arm_smmu_cmdq_batch cmds; + size_t pgsize; + + /* Get the leaf page size */ + pgsize =3D __ffs(smmu_domain->domain.pgsize_bitmap); + + arm_smmu_cmdq_batch_init(smmu, &cmds, cmd); + arm_smmu_cmdq_batch_add_range(smmu, &cmds, cmd, iova, size, granule, + pgsize); arm_smmu_cmdq_batch_submit(smmu, &cmds); } =20 @@ -2602,6 +2613,194 @@ void arm_smmu_tlb_inv_range_asid(unsigned long iova= , size_t size, int asid, __arm_smmu_tlb_inv_range(&cmd, iova, size, granule, smmu_domain); } =20 +static bool arm_smmu_inv_size_too_big(struct arm_smmu_device *smmu, size_t= size, + size_t granule) +{ + size_t max_tlbi_ops; + + /* 0 size means invalidate all */ + if (!size || size =3D=3D SIZE_MAX) + return true; + + if (smmu->features & ARM_SMMU_FEAT_RANGE_INV) + return false; + + /* + * Borrowed from the MAX_TLBI_OPS in arch/arm64/include/asm/tlbflush.h, + * this is used as a threshold to replace "size_opcode" commands with a + * single "nsize_opcode" command, when SMMU doesn't implement the range + * invalidation feature, where there can be too many per-granule TLBIs, + * resulting in a soft lockup. + */ + max_tlbi_ops =3D 1 << (ilog2(granule) - 3); + return size >=3D max_tlbi_ops * granule; +} + +/* Used by non INV_TYPE_ATS* invalidations */ +static void arm_smmu_inv_to_cmdq_batch(struct arm_smmu_inv *inv, + struct arm_smmu_cmdq_batch *cmds, + struct arm_smmu_cmdq_ent *cmd, + unsigned long iova, size_t size, + unsigned int granule) +{ + if (arm_smmu_inv_size_too_big(inv->smmu, size, granule)) { + cmd->opcode =3D inv->nsize_opcode; + /* nsize_opcode always needs a sync, no batching */ + arm_smmu_cmdq_issue_cmd_with_sync(inv->smmu, cmd); + return; + } + + cmd->opcode =3D inv->size_opcode; + arm_smmu_cmdq_batch_add_range(inv->smmu, cmds, cmd, iova, size, granule, + inv->pgsize); +} + +static inline bool arm_smmu_invs_end_batch(struct arm_smmu_inv *cur, + struct arm_smmu_inv *next) +{ + /* Changing smmu means changing command queue */ + if (cur->smmu !=3D next->smmu) + return true; + /* The batch for S2 TLBI must be done before nested S1 ASIDs */ + if (cur->type !=3D INV_TYPE_S2_VMID_S1_CLEAR && + next->type =3D=3D INV_TYPE_S2_VMID_S1_CLEAR) + return true; + /* ATS must be after a sync of the S1/S2 invalidations */ + if (!arm_smmu_inv_is_ats(cur) && arm_smmu_inv_is_ats(next)) + return true; + return false; +} + +void arm_smmu_domain_inv_range(struct arm_smmu_domain *smmu_domain, + unsigned long iova, size_t size, + unsigned int granule, bool leaf) +{ + struct arm_smmu_cmdq_batch cmds =3D {}; + struct arm_smmu_invs *invs; + struct arm_smmu_inv *cur; + struct arm_smmu_inv *end; + bool locked; + + /* + * An invalidation request must follow some IOPTE change and then load + * an invalidation array. In the meantime, a domain attachment mutates + * the array and then stores an STE/CD asking SMMU HW to acquire those + * changed IOPTEs. In other word, these two are interdependent and can + * race. + * + * In a race, the RCU design (with its underlying memory barriers) can + * ensure the invalidation array to always get updated before loaded. + * + * smp_mb() is used here, paired with the smp_mb() following the array + * update in a concurrent attach, to ensure: + * - HW sees the new IOPTEs if it walks after STE installation + * - Invalidation thread sees the updated array with the new ASID. + * + * [CPU0] | [CPU1] + * | + * change IOPTEs and TLB flush: | + * arm_smmu_domain_inv_range() { | arm_smmu_install_new_domain_invs { + * ... | rcu_assign_pointer(new_invs); + * smp_mb(); // ensure IOPTEs | smp_mb(); // ensure new_invs + * ... | kfree_rcu(old_invs, rcu); + * // load invalidation array | } + * invs =3D rcu_dereference(); | arm_smmu_install_ste_for_dev { + * | STE =3D TTB0 // read new IOPTEs + */ + smp_mb(); + + rcu_read_lock(); + + while (true) { + invs =3D rcu_dereference(smmu_domain->invs); + + /* + * Avoid locking unless ATS is being used. No ATS invalidate can + * be going on after a domain is detached. + */ + locked =3D false; + if (invs->has_ats || READ_ONCE(invs->old)) { + read_lock(&invs->rwlock); + if (invs->old) { + read_unlock(&invs->rwlock); + continue; + } + locked =3D true; + } + break; + } + + cur =3D invs->inv; + end =3D cur + READ_ONCE(invs->num_invs); + /* Skip any leading entry marked as a trash */ + for (; cur !=3D end; cur++) + if (refcount_read(&cur->users)) + break; + while (cur !=3D end) { + struct arm_smmu_device *smmu =3D cur->smmu; + struct arm_smmu_cmdq_ent cmd =3D { + /* + * Pick size_opcode to run arm_smmu_get_cmdq(). This can + * be changed to nsize_opcode, which would result in the + * same CMDQ pointer. + */ + .opcode =3D cur->size_opcode, + }; + struct arm_smmu_inv *next; + + if (!cmds.num) + arm_smmu_cmdq_batch_init(smmu, &cmds, &cmd); + + switch (cur->type) { + case INV_TYPE_S1_ASID: + cmd.tlbi.asid =3D cur->id; + cmd.tlbi.leaf =3D leaf; + arm_smmu_inv_to_cmdq_batch(cur, &cmds, &cmd, iova, size, + granule); + break; + case INV_TYPE_S2_VMID: + cmd.tlbi.vmid =3D cur->id; + cmd.tlbi.leaf =3D leaf; + arm_smmu_inv_to_cmdq_batch(cur, &cmds, &cmd, iova, size, + granule); + break; + case INV_TYPE_S2_VMID_S1_CLEAR: + /* CMDQ_OP_TLBI_S12_VMALL already flushed S1 entries */ + if (arm_smmu_inv_size_too_big(cur->smmu, size, granule)) + continue; + cmd.tlbi.vmid =3D cur->id; + arm_smmu_cmdq_batch_add(smmu, &cmds, &cmd); + break; + case INV_TYPE_ATS: + arm_smmu_atc_inv_to_cmd(cur->ssid, iova, size, &cmd); + cmd.atc.sid =3D cur->id; + arm_smmu_cmdq_batch_add(smmu, &cmds, &cmd); + break; + case INV_TYPE_ATS_FULL: + arm_smmu_atc_inv_to_cmd(IOMMU_NO_PASID, 0, 0, &cmd); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Sep 2025 23:28:58.9032 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f0abe3de-21fe-4268-e767-08ddef2f7c96 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F2.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9144 Content-Type: text/plain; charset="utf-8" Replace the old invalidation functions with arm_smmu_domain_inv_range() in all the existing invalidation routines. And deprecate the old functions. The new arm_smmu_domain_inv_range() handles the CMDQ_MAX_TLBI_OPS as well, so drop it in the SVA function. Since arm_smmu_cmdq_batch_add_range() has only one caller now, and it must be given a valid size, add a WARN_ON_ONCE to catch any missed case. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 7 - .../iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 29 +-- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 165 +----------------- 3 files changed, 11 insertions(+), 190 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index c73a94514c6d6..e9f97301ded31 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -1072,13 +1072,6 @@ int arm_smmu_set_pasid(struct arm_smmu_master *maste= r, struct arm_smmu_domain *smmu_domain, ioasid_t pasid, struct arm_smmu_cd *cd, struct iommu_domain *old); =20 -void arm_smmu_tlb_inv_asid(struct arm_smmu_device *smmu, u16 asid); -void arm_smmu_tlb_inv_range_asid(unsigned long iova, size_t size, int asid, - size_t granule, bool leaf, - struct arm_smmu_domain *smmu_domain); -int arm_smmu_atc_inv_domain(struct arm_smmu_domain *smmu_domain, - unsigned long iova, size_t size); - void arm_smmu_domain_inv_range(struct arm_smmu_domain *smmu_domain, unsigned long iova, size_t size, unsigned int granule, bool leaf); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iomm= u/arm/arm-smmu-v3/arm-smmu-v3-sva.c index fc601b494e0af..048b53f79b144 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c @@ -122,15 +122,6 @@ void arm_smmu_make_sva_cd(struct arm_smmu_cd *target, } EXPORT_SYMBOL_IF_KUNIT(arm_smmu_make_sva_cd); =20 -/* - * Cloned from the MAX_TLBI_OPS in arch/arm64/include/asm/tlbflush.h, this - * is used as a threshold to replace per-page TLBI commands to issue in the - * command queue with an address-space TLBI command, when SMMU w/o a range - * invalidation feature handles too many per-page TLBI commands, which will - * otherwise result in a soft lockup. - */ -#define CMDQ_MAX_TLBI_OPS (1 << (PAGE_SHIFT - 3)) - static void arm_smmu_mm_arch_invalidate_secondary_tlbs(struct mmu_notifier= *mn, struct mm_struct *mm, unsigned long start, @@ -146,21 +137,8 @@ static void arm_smmu_mm_arch_invalidate_secondary_tlbs= (struct mmu_notifier *mn, * range. So do a simple translation here by calculating size correctly. */ size =3D end - start; - if (!(smmu_domain->smmu->features & ARM_SMMU_FEAT_RANGE_INV)) { - if (size >=3D CMDQ_MAX_TLBI_OPS * PAGE_SIZE) - size =3D 0; - } else { - if (size =3D=3D ULONG_MAX) - size =3D 0; - } - - if (!size) - arm_smmu_tlb_inv_asid(smmu_domain->smmu, smmu_domain->cd.asid); - else - arm_smmu_tlb_inv_range_asid(start, size, smmu_domain->cd.asid, - PAGE_SIZE, false, smmu_domain); =20 - arm_smmu_atc_inv_domain(smmu_domain, start, size); + arm_smmu_domain_inv_range(smmu_domain, start, size, PAGE_SIZE, false); } =20 static void arm_smmu_mm_release(struct mmu_notifier *mn, struct mm_struct = *mm) @@ -191,8 +169,7 @@ static void arm_smmu_mm_release(struct mmu_notifier *mn= , struct mm_struct *mm) } spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); =20 - arm_smmu_tlb_inv_asid(smmu_domain->smmu, smmu_domain->cd.asid); - arm_smmu_atc_inv_domain(smmu_domain, 0, 0); + arm_smmu_domain_inv(smmu_domain); } =20 static void arm_smmu_mmu_notifier_free(struct mmu_notifier *mn) @@ -301,7 +278,7 @@ static void arm_smmu_sva_domain_free(struct iommu_domai= n *domain) /* * Ensure the ASID is empty in the iommu cache before allowing reuse. */ - arm_smmu_tlb_inv_asid(smmu_domain->smmu, smmu_domain->cd.asid); + arm_smmu_domain_inv(smmu_domain); =20 /* * Notice that the arm_smmu_mm_arch_invalidate_secondary_tlbs op can diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index c06d2dd893c11..4d8b1230f8bb9 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1023,16 +1023,6 @@ static void arm_smmu_page_response(struct device *de= v, struct iopf_fault *unused } =20 /* Context descriptor manipulation functions */ -void arm_smmu_tlb_inv_asid(struct arm_smmu_device *smmu, u16 asid) -{ - struct arm_smmu_cmdq_ent cmd =3D { - .opcode =3D smmu->features & ARM_SMMU_FEAT_E2H ? - CMDQ_OP_TLBI_EL2_ASID : CMDQ_OP_TLBI_NH_ASID, - .tlbi.asid =3D asid, - }; - - arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); -} =20 static int arm_smmu_invs_cmp(const void *_l, const void *_r) { @@ -2393,74 +2383,10 @@ static int arm_smmu_atc_inv_master(struct arm_smmu_= master *master, return arm_smmu_cmdq_batch_submit(master->smmu, &cmds); } =20 -int arm_smmu_atc_inv_domain(struct arm_smmu_domain *smmu_domain, - unsigned long iova, size_t size) -{ - struct arm_smmu_master_domain *master_domain; - int i; - unsigned long flags; - struct arm_smmu_cmdq_ent cmd =3D { - .opcode =3D CMDQ_OP_ATC_INV, - }; - struct arm_smmu_cmdq_batch cmds; - - if (!(smmu_domain->smmu->features & ARM_SMMU_FEAT_ATS)) - return 0; - - /* - * Ensure that we've completed prior invalidation of the main TLBs - * before we read 'nr_ats_masters' in case of a concurrent call to - * arm_smmu_enable_ats(): - * - * // unmap() // arm_smmu_enable_ats() - * TLBI+SYNC atomic_inc(&nr_ats_masters); - * smp_mb(); [...] - * atomic_read(&nr_ats_masters); pci_enable_ats() // writel() - * - * Ensures that we always see the incremented 'nr_ats_masters' count if - * ATS was enabled at the PCI device before completion of the TLBI. - */ - smp_mb(); - if (!atomic_read(&smmu_domain->nr_ats_masters)) - return 0; - - arm_smmu_cmdq_batch_init(smmu_domain->smmu, &cmds, &cmd); - - spin_lock_irqsave(&smmu_domain->devices_lock, flags); - list_for_each_entry(master_domain, &smmu_domain->devices, - devices_elm) { - struct arm_smmu_master *master =3D master_domain->master; - - if (!master->ats_enabled) - continue; - - if (master_domain->nested_ats_flush) { - /* - * If a S2 used as a nesting parent is changed we have - * no option but to completely flush the ATC. - */ - arm_smmu_atc_inv_to_cmd(IOMMU_NO_PASID, 0, 0, &cmd); - } else { - arm_smmu_atc_inv_to_cmd(master_domain->ssid, iova, size, - &cmd); - } - - for (i =3D 0; i < master->num_streams; i++) { - cmd.atc.sid =3D master->streams[i].id; - arm_smmu_cmdq_batch_add(smmu_domain->smmu, &cmds, &cmd); - } - } - spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); - - return arm_smmu_cmdq_batch_submit(smmu_domain->smmu, &cmds); -} - /* IO_PGTABLE API */ static void arm_smmu_tlb_inv_context(void *cookie) { struct arm_smmu_domain *smmu_domain =3D cookie; - struct arm_smmu_device *smmu =3D smmu_domain->smmu; - struct arm_smmu_cmdq_ent cmd; =20 /* * NOTE: when io-pgtable is in non-strict mode, we may get here with @@ -2469,14 +2395,7 @@ static void arm_smmu_tlb_inv_context(void *cookie) * insertion to guarantee those are observed before the TLBI. Do be * careful, 007. */ - if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1) { - arm_smmu_tlb_inv_asid(smmu, smmu_domain->cd.asid); - } else { - cmd.opcode =3D CMDQ_OP_TLBI_S12_VMALL; - cmd.tlbi.vmid =3D smmu_domain->s2_cfg.vmid; - arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); - } - arm_smmu_atc_inv_domain(smmu_domain, 0, 0); + arm_smmu_domain_inv(smmu_domain); } =20 static void arm_smmu_cmdq_batch_add_range(struct arm_smmu_device *smmu, @@ -2488,7 +2407,7 @@ static void arm_smmu_cmdq_batch_add_range(struct arm_= smmu_device *smmu, unsigned long end =3D iova + size, num_pages =3D 0, tg =3D pgsize; size_t inv_range =3D granule; =20 - if (!size) + if (WARN_ON_ONCE(!size)) return; =20 if (smmu->features & ARM_SMMU_FEAT_RANGE_INV) { @@ -2543,76 +2462,6 @@ static void arm_smmu_cmdq_batch_add_range(struct arm= _smmu_device *smmu, } } =20 -static void __arm_smmu_tlb_inv_range(struct arm_smmu_cmdq_ent *cmd, - unsigned long iova, size_t size, - size_t granule, - struct arm_smmu_domain *smmu_domain) -{ - struct arm_smmu_device *smmu =3D smmu_domain->smmu; - struct arm_smmu_cmdq_batch cmds; - size_t pgsize; - - /* Get the leaf page size */ - pgsize =3D __ffs(smmu_domain->domain.pgsize_bitmap); - - arm_smmu_cmdq_batch_init(smmu, &cmds, cmd); - arm_smmu_cmdq_batch_add_range(smmu, &cmds, cmd, iova, size, granule, - pgsize); - arm_smmu_cmdq_batch_submit(smmu, &cmds); -} - -static void arm_smmu_tlb_inv_range_domain(unsigned long iova, size_t size, - size_t granule, bool leaf, - struct arm_smmu_domain *smmu_domain) -{ - struct arm_smmu_cmdq_ent cmd =3D { - .tlbi =3D { - .leaf =3D leaf, - }, - }; - - if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1) { - cmd.opcode =3D smmu_domain->smmu->features & ARM_SMMU_FEAT_E2H ? - CMDQ_OP_TLBI_EL2_VA : CMDQ_OP_TLBI_NH_VA; - cmd.tlbi.asid =3D smmu_domain->cd.asid; - } else { - cmd.opcode =3D CMDQ_OP_TLBI_S2_IPA; - cmd.tlbi.vmid =3D smmu_domain->s2_cfg.vmid; - } - __arm_smmu_tlb_inv_range(&cmd, iova, size, granule, smmu_domain); - - if (smmu_domain->nest_parent) { - /* - * When the S2 domain changes all the nested S1 ASIDs have to be - * flushed too. - */ - cmd.opcode =3D CMDQ_OP_TLBI_NH_ALL; - arm_smmu_cmdq_issue_cmd_with_sync(smmu_domain->smmu, &cmd); - } - - /* - * Unfortunately, this can't be leaf-only since we may have - * zapped an entire table. - */ - arm_smmu_atc_inv_domain(smmu_domain, iova, size); -} - -void arm_smmu_tlb_inv_range_asid(unsigned long iova, size_t size, int asid, - size_t granule, bool leaf, - struct arm_smmu_domain *smmu_domain) -{ - struct arm_smmu_cmdq_ent cmd =3D { - .opcode =3D smmu_domain->smmu->features & ARM_SMMU_FEAT_E2H ? - CMDQ_OP_TLBI_EL2_VA : CMDQ_OP_TLBI_NH_VA, - .tlbi =3D { - .asid =3D asid, - .leaf =3D leaf, - }, - }; - - __arm_smmu_tlb_inv_range(&cmd, iova, size, granule, smmu_domain); -} - static bool arm_smmu_inv_size_too_big(struct arm_smmu_device *smmu, size_t= size, size_t granule) { @@ -2814,7 +2663,9 @@ static void arm_smmu_tlb_inv_page_nosync(struct iommu= _iotlb_gather *gather, static void arm_smmu_tlb_inv_walk(unsigned long iova, size_t size, size_t granule, void *cookie) { - arm_smmu_tlb_inv_range_domain(iova, size, granule, false, cookie); + struct arm_smmu_domain *smmu_domain =3D cookie; + + arm_smmu_domain_inv_range(smmu_domain, iova, size, granule, false); } =20 static const struct iommu_flush_ops arm_smmu_flush_ops =3D { @@ -4123,9 +3974,9 @@ static void arm_smmu_iotlb_sync(struct iommu_domain *= domain, if (!gather->pgsize) return; =20 - arm_smmu_tlb_inv_range_domain(gather->start, - gather->end - gather->start + 1, - gather->pgsize, true, smmu_domain); + arm_smmu_domain_inv_range(smmu_domain, gather->start, + gather->end - gather->start + 1, + gather->pgsize, true); } =20 static phys_addr_t --=20 2.43.0