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X-Envelope-From: akhilesh@ee.iitb.ac.in X-Qmail-Scanner-Mime-Attachments: | X-Qmail-Scanner-Zip-Files: | Received: from unknown (HELO ldns2.iitb.ac.in) (10.200.1.25) by ldns2.iitb.ac.in with SMTP; 3 Sep 2025 19:55:38 +0530 Received: from bhairav.ee.iitb.ac.in (bhairav.ee.iitb.ac.in [10.107.1.1]) by ldns2.iitb.ac.in (Postfix) with ESMTP id 063553414E2; Wed, 3 Sep 2025 19:55:38 +0530 (IST) Received: from bhairav-test.ee.iitb.ac.in (bhairav.ee.iitb.ac.in [10.107.1.1]) (Authenticated sender: akhilesh) by bhairav.ee.iitb.ac.in (Postfix) with ESMTPSA id A39901E8143E; Wed, 3 Sep 2025 19:55:37 +0530 (IST) Date: Wed, 3 Sep 2025 19:55:32 +0530 From: Akhilesh Patil To: alexandre.belloni@bootlin.com, krzk+dt@kernel.org, robh@kernel.org, conor+dt@kernel.org Cc: skhan@linuxfoundation.org, linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, akhileshpatilvnit@gmail.com Subject: [PATCH 1/7] rtc: m41t93: add device tree support Message-ID: <18ee1fef01b9f09c250f29207ec02f22b55b935d.1756908788.git.akhilesh@ee.iitb.ac.in> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device tree support for m41t93 rtc by adding of_match_table. Define compatible string - "st,m41t93" which can be used to instantiate this rtc device via DT node. Signed-off-by: Akhilesh Patil --- drivers/rtc/rtc-m41t93.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/rtc/rtc-m41t93.c b/drivers/rtc/rtc-m41t93.c index 9444cb5f5190..4e803ff0ce49 100644 --- a/drivers/rtc/rtc-m41t93.c +++ b/drivers/rtc/rtc-m41t93.c @@ -191,9 +191,16 @@ static int m41t93_probe(struct spi_device *spi) return 0; } =20 +static const struct of_device_id m41t93_dt_match[] =3D { + { .compatible =3D "st,m41t93" }, + { } +}; +MODULE_DEVICE_TABLE(of, m41t93_dt_match); + static struct spi_driver m41t93_driver =3D { .driver =3D { .name =3D "rtc-m41t93", + .of_match_table =3D m41t93_dt_match, }, .probe =3D m41t93_probe, }; --=20 2.34.1 From nobody Fri Oct 3 07:39:26 2025 Received: from smtp1.iitb.ac.in (smtpd9.iitb.ac.in [103.21.126.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 93473309DD8 for ; Wed, 3 Sep 2025 14:26:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=103.21.126.64 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756909573; cv=none; b=lfQ1MZEXNiGQyu/vJMBDwHAsLvu6TaxS+9M45zkvrqQX4x/cn5la0vSCDLy1ha+c6csBtsedYulCyvVBQY/1lRcwA+ZKgiP9LRjjxHE9UCv0VRHAeMvG9ZM8mtRXQj5EQTfGsPXlKY+4Y8qYnF/DDMW4vf+OWnxoBZF+6MoAj9E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756909573; c=relaxed/simple; bh=6Wnau2pwGtxpVXRdBkXsDWUXrJJ2EY1XKsnS4Zus4zs=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=GmJHbdFmS1ahE+9Y9Tl/YKo6z3WaZHT6bnoORYUj6BrgFek4cRPNY/8JL4abIzwB8FUeXBL2r9xnS+S8SjKLcMTjK72Mb/QlWirzDPA+lzh5mtSLnSnlZNyL4uqXwn2C9qw1HAeuELy9Rrk/Xs92MTe99iXE1u4xAqfQU18/LHs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=ee.iitb.ac.in; spf=pass smtp.mailfrom=ee.iitb.ac.in; dkim=pass (1024-bit key) header.d=iitb.ac.in header.i=@iitb.ac.in header.b=m1eVFLS+; arc=none smtp.client-ip=103.21.126.64 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=ee.iitb.ac.in Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ee.iitb.ac.in Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=iitb.ac.in header.i=@iitb.ac.in header.b="m1eVFLS+" Received: from ldns1.iitb.ac.in (ldns1.iitb.ac.in [10.200.12.1]) by smtp1.iitb.ac.in (Postfix) with SMTP id 33C431015C6C for ; Wed, 3 Sep 2025 19:56:09 +0530 (IST) DKIM-Filter: OpenDKIM Filter v2.11.0 smtp1.iitb.ac.in 33C431015C6C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=iitb.ac.in; s=mail; t=1756909569; bh=6Wnau2pwGtxpVXRdBkXsDWUXrJJ2EY1XKsnS4Zus4zs=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=m1eVFLS+GZhvGtAN0wPQPJhqoRvTHPkcA72jiycXg0aCYcAKZCJ7yNCoPiBLdlZzo sb0CZtOVJ2e5KQ/J7GwWiOYzJfdJmekrB/DdN5FEu3+rDIHOJ2xV1BDnb4LPz66sED 5S1owh3+4N/ZgPyrlHih/OtI3lfJ7GRBwhVQVlnU= Received: (qmail 21233 invoked by uid 510); 3 Sep 2025 19:56:09 +0530 X-Qmail-Scanner-Diagnostics: from 10.200.1.25 by ldns1 (envelope-from , uid 501) with qmail-scanner-2.11 spamassassin: 3.4.1. mhr: 1.0. {clamdscan: 0.101.4/26439} Clear:RC:1(10.200.1.25):SA:0(0.0/7.0):. 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X-Envelope-From: akhilesh@ee.iitb.ac.in X-Qmail-Scanner-Mime-Attachments: | X-Qmail-Scanner-Zip-Files: | Received: from unknown (HELO ldns1.iitb.ac.in) (10.200.1.25) by ldns1.iitb.ac.in with SMTP; 3 Sep 2025 19:56:05 +0530 Received: from bhairav.ee.iitb.ac.in (bhairav.ee.iitb.ac.in [10.107.1.1]) by ldns1.iitb.ac.in (Postfix) with ESMTP id 40126360036; Wed, 3 Sep 2025 19:56:05 +0530 (IST) Received: from bhairav-test.ee.iitb.ac.in (bhairav.ee.iitb.ac.in [10.107.1.1]) (Authenticated sender: akhilesh) by bhairav.ee.iitb.ac.in (Postfix) with ESMTPSA id 0EA8B1E8143E; Wed, 3 Sep 2025 19:56:05 +0530 (IST) Date: Wed, 3 Sep 2025 19:55:59 +0530 From: Akhilesh Patil To: alexandre.belloni@bootlin.com, krzk+dt@kernel.org, robh@kernel.org, conor+dt@kernel.org Cc: skhan@linuxfoundation.org, linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, akhileshpatilvnit@gmail.com Subject: [PATCH 2/7] dt-bindings: rtc: add bindings for m41t93 Message-ID: <40c91cbb07140ecdf4f91afc118c2518e85041c3.1756908788.git.akhilesh@ee.iitb.ac.in> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" add DT bindings for m41t93 rtc in YAML format. Signed-off-by: Akhilesh Patil --- .../devicetree/bindings/rtc/st,m41t93.yaml | 43 +++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 Documentation/devicetree/bindings/rtc/st,m41t93.yaml diff --git a/Documentation/devicetree/bindings/rtc/st,m41t93.yaml b/Documen= tation/devicetree/bindings/rtc/st,m41t93.yaml new file mode 100644 index 000000000000..03673adc79db --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/st,m41t93.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/st,m41t93.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ST M41T93 RTC and compatible + +maintainers: + - Alexandre Belloni + +properties: + compatible: + enum: + - st,m41t93 + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + +allOf: + - $ref: rtc.yaml + +unevaluatedProperties: false + +required: + - compatible + - reg + +examples: + - | + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + rtc@0 { + spi-max-frequency =3D <2000000>; + compatible =3D "st,m41t93"; + reg =3D <0>; + }; + }; + --=20 2.34.1 From nobody Fri Oct 3 07:39:26 2025 Received: from smtp1.iitb.ac.in (smtpd9.iitb.ac.in [103.21.126.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DA6742874F8 for ; Wed, 3 Sep 2025 14:26:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=103.21.126.64 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756909603; cv=none; b=AevCWuIQ1btLg2uMrq5SR9E3UnAgu67G0ouFWn7qkZ0c0Xh3pNc8Fjhh/plkytgrW3vTkdB2LuJNbW1Z1wn9ssq6nhpv2q204wTF25crpGyHlqEgTFO15wEvThipwkAayBMr4DF73N8LhbY/iyBm8aCDIHzPVpuNvAjgT+rIemw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756909603; c=relaxed/simple; bh=lBULx7uqbmscImIjfEPqSce/EEelZHFj7L5TbmJLI7s=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=bqrdzwRBsmBzE28ZwbaUQyVqpr9A98jy37O2sNEY6ExtZHW/+JkW+5fZR6K1WuC8wfzcfZWpEEXE8IuZCnQFWZAPKzFoseMvxFbkmp9tY5t1zsWTGbRnTeTGBQHoSi3wlh7cjgeVD0zGhwm/fc36ffi8GFjFH4WAlqHs56C9awQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=ee.iitb.ac.in; spf=pass smtp.mailfrom=ee.iitb.ac.in; dkim=pass (1024-bit key) header.d=iitb.ac.in header.i=@iitb.ac.in header.b=pwiXAK4Z; arc=none smtp.client-ip=103.21.126.64 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=ee.iitb.ac.in Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ee.iitb.ac.in Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=iitb.ac.in header.i=@iitb.ac.in header.b="pwiXAK4Z" Received: from ldns2.iitb.ac.in (ldns2.iitb.ac.in [10.200.12.2]) by smtp1.iitb.ac.in (Postfix) with SMTP id 96679101C6DE for ; Wed, 3 Sep 2025 19:56:38 +0530 (IST) DKIM-Filter: OpenDKIM Filter v2.11.0 smtp1.iitb.ac.in 96679101C6DE DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=iitb.ac.in; s=mail; t=1756909598; bh=lBULx7uqbmscImIjfEPqSce/EEelZHFj7L5TbmJLI7s=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=pwiXAK4Z+bo8FTa3VFj5nIu+M86YvkXgvfT9TWyT3L8mi7XiG5Y4P8YpbiJOr0b50 vurRH0+t50pTlILOQzRkpNKzqLfZPjornCtQop7FjB+cDioaxBuSpoc5oUNsVw9IZ7 PCPmeuHHPR+DG5M7kYPqKE0O0I7W666qhLS91WZo= Received: (qmail 32297 invoked by uid 510); 3 Sep 2025 19:56:38 +0530 X-Qmail-Scanner-Diagnostics: from 10.200.1.25 by ldns2 (envelope-from , uid 501) with qmail-scanner-2.11 spamassassin: 3.4.1. mhr: 1.0. {clamdscan: 0.100.0/26337} Clear:RC:1(10.200.1.25):SA:0(0.0/7.0):. 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X-Envelope-From: akhilesh@ee.iitb.ac.in X-Qmail-Scanner-Mime-Attachments: | X-Qmail-Scanner-Zip-Files: | Received: from unknown (HELO ldns2.iitb.ac.in) (10.200.1.25) by ldns2.iitb.ac.in with SMTP; 3 Sep 2025 19:56:34 +0530 Received: from bhairav.ee.iitb.ac.in (bhairav.ee.iitb.ac.in [10.107.1.1]) by ldns2.iitb.ac.in (Postfix) with ESMTP id 717213414EB; Wed, 3 Sep 2025 19:56:34 +0530 (IST) Received: from bhairav-test.ee.iitb.ac.in (bhairav.ee.iitb.ac.in [10.107.1.1]) (Authenticated sender: akhilesh) by bhairav.ee.iitb.ac.in (Postfix) with ESMTPSA id A51371E8143E; Wed, 3 Sep 2025 19:56:33 +0530 (IST) Date: Wed, 3 Sep 2025 19:56:28 +0530 From: Akhilesh Patil To: alexandre.belloni@bootlin.com, krzk+dt@kernel.org, robh@kernel.org, conor+dt@kernel.org Cc: skhan@linuxfoundation.org, linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, akhileshpatilvnit@gmail.com Subject: [PATCH 3/7] rtc: m41t93: migrate to regmap api for register access Message-ID: <1d7ed48e423157d9267aecf80961a7f8d18e04d1.1756908788.git.akhilesh@ee.iitb.ac.in> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Adapt driver to use regmap api with spi bus instead of direct spi subsystem calls to access device registers. Simplify and standardize the register interactions using more abstract and bus agnostic regmap api to reduce code duplication and improve maintainability. Define spi regmap config suitable for m41t93 spi bus protocol to achieve same transactions on spi bus. Tested on TI am62x sk board with m41t93 rtc chip connected over spi0. Validated set and get time using hwclock tool and verified spi bus transfers using logic analyzer. Signed-off-by: Akhilesh Patil --- drivers/rtc/rtc-m41t93.c | 121 ++++++++++++++++++++++----------------- 1 file changed, 70 insertions(+), 51 deletions(-) diff --git a/drivers/rtc/rtc-m41t93.c b/drivers/rtc/rtc-m41t93.c index 4e803ff0ce49..ad862bf706b6 100644 --- a/drivers/rtc/rtc-m41t93.c +++ b/drivers/rtc/rtc-m41t93.c @@ -12,6 +12,7 @@ #include #include #include +#include =20 #define M41T93_REG_SSEC 0 #define M41T93_REG_ST_SEC 1 @@ -31,23 +32,17 @@ #define M41T93_FLAG_BL (1 << 4) #define M41T93_FLAG_HT (1 << 6) =20 -static inline int m41t93_set_reg(struct spi_device *spi, u8 addr, u8 data) -{ - u8 buf[2]; - - /* MSB must be '1' to write */ - buf[0] =3D addr | 0x80; - buf[1] =3D data; - - return spi_write(spi, buf, sizeof(buf)); -} +struct m41t93_data { + struct rtc_device *rtc; + struct regmap *regmap; +}; =20 static int m41t93_set_time(struct device *dev, struct rtc_time *tm) { - struct spi_device *spi =3D to_spi_device(dev); - int tmp; - u8 buf[9] =3D {0x80}; /* write cmd + 8 data bytes */ - u8 * const data =3D &buf[1]; /* ptr to first data byte */ + struct m41t93_data *m41t93 =3D dev_get_drvdata(dev); + int tmp, ret; + u8 buf[8] =3D {0}; /* 8 data bytes */ + u8 * const data =3D &buf[0]; /* ptr to first data byte */ =20 dev_dbg(dev, "%s secs=3D%d, mins=3D%d, " "hours=3D%d, mday=3D%d, mon=3D%d, year=3D%d, wday=3D%d\n", @@ -56,31 +51,31 @@ static int m41t93_set_time(struct device *dev, struct r= tc_time *tm) tm->tm_mon, tm->tm_year, tm->tm_wday); =20 if (tm->tm_year < 100) { - dev_warn(&spi->dev, "unsupported date (before 2000-01-01).\n"); + dev_warn(dev, "unsupported date (before 2000-01-01).\n"); return -EINVAL; } =20 - tmp =3D spi_w8r8(spi, M41T93_REG_FLAGS); - if (tmp < 0) - return tmp; + ret =3D regmap_read(m41t93->regmap, M41T93_REG_FLAGS, &tmp); + if (ret < 0) + return ret; =20 if (tmp & M41T93_FLAG_OF) { - dev_warn(&spi->dev, "OF bit is set, resetting.\n"); - m41t93_set_reg(spi, M41T93_REG_FLAGS, tmp & ~M41T93_FLAG_OF); + dev_warn(dev, "OF bit is set, resetting.\n"); + regmap_write(m41t93->regmap, M41T93_REG_FLAGS, tmp & ~M41T93_FLAG_OF); =20 - tmp =3D spi_w8r8(spi, M41T93_REG_FLAGS); - if (tmp < 0) { - return tmp; + ret =3D regmap_read(m41t93->regmap, M41T93_REG_FLAGS, &tmp); + if (ret < 0) { + return ret; } else if (tmp & M41T93_FLAG_OF) { /* OF cannot be immediately reset: oscillator has to be * restarted. */ u8 reset_osc =3D buf[M41T93_REG_ST_SEC] | M41T93_FLAG_ST; =20 - dev_warn(&spi->dev, + dev_warn(dev, "OF bit is still set, kickstarting clock.\n"); - m41t93_set_reg(spi, M41T93_REG_ST_SEC, reset_osc); + regmap_write(m41t93->regmap, M41T93_REG_ST_SEC, reset_osc); reset_osc &=3D ~M41T93_FLAG_ST; - m41t93_set_reg(spi, M41T93_REG_ST_SEC, reset_osc); + regmap_write(m41t93->regmap, M41T93_REG_ST_SEC, reset_osc); } } =20 @@ -94,14 +89,13 @@ static int m41t93_set_time(struct device *dev, struct r= tc_time *tm) data[M41T93_REG_MON] =3D bin2bcd(tm->tm_mon + 1); data[M41T93_REG_YEAR] =3D bin2bcd(tm->tm_year % 100); =20 - return spi_write(spi, buf, sizeof(buf)); + return regmap_bulk_write(m41t93->regmap, M41T93_REG_SSEC, buf, sizeof(buf= )); } =20 =20 static int m41t93_get_time(struct device *dev, struct rtc_time *tm) { - struct spi_device *spi =3D to_spi_device(dev); - const u8 start_addr =3D 0; + struct m41t93_data *m41t93 =3D dev_get_drvdata(dev); u8 buf[8]; int century_after_1900; int tmp; @@ -113,32 +107,32 @@ static int m41t93_get_time(struct device *dev, struct= rtc_time *tm) case after poweron. Time is valid after resetting HT bit. 2. oscillator fail bit (OF) is set: time is invalid. */ - tmp =3D spi_w8r8(spi, M41T93_REG_ALM_HOUR_HT); - if (tmp < 0) - return tmp; + ret =3D regmap_read(m41t93->regmap, M41T93_REG_ALM_HOUR_HT, &tmp); + if (ret < 0) + return ret; =20 if (tmp & M41T93_FLAG_HT) { - dev_dbg(&spi->dev, "HT bit is set, reenable clock update.\n"); - m41t93_set_reg(spi, M41T93_REG_ALM_HOUR_HT, - tmp & ~M41T93_FLAG_HT); + dev_dbg(dev, "HT bit is set, reenable clock update.\n"); + regmap_write(m41t93->regmap, M41T93_REG_ALM_HOUR_HT, + tmp & ~M41T93_FLAG_HT); } =20 - tmp =3D spi_w8r8(spi, M41T93_REG_FLAGS); - if (tmp < 0) - return tmp; + ret =3D regmap_read(m41t93->regmap, M41T93_REG_FLAGS, &tmp); + if (ret < 0) + return ret; =20 if (tmp & M41T93_FLAG_OF) { ret =3D -EINVAL; - dev_warn(&spi->dev, "OF bit is set, write time to restart.\n"); + dev_warn(dev, "OF bit is set, write time to restart.\n"); } =20 if (tmp & M41T93_FLAG_BL) - dev_warn(&spi->dev, "BL bit is set, replace battery.\n"); + dev_warn(dev, "BL bit is set, replace battery.\n"); =20 /* read actual time/date */ - tmp =3D spi_write_then_read(spi, &start_addr, 1, buf, sizeof(buf)); - if (tmp < 0) - return tmp; + ret =3D regmap_bulk_read(m41t93->regmap, M41T93_REG_SSEC, buf, sizeof(buf= )); + if (ret < 0) + return ret; =20 tm->tm_sec =3D bcd2bin(buf[M41T93_REG_ST_SEC]); tm->tm_min =3D bcd2bin(buf[M41T93_REG_MIN]); @@ -167,26 +161,51 @@ static const struct rtc_class_ops m41t93_rtc_ops =3D { =20 static struct spi_driver m41t93_driver; =20 +static const struct regmap_config regmap_config =3D { + .reg_bits =3D 8, + .val_bits =3D 8, + .read_flag_mask =3D 0x00, + .write_flag_mask =3D 0x80, + .zero_flag_mask =3D true, +}; + static int m41t93_probe(struct spi_device *spi) { - struct rtc_device *rtc; - int res; + int res, ret; + struct m41t93_data *m41t93; =20 spi->bits_per_word =3D 8; spi_setup(spi); =20 - res =3D spi_w8r8(spi, M41T93_REG_WDAY); + m41t93 =3D devm_kzalloc(&spi->dev, sizeof(struct m41t93_data), GFP_KERNEL= ); + + if (!m41t93) + return -ENOMEM; + + /* Set up regmap to access device registers*/ + m41t93->regmap =3D devm_regmap_init_spi(spi, ®map_config); + if (IS_ERR(m41t93->regmap)) { + dev_err(&spi->dev, "regmap init failure\n"); + return PTR_ERR(m41t93->regmap); + } + + ret =3D regmap_read(m41t93->regmap, M41T93_REG_WDAY, &res); + if (ret < 0) { + dev_err(&spi->dev, "IO error\n"); + return -EIO; + } + if (res < 0 || (res & 0xf8) !=3D 0) { dev_err(&spi->dev, "not found 0x%x.\n", res); return -ENODEV; } =20 - rtc =3D devm_rtc_device_register(&spi->dev, m41t93_driver.driver.name, - &m41t93_rtc_ops, THIS_MODULE); - if (IS_ERR(rtc)) - return PTR_ERR(rtc); + spi_set_drvdata(spi, m41t93); =20 - spi_set_drvdata(spi, rtc); + m41t93->rtc =3D devm_rtc_device_register(&spi->dev, m41t93_driver.driver.= name, + &m41t93_rtc_ops, THIS_MODULE); + if (IS_ERR(m41t93->rtc)) + return PTR_ERR(m41t93->rtc); =20 return 0; } --=20 2.34.1 From nobody Fri Oct 3 07:39:26 2025 Received: from smtp1.iitb.ac.in (smtpd9.iitb.ac.in [103.21.126.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7481B2DAFC3 for ; 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X-Envelope-From: akhilesh@ee.iitb.ac.in X-Qmail-Scanner-Mime-Attachments: | X-Qmail-Scanner-Zip-Files: | Received: from unknown (HELO ldns2.iitb.ac.in) (10.200.1.25) by ldns2.iitb.ac.in with SMTP; 3 Sep 2025 19:57:00 +0530 Received: from bhairav.ee.iitb.ac.in (bhairav.ee.iitb.ac.in [10.107.1.1]) by ldns2.iitb.ac.in (Postfix) with ESMTP id F221B3414E2; Wed, 3 Sep 2025 19:56:59 +0530 (IST) Received: from bhairav-test.ee.iitb.ac.in (bhairav.ee.iitb.ac.in [10.107.1.1]) (Authenticated sender: akhilesh) by bhairav.ee.iitb.ac.in (Postfix) with ESMTPSA id 52A981E8143E; Wed, 3 Sep 2025 19:56:59 +0530 (IST) Date: Wed, 3 Sep 2025 19:56:54 +0530 From: Akhilesh Patil To: alexandre.belloni@bootlin.com, krzk+dt@kernel.org, robh@kernel.org, conor+dt@kernel.org Cc: skhan@linuxfoundation.org, linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, akhileshpatilvnit@gmail.com Subject: [PATCH 4/7] rtc: m41t93: Add alarm support Message-ID: <4f78f8fa113d4262e162972f5c15155410a64e8b.1756908788.git.akhilesh@ee.iitb.ac.in> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Implement alarm feature for rtc-m41t93 by adding necessary callbacks - set_alarm, read_alarm and alarm_irq_enable. Enable support to configure alarm 1 out of 2 alarms present in this rtc. Tested by observing IRQ pin (pin 12 of SOX18 package) on logic analyzer going low after alarm condition is met. Signed-off-by: Akhilesh Patil --- drivers/rtc/rtc-m41t93.c | 101 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 101 insertions(+) diff --git a/drivers/rtc/rtc-m41t93.c b/drivers/rtc/rtc-m41t93.c index ad862bf706b6..8cc179e08a4a 100644 --- a/drivers/rtc/rtc-m41t93.c +++ b/drivers/rtc/rtc-m41t93.c @@ -22,6 +22,14 @@ #define M41T93_REG_DAY 5 #define M41T93_REG_MON 6 #define M41T93_REG_YEAR 7 +#define M41T93_REG_AL1_MONTH 0xa +#define M41T93_REG_AL1_DATE 0xb +#define M41T93_REG_AL1_HOUR 0xc +#define M41T93_REG_AL1_MIN 0xd +#define M41T93_REG_AL1_SEC 0xe +#define M41T93_BIT_A1IE BIT(7) +#define M41T93_BIT_ABE BIT(5) +#define M41T93_FLAG_AF1 BIT(6) =20 =20 #define M41T93_REG_ALM_HOUR_HT 0xc @@ -153,10 +161,103 @@ static int m41t93_get_time(struct device *dev, struc= t rtc_time *tm) return ret; } =20 +static int m41t93_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) +{ + struct m41t93_data *m41t93 =3D dev_get_drvdata(dev); + int ret; + unsigned int val; + u8 alarm_vals[5] =3D {0}; + + ret =3D regmap_bulk_write(m41t93->regmap, M41T93_REG_AL1_DATE, alarm_vals= , 4); + if (ret) + return ret; + + /* Set alarm values */ + alarm_vals[0] =3D bin2bcd(alrm->time.tm_mon + 1) & 0x1f; + alarm_vals[1] =3D bin2bcd(alrm->time.tm_mday) & 0x3f; + alarm_vals[2] =3D bin2bcd(alrm->time.tm_hour) & 0x3f; + alarm_vals[3] =3D bin2bcd(alrm->time.tm_min) & 0x7f; + alarm_vals[4] =3D bin2bcd(alrm->time.tm_sec) & 0x7f; + + if (alrm->enabled) { + /* Enable alarm IRQ generation + * Note: SQWE is forced disabled while setting alarm + */ + alarm_vals[0] |=3D M41T93_BIT_A1IE | M41T93_BIT_ABE; + } + + ret =3D regmap_bulk_write(m41t93->regmap, M41T93_REG_AL1_MONTH, + alarm_vals, sizeof(alarm_vals)); + if (ret) + return ret; + + /* Device address pointer is now at FLAG register, move it to other locat= ion + * to finish setting alarm, as recommended by the datasheet. + * We do read of AL1_MONTH register to achieve this. + */ + ret =3D regmap_read(m41t93->regmap, M41T93_REG_AL1_MONTH, &val); + if (ret) + return ret; + + if (bcd2bin(val & 0x1f) =3D=3D (alrm->time.tm_mon & 0x1f)) + dev_notice(dev, "Alarm set successfully\n"); + + return 0; +} + +static int m41t93_get_alarm(struct device *dev, struct rtc_wkalrm *alrm) +{ + struct m41t93_data *m41t93 =3D dev_get_drvdata(dev); + int ret; + unsigned int val; + u8 alarm_vals[5] =3D {0}; + + ret =3D regmap_bulk_read(m41t93->regmap, M41T93_REG_AL1_MONTH, + alarm_vals, sizeof(alarm_vals)); + if (ret) + return ret; + + alrm->time.tm_mon =3D bcd2bin(alarm_vals[0] & 0x1f) - 1; + alrm->time.tm_mday =3D bcd2bin(alarm_vals[1] & 0x3f); + alrm->time.tm_hour =3D bcd2bin(alarm_vals[2] & 0x3f); + alrm->time.tm_min =3D bcd2bin(alarm_vals[3] & 0x7f); + alrm->time.tm_sec =3D bcd2bin(alarm_vals[4] & 0x7f); + + alrm->enabled =3D !!(alarm_vals[0] & M41T93_BIT_A1IE); + + ret =3D regmap_read(m41t93->regmap, M41T93_REG_FLAGS, &val); + if (ret) + return ret; + + alrm->pending =3D (val & M41T93_FLAG_AF1) && alrm->enabled; + + return 0; +} + +static int m41t93_alarm_irq_enable(struct device *dev, unsigned int enable= d) +{ + struct m41t93_data *m41t93 =3D dev_get_drvdata(dev); + unsigned int val; + int ret; + + val =3D enabled ? M41T93_BIT_A1IE | M41T93_BIT_ABE : + ~(M41T93_BIT_A1IE | M41T93_BIT_ABE); + + ret =3D regmap_update_bits(m41t93->regmap, M41T93_REG_AL1_MONTH, + M41T93_BIT_A1IE | M41T93_BIT_ABE, val); + if (ret) + return ret; + + return 0; +} + =20 static const struct rtc_class_ops m41t93_rtc_ops =3D { .read_time =3D m41t93_get_time, .set_time =3D m41t93_set_time, + .set_alarm =3D m41t93_set_alarm, + .read_alarm =3D m41t93_get_alarm, + .alarm_irq_enable =3D m41t93_alarm_irq_enable, }; =20 static struct spi_driver m41t93_driver; --=20 2.34.1 From nobody Fri Oct 3 07:39:26 2025 Received: from smtp1.iitb.ac.in (smtpd9.iitb.ac.in [103.21.126.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B5AA230AAB8 for ; Wed, 3 Sep 2025 14:27:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=103.21.126.64 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756909657; cv=none; b=Uik6+ZioyeALeO6ZybLcV7mM/iLbkRyYV+59cA+Z7b4bjNgI82romyDtNqa900SKBd8SaMvLlfqxc5UwuTQNXowCo2TxGb7iesM0W21TJdEd2Vsa7iQnji5btGSezvs7mvp0ncNXRwX9ZsCKkvT8IM3dMaPPo+GsbLOzNsY8NVE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756909657; c=relaxed/simple; bh=z7gG2wi7trHnM1dLuhDkxffPABy5/ujoFUZv+6zQlUM=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=U/uAPX+fvo3hwgNiEP6Tk1YjtScEP/7zEPXuZ6yX++41cQOqMsBS+2PaAdsjErbzdUg9pFsKcRpujb6llfoX0M/U+pNGctN6B56G4bA5sppZpTLWvbMwdEtkAaquo/jGllllwJ4ZX1S/hmdLbArMo/jxVXA3HesYDJ48m1JyCFo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=ee.iitb.ac.in; spf=pass smtp.mailfrom=ee.iitb.ac.in; dkim=pass (1024-bit key) header.d=iitb.ac.in header.i=@iitb.ac.in header.b=TAYGuZ76; arc=none smtp.client-ip=103.21.126.64 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=ee.iitb.ac.in Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ee.iitb.ac.in Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=iitb.ac.in header.i=@iitb.ac.in header.b="TAYGuZ76" Received: from ldns2.iitb.ac.in (ldns2.iitb.ac.in [10.200.12.2]) by smtp1.iitb.ac.in (Postfix) with SMTP id 372111010F83 for ; Wed, 3 Sep 2025 19:57:30 +0530 (IST) DKIM-Filter: OpenDKIM Filter v2.11.0 smtp1.iitb.ac.in 372111010F83 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=iitb.ac.in; s=mail; t=1756909650; bh=z7gG2wi7trHnM1dLuhDkxffPABy5/ujoFUZv+6zQlUM=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=TAYGuZ76CQwdYOiX64Dd9sjvOopAgKIqedT9xGMo9rs4g4zIZ+Cr+XAhkHEXRVXd4 tDrMQTqNSR9xcN0v5QdGTMIh5e9hLKoUiTk+4emMgUglM3TzFwG+TouOkdNSWv7HuX +qG8c929K4n1lagpEUXxPZauR5GHbdwkcYsi1qfg= Received: (qmail 32748 invoked by uid 510); 3 Sep 2025 19:57:30 +0530 X-Qmail-Scanner-Diagnostics: from 10.200.1.25 by ldns2 (envelope-from , uid 501) with qmail-scanner-2.11 spamassassin: 3.4.1. mhr: 1.0. {clamdscan: 0.100.0/26337} Clear:RC:1(10.200.1.25):SA:0(0.0/7.0):. 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X-Envelope-From: akhilesh@ee.iitb.ac.in X-Qmail-Scanner-Mime-Attachments: | X-Qmail-Scanner-Zip-Files: | Received: from unknown (HELO ldns2.iitb.ac.in) (10.200.1.25) by ldns2.iitb.ac.in with SMTP; 3 Sep 2025 19:57:26 +0530 Received: from bhairav.ee.iitb.ac.in (bhairav.ee.iitb.ac.in [10.107.1.1]) by ldns2.iitb.ac.in (Postfix) with ESMTP id 2D0293414ED; Wed, 3 Sep 2025 19:57:26 +0530 (IST) Received: from bhairav-test.ee.iitb.ac.in (bhairav.ee.iitb.ac.in [10.107.1.1]) (Authenticated sender: akhilesh) by bhairav.ee.iitb.ac.in (Postfix) with ESMTPSA id 0E8181E8143E; Wed, 3 Sep 2025 19:57:26 +0530 (IST) Date: Wed, 3 Sep 2025 19:57:21 +0530 From: Akhilesh Patil To: alexandre.belloni@bootlin.com, krzk+dt@kernel.org, robh@kernel.org, conor+dt@kernel.org Cc: skhan@linuxfoundation.org, linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, akhileshpatilvnit@gmail.com Subject: [PATCH 5/7] rtc: m41t93: fix device connection/detection logic during probe Message-ID: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Fix the incorrect assumption about WDAY register (0x4) bits 3 to 7 being 0 after initial power-on to test response from device during probe Do not expect these bits to be 0 after power on as datasheet does not explicitly mention these power on defaults but recommends software to clear these bits during operation. Refer section 3.15 for initial power-on default bits. Fix the random probe failures after power on by removing this condition check. Add alternate response check logic which performs write, read, compare check on device SRAM register to check device connection. Signed-off-by: Akhilesh Patil --- drivers/rtc/rtc-m41t93.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/drivers/rtc/rtc-m41t93.c b/drivers/rtc/rtc-m41t93.c index 8cc179e08a4a..902797070246 100644 --- a/drivers/rtc/rtc-m41t93.c +++ b/drivers/rtc/rtc-m41t93.c @@ -30,6 +30,7 @@ #define M41T93_BIT_A1IE BIT(7) #define M41T93_BIT_ABE BIT(5) #define M41T93_FLAG_AF1 BIT(6) +#define M41T93_SRAM_BASE 0x19 =20 =20 #define M41T93_REG_ALM_HOUR_HT 0xc @@ -290,17 +291,25 @@ static int m41t93_probe(struct spi_device *spi) return PTR_ERR(m41t93->regmap); } =20 - ret =3D regmap_read(m41t93->regmap, M41T93_REG_WDAY, &res); - if (ret < 0) { + ret =3D regmap_write(m41t93->regmap, M41T93_SRAM_BASE, 0xA5); + if (ret) { dev_err(&spi->dev, "IO error\n"); return -EIO; } =20 - if (res < 0 || (res & 0xf8) !=3D 0) { - dev_err(&spi->dev, "not found 0x%x.\n", res); + ret =3D regmap_read(m41t93->regmap, M41T93_SRAM_BASE, &res); + if (ret) { + dev_err(&spi->dev, "IO error\n"); + return -EIO; + } + + if (res !=3D 0xA5) { + dev_err(&spi->dev, "No valid response from device 0x%x.\n", res); return -ENODEV; } =20 + dev_notice(&spi->dev, "m41t93 device response success\n"); + spi_set_drvdata(spi, m41t93); =20 m41t93->rtc =3D devm_rtc_device_register(&spi->dev, m41t93_driver.driver.= name, --=20 2.34.1 From nobody Fri Oct 3 07:39:26 2025 Received: from smtp1.iitb.ac.in (smtpd9.iitb.ac.in [103.21.126.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 50CE530F52B for ; Wed, 3 Sep 2025 14:27:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=103.21.126.64 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756909679; cv=none; b=DxujMSHPVDtKt30JosTgOjK/7H+PPo8WT7eAgXcfKy9fIo7zAgAl29pgoPa3hOf1btskv9Rgc0OmjmOK8SZYi9RrT5JiYvPKYSnSM27GtaU3cQtpAgRDJChbYIE23l92lDQQFd/oZ5/FnwDOo0AybxxyLjVoBbS7D8C5IY7TnX4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756909679; c=relaxed/simple; bh=FNNYFnrFZfW3cu4lOIdFx7ZZciLmz4zTGxC7KX+Ise0=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=H0qp4+aitjJMvtfbRe9JfZJuEuhWdGbxPJ0qoHXT8cphDwGs/u/GT0GLQTSWLwPhw2rlfQYUKAkYKd1kkCucywYAhbMD0lDhMC2/YXOr4P38ijrf+qXoYqQ+xKmWTUhjB6q5ctiyo81FALJfpuq3MGq3qcuoVty3HPFOclDbU3Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=ee.iitb.ac.in; spf=pass smtp.mailfrom=ee.iitb.ac.in; dkim=pass (1024-bit key) header.d=iitb.ac.in header.i=@iitb.ac.in header.b=C3CC7LsV; arc=none smtp.client-ip=103.21.126.64 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=ee.iitb.ac.in Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ee.iitb.ac.in Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=iitb.ac.in header.i=@iitb.ac.in header.b="C3CC7LsV" Received: from ldns2.iitb.ac.in (ldns2.iitb.ac.in [10.200.12.2]) by smtp1.iitb.ac.in (Postfix) with SMTP id E565E101C6B6 for ; Wed, 3 Sep 2025 19:57:54 +0530 (IST) DKIM-Filter: OpenDKIM Filter v2.11.0 smtp1.iitb.ac.in E565E101C6B6 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=iitb.ac.in; s=mail; t=1756909674; bh=FNNYFnrFZfW3cu4lOIdFx7ZZciLmz4zTGxC7KX+Ise0=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=C3CC7LsVkbOM/oxyU9Q9d9zXtmMO3FXy6KWh7PEvF7HDBKmo4LGPYn8Xq/EPkQMcx hKc3GfF3iX/YNtxbYxa5iglC939OUliZB/r+UPOPXgJVCxcWJQluYkvwYq+nLSHt4b QJ2ndTnHQyZL8GQgZAFlcBu4R6ew8HS6wb1iLs3k= Received: (qmail 559 invoked by uid 510); 3 Sep 2025 19:57:54 +0530 X-Qmail-Scanner-Diagnostics: from 10.200.1.25 by ldns2 (envelope-from , uid 501) with qmail-scanner-2.11 spamassassin: 3.4.1. mhr: 1.0. {clamdscan: 0.100.0/26337} Clear:RC:1(10.200.1.25):SA:0(0.0/7.0):. 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X-Envelope-From: akhilesh@ee.iitb.ac.in X-Qmail-Scanner-Mime-Attachments: | X-Qmail-Scanner-Zip-Files: | Received: from unknown (HELO ldns2.iitb.ac.in) (10.200.1.25) by ldns2.iitb.ac.in with SMTP; 3 Sep 2025 19:57:51 +0530 Received: from bhairav.ee.iitb.ac.in (bhairav.ee.iitb.ac.in [10.107.1.1]) by ldns2.iitb.ac.in (Postfix) with ESMTP id AD9363414E2; Wed, 3 Sep 2025 19:57:50 +0530 (IST) Received: from bhairav-test.ee.iitb.ac.in (bhairav.ee.iitb.ac.in [10.107.1.1]) (Authenticated sender: akhilesh) by bhairav.ee.iitb.ac.in (Postfix) with ESMTPSA id 7A8441E8143E; Wed, 3 Sep 2025 19:57:50 +0530 (IST) Date: Wed, 3 Sep 2025 19:57:45 +0530 From: Akhilesh Patil To: alexandre.belloni@bootlin.com, krzk+dt@kernel.org, robh@kernel.org, conor+dt@kernel.org Cc: skhan@linuxfoundation.org, linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, akhileshpatilvnit@gmail.com Subject: [PATCH 6/7] rtc: m41t93: Add square wave clock provider support Message-ID: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Implement support to configure square wave output (SQW) of m41t93 rtc via common clock framework clock provider api. Add clock provider callbacks to control output frequency ranging from 1Hz to 32KHz as supported by this rtc chip. Tested by measuring various frequencies on pull-up connected SWQ(7) pin of m41t93 rtc chip using logic analyzer. Signed-off-by: Akhilesh Patil --- drivers/rtc/rtc-m41t93.c | 154 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 154 insertions(+) diff --git a/drivers/rtc/rtc-m41t93.c b/drivers/rtc/rtc-m41t93.c index 902797070246..83cc34c4baae 100644 --- a/drivers/rtc/rtc-m41t93.c +++ b/drivers/rtc/rtc-m41t93.c @@ -13,6 +13,7 @@ #include #include #include +#include =20 #define M41T93_REG_SSEC 0 #define M41T93_REG_ST_SEC 1 @@ -31,6 +32,10 @@ #define M41T93_BIT_ABE BIT(5) #define M41T93_FLAG_AF1 BIT(6) #define M41T93_SRAM_BASE 0x19 +#define M41T93_REG_SQW 0x13 +#define M41T93_SQW_RS_MASK 0xf0 +#define M41T93_SQW_RS_SHIFT 4 +#define M41T93_BIT_SQWE BIT(6) =20 =20 #define M41T93_REG_ALM_HOUR_HT 0xc @@ -44,6 +49,9 @@ struct m41t93_data { struct rtc_device *rtc; struct regmap *regmap; +#ifdef CONFIG_COMMON_CLK + struct clk_hw clks; +#endif }; =20 static int m41t93_set_time(struct device *dev, struct rtc_time *tm) @@ -261,6 +269,146 @@ static const struct rtc_class_ops m41t93_rtc_ops =3D { .alarm_irq_enable =3D m41t93_alarm_irq_enable, }; =20 +#ifdef CONFIG_COMMON_CLK +#define clk_sqw_to_m41t93_data(clk) \ + container_of(clk, struct m41t93_data, clks) + +/* m41t93 RTC clock output support */ +static unsigned long m41t93_clk_rates[] =3D { + 0, + 32768, /* RS3:RS0 =3D 0b0001 */ + 8192, + 4096, + 2048, + 1024, + 512, + 256, + 128, + 64, + 32, + 16, + 8, + 4, + 2, + 1, /* RS3:RS0 =3D 0b1111 */ +}; + +static unsigned long m41t93_clk_sqw_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + int ret; + unsigned int rate_id; + struct m41t93_data *m41t93 =3D clk_sqw_to_m41t93_data(hw); + + ret =3D regmap_read(m41t93->regmap, M41T93_REG_SQW, &rate_id); + if (ret) + return ret; + + rate_id &=3D M41T93_SQW_RS_MASK; + rate_id >>=3D M41T93_SQW_RS_SHIFT; + + return m41t93_clk_rates[rate_id]; +} + +static int m41t93_clk_sqw_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + int i; + + for (i =3D 1; i < ARRAY_SIZE(m41t93_clk_rates); i++) { + if (req->rate >=3D m41t93_clk_rates[i]) { + req->rate =3D m41t93_clk_rates[i]; + return 0; + } + } + + return 0; +} + +static int m41t93_clk_sqw_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + int id, ret; + struct m41t93_data *m41t93 =3D clk_sqw_to_m41t93_data(hw); + + for (id =3D 0; id < ARRAY_SIZE(m41t93_clk_rates); id++) { + if (m41t93_clk_rates[id] =3D=3D rate) + break; + } + + if (id >=3D ARRAY_SIZE(m41t93_clk_rates)) + return -EINVAL; + + ret =3D regmap_update_bits(m41t93->regmap, M41T93_REG_SQW, + M41T93_SQW_RS_MASK, id << M41T93_SQW_RS_SHIFT); + + return ret; +} + +static int m41t93_clk_sqw_prepare(struct clk_hw *hw) +{ + int ret; + struct m41t93_data *m41t93 =3D clk_sqw_to_m41t93_data(hw); + + ret =3D regmap_update_bits(m41t93->regmap, M41T93_REG_AL1_MONTH, + M41T93_BIT_SQWE, M41T93_BIT_SQWE); + + return ret; +} + +static void m41t93_clk_sqw_unprepare(struct clk_hw *hw) +{ + struct m41t93_data *m41t93 =3D clk_sqw_to_m41t93_data(hw); + + regmap_update_bits(m41t93->regmap, M41T93_REG_AL1_MONTH, + M41T93_BIT_SQWE, ~M41T93_BIT_SQWE); +} + +static int m41t93_clk_sqw_is_prepared(struct clk_hw *hw) +{ + int ret; + struct m41t93_data *m41t93 =3D clk_sqw_to_m41t93_data(hw); + unsigned int status; + + ret =3D regmap_read(m41t93->regmap, M41T93_REG_AL1_MONTH, &status); + if (ret) + return ret; + + return !!(status & M41T93_BIT_SQWE); +} + +static const struct clk_ops m41t93_clk_sqw_ops =3D { + .prepare =3D m41t93_clk_sqw_prepare, + .unprepare =3D m41t93_clk_sqw_unprepare, + .is_prepared =3D m41t93_clk_sqw_is_prepared, + .recalc_rate =3D m41t93_clk_sqw_recalc_rate, + .set_rate =3D m41t93_clk_sqw_set_rate, + .determine_rate =3D m41t93_clk_sqw_determine_rate, +}; + +static int rtc_m41t93_clks_register(struct device *dev, struct m41t93_data= *m41t93) +{ + struct device_node *node =3D dev->of_node; + struct clk *clk; + struct clk_init_data init =3D {0}; + + init.name =3D "m41t93_clk_sqw"; + init.ops =3D &m41t93_clk_sqw_ops; + + m41t93->clks.init =3D &init; + + /* Register the clock with CCF */ + clk =3D devm_clk_register(dev, &m41t93->clks); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + if (node) + of_clk_add_provider(node, of_clk_src_simple_get, clk); + + return 0; +} +#endif + static struct spi_driver m41t93_driver; =20 static const struct regmap_config regmap_config =3D { @@ -317,6 +465,12 @@ static int m41t93_probe(struct spi_device *spi) if (IS_ERR(m41t93->rtc)) return PTR_ERR(m41t93->rtc); =20 +#ifdef CONFIG_COMMON_CLK + ret =3D rtc_m41t93_clks_register(&spi->dev, m41t93); + if (ret) + dev_warn(&spi->dev, "Unable to register clock\n"); +#endif + return 0; } =20 --=20 2.34.1 From nobody Fri Oct 3 07:39:26 2025 Received: from smtp1.iitb.ac.in (smtpd9.iitb.ac.in [103.21.126.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DAE6C311C39 for ; Wed, 3 Sep 2025 14:28:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=103.21.126.64 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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X-Envelope-From: akhilesh@ee.iitb.ac.in X-Qmail-Scanner-Mime-Attachments: | X-Qmail-Scanner-Zip-Files: | Received: from unknown (HELO ldns2.iitb.ac.in) (10.200.1.25) by ldns2.iitb.ac.in with SMTP; 3 Sep 2025 19:58:17 +0530 Received: from bhairav.ee.iitb.ac.in (bhairav.ee.iitb.ac.in [10.107.1.1]) by ldns2.iitb.ac.in (Postfix) with ESMTP id 30DDB3414F0; Wed, 3 Sep 2025 19:58:17 +0530 (IST) Received: from bhairav-test.ee.iitb.ac.in (bhairav.ee.iitb.ac.in [10.107.1.1]) (Authenticated sender: akhilesh) by bhairav.ee.iitb.ac.in (Postfix) with ESMTPSA id BFFCD1E8143E; Wed, 3 Sep 2025 19:58:16 +0530 (IST) Date: Wed, 3 Sep 2025 19:58:11 +0530 From: Akhilesh Patil To: alexandre.belloni@bootlin.com, krzk+dt@kernel.org, robh@kernel.org, conor+dt@kernel.org Cc: skhan@linuxfoundation.org, linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, akhileshpatilvnit@gmail.com Subject: [PATCH 7/7] rtc: m41t93: Add watchdog support Message-ID: <694706ad8577a36ef8948e0d9ca7ea561900fbc2.1756908788.git.akhilesh@ee.iitb.ac.in> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Implement watchdog feature driver for m41t93 rtc with 1s resolution and alarm only mode. Define start, stop, ping, and set_timeout callbacks as needed by watchdog framework. Tested by observing IRQ pin(12) going low after intentionally not pinging watchdog. Signed-off-by: Akhilesh Patil --- drivers/rtc/rtc-m41t93.c | 93 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 93 insertions(+) diff --git a/drivers/rtc/rtc-m41t93.c b/drivers/rtc/rtc-m41t93.c index 83cc34c4baae..e549c5f1e11a 100644 --- a/drivers/rtc/rtc-m41t93.c +++ b/drivers/rtc/rtc-m41t93.c @@ -14,6 +14,7 @@ #include #include #include +#include =20 #define M41T93_REG_SSEC 0 #define M41T93_REG_ST_SEC 1 @@ -36,6 +37,10 @@ #define M41T93_SQW_RS_MASK 0xf0 #define M41T93_SQW_RS_SHIFT 4 #define M41T93_BIT_SQWE BIT(6) +#define M41T93_REG_WATCHDOG 0x9 +#define M41T93_WDT_RB_MASK 0x3 +#define M41T93_WDT_BMB_MASK 0x7c +#define M41T93_WDT_BMB_SHIFT 2 =20 =20 #define M41T93_REG_ALM_HOUR_HT 0xc @@ -52,6 +57,7 @@ struct m41t93_data { #ifdef CONFIG_COMMON_CLK struct clk_hw clks; #endif + struct watchdog_device wdd; }; =20 static int m41t93_set_time(struct device *dev, struct rtc_time *tm) @@ -409,6 +415,90 @@ static int rtc_m41t93_clks_register(struct device *dev= , struct m41t93_data *m41t } #endif =20 +static int m41t93_wdt_ping(struct watchdog_device *wdd) +{ + u8 resolution, mult; + u8 val =3D 0; + int ret; + struct m41t93_data *m41t93 =3D watchdog_get_drvdata(wdd); + + /* Resolution supported by hardware + * 0b00 : 1/16 seconds + * 0b01 : 1/4 second + * 0b10 : 1 second + * 0b11 : 4 seconds + */ + resolution =3D 0x2; /* hardcode resolution to 1s */ + mult =3D wdd->timeout; + val =3D resolution | (mult << M41T93_WDT_BMB_SHIFT & M41T93_WDT_BMB_MASK= ); + + ret =3D regmap_write_bits(m41t93->regmap, M41T93_REG_WATCHDOG, + M41T93_WDT_RB_MASK | M41T93_WDT_BMB_MASK, val); + + return ret; +} + +static int m41t93_wdt_start(struct watchdog_device *wdd) +{ + return m41t93_wdt_ping(wdd); +} + +static int m41t93_wdt_stop(struct watchdog_device *wdd) +{ + struct m41t93_data *m41t93 =3D watchdog_get_drvdata(wdd); + + /* Write 0 to watchdog register */ + return regmap_write_bits(m41t93->regmap, M41T93_REG_WATCHDOG, + M41T93_WDT_RB_MASK | M41T93_WDT_BMB_MASK, 0); +} + +static int m41t93_wdt_set_timeout(struct watchdog_device *wdd, + unsigned int new_timeout) +{ + wdd->timeout =3D new_timeout; + + return 0; +} + +static const struct watchdog_info m41t93_wdt_info =3D { + .identity =3D "m41t93 rtc Watchdog", + .options =3D WDIOF_ALARMONLY, +}; + +static const struct watchdog_ops m41t93_watchdog_ops =3D { + .owner =3D THIS_MODULE, + .start =3D m41t93_wdt_start, + .stop =3D m41t93_wdt_stop, + .ping =3D m41t93_wdt_ping, + .set_timeout =3D m41t93_wdt_set_timeout, +}; + +static int m41t93_watchdog_register(struct device *dev, struct m41t93_data= *m41t93) +{ + int ret; + + m41t93->wdd.parent =3D dev; + m41t93->wdd.info =3D &m41t93_wdt_info; + m41t93->wdd.ops =3D &m41t93_watchdog_ops; + m41t93->wdd.min_timeout =3D 0; + m41t93->wdd.max_timeout =3D 10; + m41t93->wdd.timeout =3D 3; /* Default timeout is 3 sec */ + m41t93->wdd.status =3D WATCHDOG_NOWAYOUT_INIT_STATUS; + + watchdog_set_drvdata(&m41t93->wdd, m41t93); + + ret =3D devm_watchdog_register_device(dev, &m41t93->wdd); + if (ret) { + dev_warn(dev, "Failed to register watchdog\n"); + return ret; + } + + /* Disable watchdog at start */ + ret =3D m41t93_wdt_stop(&m41t93->wdd); + + return ret; +} + static struct spi_driver m41t93_driver; =20 static const struct regmap_config regmap_config =3D { @@ -470,6 +560,9 @@ static int m41t93_probe(struct spi_device *spi) if (ret) dev_warn(&spi->dev, "Unable to register clock\n"); #endif + ret =3D m41t93_watchdog_register(&spi->dev, m41t93); + if (ret) + dev_warn(&spi->dev, "Unable to register watchdog\n"); =20 return 0; } --=20 2.34.1