From nobody Fri Oct 3 08:47:49 2025 Received: from pidgin.makrotopia.org (pidgin.makrotopia.org [185.142.180.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DE8531AAA1B; Tue, 2 Sep 2025 23:36:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.142.180.65 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756856162; cv=none; b=s7BnR02NbnUqt0BEznS4gmjd4a49GMfDS2NN1f5fBWMXqvntO6NBi4L/MoqSW/vZQ21H+GeLoaN8FPmbgq+oyXEkEj0/yn9JZDzbyuoxLic1JskWkxjfX1IsLN8XqZARv9AcShA+bYW8ip0xxUKGVhknV7HuxZKeyHEO/rzQCFk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756856162; c=relaxed/simple; bh=BQvZJDMZodJlpBViAy9kpZCvOy9n725TV2pRR86zggM=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=iyw6ho6JAD68nBHcPYrDfQUQB2TfgtNNHWaAs2L14YK6j8aN33FZKWoSq1d7EMIKovwXT9GClAgYyV8aHn1ibldIeSrbI08447UldJxSBUcR1H8kB2WNmysHmklXWruUJxjAm+aCfw9ZyzESz/AJgHrRWgQsdkomf7fVnUYzqfs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org; spf=pass smtp.mailfrom=makrotopia.org; arc=none smtp.client-ip=185.142.180.65 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=makrotopia.org Received: from local by pidgin.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.98.2) (envelope-from ) id 1utaXc-000000001Hh-0hCU; Tue, 02 Sep 2025 23:35:56 +0000 Date: Wed, 3 Sep 2025 00:35:52 +0100 From: Daniel Golle To: Hauke Mehrtens , Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Russell King , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Andreas Schirm , Lukas Stockmann , Alexander Sverdlin , Peter Christen , Avinash Jayaraman , Bing tao Xu , Liang Xu , Juraj Povazanec , "Fanni (Fang-Yi) Chan" , "Benny (Ying-Tsan) Weng" , "Livia M. Rosu" , John Crispin Subject: [RFC PATCH net-next 1/6] net: dsa: lantiq_gswip: convert accessors to use regmap Message-ID: <97c2b3d65a0cd550922f809f6e6f51645ccc4ef9.1756855069.git.daniel@makrotopia.org> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use regmap for register access in preparation for supporting the MaxLinear GSW1xx family of switches connected via MDIO or SPI. Rewrite the existing accessor read-poll-timeout functions to use calls to the regmap API for now. Signed-off-by: Daniel Golle --- drivers/net/dsa/lantiq/Kconfig | 1 + drivers/net/dsa/lantiq/lantiq_gswip.c | 143 ++++++++++++++++++-------- drivers/net/dsa/lantiq/lantiq_gswip.h | 6 +- 3 files changed, 106 insertions(+), 44 deletions(-) diff --git a/drivers/net/dsa/lantiq/Kconfig b/drivers/net/dsa/lantiq/Kconfig index 1cb053c823f7..3cfa16840cf5 100644 --- a/drivers/net/dsa/lantiq/Kconfig +++ b/drivers/net/dsa/lantiq/Kconfig @@ -2,6 +2,7 @@ config NET_DSA_LANTIQ_GSWIP tristate "Lantiq / Intel GSWIP" depends on HAS_IOMEM select NET_DSA_TAG_GSWIP + select REGMAP help This enables support for the Lantiq / Intel GSWIP 2.1 found in the xrx200 / VR9 SoC. diff --git a/drivers/net/dsa/lantiq/lantiq_gswip.c b/drivers/net/dsa/lantiq= /lantiq_gswip.c index 1d9b9689ef9f..00de075b027a 100644 --- a/drivers/net/dsa/lantiq/lantiq_gswip.c +++ b/drivers/net/dsa/lantiq/lantiq_gswip.c @@ -113,22 +113,40 @@ static const struct gswip_rmon_cnt_desc gswip_rmon_cn= t[] =3D { =20 static u32 gswip_switch_r(struct gswip_priv *priv, u32 offset) { - return __raw_readl(priv->gswip + (offset * 4)); + unsigned int val; + int ret; + + ret =3D regmap_read(priv->gswip, offset, &val); + if (ret) { + WARN_ON_ONCE(1); + dev_err(priv->dev, "failed to read switch register\n"); + return 0; + } + + return val; } =20 static void gswip_switch_w(struct gswip_priv *priv, u32 val, u32 offset) { - __raw_writel(val, priv->gswip + (offset * 4)); + int ret; + + ret =3D regmap_write(priv->gswip, offset, val); + if (ret) { + WARN_ON_ONCE(1); + dev_err(priv->dev, "failed to write switch register\n"); + } } =20 static void gswip_switch_mask(struct gswip_priv *priv, u32 clear, u32 set, u32 offset) { - u32 val =3D gswip_switch_r(priv, offset); + int ret; =20 - val &=3D ~(clear); - val |=3D set; - gswip_switch_w(priv, val, offset); + ret =3D regmap_write_bits(priv->gswip, offset, clear | set, set); + if (ret) { + WARN_ON_ONCE(1); + dev_err(priv->dev, "failed to update switch register\n"); + } } =20 static u32 gswip_switch_r_timeout(struct gswip_priv *priv, u32 offset, @@ -136,48 +154,58 @@ static u32 gswip_switch_r_timeout(struct gswip_priv *= priv, u32 offset, { u32 val; =20 - return readx_poll_timeout(__raw_readl, priv->gswip + (offset * 4), val, - (val & cleared) =3D=3D 0, 20, 50000); + return regmap_read_poll_timeout(priv->gswip, offset, val, + !(val & cleared), 20, 50000); } =20 static u32 gswip_mdio_r(struct gswip_priv *priv, u32 offset) { - return __raw_readl(priv->mdio + (offset * 4)); + u32 val; + int ret; + + ret =3D regmap_read(priv->mdio, offset, &val); + if (ret) { + WARN_ON_ONCE(1); + dev_err(priv->dev, "failed to read mdio register\n"); + return 0; + } + + return val; } =20 static void gswip_mdio_w(struct gswip_priv *priv, u32 val, u32 offset) { - __raw_writel(val, priv->mdio + (offset * 4)); + int ret; + + ret =3D regmap_write(priv->mdio, offset, val); + if (ret) { + WARN_ON_ONCE(1); + dev_err(priv->dev, "failed to write mdio register\n"); + } } =20 static void gswip_mdio_mask(struct gswip_priv *priv, u32 clear, u32 set, u32 offset) { - u32 val =3D gswip_mdio_r(priv, offset); - - val &=3D ~(clear); - val |=3D set; - gswip_mdio_w(priv, val, offset); -} - -static u32 gswip_mii_r(struct gswip_priv *priv, u32 offset) -{ - return __raw_readl(priv->mii + (offset * 4)); -} + int ret; =20 -static void gswip_mii_w(struct gswip_priv *priv, u32 val, u32 offset) -{ - __raw_writel(val, priv->mii + (offset * 4)); + ret =3D regmap_write_bits(priv->mdio, offset, clear | set, set); + if (ret) { + WARN_ON_ONCE(1); + dev_err(priv->dev, "failed to update mdio register\n"); + } } =20 static void gswip_mii_mask(struct gswip_priv *priv, u32 clear, u32 set, u32 offset) { - u32 val =3D gswip_mii_r(priv, offset); + int ret; =20 - val &=3D ~(clear); - val |=3D set; - gswip_mii_w(priv, val, offset); + ret =3D regmap_write_bits(priv->mii, offset, clear | set, set); + if (ret) { + WARN_ON_ONCE(1); + dev_err(priv->dev, "failed to update mdio register\n"); + } } =20 static void gswip_mii_mask_cfg(struct gswip_priv *priv, u32 clear, u32 set, @@ -220,17 +248,10 @@ static void gswip_mii_mask_pcdu(struct gswip_priv *pr= iv, u32 clear, u32 set, =20 static int gswip_mdio_poll(struct gswip_priv *priv) { - int cnt =3D 100; - - while (likely(cnt--)) { - u32 ctrl =3D gswip_mdio_r(priv, GSWIP_MDIO_CTRL); - - if ((ctrl & GSWIP_MDIO_CTRL_BUSY) =3D=3D 0) - return 0; - usleep_range(20, 40); - } + u32 ctrl; =20 - return -ETIMEDOUT; + return regmap_read_poll_timeout(priv->mdio, GSWIP_MDIO_CTRL, ctrl, + !(ctrl & GSWIP_MDIO_CTRL_BUSY), 40, 4000); } =20 static int gswip_mdio_wr(struct mii_bus *bus, int addr, int reg, u16 val) @@ -1900,9 +1921,37 @@ static int gswip_validate_cpu_port(struct dsa_switch= *ds) return 0; } =20 +static const struct regmap_config sw_regmap_config =3D { + .name =3D "switch", + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_shift =3D -2, + .val_format_endian =3D REGMAP_ENDIAN_NATIVE, + .max_register =3D GSWIP_SDMA_PCTRLp(6), +}; + +static const struct regmap_config mdio_regmap_config =3D { + .name =3D "mdio", + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_shift =3D -2, + .val_format_endian =3D REGMAP_ENDIAN_NATIVE, + .max_register =3D GSWIP_MDIO_PHYp(0), +}; + +static const struct regmap_config mii_regmap_config =3D { + .name =3D "mii", + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_shift =3D -2, + .val_format_endian =3D REGMAP_ENDIAN_NATIVE, + .max_register =3D GSWIP_MII_CFGp(6), +}; + static int gswip_probe(struct platform_device *pdev) { struct device_node *np, *gphy_fw_np; + __iomem void *gswip, *mdio, *mii; struct device *dev =3D &pdev->dev; struct gswip_priv *priv; int err; @@ -1913,15 +1962,27 @@ static int gswip_probe(struct platform_device *pdev) if (!priv) return -ENOMEM; =20 - priv->gswip =3D devm_platform_ioremap_resource(pdev, 0); + gswip =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(gswip)) + return PTR_ERR(gswip); + + mdio =3D devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(mdio)) + return PTR_ERR(mdio); + + mii =3D devm_platform_ioremap_resource(pdev, 2); + if (IS_ERR(mii)) + return PTR_ERR(mii); + + priv->gswip =3D devm_regmap_init_mmio(dev, gswip, &sw_regmap_config); if (IS_ERR(priv->gswip)) return PTR_ERR(priv->gswip); =20 - priv->mdio =3D devm_platform_ioremap_resource(pdev, 1); + priv->mdio =3D devm_regmap_init_mmio(dev, mdio, &mdio_regmap_config); if (IS_ERR(priv->mdio)) return PTR_ERR(priv->mdio); =20 - priv->mii =3D devm_platform_ioremap_resource(pdev, 2); + priv->mii =3D devm_regmap_init_mmio(dev, mii, &mii_regmap_config); if (IS_ERR(priv->mii)) return PTR_ERR(priv->mii); =20 diff --git a/drivers/net/dsa/lantiq/lantiq_gswip.h b/drivers/net/dsa/lantiq= /lantiq_gswip.h index 2df9c8e8cfd0..efc2e9041815 100644 --- a/drivers/net/dsa/lantiq/lantiq_gswip.h +++ b/drivers/net/dsa/lantiq/lantiq_gswip.h @@ -257,9 +257,9 @@ struct gswip_vlan { }; =20 struct gswip_priv { - __iomem void *gswip; - __iomem void *mdio; - __iomem void *mii; + struct regmap *gswip; + struct regmap *mdio; + struct regmap *mii; const struct gswip_hw_info *hw_info; const struct xway_gphy_match_data *gphy_fw_name_cfg; struct dsa_switch *ds; --=20 2.51.0 From nobody Fri Oct 3 08:47:49 2025 Received: from pidgin.makrotopia.org (pidgin.makrotopia.org [185.142.180.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A005127F4D5; Tue, 2 Sep 2025 23:36:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.142.180.65 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756856173; cv=none; b=ezmxHUI+V0lPb6inmaiTFGdQZr611QZZAOTSrUXoYIWtGA/f0w5BL1TUB11y+QudWnMgaX9QMFKnNaS53OD6oUpKFv5ENvjRM1my00D++BSxOEq4nHsZnoZrSe/PiS4VSpMCyOjy16M9eHCrst+3IkaNbKV4nZ4gF17wOfTCVxY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756856173; c=relaxed/simple; bh=vxeTM+fC2PyldtogFyVsaGHoexkDcpioluzkN6JCsLk=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=FcLVk6BgAdwf8lf/Xe3efHDwoVzqN0uelssJ0hmmAnYBLZ4GO8nZoEEs+BDSjVcBIAUHUpX/9ezXATPz2X4iK7lN2LGjSUPchYpb639hls+ilWWEbK5F/nxPkPQBObhuICFmXWEFMZLDYUIA8DtNLmQqG2/iTfwlx+gSWpbttIE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org; spf=pass smtp.mailfrom=makrotopia.org; arc=none smtp.client-ip=185.142.180.65 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=makrotopia.org Received: from local by pidgin.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.98.2) (envelope-from ) id 1utaXm-000000001Hw-2wGL; Tue, 02 Sep 2025 23:36:06 +0000 Date: Wed, 3 Sep 2025 00:36:03 +0100 From: Daniel Golle To: Hauke Mehrtens , Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Russell King , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Andreas Schirm , Lukas Stockmann , Alexander Sverdlin , Peter Christen , Avinash Jayaraman , Bing tao Xu , Liang Xu , Juraj Povazanec , "Fanni (Fang-Yi) Chan" , "Benny (Ying-Tsan) Weng" , "Livia M. Rosu" , John Crispin Subject: [RFC PATCH net-next 2/6] net: dsa: lantiq_gswip: convert trivial accessor uses to regmap Message-ID: <3906ead231ea6f62c22f45d2a50afdf5a9374a5a.1756855069.git.daniel@makrotopia.org> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use coccinelle semantic patch to convert all trivial uses of the register accessor functions to use the regmap API directly. // Replace gswip_switch_w with regmap_write @@ expression priv, val, offset; @@ - gswip_switch_w(priv, val, offset) + regmap_write(priv->gswip, offset, val) // Replace gswip_mdio_w with regmap_write @@ expression priv, val, offset; @@ - gswip_mdio_w(priv, val, offset) + regmap_write(priv->mdio, offset, val) // Replace gswip_switch_r in simple assignment - only for u32 @@ expression priv, offset; u32 var; @@ - var =3D gswip_switch_r(priv, offset) + regmap_read(priv->gswip, offset, &var) // Replace gswip_switch_mask with regmap_set_bits when clear is 0 @@ expression priv, set, offset; @@ - gswip_switch_mask(priv, 0, set, offset) + regmap_set_bits(priv->gswip, offset, set) // Replace gswip_mdio_mask with regmap_set_bits when clear is 0 @@ expression priv, set, offset; @@ - gswip_mdio_mask(priv, 0, set, offset) + regmap_set_bits(priv->mdio, offset, set) // Replace gswip_switch_mask with regmap_clear_bits when set is 0 @@ expression priv, clear, offset; @@ - gswip_switch_mask(priv, clear, 0, offset) + regmap_clear_bits(priv->gswip, offset, clear) // Replace gswip_mdio_mask with regmap_clear_bits when set is 0 @@ expression priv, clear, offset; @@ - gswip_mdio_mask(priv, clear, 0, offset) + regmap_clear_bits(priv->mdio, offset, clear) Remove gswip_switch_w() and gswip_mdio_w() functions as they now no longer have any users. Signed-off-by: Daniel Golle --- drivers/net/dsa/lantiq/lantiq_gswip.c | 176 ++++++++++++-------------- 1 file changed, 78 insertions(+), 98 deletions(-) diff --git a/drivers/net/dsa/lantiq/lantiq_gswip.c b/drivers/net/dsa/lantiq= /lantiq_gswip.c index 00de075b027a..4c46b8f0ab3d 100644 --- a/drivers/net/dsa/lantiq/lantiq_gswip.c +++ b/drivers/net/dsa/lantiq/lantiq_gswip.c @@ -126,17 +126,6 @@ static u32 gswip_switch_r(struct gswip_priv *priv, u32= offset) return val; } =20 -static void gswip_switch_w(struct gswip_priv *priv, u32 val, u32 offset) -{ - int ret; - - ret =3D regmap_write(priv->gswip, offset, val); - if (ret) { - WARN_ON_ONCE(1); - dev_err(priv->dev, "failed to write switch register\n"); - } -} - static void gswip_switch_mask(struct gswip_priv *priv, u32 clear, u32 set, u32 offset) { @@ -173,17 +162,6 @@ static u32 gswip_mdio_r(struct gswip_priv *priv, u32 o= ffset) return val; } =20 -static void gswip_mdio_w(struct gswip_priv *priv, u32 val, u32 offset) -{ - int ret; - - ret =3D regmap_write(priv->mdio, offset, val); - if (ret) { - WARN_ON_ONCE(1); - dev_err(priv->dev, "failed to write mdio register\n"); - } -} - static void gswip_mdio_mask(struct gswip_priv *priv, u32 clear, u32 set, u32 offset) { @@ -265,11 +243,11 @@ static int gswip_mdio_wr(struct mii_bus *bus, int add= r, int reg, u16 val) return err; } =20 - gswip_mdio_w(priv, val, GSWIP_MDIO_WRITE); - gswip_mdio_w(priv, GSWIP_MDIO_CTRL_BUSY | GSWIP_MDIO_CTRL_WR | - ((addr & GSWIP_MDIO_CTRL_PHYAD_MASK) << GSWIP_MDIO_CTRL_PHYAD_SHIFT) | - (reg & GSWIP_MDIO_CTRL_REGAD_MASK), - GSWIP_MDIO_CTRL); + regmap_write(priv->mdio, GSWIP_MDIO_WRITE, val); + regmap_write(priv->mdio, GSWIP_MDIO_CTRL, + GSWIP_MDIO_CTRL_BUSY | GSWIP_MDIO_CTRL_WR | + ((addr & GSWIP_MDIO_CTRL_PHYAD_MASK) << GSWIP_MDIO_CTRL_PHYAD_SHIFT= ) | + (reg & GSWIP_MDIO_CTRL_REGAD_MASK)); =20 return 0; } @@ -285,10 +263,10 @@ static int gswip_mdio_rd(struct mii_bus *bus, int add= r, int reg) return err; } =20 - gswip_mdio_w(priv, GSWIP_MDIO_CTRL_BUSY | GSWIP_MDIO_CTRL_RD | - ((addr & GSWIP_MDIO_CTRL_PHYAD_MASK) << GSWIP_MDIO_CTRL_PHYAD_SHIFT) | - (reg & GSWIP_MDIO_CTRL_REGAD_MASK), - GSWIP_MDIO_CTRL); + regmap_write(priv->mdio, GSWIP_MDIO_CTRL, + GSWIP_MDIO_CTRL_BUSY | GSWIP_MDIO_CTRL_RD | + ((addr & GSWIP_MDIO_CTRL_PHYAD_MASK) << GSWIP_MDIO_CTRL_PHYAD_SHIFT= ) | + (reg & GSWIP_MDIO_CTRL_REGAD_MASK)); =20 err =3D gswip_mdio_poll(priv); if (err) { @@ -352,7 +330,7 @@ static int gswip_pce_table_entry_read(struct gswip_priv= *priv, return err; } =20 - gswip_switch_w(priv, tbl->index, GSWIP_PCE_TBL_ADDR); + regmap_write(priv->gswip, GSWIP_PCE_TBL_ADDR, tbl->index); gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | GSWIP_PCE_TBL_CTRL_OPMOD_MASK, tbl->table | addr_mode | GSWIP_PCE_TBL_CTRL_BAS, @@ -402,24 +380,24 @@ static int gswip_pce_table_entry_write(struct gswip_p= riv *priv, return err; } =20 - gswip_switch_w(priv, tbl->index, GSWIP_PCE_TBL_ADDR); + regmap_write(priv->gswip, GSWIP_PCE_TBL_ADDR, tbl->index); gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | GSWIP_PCE_TBL_CTRL_OPMOD_MASK, tbl->table | addr_mode, GSWIP_PCE_TBL_CTRL); =20 for (i =3D 0; i < ARRAY_SIZE(tbl->key); i++) - gswip_switch_w(priv, tbl->key[i], GSWIP_PCE_TBL_KEY(i)); + regmap_write(priv->gswip, GSWIP_PCE_TBL_KEY(i), tbl->key[i]); =20 for (i =3D 0; i < ARRAY_SIZE(tbl->val); i++) - gswip_switch_w(priv, tbl->val[i], GSWIP_PCE_TBL_VAL(i)); + regmap_write(priv->gswip, GSWIP_PCE_TBL_VAL(i), tbl->val[i]); =20 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | GSWIP_PCE_TBL_CTRL_OPMOD_MASK, tbl->table | addr_mode, GSWIP_PCE_TBL_CTRL); =20 - gswip_switch_w(priv, tbl->mask, GSWIP_PCE_TBL_MASK); + regmap_write(priv->gswip, GSWIP_PCE_TBL_MASK, tbl->mask); =20 crtl =3D gswip_switch_r(priv, GSWIP_PCE_TBL_CTRL); crtl &=3D ~(GSWIP_PCE_TBL_CTRL_TYPE | GSWIP_PCE_TBL_CTRL_VLD | @@ -430,7 +408,7 @@ static int gswip_pce_table_entry_write(struct gswip_pri= v *priv, crtl |=3D GSWIP_PCE_TBL_CTRL_VLD; crtl |=3D (tbl->gmap << 7) & GSWIP_PCE_TBL_CTRL_GMAP_MASK; crtl |=3D GSWIP_PCE_TBL_CTRL_BAS; - gswip_switch_w(priv, crtl, GSWIP_PCE_TBL_CTRL); + regmap_write(priv->gswip, GSWIP_PCE_TBL_CTRL, crtl); =20 err =3D gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, GSWIP_PCE_TBL_CTRL_BAS); @@ -500,14 +478,13 @@ static int gswip_port_enable(struct dsa_switch *ds, i= nt port, } =20 /* RMON Counter Enable for port */ - gswip_switch_w(priv, GSWIP_BM_PCFG_CNTEN, GSWIP_BM_PCFGp(port)); + regmap_write(priv->gswip, GSWIP_BM_PCFGp(port), GSWIP_BM_PCFG_CNTEN); =20 /* enable port fetch/store dma & VLAN Modification */ - gswip_switch_mask(priv, 0, GSWIP_FDMA_PCTRL_EN | - GSWIP_FDMA_PCTRL_VLANMOD_BOTH, - GSWIP_FDMA_PCTRLp(port)); - gswip_switch_mask(priv, 0, GSWIP_SDMA_PCTRL_EN, - GSWIP_SDMA_PCTRLp(port)); + regmap_set_bits(priv->gswip, GSWIP_FDMA_PCTRLp(port), + GSWIP_FDMA_PCTRL_EN | GSWIP_FDMA_PCTRL_VLANMOD_BOTH); + regmap_set_bits(priv->gswip, GSWIP_SDMA_PCTRLp(port), + GSWIP_SDMA_PCTRL_EN); =20 return 0; } @@ -516,10 +493,10 @@ static void gswip_port_disable(struct dsa_switch *ds,= int port) { struct gswip_priv *priv =3D ds->priv; =20 - gswip_switch_mask(priv, GSWIP_FDMA_PCTRL_EN, 0, - GSWIP_FDMA_PCTRLp(port)); - gswip_switch_mask(priv, GSWIP_SDMA_PCTRL_EN, 0, - GSWIP_SDMA_PCTRLp(port)); + regmap_clear_bits(priv->gswip, GSWIP_FDMA_PCTRLp(port), + GSWIP_FDMA_PCTRL_EN); + regmap_clear_bits(priv->gswip, GSWIP_SDMA_PCTRLp(port), + GSWIP_SDMA_PCTRL_EN); } =20 static int gswip_pce_load_microcode(struct gswip_priv *priv) @@ -530,22 +507,22 @@ static int gswip_pce_load_microcode(struct gswip_priv= *priv) gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | GSWIP_PCE_TBL_CTRL_OPMOD_MASK, GSWIP_PCE_TBL_CTRL_OPMOD_ADWR, GSWIP_PCE_TBL_CTRL); - gswip_switch_w(priv, 0, GSWIP_PCE_TBL_MASK); + regmap_write(priv->gswip, GSWIP_PCE_TBL_MASK, 0); =20 for (i =3D 0; i < priv->hw_info->pce_microcode_size; i++) { - gswip_switch_w(priv, i, GSWIP_PCE_TBL_ADDR); - gswip_switch_w(priv, (*priv->hw_info->pce_microcode)[i].val_0, - GSWIP_PCE_TBL_VAL(0)); - gswip_switch_w(priv, (*priv->hw_info->pce_microcode)[i].val_1, - GSWIP_PCE_TBL_VAL(1)); - gswip_switch_w(priv, (*priv->hw_info->pce_microcode)[i].val_2, - GSWIP_PCE_TBL_VAL(2)); - gswip_switch_w(priv, (*priv->hw_info->pce_microcode)[i].val_3, - GSWIP_PCE_TBL_VAL(3)); + regmap_write(priv->gswip, GSWIP_PCE_TBL_ADDR, i); + regmap_write(priv->gswip, GSWIP_PCE_TBL_VAL(0), + (*priv->hw_info->pce_microcode)[i].val_0); + regmap_write(priv->gswip, GSWIP_PCE_TBL_VAL(1), + (*priv->hw_info->pce_microcode)[i].val_1); + regmap_write(priv->gswip, GSWIP_PCE_TBL_VAL(2), + (*priv->hw_info->pce_microcode)[i].val_2); + regmap_write(priv->gswip, GSWIP_PCE_TBL_VAL(3), + (*priv->hw_info->pce_microcode)[i].val_3); =20 /* start the table access: */ - gswip_switch_mask(priv, 0, GSWIP_PCE_TBL_CTRL_BAS, - GSWIP_PCE_TBL_CTRL); + regmap_set_bits(priv->gswip, GSWIP_PCE_TBL_CTRL, + GSWIP_PCE_TBL_CTRL_BAS); err =3D gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, GSWIP_PCE_TBL_CTRL_BAS); if (err) @@ -553,8 +530,8 @@ static int gswip_pce_load_microcode(struct gswip_priv *= priv) } =20 /* tell the switch that the microcode is loaded */ - gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_MC_VALID, - GSWIP_PCE_GCTRL_0); + regmap_set_bits(priv->gswip, GSWIP_PCE_GCTRL_0, + GSWIP_PCE_GCTRL_0_MC_VALID); =20 return 0; } @@ -580,8 +557,8 @@ static int gswip_port_vlan_filtering(struct dsa_switch = *ds, int port, GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR | GSWIP_PCE_VCTRL_VEMR, GSWIP_PCE_VCTRL(port)); - gswip_switch_mask(priv, GSWIP_PCE_PCTRL_0_TVM, 0, - GSWIP_PCE_PCTRL_0p(port)); + regmap_clear_bits(priv->gswip, GSWIP_PCE_PCTRL_0p(port), + GSWIP_PCE_PCTRL_0_TVM); } else { /* Use port based VLAN */ gswip_switch_mask(priv, @@ -589,8 +566,8 @@ static int gswip_port_vlan_filtering(struct dsa_switch = *ds, int port, GSWIP_PCE_VCTRL_VEMR, GSWIP_PCE_VCTRL_VSR, GSWIP_PCE_VCTRL(port)); - gswip_switch_mask(priv, 0, GSWIP_PCE_PCTRL_0_TVM, - GSWIP_PCE_PCTRL_0p(port)); + regmap_set_bits(priv->gswip, GSWIP_PCE_PCTRL_0p(port), + GSWIP_PCE_PCTRL_0_TVM); } =20 return 0; @@ -603,9 +580,9 @@ static int gswip_setup(struct dsa_switch *ds) struct dsa_port *cpu_dp; int err, i; =20 - gswip_switch_w(priv, GSWIP_SWRES_R0, GSWIP_SWRES); + regmap_write(priv->gswip, GSWIP_SWRES, GSWIP_SWRES_R0); usleep_range(5000, 10000); - gswip_switch_w(priv, 0, GSWIP_SWRES); + regmap_write(priv->gswip, GSWIP_SWRES, 0); =20 /* disable port fetch/store dma on all ports */ for (i =3D 0; i < priv->hw_info->max_ports; i++) { @@ -614,7 +591,7 @@ static int gswip_setup(struct dsa_switch *ds) } =20 /* enable Switch */ - gswip_mdio_mask(priv, 0, GSWIP_MDIO_GLOB_ENABLE, GSWIP_MDIO_GLOB); + regmap_set_bits(priv->mdio, GSWIP_MDIO_GLOB, GSWIP_MDIO_GLOB_ENABLE); =20 err =3D gswip_pce_load_microcode(priv); if (err) { @@ -623,9 +600,9 @@ static int gswip_setup(struct dsa_switch *ds) } =20 /* Default unknown Broadcast/Multicast/Unicast port maps */ - gswip_switch_w(priv, cpu_ports, GSWIP_PCE_PMAP1); - gswip_switch_w(priv, cpu_ports, GSWIP_PCE_PMAP2); - gswip_switch_w(priv, cpu_ports, GSWIP_PCE_PMAP3); + regmap_write(priv->gswip, GSWIP_PCE_PMAP1, cpu_ports); + regmap_write(priv->gswip, GSWIP_PCE_PMAP2, cpu_ports); + regmap_write(priv->gswip, GSWIP_PCE_PMAP3, cpu_ports); =20 /* Deactivate MDIO PHY auto polling. Some PHYs as the AR8030 have an * interoperability problem with this auto polling mechanism because @@ -643,7 +620,7 @@ static int gswip_setup(struct dsa_switch *ds) * Testing shows that when PHY auto polling is disabled these problems * go away. */ - gswip_mdio_w(priv, 0x0, GSWIP_MDIO_MDC_CFG0); + regmap_write(priv->mdio, GSWIP_MDIO_MDC_CFG0, 0x0); =20 /* Configure the MDIO Clock 2.5 MHz */ gswip_mdio_mask(priv, 0xff, 0x09, GSWIP_MDIO_MDC_CFG1); @@ -663,22 +640,25 @@ static int gswip_setup(struct dsa_switch *ds) =20 dsa_switch_for_each_cpu_port(cpu_dp, ds) { /* enable special tag insertion on cpu port */ - gswip_switch_mask(priv, 0, GSWIP_FDMA_PCTRL_STEN, - GSWIP_FDMA_PCTRLp(cpu_dp->index)); + regmap_set_bits(priv->gswip, GSWIP_FDMA_PCTRLp(cpu_dp->index), + GSWIP_FDMA_PCTRL_STEN); =20 /* accept special tag in ingress direction */ - gswip_switch_mask(priv, 0, GSWIP_PCE_PCTRL_0_INGRESS, - GSWIP_PCE_PCTRL_0p(cpu_dp->index)); + regmap_set_bits(priv->gswip, + GSWIP_PCE_PCTRL_0p(cpu_dp->index), + GSWIP_PCE_PCTRL_0_INGRESS); } =20 - gswip_switch_mask(priv, 0, GSWIP_BM_QUEUE_GCTRL_GL_MOD, - GSWIP_BM_QUEUE_GCTRL); + regmap_set_bits(priv->gswip, GSWIP_BM_QUEUE_GCTRL, + GSWIP_BM_QUEUE_GCTRL_GL_MOD); =20 /* VLAN aware Switching */ - gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_VLAN, GSWIP_PCE_GCTRL_0); + regmap_set_bits(priv->gswip, GSWIP_PCE_GCTRL_0, + GSWIP_PCE_GCTRL_0_VLAN); =20 /* Flush MAC Table */ - gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_MTFL, GSWIP_PCE_GCTRL_0); + regmap_set_bits(priv->gswip, GSWIP_PCE_GCTRL_0, + GSWIP_PCE_GCTRL_0_MTFL); =20 err =3D gswip_switch_r_timeout(priv, GSWIP_PCE_GCTRL_0, GSWIP_PCE_GCTRL_0_MTFL); @@ -817,7 +797,7 @@ static int gswip_vlan_add_unaware(struct gswip_priv *pr= iv, return err; } =20 - gswip_switch_w(priv, 0, GSWIP_PCE_DEFPVID(port)); + regmap_write(priv->gswip, GSWIP_PCE_DEFPVID(port), 0); return 0; } =20 @@ -892,7 +872,7 @@ static int gswip_vlan_add_aware(struct gswip_priv *priv, } =20 if (pvid) - gswip_switch_w(priv, idx, GSWIP_PCE_DEFPVID(port)); + regmap_write(priv->gswip, GSWIP_PCE_DEFPVID(port), idx); =20 return 0; } @@ -949,7 +929,7 @@ static int gswip_vlan_remove(struct gswip_priv *priv, =20 /* GSWIP 2.2 (GRX300) and later program here the VID directly. */ if (pvid) - gswip_switch_w(priv, 0, GSWIP_PCE_DEFPVID(port)); + regmap_write(priv->gswip, GSWIP_PCE_DEFPVID(port), 0); =20 return 0; } @@ -1127,8 +1107,8 @@ static void gswip_port_stp_state_set(struct dsa_switc= h *ds, int port, u8 state) =20 switch (state) { case BR_STATE_DISABLED: - gswip_switch_mask(priv, GSWIP_SDMA_PCTRL_EN, 0, - GSWIP_SDMA_PCTRLp(port)); + regmap_clear_bits(priv->gswip, GSWIP_SDMA_PCTRLp(port), + GSWIP_SDMA_PCTRL_EN); return; case BR_STATE_BLOCKING: case BR_STATE_LISTENING: @@ -1145,8 +1125,8 @@ static void gswip_port_stp_state_set(struct dsa_switc= h *ds, int port, u8 state) return; } =20 - gswip_switch_mask(priv, 0, GSWIP_SDMA_PCTRL_EN, - GSWIP_SDMA_PCTRLp(port)); + regmap_set_bits(priv->gswip, GSWIP_SDMA_PCTRLp(port), + GSWIP_SDMA_PCTRL_EN); gswip_switch_mask(priv, GSWIP_PCE_PCTRL_0_PSTATE_MASK, stp_state, GSWIP_PCE_PCTRL_0p(port)); } @@ -1272,19 +1252,19 @@ static int gswip_port_change_mtu(struct dsa_switch = *ds, int port, int new_mtu) */ if (dsa_is_cpu_port(ds, port)) { new_mtu +=3D 8; - gswip_switch_w(priv, VLAN_ETH_HLEN + new_mtu + ETH_FCS_LEN, - GSWIP_MAC_FLEN); + regmap_write(priv->gswip, GSWIP_MAC_FLEN, + VLAN_ETH_HLEN + new_mtu + ETH_FCS_LEN); } =20 /* Enable MLEN for ports with non-standard MTUs, including the special * header on the CPU port added above. */ if (new_mtu !=3D ETH_DATA_LEN) - gswip_switch_mask(priv, 0, GSWIP_MAC_CTRL_2_MLEN, - GSWIP_MAC_CTRL_2p(port)); + regmap_set_bits(priv->gswip, GSWIP_MAC_CTRL_2p(port), + GSWIP_MAC_CTRL_2_MLEN); else - gswip_switch_mask(priv, GSWIP_MAC_CTRL_2_MLEN, 0, - GSWIP_MAC_CTRL_2p(port)); + regmap_clear_bits(priv->gswip, GSWIP_MAC_CTRL_2p(port), + GSWIP_MAC_CTRL_2_MLEN); =20 return 0; } @@ -1586,7 +1566,7 @@ static u32 gswip_bcm_ram_entry_read(struct gswip_priv= *priv, u32 table, u32 result; int err; =20 - gswip_switch_w(priv, index, GSWIP_BM_RAM_ADDR); + regmap_write(priv->gswip, GSWIP_BM_RAM_ADDR, index); gswip_switch_mask(priv, GSWIP_BM_RAM_CTRL_ADDR_MASK | GSWIP_BM_RAM_CTRL_OPMOD, table | GSWIP_BM_RAM_CTRL_BAS, @@ -1600,7 +1580,7 @@ static u32 gswip_bcm_ram_entry_read(struct gswip_priv= *priv, u32 table, return 0; } =20 - result =3D gswip_switch_r(priv, GSWIP_BM_RAM_VAL(0)); + regmap_read(priv->gswip, GSWIP_BM_RAM_VAL(0), &result); result |=3D gswip_switch_r(priv, GSWIP_BM_RAM_VAL(1)) << 16; =20 return result; @@ -2001,7 +1981,7 @@ static int gswip_probe(struct platform_device *pdev) priv->ds->phylink_mac_ops =3D &gswip_phylink_mac_ops; priv->dev =3D dev; mutex_init(&priv->pce_table_lock); - version =3D gswip_switch_r(priv, GSWIP_VERSION); + regmap_read(priv->gswip, GSWIP_VERSION, &version); =20 /* The hardware has the 'major/minor' version bytes in the wrong order * preventing numerical comparisons. Construct a 16-bit unsigned integer @@ -2058,7 +2038,7 @@ static int gswip_probe(struct platform_device *pdev) return 0; =20 disable_switch: - gswip_mdio_mask(priv, GSWIP_MDIO_GLOB_ENABLE, 0, GSWIP_MDIO_GLOB); + regmap_clear_bits(priv->mdio, GSWIP_MDIO_GLOB, GSWIP_MDIO_GLOB_ENABLE); dsa_unregister_switch(priv->ds); gphy_fw_remove: for (i =3D 0; i < priv->num_gphy_fw; i++) @@ -2075,7 +2055,7 @@ static void gswip_remove(struct platform_device *pdev) return; =20 /* disable the switch */ - gswip_mdio_mask(priv, GSWIP_MDIO_GLOB_ENABLE, 0, GSWIP_MDIO_GLOB); + regmap_clear_bits(priv->mdio, GSWIP_MDIO_GLOB, GSWIP_MDIO_GLOB_ENABLE); =20 dsa_unregister_switch(priv->ds); =20 --=20 2.51.0 From nobody Fri Oct 3 08:47:49 2025 Received: from pidgin.makrotopia.org (pidgin.makrotopia.org [185.142.180.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 45B45126C05; Tue, 2 Sep 2025 23:36:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.142.180.65 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756856182; cv=none; b=Pvh2A4+NmNnBz0u3BSklsb+nAI0Zyy+SjsKDhHIDOL9ecjMYEqI8MnOHZu4BAtuyZxPuTC2zH/yO8vx+YSlBYA+EJWwHjYql3bpXmaReWrfRSmDgoOPJqvZsMyVQpu+YBkEl4K1WsgFE4YxRczrc8OjEQUed1X3pgMaP53GexMM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756856182; c=relaxed/simple; bh=2pIxf0HoF6Z6UiQch8+8jOIMygT02+QakPHOWqDwM94=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=fv9F0bcbLAVjPfVYbfhqGeiUjvJm8XSaMZKbCKa2hK+qIXQK7jNMxP3WzrO8ZOEZBDc7xWKbGgDoSFuj1P0onTFcpZGv3rKUetf8zYZy1AGhQOMW73f92utV0Z7/2BWTAVabME8MlcN4gCDLYIkDj4yCQKg2RRRmv1w11xaHgb4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org; spf=pass smtp.mailfrom=makrotopia.org; arc=none smtp.client-ip=185.142.180.65 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=makrotopia.org Received: from local by pidgin.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.98.2) (envelope-from ) id 1utaXw-000000001IK-2JIC; Tue, 02 Sep 2025 23:36:16 +0000 Date: Wed, 3 Sep 2025 00:36:13 +0100 From: Daniel Golle To: Hauke Mehrtens , Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Russell King , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Andreas Schirm , Lukas Stockmann , Alexander Sverdlin , Peter Christen , Avinash Jayaraman , Bing tao Xu , Liang Xu , Juraj Povazanec , "Fanni (Fang-Yi) Chan" , "Benny (Ying-Tsan) Weng" , "Livia M. Rosu" , John Crispin Subject: [RFC PATCH net-next 3/6] net: dsa: lantiq_gswip: manually convert remaining uses of read accessors Message-ID: <08a08504d030b8b9f4587097ef81e014acc98846.1756855069.git.daniel@makrotopia.org> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Manually convert the remaining uses of the read accessor functions and remove them now that they are unused. Signed-off-by: Daniel Golle --- drivers/net/dsa/lantiq/lantiq_gswip.c | 77 ++++++++++++--------------- 1 file changed, 34 insertions(+), 43 deletions(-) diff --git a/drivers/net/dsa/lantiq/lantiq_gswip.c b/drivers/net/dsa/lantiq= /lantiq_gswip.c index 4c46b8f0ab3d..7ba562f02b57 100644 --- a/drivers/net/dsa/lantiq/lantiq_gswip.c +++ b/drivers/net/dsa/lantiq/lantiq_gswip.c @@ -111,21 +111,6 @@ static const struct gswip_rmon_cnt_desc gswip_rmon_cnt= [] =3D { MIB_DESC(2, 0x0E, "TxGoodBytes"), }; =20 -static u32 gswip_switch_r(struct gswip_priv *priv, u32 offset) -{ - unsigned int val; - int ret; - - ret =3D regmap_read(priv->gswip, offset, &val); - if (ret) { - WARN_ON_ONCE(1); - dev_err(priv->dev, "failed to read switch register\n"); - return 0; - } - - return val; -} - static void gswip_switch_mask(struct gswip_priv *priv, u32 clear, u32 set, u32 offset) { @@ -147,21 +132,6 @@ static u32 gswip_switch_r_timeout(struct gswip_priv *p= riv, u32 offset, !(val & cleared), 20, 50000); } =20 -static u32 gswip_mdio_r(struct gswip_priv *priv, u32 offset) -{ - u32 val; - int ret; - - ret =3D regmap_read(priv->mdio, offset, &val); - if (ret) { - WARN_ON_ONCE(1); - dev_err(priv->dev, "failed to read mdio register\n"); - return 0; - } - - return val; -} - static void gswip_mdio_mask(struct gswip_priv *priv, u32 clear, u32 set, u32 offset) { @@ -255,6 +225,7 @@ static int gswip_mdio_wr(struct mii_bus *bus, int addr,= int reg, u16 val) static int gswip_mdio_rd(struct mii_bus *bus, int addr, int reg) { struct gswip_priv *priv =3D bus->priv; + u32 val; int err; =20 err =3D gswip_mdio_poll(priv); @@ -274,7 +245,11 @@ static int gswip_mdio_rd(struct mii_bus *bus, int addr= , int reg) return err; } =20 - return gswip_mdio_r(priv, GSWIP_MDIO_READ); + err =3D regmap_read(priv->mdio, GSWIP_MDIO_READ, &val); + if (err) + return err; + + return val; } =20 static int gswip_mdio(struct gswip_priv *priv) @@ -318,6 +293,7 @@ static int gswip_pce_table_entry_read(struct gswip_priv= *priv, int i; int err; u16 crtl; + u32 tmp; u16 addr_mode =3D tbl->key_mode ? GSWIP_PCE_TBL_CTRL_OPMOD_KSRD : GSWIP_PCE_TBL_CTRL_OPMOD_ADRD; =20 @@ -343,16 +319,29 @@ static int gswip_pce_table_entry_read(struct gswip_pr= iv *priv, return err; } =20 - for (i =3D 0; i < ARRAY_SIZE(tbl->key); i++) - tbl->key[i] =3D gswip_switch_r(priv, GSWIP_PCE_TBL_KEY(i)); - - for (i =3D 0; i < ARRAY_SIZE(tbl->val); i++) - tbl->val[i] =3D gswip_switch_r(priv, GSWIP_PCE_TBL_VAL(i)); + for (i =3D 0; i < ARRAY_SIZE(tbl->key); i++) { + err =3D regmap_read(priv->gswip, GSWIP_PCE_TBL_KEY(i), &tmp); + if (err) + return err; + tbl->key[i] =3D tmp; + } + for (i =3D 0; i < ARRAY_SIZE(tbl->val); i++) { + err =3D regmap_read(priv->gswip, GSWIP_PCE_TBL_VAL(i), &tmp); + if (err) + return err; + tbl->val[i] =3D tmp; + } =20 - tbl->mask =3D gswip_switch_r(priv, GSWIP_PCE_TBL_MASK); + err =3D regmap_read(priv->gswip, GSWIP_PCE_TBL_MASK, &tmp); + if (err) + return err; =20 - crtl =3D gswip_switch_r(priv, GSWIP_PCE_TBL_CTRL); + tbl->mask =3D tmp; + err =3D regmap_read(priv->gswip, GSWIP_PCE_TBL_CTRL, &tmp); + if (err) + return err; =20 + crtl =3D tmp; tbl->type =3D !!(crtl & GSWIP_PCE_TBL_CTRL_TYPE); tbl->valid =3D !!(crtl & GSWIP_PCE_TBL_CTRL_VLD); tbl->gmap =3D (crtl & GSWIP_PCE_TBL_CTRL_GMAP_MASK) >> 7; @@ -368,6 +357,7 @@ static int gswip_pce_table_entry_write(struct gswip_pri= v *priv, int i; int err; u16 crtl; + u32 tmp; u16 addr_mode =3D tbl->key_mode ? GSWIP_PCE_TBL_CTRL_OPMOD_KSWR : GSWIP_PCE_TBL_CTRL_OPMOD_ADWR; =20 @@ -399,9 +389,9 @@ static int gswip_pce_table_entry_write(struct gswip_pri= v *priv, =20 regmap_write(priv->gswip, GSWIP_PCE_TBL_MASK, tbl->mask); =20 - crtl =3D gswip_switch_r(priv, GSWIP_PCE_TBL_CTRL); - crtl &=3D ~(GSWIP_PCE_TBL_CTRL_TYPE | GSWIP_PCE_TBL_CTRL_VLD | - GSWIP_PCE_TBL_CTRL_GMAP_MASK); + regmap_read(priv->gswip, GSWIP_PCE_TBL_CTRL, &tmp); + crtl =3D tmp & ~(GSWIP_PCE_TBL_CTRL_TYPE | GSWIP_PCE_TBL_CTRL_VLD | + GSWIP_PCE_TBL_CTRL_GMAP_MASK); if (tbl->type) crtl |=3D GSWIP_PCE_TBL_CTRL_TYPE; if (tbl->valid) @@ -1563,7 +1553,7 @@ static void gswip_get_strings(struct dsa_switch *ds, = int port, u32 stringset, static u32 gswip_bcm_ram_entry_read(struct gswip_priv *priv, u32 table, u32 index) { - u32 result; + u32 result, val; int err; =20 regmap_write(priv->gswip, GSWIP_BM_RAM_ADDR, index); @@ -1581,7 +1571,8 @@ static u32 gswip_bcm_ram_entry_read(struct gswip_priv= *priv, u32 table, } =20 regmap_read(priv->gswip, GSWIP_BM_RAM_VAL(0), &result); - result |=3D gswip_switch_r(priv, GSWIP_BM_RAM_VAL(1)) << 16; + regmap_read(priv->gswip, GSWIP_BM_RAM_VAL(1), &val); + result |=3D val << 16; =20 return result; } --=20 2.51.0 From nobody Fri Oct 3 08:47:49 2025 Received: from pidgin.makrotopia.org (pidgin.makrotopia.org [185.142.180.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7469627FD72; Tue, 2 Sep 2025 23:36:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.142.180.65 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756856192; cv=none; b=Ipsot5dY56zCnRDt3XQ0hR4MPTU49rimUUzK7T9LFJcWDPm+e9hEzTXZvnGRNbHe8B5nK0mcOgOHRatBjwcgeDK3oWVSQeVe2zwyxA7r0UmgV06Uf0Hj5qV5F5L5OJcKDA8lS+0hxqJka++lgmchiFySHIDT68FaOsAd1JrH7qI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756856192; c=relaxed/simple; bh=QyV7zRqGf/Cods92Nyjkn7Q+43zQI1GpE39BoFbYpDc=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=jSeytibImEXqmwxAC9GrUX2V4Dj586uEEsMDlleW7VINPkolxDDMrwWjBjmiQwylXIIhcc/phenNKacS12ZpXKBn7neVF6iO+63FFn+4fX8fhO/1W4CuCqfO46i7qtSlZdD+lzxgd9qRyxUHiLnTgwgHyxB6tOa0U6s25cbxudc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org; spf=pass smtp.mailfrom=makrotopia.org; arc=none smtp.client-ip=185.142.180.65 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=makrotopia.org Received: from local by pidgin.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.98.2) (envelope-from ) id 1utaY5-000000001Iu-44fF; Tue, 02 Sep 2025 23:36:26 +0000 Date: Wed, 3 Sep 2025 00:36:22 +0100 From: Daniel Golle To: Hauke Mehrtens , Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Russell King , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Andreas Schirm , Lukas Stockmann , Alexander Sverdlin , Peter Christen , Avinash Jayaraman , Bing tao Xu , Liang Xu , Juraj Povazanec , "Fanni (Fang-Yi) Chan" , "Benny (Ying-Tsan) Weng" , "Livia M. Rosu" , John Crispin Subject: [RFC PATCH net-next 4/6] net: dsa: lantiq_gswip: replace *_mask() functions with regmap API Message-ID: <09e2fb66a9b4a35057c89160de4beb312f13b688.1756855069.git.daniel@makrotopia.org> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use coccinelle to replace all uses of *_mask() with an equivalent call to regmap_write_bits(). // Replace gswip_switch_mask with regmap_write_bits @@ expression priv, clear, set, offset; @@ - gswip_switch_mask(priv, clear, set, offset) + regmap_write_bits(priv->gswip, offset, clear | set, set) // Replace gswip_mdio_mask with regmap_write_bits @@ expression priv, clear, set, offset; @@ - gswip_mdio_mask(priv, clear, set, offset) + regmap_write_bits(priv->mdio, offset, clear | set, set) // Replace gswip_mii_mask with regmap_write_bits @@ expression priv, clear, set, offset; @@ - gswip_mii_mask(priv, clear, set, offset) + regmap_write_bits(priv->mii, offset, clear | set, set) Remove the new unused *_mask() functions. This naive approach will be further optmized manually in the next commit. Signed-off-by: Daniel Golle --- drivers/net/dsa/lantiq/lantiq_gswip.c | 148 +++++++++++--------------- 1 file changed, 63 insertions(+), 85 deletions(-) diff --git a/drivers/net/dsa/lantiq/lantiq_gswip.c b/drivers/net/dsa/lantiq= /lantiq_gswip.c index 7ba562f02b57..1fd18b3899b7 100644 --- a/drivers/net/dsa/lantiq/lantiq_gswip.c +++ b/drivers/net/dsa/lantiq/lantiq_gswip.c @@ -111,18 +111,6 @@ static const struct gswip_rmon_cnt_desc gswip_rmon_cnt= [] =3D { MIB_DESC(2, 0x0E, "TxGoodBytes"), }; =20 -static void gswip_switch_mask(struct gswip_priv *priv, u32 clear, u32 set, - u32 offset) -{ - int ret; - - ret =3D regmap_write_bits(priv->gswip, offset, clear | set, set); - if (ret) { - WARN_ON_ONCE(1); - dev_err(priv->dev, "failed to update switch register\n"); - } -} - static u32 gswip_switch_r_timeout(struct gswip_priv *priv, u32 offset, u32 cleared) { @@ -132,30 +120,6 @@ static u32 gswip_switch_r_timeout(struct gswip_priv *p= riv, u32 offset, !(val & cleared), 20, 50000); } =20 -static void gswip_mdio_mask(struct gswip_priv *priv, u32 clear, u32 set, - u32 offset) -{ - int ret; - - ret =3D regmap_write_bits(priv->mdio, offset, clear | set, set); - if (ret) { - WARN_ON_ONCE(1); - dev_err(priv->dev, "failed to update mdio register\n"); - } -} - -static void gswip_mii_mask(struct gswip_priv *priv, u32 clear, u32 set, - u32 offset) -{ - int ret; - - ret =3D regmap_write_bits(priv->mii, offset, clear | set, set); - if (ret) { - WARN_ON_ONCE(1); - dev_err(priv->dev, "failed to update mdio register\n"); - } -} - static void gswip_mii_mask_cfg(struct gswip_priv *priv, u32 clear, u32 set, int port) { @@ -167,7 +131,8 @@ static void gswip_mii_mask_cfg(struct gswip_priv *priv,= u32 clear, u32 set, =20 reg_port =3D port + priv->hw_info->mii_port_reg_offset; =20 - gswip_mii_mask(priv, clear, set, GSWIP_MII_CFGp(reg_port)); + regmap_write_bits(priv->mii, GSWIP_MII_CFGp(reg_port), clear | set, + set); } =20 static void gswip_mii_mask_pcdu(struct gswip_priv *priv, u32 clear, u32 se= t, @@ -183,13 +148,16 @@ static void gswip_mii_mask_pcdu(struct gswip_priv *pr= iv, u32 clear, u32 set, =20 switch (reg_port) { case 0: - gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU0); + regmap_write_bits(priv->mii, GSWIP_MII_PCDU0, clear | set, + set); break; case 1: - gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU1); + regmap_write_bits(priv->mii, GSWIP_MII_PCDU1, clear | set, + set); break; case 5: - gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU5); + regmap_write_bits(priv->mii, GSWIP_MII_PCDU5, clear | set, + set); break; } } @@ -307,10 +275,11 @@ static int gswip_pce_table_entry_read(struct gswip_pr= iv *priv, } =20 regmap_write(priv->gswip, GSWIP_PCE_TBL_ADDR, tbl->index); - gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | - GSWIP_PCE_TBL_CTRL_OPMOD_MASK, + regmap_write_bits(priv->gswip, GSWIP_PCE_TBL_CTRL, + GSWIP_PCE_TBL_CTRL_ADDR_MASK | + GSWIP_PCE_TBL_CTRL_OPMOD_MASK | tbl->table | addr_mode | GSWIP_PCE_TBL_CTRL_BAS, - GSWIP_PCE_TBL_CTRL); + tbl->table | addr_mode | GSWIP_PCE_TBL_CTRL_BAS); =20 err =3D gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, GSWIP_PCE_TBL_CTRL_BAS); @@ -371,10 +340,11 @@ static int gswip_pce_table_entry_write(struct gswip_p= riv *priv, } =20 regmap_write(priv->gswip, GSWIP_PCE_TBL_ADDR, tbl->index); - gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | - GSWIP_PCE_TBL_CTRL_OPMOD_MASK, + regmap_write_bits(priv->gswip, GSWIP_PCE_TBL_CTRL, + GSWIP_PCE_TBL_CTRL_ADDR_MASK | + GSWIP_PCE_TBL_CTRL_OPMOD_MASK | tbl->table | addr_mode, - GSWIP_PCE_TBL_CTRL); + tbl->table | addr_mode); =20 for (i =3D 0; i < ARRAY_SIZE(tbl->key); i++) regmap_write(priv->gswip, GSWIP_PCE_TBL_KEY(i), tbl->key[i]); @@ -382,10 +352,11 @@ static int gswip_pce_table_entry_write(struct gswip_p= riv *priv, for (i =3D 0; i < ARRAY_SIZE(tbl->val); i++) regmap_write(priv->gswip, GSWIP_PCE_TBL_VAL(i), tbl->val[i]); =20 - gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | - GSWIP_PCE_TBL_CTRL_OPMOD_MASK, + regmap_write_bits(priv->gswip, GSWIP_PCE_TBL_CTRL, + GSWIP_PCE_TBL_CTRL_ADDR_MASK | + GSWIP_PCE_TBL_CTRL_OPMOD_MASK | tbl->table | addr_mode, - GSWIP_PCE_TBL_CTRL); + tbl->table | addr_mode); =20 regmap_write(priv->gswip, GSWIP_PCE_TBL_MASK, tbl->mask); =20 @@ -463,8 +434,9 @@ static int gswip_port_enable(struct dsa_switch *ds, int= port, if (phydev) mdio_phy =3D phydev->mdio.addr & GSWIP_MDIO_PHY_ADDR_MASK; =20 - gswip_mdio_mask(priv, GSWIP_MDIO_PHY_ADDR_MASK, mdio_phy, - GSWIP_MDIO_PHYp(port)); + regmap_write_bits(priv->mdio, GSWIP_MDIO_PHYp(port), + GSWIP_MDIO_PHY_ADDR_MASK | mdio_phy, + mdio_phy); } =20 /* RMON Counter Enable for port */ @@ -494,9 +466,11 @@ static int gswip_pce_load_microcode(struct gswip_priv = *priv) int i; int err; =20 - gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | - GSWIP_PCE_TBL_CTRL_OPMOD_MASK, - GSWIP_PCE_TBL_CTRL_OPMOD_ADWR, GSWIP_PCE_TBL_CTRL); + regmap_write_bits(priv->gswip, GSWIP_PCE_TBL_CTRL, + GSWIP_PCE_TBL_CTRL_ADDR_MASK | + GSWIP_PCE_TBL_CTRL_OPMOD_MASK | + GSWIP_PCE_TBL_CTRL_OPMOD_ADWR, + GSWIP_PCE_TBL_CTRL_OPMOD_ADWR); regmap_write(priv->gswip, GSWIP_PCE_TBL_MASK, 0); =20 for (i =3D 0; i < priv->hw_info->pce_microcode_size; i++) { @@ -542,20 +516,24 @@ static int gswip_port_vlan_filtering(struct dsa_switc= h *ds, int port, =20 if (vlan_filtering) { /* Use tag based VLAN */ - gswip_switch_mask(priv, - GSWIP_PCE_VCTRL_VSR, - GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR | + regmap_write_bits(priv->gswip, GSWIP_PCE_VCTRL(port), + GSWIP_PCE_VCTRL_VSR | + GSWIP_PCE_VCTRL_UVR | + GSWIP_PCE_VCTRL_VIMR | GSWIP_PCE_VCTRL_VEMR, - GSWIP_PCE_VCTRL(port)); + GSWIP_PCE_VCTRL_UVR | + GSWIP_PCE_VCTRL_VIMR | + GSWIP_PCE_VCTRL_VEMR); regmap_clear_bits(priv->gswip, GSWIP_PCE_PCTRL_0p(port), GSWIP_PCE_PCTRL_0_TVM); } else { /* Use port based VLAN */ - gswip_switch_mask(priv, - GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR | - GSWIP_PCE_VCTRL_VEMR, + regmap_write_bits(priv->gswip, GSWIP_PCE_VCTRL(port), + GSWIP_PCE_VCTRL_UVR | + GSWIP_PCE_VCTRL_VIMR | + GSWIP_PCE_VCTRL_VEMR | GSWIP_PCE_VCTRL_VSR, - GSWIP_PCE_VCTRL(port)); + GSWIP_PCE_VCTRL_VSR); regmap_set_bits(priv->gswip, GSWIP_PCE_PCTRL_0p(port), GSWIP_PCE_PCTRL_0_TVM); } @@ -613,7 +591,7 @@ static int gswip_setup(struct dsa_switch *ds) regmap_write(priv->mdio, GSWIP_MDIO_MDC_CFG0, 0x0); =20 /* Configure the MDIO Clock 2.5 MHz */ - gswip_mdio_mask(priv, 0xff, 0x09, GSWIP_MDIO_MDC_CFG1); + regmap_write_bits(priv->mdio, GSWIP_MDIO_MDC_CFG1, 0xff | 0x09, 0x09); =20 /* bring up the mdio bus */ err =3D gswip_mdio(priv); @@ -1117,8 +1095,9 @@ static void gswip_port_stp_state_set(struct dsa_switc= h *ds, int port, u8 state) =20 regmap_set_bits(priv->gswip, GSWIP_SDMA_PCTRLp(port), GSWIP_SDMA_PCTRL_EN); - gswip_switch_mask(priv, GSWIP_PCE_PCTRL_0_PSTATE_MASK, stp_state, - GSWIP_PCE_PCTRL_0p(port)); + regmap_write_bits(priv->gswip, GSWIP_PCE_PCTRL_0p(port), + GSWIP_PCE_PCTRL_0_PSTATE_MASK | stp_state, + stp_state); } =20 static int gswip_port_fdb(struct dsa_switch *ds, int port, @@ -1344,8 +1323,8 @@ static void gswip_port_set_link(struct gswip_priv *pr= iv, int port, bool link) else mdio_phy =3D GSWIP_MDIO_PHY_LINK_DOWN; =20 - gswip_mdio_mask(priv, GSWIP_MDIO_PHY_LINK_MASK, mdio_phy, - GSWIP_MDIO_PHYp(port)); + regmap_write_bits(priv->mdio, GSWIP_MDIO_PHYp(port), + GSWIP_MDIO_PHY_LINK_MASK | mdio_phy, mdio_phy); } =20 static void gswip_port_set_speed(struct gswip_priv *priv, int port, int sp= eed, @@ -1385,11 +1364,11 @@ static void gswip_port_set_speed(struct gswip_priv = *priv, int port, int speed, break; } =20 - gswip_mdio_mask(priv, GSWIP_MDIO_PHY_SPEED_MASK, mdio_phy, - GSWIP_MDIO_PHYp(port)); + regmap_write_bits(priv->mdio, GSWIP_MDIO_PHYp(port), + GSWIP_MDIO_PHY_SPEED_MASK | mdio_phy, mdio_phy); gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_RATE_MASK, mii_cfg, port); - gswip_switch_mask(priv, GSWIP_MAC_CTRL_0_GMII_MASK, mac_ctrl_0, - GSWIP_MAC_CTRL_0p(port)); + regmap_write_bits(priv->gswip, GSWIP_MAC_CTRL_0p(port), + GSWIP_MAC_CTRL_0_GMII_MASK | mac_ctrl_0, mac_ctrl_0); } =20 static void gswip_port_set_duplex(struct gswip_priv *priv, int port, int d= uplex) @@ -1404,10 +1383,10 @@ static void gswip_port_set_duplex(struct gswip_priv= *priv, int port, int duplex) mdio_phy =3D GSWIP_MDIO_PHY_FDUP_DIS; } =20 - gswip_switch_mask(priv, GSWIP_MAC_CTRL_0_FDUP_MASK, mac_ctrl_0, - GSWIP_MAC_CTRL_0p(port)); - gswip_mdio_mask(priv, GSWIP_MDIO_PHY_FDUP_MASK, mdio_phy, - GSWIP_MDIO_PHYp(port)); + regmap_write_bits(priv->gswip, GSWIP_MAC_CTRL_0p(port), + GSWIP_MAC_CTRL_0_FDUP_MASK | mac_ctrl_0, mac_ctrl_0); + regmap_write_bits(priv->mdio, GSWIP_MDIO_PHYp(port), + GSWIP_MDIO_PHY_FDUP_MASK | mdio_phy, mdio_phy); } =20 static void gswip_port_set_pause(struct gswip_priv *priv, int port, @@ -1433,12 +1412,11 @@ static void gswip_port_set_pause(struct gswip_priv = *priv, int port, GSWIP_MDIO_PHY_FCONRX_DIS; } =20 - gswip_switch_mask(priv, GSWIP_MAC_CTRL_0_FCON_MASK, - mac_ctrl_0, GSWIP_MAC_CTRL_0p(port)); - gswip_mdio_mask(priv, - GSWIP_MDIO_PHY_FCONTX_MASK | - GSWIP_MDIO_PHY_FCONRX_MASK, - mdio_phy, GSWIP_MDIO_PHYp(port)); + regmap_write_bits(priv->gswip, GSWIP_MAC_CTRL_0p(port), + GSWIP_MAC_CTRL_0_FCON_MASK | mac_ctrl_0, mac_ctrl_0); + regmap_write_bits(priv->mdio, GSWIP_MDIO_PHYp(port), + GSWIP_MDIO_PHY_FCONTX_MASK | GSWIP_MDIO_PHY_FCONRX_MASK | mdio_phy, + mdio_phy); } =20 static void gswip_phylink_mac_config(struct phylink_config *config, @@ -1557,10 +1535,10 @@ static u32 gswip_bcm_ram_entry_read(struct gswip_pr= iv *priv, u32 table, int err; =20 regmap_write(priv->gswip, GSWIP_BM_RAM_ADDR, index); - gswip_switch_mask(priv, GSWIP_BM_RAM_CTRL_ADDR_MASK | - GSWIP_BM_RAM_CTRL_OPMOD, - table | GSWIP_BM_RAM_CTRL_BAS, - GSWIP_BM_RAM_CTRL); + regmap_write_bits(priv->gswip, GSWIP_BM_RAM_CTRL, + GSWIP_BM_RAM_CTRL_ADDR_MASK | GSWIP_BM_RAM_CTRL_OPMOD | + table | GSWIP_BM_RAM_CTRL_BAS, + table | GSWIP_BM_RAM_CTRL_BAS); =20 err =3D gswip_switch_r_timeout(priv, GSWIP_BM_RAM_CTRL, GSWIP_BM_RAM_CTRL_BAS); --=20 2.51.0 From nobody Fri Oct 3 08:47:50 2025 Received: from pidgin.makrotopia.org (pidgin.makrotopia.org [185.142.180.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7154F283FD8; Tue, 2 Sep 2025 23:36:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.142.180.65 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756856203; cv=none; b=plBFEvM9KP7nnkWoEyse5bdpIGf26s1Hp7r7URkEWLh8AwuQMfC/IaXf48ZLLjXa3YL0nXeEWECTPhrhuwi4bSNvQNLmj7o0Mpk3ZNDZEwUR70S38pEdpjaHIMhkDjsEi/5i1Q+qbkLSyKe6DTkQOBs3huCkwPnU3rQuOJue+as= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756856203; c=relaxed/simple; bh=SqW5rL6tPt8FEZ6wHBs4qEYofN3IQ+erQHIFkyk6/O8=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=OmR621UCtZ+KuK4q4Q6X5NoBVk3C0lI2G0r3rrIKVPv37aMdcpkFTTLJIcAiVBpUPCDKQPlk/fNw+zyhs9l4nNIzQzPHtv1WzCBTfprATmMWKiTEWFdiF2LqKDy8MbTOKGoqKvAacUF1vbF9yYiIFiPudeAl/zPS7MLMrupdrHI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org; spf=pass smtp.mailfrom=makrotopia.org; arc=none smtp.client-ip=185.142.180.65 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=makrotopia.org Received: from local by pidgin.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.98.2) (envelope-from ) id 1utaYF-000000001J9-3i0s; Tue, 02 Sep 2025 23:36:35 +0000 Date: Wed, 3 Sep 2025 00:36:32 +0100 From: Daniel Golle To: Hauke Mehrtens , Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Russell King , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Andreas Schirm , Lukas Stockmann , Alexander Sverdlin , Peter Christen , Avinash Jayaraman , Bing tao Xu , Liang Xu , Juraj Povazanec , "Fanni (Fang-Yi) Chan" , "Benny (Ying-Tsan) Weng" , "Livia M. Rosu" , John Crispin Subject: [RFC PATCH net-next 5/6] net: dsa: lantiq_gswip: optimize regmap_write_bits() statements Message-ID: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Further optimize the previous naive conversion of the *_mask() accessor functions to regmap_write_bits by manually removing redundant mask operands. Signed-off-by: Daniel Golle --- drivers/net/dsa/lantiq/lantiq_gswip.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/net/dsa/lantiq/lantiq_gswip.c b/drivers/net/dsa/lantiq= /lantiq_gswip.c index 1fd18b3899b7..b26daf39d3d2 100644 --- a/drivers/net/dsa/lantiq/lantiq_gswip.c +++ b/drivers/net/dsa/lantiq/lantiq_gswip.c @@ -278,7 +278,7 @@ static int gswip_pce_table_entry_read(struct gswip_priv= *priv, regmap_write_bits(priv->gswip, GSWIP_PCE_TBL_CTRL, GSWIP_PCE_TBL_CTRL_ADDR_MASK | GSWIP_PCE_TBL_CTRL_OPMOD_MASK | - tbl->table | addr_mode | GSWIP_PCE_TBL_CTRL_BAS, + GSWIP_PCE_TBL_CTRL_BAS, tbl->table | addr_mode | GSWIP_PCE_TBL_CTRL_BAS); =20 err =3D gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, @@ -342,8 +342,7 @@ static int gswip_pce_table_entry_write(struct gswip_pri= v *priv, regmap_write(priv->gswip, GSWIP_PCE_TBL_ADDR, tbl->index); regmap_write_bits(priv->gswip, GSWIP_PCE_TBL_CTRL, GSWIP_PCE_TBL_CTRL_ADDR_MASK | - GSWIP_PCE_TBL_CTRL_OPMOD_MASK | - tbl->table | addr_mode, + GSWIP_PCE_TBL_CTRL_OPMOD_MASK, tbl->table | addr_mode); =20 for (i =3D 0; i < ARRAY_SIZE(tbl->key); i++) @@ -354,8 +353,7 @@ static int gswip_pce_table_entry_write(struct gswip_pri= v *priv, =20 regmap_write_bits(priv->gswip, GSWIP_PCE_TBL_CTRL, GSWIP_PCE_TBL_CTRL_ADDR_MASK | - GSWIP_PCE_TBL_CTRL_OPMOD_MASK | - tbl->table | addr_mode, + GSWIP_PCE_TBL_CTRL_OPMOD_MASK, tbl->table | addr_mode); =20 regmap_write(priv->gswip, GSWIP_PCE_TBL_MASK, tbl->mask); --=20 2.51.0 From nobody Fri Oct 3 08:47:50 2025 Received: from pidgin.makrotopia.org (pidgin.makrotopia.org [185.142.180.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C7FA12DF15E; Tue, 2 Sep 2025 23:36:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.142.180.65 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756856212; cv=none; b=gNMktpKffF5fK1rffz7o7SpQEzZoR4rH7A5foxRvgiDRS3zw9kh3H/IAj4/bWGqzA7uWG2YmY6qA6t3MuckL/w8zf7TGp789n4q+r6IklDxcDfJ+e/2NV721U0F/X4g9m4Xs/RsX1NpCJR3s3V9Bg3+4LkFDu3bDlouPedR3yck= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756856212; c=relaxed/simple; bh=5c/GflacaImGqO9YWs2+t2235Nu4VL/PkkGmtZ+PqqA=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=hgQeBQ+EnNRRiIXiL8J3ZwLH8Csr+7a5AaTV/e8IBU7BKX4hMiJXKsYTdrDz/sYEXSw6jT1U9jub4xPOAMs5jqN5NcXz+D6AYNsxHADSbZfEkiU1CEJPPiDB92fdZXGe8NLR5mO6vBN8gONpiX/8meaTofht8aQfH3eJCSwNwvo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org; spf=pass smtp.mailfrom=makrotopia.org; arc=none smtp.client-ip=185.142.180.65 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=makrotopia.org Received: from local by pidgin.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.98.2) (envelope-from ) id 1utaYQ-000000001JY-05el; Tue, 02 Sep 2025 23:36:46 +0000 Date: Wed, 3 Sep 2025 00:36:42 +0100 From: Daniel Golle To: Hauke Mehrtens , Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Russell King , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Andreas Schirm , Lukas Stockmann , Alexander Sverdlin , Peter Christen , Avinash Jayaraman , Bing tao Xu , Liang Xu , Juraj Povazanec , "Fanni (Fang-Yi) Chan" , "Benny (Ying-Tsan) Weng" , "Livia M. Rosu" , John Crispin Subject: [RFC PATCH net-next 6/6] net: dsa: lantiq_gswip: harmonize gswip_mii_mask_*() parameters Message-ID: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The 'clear' parameter of gswip_mii_mask_cfg() and gswip_mii_mask_pcdu() is inconsistent with the semantics of regmap_write_bits() which also applies the mask to the value to be written. Change the semantic mask/set of the functions gswip_mii_mask_cfg() and gswip_mii_mask_pcdu() to follow the regmap_write_bits() pattern. Signed-off-by: Daniel Golle --- drivers/net/dsa/lantiq/lantiq_gswip.c | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/drivers/net/dsa/lantiq/lantiq_gswip.c b/drivers/net/dsa/lantiq= /lantiq_gswip.c index b26daf39d3d2..566536061886 100644 --- a/drivers/net/dsa/lantiq/lantiq_gswip.c +++ b/drivers/net/dsa/lantiq/lantiq_gswip.c @@ -120,7 +120,7 @@ static u32 gswip_switch_r_timeout(struct gswip_priv *pr= iv, u32 offset, !(val & cleared), 20, 50000); } =20 -static void gswip_mii_mask_cfg(struct gswip_priv *priv, u32 clear, u32 set, +static void gswip_mii_mask_cfg(struct gswip_priv *priv, u32 mask, u32 set, int port) { int reg_port; @@ -131,11 +131,11 @@ static void gswip_mii_mask_cfg(struct gswip_priv *pri= v, u32 clear, u32 set, =20 reg_port =3D port + priv->hw_info->mii_port_reg_offset; =20 - regmap_write_bits(priv->mii, GSWIP_MII_CFGp(reg_port), clear | set, + regmap_write_bits(priv->mii, GSWIP_MII_CFGp(reg_port), mask, set); } =20 -static void gswip_mii_mask_pcdu(struct gswip_priv *priv, u32 clear, u32 se= t, +static void gswip_mii_mask_pcdu(struct gswip_priv *priv, u32 mask, u32 set, int port) { int reg_port; @@ -148,16 +148,13 @@ static void gswip_mii_mask_pcdu(struct gswip_priv *pr= iv, u32 clear, u32 set, =20 switch (reg_port) { case 0: - regmap_write_bits(priv->mii, GSWIP_MII_PCDU0, clear | set, - set); + regmap_write_bits(priv->mii, GSWIP_MII_PCDU0, mask, set); break; case 1: - regmap_write_bits(priv->mii, GSWIP_MII_PCDU1, clear | set, - set); + regmap_write_bits(priv->mii, GSWIP_MII_PCDU1, mask, set); break; case 5: - regmap_write_bits(priv->mii, GSWIP_MII_PCDU5, clear | set, - set); + regmap_write_bits(priv->mii, GSWIP_MII_PCDU5, mask, set); break; } } @@ -1511,7 +1508,7 @@ static void gswip_phylink_mac_link_up(struct phylink_= config *config, gswip_port_set_pause(priv, port, tx_pause, rx_pause); } =20 - gswip_mii_mask_cfg(priv, 0, GSWIP_MII_CFG_EN, port); + gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, GSWIP_MII_CFG_EN, port); } =20 static void gswip_get_strings(struct dsa_switch *ds, int port, u32 strings= et, --=20 2.51.0