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Tue, 02 Sep 2025 05:24:00 -0700 (PDT) Received: from mva-rohm ([213.255.186.46]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-337f4c50f88sm4387551fa.13.2025.09.02.05.23.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Sep 2025 05:23:59 -0700 (PDT) Date: Tue, 2 Sep 2025 15:23:54 +0300 From: Matti Vaittinen To: Matti Vaittinen , Matti Vaittinen Cc: Jonathan Cameron , David Lechner , Nuno =?iso-8859-1?Q?S=E1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Bartosz Golaszewski , Matti Vaittinen , Marcelo Schmitt , Javier Carrasco , Tobias Sperling , Antoniu Miclaus , Trevor Gamblin , Esteban Blanc , Ramona Alexandra Nechita , Thomas Bonnefille , Hans de Goede , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org Subject: [PATCH 1/3] dt-bindings: iio: adc: ROHM BD79112 ADC/GPIO Message-ID: <77c36ecaf5992ebcabf6ce862bf2a6ec72d9f606.1756813980.git.mazziesaccount@gmail.com> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="tl6oCcfwafGdyC8p" Content-Disposition: inline In-Reply-To: --tl6oCcfwafGdyC8p Content-Disposition: inline Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The ROHM BD79112 is an ADC/GPIO with 32 channels. The channel inputs can be used as ADC or GPIO. Using the GPIOs as IRQ sources isn't supported. The ADC is 12-bit, supporting input voltages up to 5.7V, and separate I/O voltage supply. Maximum SPI clock rate is 20 MHz (10 MHz with daisy-chain configuration) and maximum sampling rate is 1MSPS. Add a device tree binding document for the ROHM BD79112. Signed-off-by: Matti Vaittinen --- .../bindings/iio/adc/rohm,bd79112.yaml | 118 ++++++++++++++++++ 1 file changed, 118 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/adc/rohm,bd79112.= yaml diff --git a/Documentation/devicetree/bindings/iio/adc/rohm,bd79112.yaml b/= Documentation/devicetree/bindings/iio/adc/rohm,bd79112.yaml new file mode 100644 index 000000000000..c340a05fbbda --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/rohm,bd79112.yaml @@ -0,0 +1,118 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/rohm,bd79112.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ROHM BD79112 ADC/GPO + +maintainers: + - Matti Vaittinen + +description: | + The ROHM BD79112 is a 12-bit, 32-channel, SAR ADC. ADC input pins can be + also configured as general purpose inputs/outputs. SPI should use MODE 3. + +properties: + compatible: + const: rohm,bd79112 + + reg: + maxItems: 1 + + spi-cpha: true + spi-cpol: true + + gpio-controller: true + + "#gpio-cells": + const: 1 + description: + The pin number. + + vdd-supply: true + + iovdd-supply: true + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^channel@([0-9]|[12][0-9]|3[01])$": + type: object + $ref: /schemas/iio/adc/adc.yaml# + description: Represents ADC channel. Omitted channels' inputs are GPIO= s. + + properties: + reg: + description: AIN pin number + minimum: 0 + maximum: 31 + + required: + - reg + + additionalProperties: false + +required: + - compatible + - reg + - iovdd-supply + - vdd-supply + - spi-cpha + - spi-cpol + +additionalProperties: false + +examples: + - | + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + adc: adc@0 { + compatible =3D "rohm,bd79112"; + reg =3D <0x0>; + + spi-cpha; + spi-cpol; + + vdd-supply =3D <&dummyreg>; + iovdd-supply =3D <&dummyreg>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + gpio-controller; + + channel@0 { + reg =3D <0>; + }; + channel@1 { + reg =3D <1>; + }; + channel@2 { + reg =3D <2>; + }; + channel@3 { + reg =3D <3>; + }; + channel@4 { + reg =3D <4>; + }; + channel@5 { + reg =3D <5>; + }; + channel@6 { + reg =3D <6>; + }; + channel@16 { + reg =3D <16>; + }; + channel@20 { + reg =3D <20>; + }; + }; + }; --=20 2.51.0 --tl6oCcfwafGdyC8p Content-Type: application/pgp-signature; name=signature.asc -----BEGIN PGP SIGNATURE----- iQEzBAEBCgAdFiEEIx+f8wZb28fLKEhTeFA3/03aocUFAmi24doACgkQeFA3/03a ocXwXgf/YrBxkSf2PjK8NQ0EGq8EPTQOX/KLapX0ICGGJOPSNHAGSvuoUImyxwC4 aoeoqAGoAegynOZsITfcuS50kkx6C6cEcwk2uswIKB2qhuCSR/WHyGs6D2J75x6m lj9gMUGGLjZsc94njLD4nxDP1KqdYL++Ir/llOBYJINod6CG0perT1M7ttMFswmL /c1X7E9cdBUUMkDChKIbxaHiKZOpY/AXu0q7LPa5Ynd9Bnmz5ypAYkVrHCCs8fAz f0kUmVlcu88qqtsjm5QHMqvy0sDTiBgSpoK+QtHm6RnPd0MyCqMFN2cb1c4Zjtig T09gDC9Cfl8gyUmQVe7wiJGzyOzihQ== =e4mD -----END PGP SIGNATURE----- --tl6oCcfwafGdyC8p-- From nobody Fri Oct 3 10:10:26 2025 Received: from mail-lj1-f182.google.com (mail-lj1-f182.google.com [209.85.208.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8DC3D81ACA; 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Tue, 02 Sep 2025 05:24:36 -0700 (PDT) Received: from mva-rohm ([213.255.186.46]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-337f5069b12sm4381651fa.48.2025.09.02.05.24.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Sep 2025 05:24:35 -0700 (PDT) Date: Tue, 2 Sep 2025 15:24:31 +0300 From: Matti Vaittinen To: Matti Vaittinen , Matti Vaittinen Cc: Jonathan Cameron , David Lechner , Nuno =?iso-8859-1?Q?S=E1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Bartosz Golaszewski , Matti Vaittinen , Marcelo Schmitt , Javier Carrasco , Tobias Sperling , Antoniu Miclaus , Trevor Gamblin , Esteban Blanc , Ramona Alexandra Nechita , Thomas Bonnefille , Hans de Goede , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org Subject: [PATCH 2/3] iio: adc: Support ROHM BD79112 ADC/GPIO Message-ID: <08929460fe11dd0b749c50a72a634423f13f4104.1756813980.git.mazziesaccount@gmail.com> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="Zll8XmoJ+NDqc7os" Content-Disposition: inline In-Reply-To: --Zll8XmoJ+NDqc7os Content-Disposition: inline Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The ROHM BD79112 is an ADC/GPIO with 32 channels. The channel inputs can be used as ADC or GPIO. Using the GPIOs as IRQ sources isn't supported. The ADC is 12-bit, supporting input voltages up to 5.7V, and separate I/O voltage supply. Maximum SPI clock rate is 20 MHz (10 MHz with daisy-chain configuration) and maximum sampling rate is 1MSPS. The IC does also support CRC but it is not implemented in the driver. Signed-off-by: Matti Vaittinen --- drivers/iio/adc/Kconfig | 10 + drivers/iio/adc/Makefile | 1 + drivers/iio/adc/rohm-bd79112.c | 542 +++++++++++++++++++++++++++++++++ 3 files changed, 553 insertions(+) create mode 100644 drivers/iio/adc/rohm-bd79112.c diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index e3d3826c3357..4b78929bb257 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -1309,6 +1309,16 @@ config RN5T618_ADC This driver can also be built as a module. If so, the module will be called rn5t618-adc. =20 +config ROHM_BD79112 + tristate "Rohm BD79112 ADC driver" + depends on I2C && GPIOLIB + select REGMAP_I2C + select IIO_ADC_HELPER + help + Say yes here to build support for the ROHM BD79112 ADC. The + ROHM BD79112 is a 12-bit, 32-channel, SAR ADC, which analog + inputs can also be used for GPIO. + config ROHM_BD79124 tristate "Rohm BD79124 ADC driver" depends on I2C diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index 89d72bf9ce70..34b40c34cf71 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -117,6 +117,7 @@ obj-$(CONFIG_QCOM_VADC_COMMON) +=3D qcom-vadc-common.o obj-$(CONFIG_RCAR_GYRO_ADC) +=3D rcar-gyroadc.o obj-$(CONFIG_RICHTEK_RTQ6056) +=3D rtq6056.o obj-$(CONFIG_RN5T618_ADC) +=3D rn5t618-adc.o +obj-$(CONFIG_ROHM_BD79112) +=3D rohm-bd79112.o obj-$(CONFIG_ROHM_BD79124) +=3D rohm-bd79124.o obj-$(CONFIG_ROCKCHIP_SARADC) +=3D rockchip_saradc.o obj-$(CONFIG_RZG2L_ADC) +=3D rzg2l_adc.o diff --git a/drivers/iio/adc/rohm-bd79112.c b/drivers/iio/adc/rohm-bd79112.c new file mode 100644 index 000000000000..84d9768fb343 --- /dev/null +++ b/drivers/iio/adc/rohm-bd79112.c @@ -0,0 +1,542 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * ROHM ADC driver for BD79112 signal monitoring hub. + * Copyright (C) 2025, ROHM Semiconductor. + * + * SPI communication derived from ad7923.c and ti-ads7950.c + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define BD79112_MAX_NUM_CHANNELS 32 + +struct bd79112_data { + struct spi_device *spi; + struct regmap *map; + struct device *dev; + struct gpio_chip gc; + unsigned long gpio_valid_mask; + unsigned int vref_mv; + struct spi_transfer read_xfer[2]; + struct spi_transfer write_xfer; + struct spi_message read_msg; + struct spi_message write_msg; + /* 16-bit TX, valid data in high byte */ + u8 read_tx[2] __aligned(IIO_DMA_MINALIGN); + /* 8-bit address followed by 8-bit data */ + u8 reg_write_tx[2] __aligned(IIO_DMA_MINALIGN); + /* 12-bit of ADC data or 8 bit of reg data */ + __be16 read_rx __aligned(IIO_DMA_MINALIGN); +}; + +/* + * The ADC data is read issuing SPI-command matching the channel number. + * We treat this as a register address. + */ +#define BD79112_REG_AGIO0A 0x0 +#define BD79112_REG_AGIO15B 0x1f + +/* + * ADC STATUS_FLAG appended to ADC data will be set, if the ADC result is = being + * read for a channel, which input pin is muxed to be a GPIO. + */ +#define BD79112_ADC_STATUS_FLAG BIT(14) + +/* + * The BD79112 requires "R/W bit" to be set for SPI register (not ADC data) + * reads and an "IO bit" to be set for read/write operations (which aren't + * reading the ADC data). + */ +#define BD79112_BIT_RW BIT(4) +#define BD79112_BIT_IO BIT(5) + +/* + * The data-sheet explains register I/O communication as follows: + * + * Read, two 16-bit sequences separated by CSB: + * MOSI: + * SCK: | 1 | 2 | 3 | 4 | 5 .. 8 | 9 .. 16 | + * data:| 0 | 0 |IOSET| RW (1) | ADDR | 8'b0 | + * + * MISO: + * SCK: | 1 .. 8 | 9 .. 16 | + * data:| 8'b0 | data | + * + * Note, CSB is shown to be released between writing the address (MOSI) and + * reading the register data (MISO). + * + * Write, single 16-bit sequence: + * MOSI: + * SCK: | 1 | 2 | 3 | 4 | 5 .. 8 | + * data:| 0 | 0 |IOSET| RW(0) | ADDR | + * + * MISO: + * SCK: | 1 .. 8 | + * data:| data | + * + */ + +#define BD79112_REG_GPI_VALUE_B8_15 (BD79112_BIT_IO | 0x0) +#define BD79112_REG_GPI_VALUE_B0_B7 (BD79112_BIT_IO | 0x1) +#define BD79112_REG_GPI_VALUE_A8_15 (BD79112_BIT_IO | 0x2) +#define BD79112_REG_GPI_VALUE_A0_A7 (BD79112_BIT_IO | 0x3) + +#define BD79112_REG_GPI_EN_B7_B15 (BD79112_BIT_IO | 0x4) +#define BD79112_REG_GPI_EN_B0_B7 (BD79112_BIT_IO | 0x5) +#define BD79112_REG_GPI_EN_A8_A15 (BD79112_BIT_IO | 0x6) +#define BD79112_REG_GPI_EN_A0_A7 (BD79112_BIT_IO | 0x7) + +#define BD79112_REG_GPO_EN_B7_B15 (BD79112_BIT_IO | 0x8) +#define BD79112_REG_GPO_EN_B0_B7 (BD79112_BIT_IO | 0x9) +#define BD79112_REG_GPO_EN_A8_A15 (BD79112_BIT_IO | 0xa) +#define BD79112_REG_GPO_EN_A0_A7 (BD79112_BIT_IO | 0xb) + +#define BD79112_NUM_GPIO_EN_REGS 8 +#define BD79112_FIRST_GPIO_EN_REG BD79112_REG_GPI_EN_B7_B15 + +#define BD79112_REG_GPO_VALUE_B8_15 (BD79112_BIT_IO | 0xc) +#define BD79112_REG_GPO_VALUE_B0_B7 (BD79112_BIT_IO | 0xd) +#define BD79112_REG_GPO_VALUE_A8_15 (BD79112_BIT_IO | 0xe) +#define BD79112_REG_GPO_VALUE_A0_A7 (BD79112_BIT_IO | 0xf) + +#define BD79112_REG_MAX BD79112_REG_GPO_VALUE_A0_A7 + +static int _get_gpio_reg(int offset, unsigned int base) +{ + int regoffset =3D offset / 8; + + if (offset > 31 || offset < 0) + return -EINVAL; + + return base - regoffset; +} + +#define GET_GPIO_BIT(offset) BIT((offset) % 8) +#define GET_GPO_EN_REG(offset) _get_gpio_reg((offset), BD79112_REG_GPO_EN= _A0_A7) +#define GET_GPI_EN_REG(offset) _get_gpio_reg((offset), BD79112_REG_GPI_EN= _A0_A7) +#define GET_GPO_VAL_REG(offset) _get_gpio_reg((offset), BD79112_REG_GPO_V= ALUE_A0_A7) +#define GET_GPI_VAL_REG(offset) _get_gpio_reg((offset), BD79112_REG_GPI_V= ALUE_A0_A7) + +static const struct regmap_range bd71815_volatile_ro_ranges[] =3D { + { + /* Read ADC data */ + .range_min =3D BD79112_REG_AGIO0A, + .range_max =3D BD79112_REG_AGIO15B, + }, { + /* GPI state */ + .range_min =3D BD79112_REG_GPI_VALUE_B8_15, + .range_max =3D BD79112_REG_GPI_VALUE_A0_A7, + }, +}; + +static const struct regmap_access_table bd79112_volatile_regs =3D { + .yes_ranges =3D &bd71815_volatile_ro_ranges[0], + .n_yes_ranges =3D ARRAY_SIZE(bd71815_volatile_ro_ranges), +}; + +static const struct regmap_access_table bd79112_ro_regs =3D { + .no_ranges =3D &bd71815_volatile_ro_ranges[0], + .n_no_ranges =3D ARRAY_SIZE(bd71815_volatile_ro_ranges), +}; + +static int bd79112_reg_read(void *context, unsigned int reg, unsigned int = *val) +{ + struct bd79112_data *data =3D context; + int ret; + + if (reg & BD79112_BIT_IO) + reg |=3D BD79112_BIT_RW; + + data->read_tx[0] =3D reg; + + ret =3D spi_sync(data->spi, &data->read_msg); + if (!ret) + *val =3D be16_to_cpu(data->read_rx); + + if (reg & BD79112_BIT_IO) + if (*val & BD79112_ADC_STATUS_FLAG) + dev_err(data->dev, "ADC pin configured as GPIO\n"); + + return ret; +} + +static int bd79112_reg_write(void *context, unsigned int reg, unsigned int= val) +{ + struct bd79112_data *data =3D context; + + data->reg_write_tx[0] =3D reg; + data->reg_write_tx[1] =3D val; + + return spi_sync(data->spi, &data->write_msg); +} + +static const struct regmap_config bd79112_regmap =3D { + .reg_read =3D bd79112_reg_read, + .reg_write =3D bd79112_reg_write, + .volatile_table =3D &bd79112_volatile_regs, + .wr_table =3D &bd79112_ro_regs, + .cache_type =3D REGCACHE_MAPLE, + .max_register =3D BD79112_REG_MAX, +}; + +static int bd79112_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int *val, + int *val2, long m) +{ + struct bd79112_data *data =3D iio_priv(indio_dev); + int ret; + + switch (m) { + case IIO_CHAN_INFO_RAW: + ret =3D regmap_read(data->map, chan->channel, val); + if (ret < 0) + return ret; + + return IIO_VAL_INT; + + case IIO_CHAN_INFO_SCALE: + *val =3D data->vref_mv; + *val2 =3D 12; + + return IIO_VAL_FRACTIONAL_LOG2; + } + + return -EINVAL; +} + +static const struct iio_info bd79112_info =3D { + .read_raw =3D bd79112_read_raw, +}; + +static const struct iio_chan_spec bd79112_chan_template =3D { + .type =3D IIO_VOLTAGE, + .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW), + .info_mask_shared_by_type =3D BIT(IIO_CHAN_INFO_SCALE), + .indexed =3D 1, +}; + +static int bd79112_gpio_init_valid_mask(struct gpio_chip *gc, + unsigned long *valid_mask, + unsigned int ngpios) +{ + struct bd79112_data *data =3D gpiochip_get_data(gc); + + *valid_mask =3D data->gpio_valid_mask; + + return 0; +} + +static int bd79112_gpio_dir_get(struct gpio_chip *gc, unsigned int offset) +{ + struct bd79112_data *data =3D gpiochip_get_data(gc); + unsigned int reg, bit, val; + int ret; + + bit =3D GET_GPIO_BIT(offset); + reg =3D GET_GPO_EN_REG(offset); + + ret =3D regmap_read(data->map, reg, &val); + if (ret) + return ret; + + if (bit & val) + return GPIO_LINE_DIRECTION_OUT; + + reg =3D GET_GPI_EN_REG(offset); + ret =3D regmap_read(data->map, reg, &val); + if (ret) + return ret; + + if (bit & val) + return GPIO_LINE_DIRECTION_IN; + + /* + * Ouch. Seems the pin is ADC input - shouldn't happen as changing mux + * at runtime is not supported and non GPIO pins should be invalidated + * by the valid_mask at probe. Maybe someone wrote register bypassing + * the driver? + */ + dev_err(data->dev, "Pin not a GPIO\n"); + + return -EINVAL; +} + +static int bd79112_gpio_get(struct gpio_chip *gc, unsigned int offset) +{ + struct bd79112_data *data =3D gpiochip_get_data(gc); + unsigned int reg, bit, val; + int ret; + + bit =3D GET_GPIO_BIT(offset); + reg =3D GET_GPI_VAL_REG(offset); + + ret =3D regmap_read(data->map, reg, &val); + if (ret) + return ret; + + return !!(val & bit); +} + +static int bd79112_gpio_set(struct gpio_chip *gc, unsigned int offset, + int value) +{ + struct bd79112_data *data =3D gpiochip_get_data(gc); + unsigned int reg, bit; + + bit =3D GET_GPIO_BIT(offset); + reg =3D GET_GPO_VAL_REG(offset); + + return regmap_assign_bits(data->map, reg, bit, value); +} + +static int bd79112_gpio_set_multiple(struct gpio_chip *gc, unsigned long *= mask, + unsigned long *bits) +{ + struct bd79112_data *data =3D gpiochip_get_data(gc); + unsigned int i; + + for (i =3D 0; i < 4; i++) { + unsigned int bank_mask, reg, regval, regmask; + int ret; + + bank_mask =3D 0xff << 8 * i; + regmask =3D (*mask & bank_mask) << 8 * i; + + if (!regmask) + continue; + + reg =3D BD79112_REG_GPO_VALUE_A0_A7 - i; + regval =3D (*bits & bank_mask) >> 8 * i; + ret =3D regmap_update_bits(data->map, reg, regmask, regval); + if (ret) + return ret; + } + + return 0; +} + +static int bd79112_gpio_dir_set(struct bd79112_data *data, unsigned int of= fset, + int dir) +{ + unsigned int set_reg, clear_reg, bit; + int ret; + + bit =3D GET_GPIO_BIT(offset); + + if (dir =3D=3D GPIO_LINE_DIRECTION_IN) { + set_reg =3D GET_GPI_EN_REG(offset); + clear_reg =3D GET_GPO_EN_REG(offset); + } else { + set_reg =3D GET_GPO_EN_REG(offset); + clear_reg =3D GET_GPI_EN_REG(offset); + } + + ret =3D regmap_set_bits(data->map, set_reg, bit); + if (ret) + return ret; + + return regmap_clear_bits(data->map, clear_reg, bit); +} + +static int bd79112_gpio_input(struct gpio_chip *gc, unsigned int offset) +{ + struct bd79112_data *data =3D gpiochip_get_data(gc); + + return bd79112_gpio_dir_set(data, offset, GPIO_LINE_DIRECTION_IN); +} + +static int bd79112_gpio_output(struct gpio_chip *gc, unsigned int offset, + int value) +{ + struct bd79112_data *data =3D gpiochip_get_data(gc); + int ret; + + ret =3D bd79112_gpio_set(gc, offset, value); + if (ret) + return ret; + + return bd79112_gpio_dir_set(data, offset, GPIO_LINE_DIRECTION_OUT); +} + +static const struct gpio_chip bd79112_gpio_chip =3D { + .label =3D "bd79112-gpio", + .get_direction =3D bd79112_gpio_dir_get, + .direction_input =3D bd79112_gpio_input, + .direction_output =3D bd79112_gpio_output, + .get =3D bd79112_gpio_get, + .set =3D bd79112_gpio_set, + .set_multiple =3D bd79112_gpio_set_multiple, + .init_valid_mask =3D bd79112_gpio_init_valid_mask, + .can_sleep =3D true, + .ngpio =3D 32, + .base =3D -1, +}; + +static int bd79112_get_gpio_pins(const struct iio_chan_spec *cs, int num_c= hannels) +{ + int i, gpio_channels; + + /* + * Let's initialize the mux config to say that all 32 channels are + * GPIOs. Then we can just loop through the iio_chan_spec and clear the + * bits for found ADC channels. + */ + gpio_channels =3D GENMASK(31, 0); + for (i =3D 0; i < num_channels; i++) + gpio_channels &=3D ~BIT(cs[i].channel); + + return gpio_channels; +} + +static int bd79112_probe(struct spi_device *spi) +{ + /* ADC channels as named in the data-sheet */ + static const char * const chan_names[] =3D { + "AGIO0A", "AGIO1A", "AGIO2A", "AGIO3A", "AGIO4A", "AGIO5A", + "AGIO6A", "AGIO7A", "AGIO8A", "AGIO9A", "AGIO10A", "AGIO11A", + "AGIO11A", "AGIO12A", "AGIO13A", "AGIO14A", "AGIO15A", + "AGIO0B", "AGIO1B", "AGIO2B", "AGIO3B", "AGIO4B", "AGIO5B", + "AGIO6B", "AGIO7B", "AGIO8B", "AGIO9B", "AGIO10B", "AGIO11B", + "AGIO11B", "AGIO12B", "AGIO13B", "AGIO14B", "AGIO15B", + }; + struct bd79112_data *data; + struct iio_dev *iio_dev; + struct iio_chan_spec *cs; + struct device *dev =3D &spi->dev; + unsigned long gpio_pins, pin; + unsigned int i; + int ret; + + iio_dev =3D devm_iio_device_alloc(dev, sizeof(*data)); + if (!iio_dev) + return -ENOMEM; + + data =3D iio_priv(iio_dev); + data->spi =3D spi; + data->dev =3D dev; + data->map =3D devm_regmap_init(&spi->dev, NULL, data, &bd79112_regmap); + if (IS_ERR(data->map)) + return dev_err_probe(dev, PTR_ERR(data->map), + "Failed to initialize Regmap\n"); + + ret =3D devm_regulator_get_enable_read_voltage(dev, "vdd"); + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to get the Vdd\n"); + + data->vref_mv =3D ret / 1000; + + ret =3D devm_regulator_get_enable(dev, "iovdd"); + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to enable I/O voltage\n"); + + data->read_xfer[0].tx_buf =3D &data->read_tx[0]; + data->read_xfer[0].len =3D sizeof(data->read_tx); + data->read_xfer[0].cs_change =3D 1; + data->read_xfer[1].rx_buf =3D &data->read_rx; + data->read_xfer[1].len =3D sizeof(data->read_rx); + spi_message_init_with_transfers(&data->read_msg, data->read_xfer, 2); + + data->write_xfer.tx_buf =3D &data->reg_write_tx[0]; + data->write_xfer.len =3D sizeof(data->reg_write_tx); + spi_message_init_with_transfers(&data->write_msg, &data->write_xfer, 1); + + ret =3D devm_iio_adc_device_alloc_chaninfo_se(dev, &bd79112_chan_template, + BD79112_MAX_NUM_CHANNELS - 1, &cs); + if (ret < 0) { + /* Register all pins as GPIOs if there are no ADC channels */ + if (ret =3D=3D -ENOENT) + goto register_gpios; + + return ret; + } + + /* Let's assign data-sheet names to channels */ + for (i =3D 0; i < iio_dev->num_channels; i++) { + unsigned int ch =3D cs[i].channel; + + cs[i].datasheet_name =3D chan_names[ch]; + } + + iio_dev->channels =3D cs; + iio_dev->num_channels =3D ret; + iio_dev->info =3D &bd79112_info; + iio_dev->name =3D "bd79112"; + iio_dev->modes =3D INDIO_DIRECT_MODE; + + /* + * Ensure all channels are ADCs. This allows us to register the IIO + * device early (before checking which pins are to be used for GPIO) + * without having to worry about some pins being initially used for + * GPIO. + */ + for (i =3D 0; i < BD79112_NUM_GPIO_EN_REGS; i++) { + ret =3D regmap_write(data->map, BD79112_FIRST_GPIO_EN_REG + i, 0); + if (ret) + return dev_err_probe(dev, ret, + "Failed to initialize channels\n"); + } + + ret =3D devm_iio_device_register(data->dev, iio_dev); + if (ret) + return dev_err_probe(data->dev, ret, "Failed to register ADC\n"); + +register_gpios: + gpio_pins =3D bd79112_get_gpio_pins(iio_dev->channels, + iio_dev->num_channels); + + /* We're done if all channels are reserved for ADC. */ + if (!gpio_pins) + return 0; + + /* Default all the GPIO pins to GPI */ + for_each_set_bit(pin, &gpio_pins, BD79112_MAX_NUM_CHANNELS) { + ret =3D bd79112_gpio_dir_set(data, pin, GPIO_LINE_DIRECTION_IN); + if (ret) + return dev_err_probe(dev, ret, + "Failed to mark pin as GPI\n"); + } + + data->gpio_valid_mask =3D gpio_pins; + data->gc =3D bd79112_gpio_chip; + data->gc.parent =3D dev; + + return devm_gpiochip_add_data(dev, &data->gc, data); +} + +static const struct of_device_id bd79112_of_match[] =3D { + { .compatible =3D "rohm,bd79112" }, + { } +}; +MODULE_DEVICE_TABLE(of, bd79112_of_match); + +static const struct spi_device_id bd79112_id[] =3D { + { "bd79112" }, + { } +}; +MODULE_DEVICE_TABLE(spi, bd79112_id); + +static struct spi_driver bd79112_driver =3D { + .driver =3D { + .name =3D "bd79112", + .of_match_table =3D bd79112_of_match, + }, + .probe =3D bd79112_probe, + .id_table =3D bd79112_id, +}; +module_spi_driver(bd79112_driver); + +MODULE_AUTHOR("Matti Vaittinen "); +MODULE_DESCRIPTION("Driver for ROHM BD79112 ADC/GPIO"); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("IIO_DRIVER"); --=20 2.51.0 --Zll8XmoJ+NDqc7os Content-Type: application/pgp-signature; name=signature.asc -----BEGIN PGP SIGNATURE----- iQEzBAEBCgAdFiEEIx+f8wZb28fLKEhTeFA3/03aocUFAmi24f8ACgkQeFA3/03a ocWLqwf7BGIsP2QG5W+SCZqnISivWZ1+7RS9oFB/qTw7TTxh18JnoN+EYy1L3iYH HjWn96d1iwAqQ0wqkRnJEnEjKrWIN8Np0kNoRSeFvI+mzqzvz5MI3cJQsI9MY+YK QQDh7BWMMjntOL17kyFjmOKTNEqRc/Dj/0ttKYuSICFtBqd7mYgLyY1jPCsGQKqX D7KJ3J4iSBDDMPa8YKZTrKbK7KM/Zvyy5DMy4rbapdrSQgWhV4WAaA3KaiqRtZL6 hr+jxKDFXxWwmhUR+IAxw9zLFL8/DiWa3+nBli20M0kG6t2XP00r+9iChoUg75dP 5i4YtD2zwN3cqHM/0aBVqQIZlmjRzw== =Qc1g -----END PGP SIGNATURE----- --Zll8XmoJ+NDqc7os-- From nobody Fri Oct 3 10:10:26 2025 Received: from mail-lf1-f44.google.com (mail-lf1-f44.google.com [209.85.167.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 61FED212574; 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Tue, 02 Sep 2025 05:30:54 -0700 (PDT) Received: from mva-rohm ([213.255.186.46]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-560826d1137sm678207e87.10.2025.09.02.05.30.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Sep 2025 05:30:53 -0700 (PDT) Date: Tue, 2 Sep 2025 15:30:48 +0300 From: Matti Vaittinen To: Matti Vaittinen , Matti Vaittinen Cc: Jonathan Cameron , David Lechner , Nuno =?iso-8859-1?Q?S=E1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matti Vaittinen , Linus Walleij , Bartosz Golaszewski , Marcelo Schmitt , Javier Carrasco , Tobias Sperling , Antoniu Miclaus , Trevor Gamblin , Esteban Blanc , Eason Yang , Alisa-Dariana Roman , Thomas Bonnefille , Pop Ioan Daniel , Ana-Maria Cusco , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org Subject: [PATCH 3/3] MAINTAINERS: Support ROHM BD79112 ADC Message-ID: <2af3a3ec00c4a21bd9df2b1746b96e0b84080b92.1756813980.git.mazziesaccount@gmail.com> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="LQvTRu61ZzJ2UjtA" Content-Disposition: inline In-Reply-To: --LQvTRu61ZzJ2UjtA Content-Disposition: inline Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add the ROHM BD79112 ADC in the list of the BD791xx ADC drivers which are maintained by undersigned. Signed-off-by: Matti Vaittinen --- This patch got some last minute changes after other patches were already sent. I hope I got the message-IDs right - but if I didin't - I'm sorry. In that case I'll re-spin series after some delay :) MAINTAINERS | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index af1c8d2bfb3d..8e78a1168c17 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21864,9 +21864,10 @@ S: Supported F: drivers/power/supply/bd99954-charger.c F: drivers/power/supply/bd99954-charger.h =20 -ROHM BD79124 ADC / GPO IC +ROHM BD791xx ADC / GPO IC M: Matti Vaittinen S: Supported +F: drivers/iio/adc/rohm-bd79112.c F: drivers/iio/adc/rohm-bd79124.c =20 ROHM BH1745 COLOUR SENSOR --=20 2.51.0 --LQvTRu61ZzJ2UjtA Content-Type: application/pgp-signature; name=signature.asc -----BEGIN PGP SIGNATURE----- iQEzBAEBCgAdFiEEIx+f8wZb28fLKEhTeFA3/03aocUFAmi243gACgkQeFA3/03a ocUBzQf+IzkBnlIznAD2RxHhu6rZUnGRgCKBWdPvTcAGue3HUdtFr6vB2s+afHaH HWTFTtgXiaDEdvIlDuiRqrCjODgx+b3QCU645Sj1Eh9PP7Uwbl16NmLFTUIXIkqY qk+qC8KHZ/lJk1XbVKNKUWfvk8zJMWq6XEFrNJfYDwsLqYNv41esa/VquR11HIB8 KzY6PHS/62kLm8VxzGcK/GWvb0FB3mf1AwARw3E+Uc17idDGtPRIvQORPV0U+Q9N roYvRbIJPvgPouwb+99rzJVZ6CU26IIg1ubjrL4oLbC6HcbLEpEn90wPolJjZK9a LDti2BfOT20YnOH/27C1F4a5937K3w== =32le -----END PGP SIGNATURE----- --LQvTRu61ZzJ2UjtA--