From nobody Sun Dec 14 07:50:22 2025 Received: from pegase2.c-s.fr (pegase2.c-s.fr [93.17.235.10]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D9EFD31DD9A; Mon, 1 Sep 2025 12:20:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=93.17.235.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756729255; cv=none; b=uZNDq+qHVUddBOSUh7dLr4UY+TIKzhJPrqEOIxutWC9Y6XYj+ipIOeqH4+qI9XUrSGU39dK+dXEh9UdrcXpfTMTmxX6/eEq7p2Kyt9Wq6qNV6iAQpVngybVuvl8j/83OWY4VTinDPbrfcABMnKtLoNzYaujhvEWecfGchQWxzkE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756729255; c=relaxed/simple; bh=G7scsgL+yrYA4D+2n/22/LhhZgPYYRLFCIoU4FAox1M=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=tH+JyZDciJQXAgeKMxDIMAVW2P0DZtiZG82w8xpcUAScEXQPOCien8eTtmdJfczsBQ2+SD7PY9e+0DSiC3E6HN616p6Js2r+kDLcNqO+m30MSZj4b+lxOKsbWrMxafD3OtoNPKDKmwFcSMCtChfmo8QN83+zhbYXpt+A6rsw1Pw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=csgroup.eu; spf=pass smtp.mailfrom=csgroup.eu; arc=none smtp.client-ip=93.17.235.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=csgroup.eu Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=csgroup.eu Received: from localhost (mailhub4.si.c-s.fr [172.26.127.67]) by localhost (Postfix) with ESMTP id 4cFndD0jHzz9sSt; Mon, 1 Sep 2025 14:05:36 +0200 (CEST) X-Virus-Scanned: amavisd-new at c-s.fr Received: from pegase2.c-s.fr ([172.26.127.65]) by localhost (pegase2.c-s.fr [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id xYKkqZEcVcMN; Mon, 1 Sep 2025 14:05:36 +0200 (CEST) Received: from messagerie.si.c-s.fr (messagerie.si.c-s.fr [192.168.25.192]) by pegase2.c-s.fr (Postfix) with ESMTP id 4cFndC2JMCz9sSb; Mon, 1 Sep 2025 14:05:35 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by messagerie.si.c-s.fr (Postfix) with ESMTP id 365E48B790; Mon, 1 Sep 2025 14:05:35 +0200 (CEST) X-Virus-Scanned: amavisd-new at c-s.fr Received: from messagerie.si.c-s.fr ([127.0.0.1]) by localhost (messagerie.si.c-s.fr [127.0.0.1]) (amavisd-new, port 10023) with ESMTP id V01hOpFiDPpU; Mon, 1 Sep 2025 14:05:35 +0200 (CEST) Received: from PO20335.idsi0.si.c-s.fr (unknown [10.25.207.160]) by messagerie.si.c-s.fr (Postfix) with ESMTP id 003E48B78C; Mon, 1 Sep 2025 14:05:34 +0200 (CEST) From: Christophe Leroy To: Qiang Zhao , Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Christophe Leroy , linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v5 1/7] soc: fsl: qe: Add an interrupt controller for QUICC Engine Ports Date: Mon, 1 Sep 2025 14:05:08 +0200 Message-ID: <5d7d9e236b638519b210d8401982a8c275520f25.1756727747.git.christophe.leroy@csgroup.eu> X-Mailer: git-send-email 2.49.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756728308; l=5183; i=christophe.leroy@csgroup.eu; s=20211009; h=from:subject:message-id; bh=G7scsgL+yrYA4D+2n/22/LhhZgPYYRLFCIoU4FAox1M=; b=3pUtK+QB1fKQzXx+BZc8q7IwWOWqvoZ7mDNJ3iBLQy0CPXl83KHuczuRMxqrHjlrpue9UcnlH e48EMSGUVW1CYMRb24pqE+cf64x9JChqyLf4vrMxyhEkjA058uLYTNp X-Developer-Key: i=christophe.leroy@csgroup.eu; a=ed25519; pk=HIzTzUj91asvincQGOFx6+ZF5AoUuP9GdOtQChs7Mm0= Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The QUICC Engine provides interrupts for a few I/O ports. This is handled via a separate interrupt ID and managed via a triplet of dedicated registers hosted by the SoC. Implement an interrupt driver for it for that those IRQs can then be linked to the related GPIOs. The number of ports for which interrupts are supported depends on the microcontroller: - mpc8323 has 10 interrupts - mpc8360 has 28 interrupts - mpc8568 has 18 interrupts So add this information as data of the compatible. Signed-off-by: Christophe Leroy --- drivers/soc/fsl/qe/Makefile | 2 +- drivers/soc/fsl/qe/qe_ports_ic.c | 156 +++++++++++++++++++++++++++++++ 2 files changed, 157 insertions(+), 1 deletion(-) create mode 100644 drivers/soc/fsl/qe/qe_ports_ic.c diff --git a/drivers/soc/fsl/qe/Makefile b/drivers/soc/fsl/qe/Makefile index ec8506e13113..901a9c40d5eb 100644 --- a/drivers/soc/fsl/qe/Makefile +++ b/drivers/soc/fsl/qe/Makefile @@ -11,4 +11,4 @@ obj-$(CONFIG_UCC_SLOW) +=3D ucc_slow.o obj-$(CONFIG_UCC_FAST) +=3D ucc_fast.o obj-$(CONFIG_QE_TDM) +=3D qe_tdm.o obj-$(CONFIG_QE_USB) +=3D usb.o -obj-$(CONFIG_QE_GPIO) +=3D gpio.o +obj-$(CONFIG_QE_GPIO) +=3D gpio.o qe_ports_ic.o diff --git a/drivers/soc/fsl/qe/qe_ports_ic.c b/drivers/soc/fsl/qe/qe_ports= _ic.c new file mode 100644 index 000000000000..9715643d36a6 --- /dev/null +++ b/drivers/soc/fsl/qe/qe_ports_ic.c @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * QUICC ENGINE I/O Ports Interrupt Controller + * + * Copyright (c) 2025 Christophe Leroy CS GROUP France (christophe.leroy@c= sgroup.eu) + */ + +#include +#include +#include + +/* QE IC registers offset */ +#define CEPIER 0x0c +#define CEPIMR 0x10 +#define CEPICR 0x14 + +struct qepic_data { + void __iomem *reg; + struct irq_domain *host; +}; + +static void qepic_mask(struct irq_data *d) +{ + struct qepic_data *data =3D irq_data_get_irq_chip_data(d); + + clrbits32(data->reg + CEPIMR, 1 << (31 - irqd_to_hwirq(d))); +} + +static void qepic_unmask(struct irq_data *d) +{ + struct qepic_data *data =3D irq_data_get_irq_chip_data(d); + + setbits32(data->reg + CEPIMR, 1 << (31 - irqd_to_hwirq(d))); +} + +static void qepic_end(struct irq_data *d) +{ + struct qepic_data *data =3D irq_data_get_irq_chip_data(d); + + out_be32(data->reg + CEPIER, 1 << (31 - irqd_to_hwirq(d))); +} + +static int qepic_set_type(struct irq_data *d, unsigned int flow_type) +{ + struct qepic_data *data =3D irq_data_get_irq_chip_data(d); + unsigned int vec =3D (unsigned int)irqd_to_hwirq(d); + + switch (flow_type & IRQ_TYPE_SENSE_MASK) { + case IRQ_TYPE_EDGE_FALLING: + setbits32(data->reg + CEPICR, 1 << (31 - vec)); + return 0; + case IRQ_TYPE_EDGE_BOTH: + case IRQ_TYPE_NONE: + clrbits32(data->reg + CEPICR, 1 << (31 - vec)); + return 0; + } + return -EINVAL; +} + +static struct irq_chip qepic =3D { + .name =3D "QEPIC", + .irq_mask =3D qepic_mask, + .irq_unmask =3D qepic_unmask, + .irq_eoi =3D qepic_end, + .irq_set_type =3D qepic_set_type, +}; + +static int qepic_get_irq(struct irq_desc *desc) +{ + struct qepic_data *data =3D irq_desc_get_handler_data(desc); + u32 event =3D in_be32(data->reg + CEPIER); + + if (!event) + return -1; + + return irq_find_mapping(data->host, 32 - ffs(event)); +} + +static void qepic_cascade(struct irq_desc *desc) +{ + generic_handle_irq(qepic_get_irq(desc)); +} + +static int qepic_host_map(struct irq_domain *h, unsigned int virq, irq_hw_= number_t hw) +{ + irq_set_chip_data(virq, h->host_data); + irq_set_chip_and_handler(virq, &qepic, handle_fasteoi_irq); + return 0; +} + +static const struct irq_domain_ops qepic_host_ops =3D { + .map =3D qepic_host_map, +}; + +static int qepic_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct qepic_data *data; + unsigned long nb; + int irq; + + nb =3D (unsigned long)of_device_get_match_data(dev); + if (nb < 1 || nb > 32) + return -EINVAL; + + data =3D devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->reg =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(data->reg)) + return PTR_ERR(data->reg); + + irq =3D platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + data->host =3D irq_domain_add_linear(dev->of_node, nb, &qepic_host_ops, d= ata); + if (!data->host) + return -ENODEV; + + irq_set_handler_data(irq, data); + irq_set_chained_handler(irq, qepic_cascade); + + return 0; +} + +static const struct of_device_id qepic_match[] =3D { + { + .compatible =3D "fsl,mpc8323-qe-ports-ic", + .data =3D (void *)10, + }, + { + .compatible =3D "fsl,mpc8360-qe-ports-ic", + .data =3D (void *)28, + }, + { + .compatible =3D "fsl,mpc8568-qe-ports-ic", + .data =3D (void *)18, + }, + {}, +}; + +static struct platform_driver qepic_driver =3D { + .driver =3D { + .name =3D "qe_ports_ic", + .of_match_table =3D qepic_match, + }, + .probe =3D qepic_probe, +}; + +static int __init qepic_init(void) +{ + return platform_driver_register(&qepic_driver); +} +arch_initcall(qepic_init); --=20 2.49.0 From nobody Sun Dec 14 07:50:22 2025 Received: from pegase2.c-s.fr (pegase2.c-s.fr [93.17.235.10]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1496731355E; Mon, 1 Sep 2025 12:20:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=93.17.235.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756729246; cv=none; b=ox7hcdqy4RIAcbSWQdeaVtSmDItwwaXOwEpvorXji4doFn52oK5un1/neIdq5OkGwVZHYplhr/J1iqbD76coVV6LShyk2nHAEwIIy4H5yjeJP7EJxxHn+R2OWa/IbA3cKTfzSrTzp2GkVchfeZamAEpItkBuvLjGg//0yIAQBx4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756729246; c=relaxed/simple; bh=2f7yMXfZqmnt4TnAL1vLrmJcXWLAvkgUDWqAJg/zucU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=fUwvV0h56pxhN0Q5Pu8cuNpSSbFPaCSsbuBqaHNaAtVFzQVI1EswZTDQsFPy+zyIxm3FyRaJT/tPkls3kTAMx9qbsp6AefsKcX1J45oXgcMhlzDfFuzIRqNtPSB0w9IOU5Q5w5l7vSYxPzBn8ppRjpCoUhYmitcEoPSs1GmqqbE= ARC-Authentication-Results: i=1; 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Mon, 1 Sep 2025 14:05:35 +0200 (CEST) X-Virus-Scanned: amavisd-new at c-s.fr Received: from messagerie.si.c-s.fr ([127.0.0.1]) by localhost (messagerie.si.c-s.fr [127.0.0.1]) (amavisd-new, port 10023) with ESMTP id zQI-rZ0Nw15p; Mon, 1 Sep 2025 14:05:35 +0200 (CEST) Received: from PO20335.idsi0.si.c-s.fr (unknown [10.25.207.160]) by messagerie.si.c-s.fr (Postfix) with ESMTP id 229D28B77B; Mon, 1 Sep 2025 14:05:35 +0200 (CEST) From: Christophe Leroy To: Qiang Zhao , Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Christophe Leroy , linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, Bartosz Golaszewski Subject: [PATCH v5 2/7] soc: fsl: qe: Change GPIO driver to a proper platform driver Date: Mon, 1 Sep 2025 14:05:09 +0200 Message-ID: <12fefcd1c190b37b85e604f7e8e286f445a4564a.1756727747.git.christophe.leroy@csgroup.eu> X-Mailer: git-send-email 2.49.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756728308; l=4836; i=christophe.leroy@csgroup.eu; s=20211009; h=from:subject:message-id; bh=2f7yMXfZqmnt4TnAL1vLrmJcXWLAvkgUDWqAJg/zucU=; b=yaX9PZ/esSZhQqPq3cYQLnzsBXR56oVU06ZFDZX6TmOxmumNzoUCXILiJ6k7QKCzwJyO7HzCs 0YOYg6EZM5MBhCokhLUj8GnDQtXu0oN3hRujQTx9SCIaEnOonvNUasf X-Developer-Key: i=christophe.leroy@csgroup.eu; a=ed25519; pk=HIzTzUj91asvincQGOFx6+ZF5AoUuP9GdOtQChs7Mm0= Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In order to be able to add interrupts to the GPIOs, first change the QE GPIO driver to the proper platform driver in order to allow initialisation to be done in the right order, otherwise the GPIOs get added before the interrupts are registered. Remove linux/of.h and linux/property.h which are unused. And to improve readability and reduce risk of errors, add a macro to transform a pin number into the mask that matches the associated bit in registers. Signed-off-by: Christophe Leroy Reviewed-by: Bartosz Golaszewski --- v5: Added the PIN_MASK() macro --- drivers/soc/fsl/qe/gpio.c | 98 +++++++++++++++++++++------------------ 1 file changed, 53 insertions(+), 45 deletions(-) diff --git a/drivers/soc/fsl/qe/gpio.c b/drivers/soc/fsl/qe/gpio.c index 8df1e8fa86a5..04b44fc2bb58 100644 --- a/drivers/soc/fsl/qe/gpio.c +++ b/drivers/soc/fsl/qe/gpio.c @@ -12,16 +12,17 @@ #include #include #include -#include #include #include #include #include #include -#include +#include =20 #include =20 +#define PIN_MASK(gpio) (1UL << (QE_PIO_PINS - 1 - (gpio))) + struct qe_gpio_chip { struct of_mm_gpio_chip mm_gc; spinlock_t lock; @@ -52,7 +53,7 @@ static int qe_gpio_get(struct gpio_chip *gc, unsigned int= gpio) { struct of_mm_gpio_chip *mm_gc =3D to_of_mm_gpio_chip(gc); struct qe_pio_regs __iomem *regs =3D mm_gc->regs; - u32 pin_mask =3D 1 << (QE_PIO_PINS - 1 - gpio); + u32 pin_mask =3D PIN_MASK(gpio); =20 return !!(ioread32be(®s->cpdata) & pin_mask); } @@ -63,7 +64,7 @@ static int qe_gpio_set(struct gpio_chip *gc, unsigned int= gpio, int val) struct qe_gpio_chip *qe_gc =3D gpiochip_get_data(gc); struct qe_pio_regs __iomem *regs =3D mm_gc->regs; unsigned long flags; - u32 pin_mask =3D 1 << (QE_PIO_PINS - 1 - gpio); + u32 pin_mask =3D PIN_MASK(gpio); =20 spin_lock_irqsave(&qe_gc->lock, flags); =20 @@ -95,9 +96,9 @@ static int qe_gpio_set_multiple(struct gpio_chip *gc, break; if (__test_and_clear_bit(i, mask)) { if (test_bit(i, bits)) - qe_gc->cpdata |=3D (1U << (QE_PIO_PINS - 1 - i)); + qe_gc->cpdata |=3D PIN_MASK(i); else - qe_gc->cpdata &=3D ~(1U << (QE_PIO_PINS - 1 - i)); + qe_gc->cpdata &=3D ~PIN_MASK(i); } } =20 @@ -295,45 +296,52 @@ void qe_pin_set_gpio(struct qe_pin *qe_pin) } EXPORT_SYMBOL(qe_pin_set_gpio); =20 -static int __init qe_add_gpiochips(void) +static int qe_gpio_probe(struct platform_device *ofdev) { - struct device_node *np; - - for_each_compatible_node(np, NULL, "fsl,mpc8323-qe-pario-bank") { - int ret; - struct qe_gpio_chip *qe_gc; - struct of_mm_gpio_chip *mm_gc; - struct gpio_chip *gc; - - qe_gc =3D kzalloc(sizeof(*qe_gc), GFP_KERNEL); - if (!qe_gc) { - ret =3D -ENOMEM; - goto err; - } + struct device *dev =3D &ofdev->dev; + struct device_node *np =3D dev->of_node; + struct qe_gpio_chip *qe_gc; + struct of_mm_gpio_chip *mm_gc; + struct gpio_chip *gc; =20 - spin_lock_init(&qe_gc->lock); - - mm_gc =3D &qe_gc->mm_gc; - gc =3D &mm_gc->gc; - - mm_gc->save_regs =3D qe_gpio_save_regs; - gc->ngpio =3D QE_PIO_PINS; - gc->direction_input =3D qe_gpio_dir_in; - gc->direction_output =3D qe_gpio_dir_out; - gc->get =3D qe_gpio_get; - gc->set =3D qe_gpio_set; - gc->set_multiple =3D qe_gpio_set_multiple; - - ret =3D of_mm_gpiochip_add_data(np, mm_gc, qe_gc); - if (ret) - goto err; - continue; -err: - pr_err("%pOF: registration failed with status %d\n", - np, ret); - kfree(qe_gc); - /* try others anyway */ - } - return 0; + qe_gc =3D devm_kzalloc(dev, sizeof(*qe_gc), GFP_KERNEL); + if (!qe_gc) + return -ENOMEM; + + spin_lock_init(&qe_gc->lock); + + mm_gc =3D &qe_gc->mm_gc; + gc =3D &mm_gc->gc; + + mm_gc->save_regs =3D qe_gpio_save_regs; + gc->ngpio =3D QE_PIO_PINS; + gc->direction_input =3D qe_gpio_dir_in; + gc->direction_output =3D qe_gpio_dir_out; + gc->get =3D qe_gpio_get; + gc->set =3D qe_gpio_set; + gc->set_multiple =3D qe_gpio_set_multiple; + + return of_mm_gpiochip_add_data(np, mm_gc, qe_gc); +} + +static const struct of_device_id qe_gpio_match[] =3D { + { + .compatible =3D "fsl,mpc8323-qe-pario-bank", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, qe_gpio_match); + +static struct platform_driver qe_gpio_driver =3D { + .probe =3D qe_gpio_probe, + .driver =3D { + .name =3D "qe-gpio", + .of_match_table =3D qe_gpio_match, + }, +}; + +static int __init qe_gpio_init(void) +{ + return platform_driver_register(&qe_gpio_driver); } -arch_initcall(qe_add_gpiochips); +arch_initcall(qe_gpio_init); --=20 2.49.0 From nobody Sun Dec 14 07:50:22 2025 Received: from pegase2.c-s.fr (pegase2.c-s.fr [93.17.235.10]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 3F973326D50; Mon, 1 Sep 2025 12:20:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=93.17.235.10 ARC-Seal: i=1; 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Mon, 1 Sep 2025 14:05:35 +0200 (CEST) From: Christophe Leroy To: Qiang Zhao , Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Christophe Leroy , linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v5 3/7] soc: fsl: qe: Drop legacy-of-mm-gpiochip.h header from GPIO driver Date: Mon, 1 Sep 2025 14:05:10 +0200 Message-ID: X-Mailer: git-send-email 2.49.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756728308; l=7337; i=christophe.leroy@csgroup.eu; s=20211009; h=from:subject:message-id; bh=zHMhkGOir99C4zE6CP2P9w4fbrPG2js+Iq37Oh0usVQ=; b=JCxpWDQg8OT10Z6xzFFQz7qWBVLJ3RJwav5YcIOtO07QXfDpRAg1A9uG5tFz3Z3jwLeuwAyfi deFgDBXXM30Alvf3L3FJ/ZG2MGYKdoX18I2J2JmSoeiso2DstWnIpJG X-Developer-Key: i=christophe.leroy@csgroup.eu; a=ed25519; pk=HIzTzUj91asvincQGOFx6+ZF5AoUuP9GdOtQChs7Mm0= Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Remove legacy-of-mm-gpiochip.h header file. The above mentioned file provides an OF API that's deprecated. There is no agnostic alternatives to it and we have to open code the logic which was hidden behind of_mm_gpiochip_add_data(). Note, most of the GPIO drivers are using their own labeling schemas and resource retrieval that only a few may gain of the code deduplication, so whenever alternative is appear we can move drivers again to use that one. As a side effect this change fixes a potential memory leak on an error path, if of_mm_gpiochip_add_data() fails. [Text copied from commit 34064c8267a6 ("powerpc/8xx: Drop legacy-of-mm-gpiochip.h header")] Suggested-by: Bartosz Golaszewski Signed-off-by: Christophe Leroy Reviewed-by: Bartosz Golaszewski --- arch/powerpc/platforms/Kconfig | 1 - drivers/soc/fsl/qe/gpio.c | 51 ++++++++++++++++++---------------- 2 files changed, 27 insertions(+), 25 deletions(-) diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig index fea3766eac0f..5b689bd3ddf4 100644 --- a/arch/powerpc/platforms/Kconfig +++ b/arch/powerpc/platforms/Kconfig @@ -232,7 +232,6 @@ config QE_GPIO bool "QE GPIO support" depends on QUICC_ENGINE select GPIOLIB - select OF_GPIO_MM_GPIOCHIP help Say Y here if you're going to use hardware that connects to the QE GPIOs. diff --git a/drivers/soc/fsl/qe/gpio.c b/drivers/soc/fsl/qe/gpio.c index 04b44fc2bb58..c54154b404df 100644 --- a/drivers/soc/fsl/qe/gpio.c +++ b/drivers/soc/fsl/qe/gpio.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include #include @@ -24,7 +23,8 @@ #define PIN_MASK(gpio) (1UL << (QE_PIO_PINS - 1 - (gpio))) =20 struct qe_gpio_chip { - struct of_mm_gpio_chip mm_gc; + struct gpio_chip gc; + void __iomem *regs; spinlock_t lock; =20 /* shadowed data register to clear/set bits safely */ @@ -34,11 +34,9 @@ struct qe_gpio_chip { struct qe_pio_regs saved_regs; }; =20 -static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_gc) +static void qe_gpio_save_regs(struct qe_gpio_chip *qe_gc) { - struct qe_gpio_chip *qe_gc =3D - container_of(mm_gc, struct qe_gpio_chip, mm_gc); - struct qe_pio_regs __iomem *regs =3D mm_gc->regs; + struct qe_pio_regs __iomem *regs =3D qe_gc->regs; =20 qe_gc->cpdata =3D ioread32be(®s->cpdata); qe_gc->saved_regs.cpdata =3D qe_gc->cpdata; @@ -51,8 +49,8 @@ static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_= gc) =20 static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio) { - struct of_mm_gpio_chip *mm_gc =3D to_of_mm_gpio_chip(gc); - struct qe_pio_regs __iomem *regs =3D mm_gc->regs; + struct qe_gpio_chip *qe_gc =3D gpiochip_get_data(gc); + struct qe_pio_regs __iomem *regs =3D qe_gc->regs; u32 pin_mask =3D PIN_MASK(gpio); =20 return !!(ioread32be(®s->cpdata) & pin_mask); @@ -60,9 +58,8 @@ static int qe_gpio_get(struct gpio_chip *gc, unsigned int= gpio) =20 static int qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) { - struct of_mm_gpio_chip *mm_gc =3D to_of_mm_gpio_chip(gc); struct qe_gpio_chip *qe_gc =3D gpiochip_get_data(gc); - struct qe_pio_regs __iomem *regs =3D mm_gc->regs; + struct qe_pio_regs __iomem *regs =3D qe_gc->regs; unsigned long flags; u32 pin_mask =3D PIN_MASK(gpio); =20 @@ -83,9 +80,8 @@ static int qe_gpio_set(struct gpio_chip *gc, unsigned int= gpio, int val) static int qe_gpio_set_multiple(struct gpio_chip *gc, unsigned long *mask, unsigned long *bits) { - struct of_mm_gpio_chip *mm_gc =3D to_of_mm_gpio_chip(gc); struct qe_gpio_chip *qe_gc =3D gpiochip_get_data(gc); - struct qe_pio_regs __iomem *regs =3D mm_gc->regs; + struct qe_pio_regs __iomem *regs =3D qe_gc->regs; unsigned long flags; int i; =20 @@ -111,13 +107,12 @@ static int qe_gpio_set_multiple(struct gpio_chip *gc, =20 static int qe_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio) { - struct of_mm_gpio_chip *mm_gc =3D to_of_mm_gpio_chip(gc); struct qe_gpio_chip *qe_gc =3D gpiochip_get_data(gc); unsigned long flags; =20 spin_lock_irqsave(&qe_gc->lock, flags); =20 - __par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_IN, 0, 0, 0); + __par_io_config_pin(qe_gc->regs, gpio, QE_PIO_DIR_IN, 0, 0, 0); =20 spin_unlock_irqrestore(&qe_gc->lock, flags); =20 @@ -126,7 +121,6 @@ static int qe_gpio_dir_in(struct gpio_chip *gc, unsigne= d int gpio) =20 static int qe_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int va= l) { - struct of_mm_gpio_chip *mm_gc =3D to_of_mm_gpio_chip(gc); struct qe_gpio_chip *qe_gc =3D gpiochip_get_data(gc); unsigned long flags; =20 @@ -134,7 +128,7 @@ static int qe_gpio_dir_out(struct gpio_chip *gc, unsign= ed int gpio, int val) =20 spin_lock_irqsave(&qe_gc->lock, flags); =20 - __par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_OUT, 0, 0, 0); + __par_io_config_pin(qe_gc->regs, gpio, QE_PIO_DIR_OUT, 0, 0, 0); =20 spin_unlock_irqrestore(&qe_gc->lock, flags); =20 @@ -240,7 +234,7 @@ EXPORT_SYMBOL(qe_pin_free); void qe_pin_set_dedicated(struct qe_pin *qe_pin) { struct qe_gpio_chip *qe_gc =3D qe_pin->controller; - struct qe_pio_regs __iomem *regs =3D qe_gc->mm_gc.regs; + struct qe_pio_regs __iomem *regs =3D qe_gc->regs; struct qe_pio_regs *sregs =3D &qe_gc->saved_regs; int pin =3D qe_pin->num; u32 mask1 =3D 1 << (QE_PIO_PINS - (pin + 1)); @@ -269,7 +263,6 @@ void qe_pin_set_dedicated(struct qe_pin *qe_pin) =20 iowrite32be(qe_gc->cpdata, ®s->cpdata); qe_clrsetbits_be32(®s->cpodr, mask1, sregs->cpodr & mask1); - spin_unlock_irqrestore(&qe_gc->lock, flags); } EXPORT_SYMBOL(qe_pin_set_dedicated); @@ -284,7 +277,7 @@ EXPORT_SYMBOL(qe_pin_set_dedicated); void qe_pin_set_gpio(struct qe_pin *qe_pin) { struct qe_gpio_chip *qe_gc =3D qe_pin->controller; - struct qe_pio_regs __iomem *regs =3D qe_gc->mm_gc.regs; + struct qe_pio_regs __iomem *regs =3D qe_gc->regs; unsigned long flags; =20 spin_lock_irqsave(&qe_gc->lock, flags); @@ -301,7 +294,6 @@ static int qe_gpio_probe(struct platform_device *ofdev) struct device *dev =3D &ofdev->dev; struct device_node *np =3D dev->of_node; struct qe_gpio_chip *qe_gc; - struct of_mm_gpio_chip *mm_gc; struct gpio_chip *gc; =20 qe_gc =3D devm_kzalloc(dev, sizeof(*qe_gc), GFP_KERNEL); @@ -310,18 +302,29 @@ static int qe_gpio_probe(struct platform_device *ofde= v) =20 spin_lock_init(&qe_gc->lock); =20 - mm_gc =3D &qe_gc->mm_gc; - gc =3D &mm_gc->gc; + gc =3D &qe_gc->gc; =20 - mm_gc->save_regs =3D qe_gpio_save_regs; + gc->base =3D -1; gc->ngpio =3D QE_PIO_PINS; gc->direction_input =3D qe_gpio_dir_in; gc->direction_output =3D qe_gpio_dir_out; gc->get =3D qe_gpio_get; gc->set =3D qe_gpio_set; gc->set_multiple =3D qe_gpio_set_multiple; + gc->parent =3D dev; + gc->owner =3D THIS_MODULE; + + gc->label =3D devm_kasprintf(dev, GFP_KERNEL, "%pOF", np); + if (!gc->label) + return -ENOMEM; + + qe_gc->regs =3D devm_of_iomap(dev, np, 0, NULL); + if (IS_ERR(qe_gc->regs)) + return PTR_ERR(qe_gc->regs); + + qe_gpio_save_regs(qe_gc); =20 - return of_mm_gpiochip_add_data(np, mm_gc, qe_gc); + return devm_gpiochip_add_data(dev, gc, qe_gc); } =20 static const struct of_device_id qe_gpio_match[] =3D { --=20 2.49.0 From nobody Sun Dec 14 07:50:22 2025 Received: from pegase2.c-s.fr (pegase2.c-s.fr [93.17.235.10]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 79ABF31DD9A; Mon, 1 Sep 2025 12:20:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=93.17.235.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756729260; cv=none; b=ItzrnqmUp7hWRls6HfjlHYEciVui9T24RZ4bVUiIHXB8ZkiYvaqLt220XKoV3Rex+lFdeXGSxRm/zMrqzvmQ7w7uRuCtjqm70blAPY4p9xc3RuESp+wVLOqpdImAxFSNB0B4+Dq+rw+sYj/Y+1twUPhXF18fCljRLqm2SEzj3Pg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756729260; c=relaxed/simple; bh=s8KjGqMF8kQALqNMwLbzLGaJh7U5Yszt7n4kjPjPFPY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=u4FJPPmFDZTgdfTNEGF67RTXCpw5Hyzvr2cTt9ozk5kmmJErt3gEq6hk3a53EwQP7KcFzrWYCPTvyQjUL0mex6fJ7nNWC1PxVcHbEVvK/dkjA3HcKKLkO5hRvNlDAd2hi9dIsvWeJy9fYRXo8yBsosd6gN96ypcH9F6t/k3SHCg= ARC-Authentication-Results: i=1; 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Mon, 1 Sep 2025 14:05:35 +0200 (CEST) X-Virus-Scanned: amavisd-new at c-s.fr Received: from messagerie.si.c-s.fr ([127.0.0.1]) by localhost (messagerie.si.c-s.fr [127.0.0.1]) (amavisd-new, port 10023) with ESMTP id edUMA0anltQY; Mon, 1 Sep 2025 14:05:35 +0200 (CEST) Received: from PO20335.idsi0.si.c-s.fr (unknown [10.25.207.160]) by messagerie.si.c-s.fr (Postfix) with ESMTP id 5A3228B77B; Mon, 1 Sep 2025 14:05:35 +0200 (CEST) From: Christophe Leroy To: Qiang Zhao , Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Christophe Leroy , linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, Bartosz Golaszewski Subject: [PATCH v5 4/7] soc: fsl: qe: Add support of IRQ in QE GPIO Date: Mon, 1 Sep 2025 14:05:11 +0200 Message-ID: <1234b2b7105443654c5f2bb97d25cf16408d6003.1756727747.git.christophe.leroy@csgroup.eu> X-Mailer: git-send-email 2.49.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756728308; l=6021; i=christophe.leroy@csgroup.eu; s=20211009; h=from:subject:message-id; bh=s8KjGqMF8kQALqNMwLbzLGaJh7U5Yszt7n4kjPjPFPY=; b=5Q0lKuhrQBfag3F7DCmjgG6MlKlaxMv0YyRWMF8h3A82sy9PbLmMLb+o/21C9Bt418k4hJ5m/ 6sPuEoVkJz7D1rfCaQRi8Vuo7IC6FUSSLs9q+m8UgwIgu9cYetjKS/I X-Developer-Key: i=christophe.leroy@csgroup.eu; a=ed25519; pk=HIzTzUj91asvincQGOFx6+ZF5AoUuP9GdOtQChs7Mm0= Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In the QE, a few GPIOs have an associated IRQ to notify changes. Add IRQ support to QE GPIO. As not all GPIOs have an associated IRQ, the driver needs to know to which GPIO corresponds each provided IRQ. This is provided via multiple compatible properties: compatible =3D "fsl,mpc8323-qe-pario-bank-a" compatible =3D "fsl,mpc8323-qe-pario-bank-b" compatible =3D "fsl,mpc8323-qe-pario-bank-c" compatible =3D "fsl,mpc8360-qe-pario-bank-a" compatible =3D "fsl,mpc8360-qe-pario-bank-b" compatible =3D "fsl,mpc8360-qe-pario-bank-c" compatible =3D "fsl,mpc8360-qe-pario-bank-d" compatible =3D "fsl,mpc8360-qe-pario-bank-e" compatible =3D "fsl,mpc8360-qe-pario-bank-f" compatible =3D "fsl,mpc8360-qe-pario-bank-g" compatible =3D "fsl,mpc8568-qe-pario-bank-a" compatible =3D "fsl,mpc8568-qe-pario-bank-b" compatible =3D "fsl,mpc8568-qe-pario-bank-c" compatible =3D "fsl,mpc8568-qe-pario-bank-d" compatible =3D "fsl,mpc8568-qe-pario-bank-e" compatible =3D "fsl,mpc8568-qe-pario-bank-f" When not using IRQ and for banks having no IRQ (like bank D on mpc8323) the origin compatible =3D "fsl,mpc8323-qe-pario-bank" is sufficient. Here is an exemple for port B of mpc8323 which has IRQs for GPIOs PB7, PB9, PB25 and PB27. qe_pio_b: gpio-controller@1418 { compatible =3D "fsl,mpc8323-qe-pario-bank-b"; reg =3D <0x1418 0x18>; interrupts =3D <4 5 6 7>; interrupt-parent =3D <&qepic>; gpio-controller; #gpio-cells =3D <2>; }; Signed-off-by: Christophe Leroy Reviewed-by: Bartosz Golaszewski --- v5: Provide the mask via the compatible data instead of adding a property i= n device tree --- drivers/soc/fsl/qe/gpio.c | 72 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/drivers/soc/fsl/qe/gpio.c b/drivers/soc/fsl/qe/gpio.c index c54154b404df..8632b0d37255 100644 --- a/drivers/soc/fsl/qe/gpio.c +++ b/drivers/soc/fsl/qe/gpio.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -32,6 +33,8 @@ struct qe_gpio_chip { =20 /* saved_regs used to restore dedicated functions */ struct qe_pio_regs saved_regs; + + int irq[QE_PIO_PINS]; }; =20 static void qe_gpio_save_regs(struct qe_gpio_chip *qe_gc) @@ -135,6 +138,13 @@ static int qe_gpio_dir_out(struct gpio_chip *gc, unsig= ned int gpio, int val) return 0; } =20 +static int qe_gpio_to_irq(struct gpio_chip *gc, unsigned int gpio) +{ + struct qe_gpio_chip *qe_gc =3D gpiochip_get_data(gc); + + return qe_gc->irq[gpio] ? : -ENXIO; +} + struct qe_pin { /* * The qe_gpio_chip name is unfortunate, we should change that to @@ -295,6 +305,7 @@ static int qe_gpio_probe(struct platform_device *ofdev) struct device_node *np =3D dev->of_node; struct qe_gpio_chip *qe_gc; struct gpio_chip *gc; + u32 mask; =20 qe_gc =3D devm_kzalloc(dev, sizeof(*qe_gc), GFP_KERNEL); if (!qe_gc) @@ -302,6 +313,15 @@ static int qe_gpio_probe(struct platform_device *ofdev) =20 spin_lock_init(&qe_gc->lock); =20 + mask =3D (u32)of_device_get_match_data(dev); + if (mask) { + int i, j; + + for (i =3D 0, j =3D 0; i < ARRAY_SIZE(qe_gc->irq); i++) + if (mask & PIN_MASK(i)) + qe_gc->irq[i] =3D irq_of_parse_and_map(np, j++); + } + gc =3D &qe_gc->gc; =20 gc->base =3D -1; @@ -311,6 +331,7 @@ static int qe_gpio_probe(struct platform_device *ofdev) gc->get =3D qe_gpio_get; gc->set =3D qe_gpio_set; gc->set_multiple =3D qe_gpio_set_multiple; + gc->to_irq =3D qe_gpio_to_irq; gc->parent =3D dev; gc->owner =3D THIS_MODULE; =20 @@ -330,6 +351,57 @@ static int qe_gpio_probe(struct platform_device *ofdev) static const struct of_device_id qe_gpio_match[] =3D { { .compatible =3D "fsl,mpc8323-qe-pario-bank", + }, { + .compatible =3D "fsl,mpc8323-qe-pario-bank-a", + .data =3D (void *)(PIN_MASK(8) | PIN_MASK(10) | PIN_MASK(26) | PIN_MASK(= 28)), + }, { + .compatible =3D "fsl,mpc8323-qe-pario-bank-b", + .data =3D (void *)(PIN_MASK(7) | PIN_MASK(9) | PIN_MASK(25) | PIN_MASK(2= 7)), + }, { + .compatible =3D "fsl,mpc8323-qe-pario-bank-c", + .data =3D (void *)(PIN_MASK(24) | PIN_MASK(29)), + }, { + .compatible =3D "fsl,mpc8360-qe-pario-bank-a", + .data =3D (void *)(PIN_MASK(15) | PIN_MASK(16) | PIN_MASK(29) | PIN_MASK= (30)), + }, { + .compatible =3D "fsl,mpc8360-qe-pario-bank-b", + .data =3D (void *)(PIN_MASK(3) | PIN_MASK(5) | PIN_MASK(12) | PIN_MASK(1= 3) | + PIN_MASK(26) | PIN_MASK(27)), + }, { + .compatible =3D "fsl,mpc8360-qe-pario-bank-c", + .data =3D (void *)(PIN_MASK(27) | PIN_MASK(28) | PIN_MASK(29)), + }, { + .compatible =3D "fsl,mpc8360-qe-pario-bank-d", + .data =3D (void *)(PIN_MASK(12) | PIN_MASK(13) | PIN_MASK(16) | PIN_MASK= (17) | + PIN_MASK(26) | PIN_MASK(27)), + }, { + .compatible =3D "fsl,mpc8360-qe-pario-bank-e", + .data =3D (void *)(PIN_MASK(12) | PIN_MASK(13) | PIN_MASK(24) | PIN_MASK= (25) | + PIN_MASK(26) | PIN_MASK(27) | PIN_MASK(31)), + }, { + .compatible =3D "fsl,mpc8360-qe-pario-bank-f", + .data =3D (void *)(PIN_MASK(20)), + }, { + .compatible =3D "fsl,mpc8360-qe-pario-bank-g", + .data =3D (void *)(PIN_MASK(31)), + }, { + .compatible =3D "fsl,mpc8568-qe-pario-bank-a", + .data =3D (void *)(PIN_MASK(22) | PIN_MASK(23)), + }, { + .compatible =3D "fsl,mpc8568-qe-pario-bank-b", + .data =3D (void *)(PIN_MASK(12) | PIN_MASK(13) | PIN_MASK(28) | PIN_MASK= (29)), + }, { + .compatible =3D "fsl,mpc8568-qe-pario-bank-c", + .data =3D (void *)(PIN_MASK(16) | PIN_MASK(17) | PIN_MASK(25) | PIN_MASK= (26)), + }, { + .compatible =3D "fsl,mpc8568-qe-pario-bank-d", + .data =3D (void *)(PIN_MASK(18) | PIN_MASK(19)), + }, { + .compatible =3D "fsl,mpc8568-qe-pario-bank-e", + .data =3D (void *)(PIN_MASK(12) | PIN_MASK(16) | PIN_MASK(30)), + }, { + .compatible =3D "fsl,mpc8568-qe-pario-bank-f", + .data =3D (void *)(PIN_MASK(12) | PIN_MASK(16) | PIN_MASK(30)), }, {}, }; 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Mon, 1 Sep 2025 14:05:35 +0200 (CEST) X-Virus-Scanned: amavisd-new at c-s.fr Received: from messagerie.si.c-s.fr ([127.0.0.1]) by localhost (messagerie.si.c-s.fr [127.0.0.1]) (amavisd-new, port 10023) with ESMTP id UrGKXVX00Xao; Mon, 1 Sep 2025 14:05:35 +0200 (CEST) Received: from PO20335.idsi0.si.c-s.fr (unknown [10.25.207.160]) by messagerie.si.c-s.fr (Postfix) with ESMTP id 7B3FA8B78C; Mon, 1 Sep 2025 14:05:35 +0200 (CEST) From: Christophe Leroy To: Qiang Zhao , Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Christophe Leroy , linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, Conor Dooley Subject: [PATCH v5 5/7] dt-bindings: soc: fsl: qe: Add an interrupt controller for QUICC Engine Ports Date: Mon, 1 Sep 2025 14:05:12 +0200 Message-ID: X-Mailer: git-send-email 2.49.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756728308; l=2384; i=christophe.leroy@csgroup.eu; s=20211009; h=from:subject:message-id; bh=6GGB8fj116M7fld93yabp+Sk9w91NwwwbI5I6K0AiZU=; b=jR+31eCAFRr4bN9Eu6xmfDeciVfmvlPu9ExV5VARP8nsAOGNFwb90XySqHjMyi1lIHHu36+2y LGi6cKMqC+ICyMni+CveDj7l2leszHXF7NXGxdBQNi1fciTurQMzy/U X-Developer-Key: i=christophe.leroy@csgroup.eu; a=ed25519; pk=HIzTzUj91asvincQGOFx6+ZF5AoUuP9GdOtQChs7Mm0= Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The QUICC Engine provides interrupts for a few I/O ports. This is handled via a separate interrupt ID and managed via a triplet of dedicated registers hosted by the SoC. Implement an interrupt driver for it for that those IRQs can then be linked to the related GPIOs. Signed-off-by: Christophe Leroy Acked-by: Conor Dooley --- .../soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe= -ports-ic.yaml diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-= ic.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-ic.= yaml new file mode 100644 index 000000000000..a356ad8b13f5 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale QUICC Engine I/O Ports Interrupt Controller + +maintainers: + - Christophe Leroy + +description: + Interrupt controller for the QUICC Engine I/O ports found on some Freesc= ale/NXP PowerQUICC and QorIQ SoCs. + +properties: + compatible: + enum: + - fsl,mpc8323-qe-ports-ic + - fsl,mpc8360-qe-ports-ic + - fsl,mpc8568-qe-ports-ic + + reg: + maxItems: 1 + description: Base address and size of the QE I/O Ports Interrupt Contr= oller registers. + + interrupt-controller: true + + '#address-cells': + const: 0 + + '#interrupt-cells': + const: 1 + + interrupts: + maxItems: 1 + description: Interrupt line to which the QE I/O Ports controller is co= nnected. + +required: + - compatible + - reg + - interrupt-controller + - '#address-cells' + - '#interrupt-cells' + - interrupts + +additionalProperties: false + +examples: + - | + interrupt-controller@c00 { + compatible =3D "fsl,mpc8323-qe-ports-ic"; + reg =3D <0xc00 0x18>; + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + interrupts =3D <74 0x8>; + interrupt-parent =3D <&ipic>; + }; --=20 2.49.0 From nobody Sun Dec 14 07:50:22 2025 Received: from pegase2.c-s.fr (pegase2.c-s.fr [93.17.235.10]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 6949731355E; Mon, 1 Sep 2025 12:20:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=93.17.235.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756729251; cv=none; b=J12EiEQx5F28bkWs92O0SlfU8uS/MoUUeGaY1KPfthe9Bh8AUoUt0KBksDrDcuPlvs84fLh9p12vwy12IhEXMm+nMqQpYCDk7MMDGwc+MqWe71TzVRaLJrNISumMu77kIYCU8bwlWPf6NG2JyF4uQikPIk8XU5nFvtZyxFIXExc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756729251; c=relaxed/simple; bh=NiGGEzSVsJLntFwP1MIryFHdxpjk8igr3FrrVNxKPP0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=DOZK1LMOZZ82eY8dyQrrfqcawmHGqcQeA8yZE4NZ2jqxd0g0khhy9iObOSPKdo940F7gKCmxw7/LoAUrxX2V9PjHKpGMx9NuIw241mAY6vY+iLtZjWeJv711DkuCdVt+fbQM9kXH/sr4fVR0SNNX7P6FJPedGrNL1yvs37fLnZ8= ARC-Authentication-Results: i=1; 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Mon, 1 Sep 2025 14:05:35 +0200 (CEST) X-Virus-Scanned: amavisd-new at c-s.fr Received: from messagerie.si.c-s.fr ([127.0.0.1]) by localhost (messagerie.si.c-s.fr [127.0.0.1]) (amavisd-new, port 10023) with ESMTP id r-KaAi8_MPiL; Mon, 1 Sep 2025 14:05:35 +0200 (CEST) Received: from PO20335.idsi0.si.c-s.fr (unknown [10.25.207.160]) by messagerie.si.c-s.fr (Postfix) with ESMTP id 9AED58B77B; Mon, 1 Sep 2025 14:05:35 +0200 (CEST) From: Christophe Leroy To: Qiang Zhao , Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Christophe Leroy , linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v5 6/7] dt-bindings: soc: fsl: qe: Convert QE GPIO to DT schema Date: Mon, 1 Sep 2025 14:05:13 +0200 Message-ID: <48b4e7b25878b94dcb738f8239c815be484cf9c9.1756727747.git.christophe.leroy@csgroup.eu> X-Mailer: git-send-email 2.49.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756728308; l=3362; i=christophe.leroy@csgroup.eu; s=20211009; h=from:subject:message-id; bh=NiGGEzSVsJLntFwP1MIryFHdxpjk8igr3FrrVNxKPP0=; b=5WGZ5OgL+UExib3sv3fqbTbNCnvFZWxhkGlIIBNdXJikd0CcgFn/iAKdoshFpSqdsfhcw8u+A AJl1zujb3KNA/2ZISoit2AJr8HNP+vrVFJqtJpC2pYIMie16Qi8gN0s X-Developer-Key: i=christophe.leroy@csgroup.eu; a=ed25519; pk=HIzTzUj91asvincQGOFx6+ZF5AoUuP9GdOtQChs7Mm0= Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Convert QE QPIO devicetree binding to DT schema. Signed-off-by: Christophe Leroy --- v5: New --- .../fsl/cpm_qe/fsl,mpc8323-qe-pario-bank.yaml | 53 +++++++++++++++++++ .../bindings/soc/fsl/cpm_qe/qe/par_io.txt | 26 +-------- 2 files changed, 54 insertions(+), 25 deletions(-) create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,mp= c8323-qe-pario-bank.yaml diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,mpc8323-q= e-pario-bank.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,mp= c8323-qe-pario-bank.yaml new file mode 100644 index 000000000000..e6ba319a75c1 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,mpc8323-qe-pario= -bank.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,mpc8323-qe-pario-ban= k.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale QUICC Engine Parallel I/O (QE PARIO) GPIO Bank + +maintainers: + - Christophe Leroy + +description: + Bindings for the Freescale QUICC Engine Parallel I/O (PARIO) GPIO contro= ller. + +properties: + compatible: + items: + - enum: + - fsl,chip-qe-pario-bank + - const: fsl,mpc8323-qe-pario-bank + + reg: + maxItems: 1 + description: Offset to the register set and its length. + + gpio-controller: true + + '#gpio-cells': + const: 2 + +required: + - compatible + - reg + - gpio-controller + - '#gpio-cells' + +additionalProperties: false + +examples: + - | + qe_pio_a: gpio-controller@1400 { + compatible =3D "fsl,mpc8360-qe-pario-bank", "fsl,mpc8323-qe-pario-= bank"; + reg =3D <0x1400 0x18>; + gpio-controller; + #gpio-cells =3D <2>; + }; + + qe_pio_e: gpio-controller@1460 { + compatible =3D "fsl,mpc8360-qe-pario-bank", "fsl,mpc8323-qe-pario-= bank"; + reg =3D <0x1460 0x18>; + gpio-controller; + #gpio-cells =3D <2>; + }; diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/par_io.txt= b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/par_io.txt index 09b1b05fa677..782699c14567 100644 --- a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/par_io.txt +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/par_io.txt @@ -24,28 +24,4 @@ par_io@1400 { =20 Note that "par_io" nodes are obsolete, and should not be used for the new device trees. Instead, each Par I/O bank should be represented -via its own gpio-controller node: - -Required properties: -- #gpio-cells : should be "2". -- compatible : should be "fsl,-qe-pario-bank", - "fsl,mpc8323-qe-pario-bank". -- reg : offset to the register set and its length. -- gpio-controller : node to identify gpio controllers. - -Example: - qe_pio_a: gpio-controller@1400 { - #gpio-cells =3D <2>; - compatible =3D "fsl,mpc8360-qe-pario-bank", - "fsl,mpc8323-qe-pario-bank"; - reg =3D <0x1400 0x18>; - gpio-controller; - }; - - qe_pio_e: gpio-controller@1460 { - #gpio-cells =3D <2>; - compatible =3D "fsl,mpc8360-qe-pario-bank", - "fsl,mpc8323-qe-pario-bank"; - reg =3D <0x1460 0x18>; - gpio-controller; - }; +via its own gpio-controller node. --=20 2.49.0 From nobody Sun Dec 14 07:50:22 2025 Received: from pegase2.c-s.fr (pegase2.c-s.fr [93.17.235.10]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 6BB1C30BF7B; Mon, 1 Sep 2025 12:21:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=93.17.235.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756729265; cv=none; b=W8bhode5xTqFmLIYARkvEJXpw0H8AL35DhgwW0+wIPyrbE9LaP7csNN9x810bl82Gcr8XSQPg3rLO1qeRuwUra4kGPDzw5RbIJTh0GphqdJMTTEvwqF1UnVaFyl6Lgeia80/gS8QDgFdqVo/cgeCaBT3Jw/bEv1OCAcF0iXtlpI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756729265; c=relaxed/simple; bh=59wZHIxllxZcwCrUxSll7FEcA0fEA5AxS+AodcoXc0o=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=WYjyuFAp6VLMOh1NvbvR5S0FEDgpy5RV3UH/50l50xIzznOlpkDYEB6/8Nf98pXuEe5VwpN9FcHyONbgZVHJ/QJT+Zmg2ApgbzUnpoQIAexuqOO5VElQLHXf3czz0mP9yJg3V+V4py83u3YqSzRU0/YWOmIHyr9J8/I0ipAkF1w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=csgroup.eu; spf=pass smtp.mailfrom=csgroup.eu; arc=none smtp.client-ip=93.17.235.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=csgroup.eu Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=csgroup.eu Received: from localhost (mailhub4.si.c-s.fr [172.26.127.67]) by localhost (Postfix) with ESMTP id 4cFndL0hyTz9sT8; Mon, 1 Sep 2025 14:05:42 +0200 (CEST) X-Virus-Scanned: amavisd-new at c-s.fr Received: from pegase2.c-s.fr ([172.26.127.65]) by localhost (pegase2.c-s.fr [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 8chmUpmbiw-6; Mon, 1 Sep 2025 14:05:42 +0200 (CEST) Received: from messagerie.si.c-s.fr (messagerie.si.c-s.fr [192.168.25.192]) by pegase2.c-s.fr (Postfix) with ESMTP id 4cFndD0SFrz9sSs; Mon, 1 Sep 2025 14:05:36 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by messagerie.si.c-s.fr (Postfix) with ESMTP id ECB808B77B; Mon, 1 Sep 2025 14:05:35 +0200 (CEST) X-Virus-Scanned: amavisd-new at c-s.fr Received: from messagerie.si.c-s.fr ([127.0.0.1]) by localhost (messagerie.si.c-s.fr [127.0.0.1]) (amavisd-new, port 10023) with ESMTP id vyRL5fj0VNV1; Mon, 1 Sep 2025 14:05:35 +0200 (CEST) Received: from PO20335.idsi0.si.c-s.fr (unknown [10.25.207.160]) by messagerie.si.c-s.fr (Postfix) with ESMTP id BB70F8B78C; Mon, 1 Sep 2025 14:05:35 +0200 (CEST) From: Christophe Leroy To: Qiang Zhao , Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Christophe Leroy , linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v5 7/7] dt-bindings: soc: fsl: qe: Add support of IRQ in QE GPIO Date: Mon, 1 Sep 2025 14:05:14 +0200 Message-ID: <4d7560f77dbd60f6297958acbc0cf412d8921856.1756727747.git.christophe.leroy@csgroup.eu> X-Mailer: git-send-email 2.49.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756728308; l=3640; i=christophe.leroy@csgroup.eu; s=20211009; h=from:subject:message-id; bh=59wZHIxllxZcwCrUxSll7FEcA0fEA5AxS+AodcoXc0o=; b=cy9tS21IUHMGiZz2LkFhr/4YksRHLYEUvFGDBOX1axyjBo+bzEtfYV3xtcm8RSYCvbvRHjfst 3wmxkdbNoD3BJ0zgTn8FewQGYmGd3efkqIdatLK/NyqRDmBjpdLHkdM X-Developer-Key: i=christophe.leroy@csgroup.eu; a=ed25519; pk=HIzTzUj91asvincQGOFx6+ZF5AoUuP9GdOtQChs7Mm0= Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In the QE, a few GPIOs have an associated IRQ to notify changes. Add IRQ support to QE GPIO. As not all GPIOs have an associated IRQ, the driver needs to know to which GPIO corresponds each provided IRQ. This is provided via multiple compatible properties: compatible =3D "fsl,mpc8323-qe-pario-bank-a" compatible =3D "fsl,mpc8323-qe-pario-bank-b" compatible =3D "fsl,mpc8323-qe-pario-bank-c" compatible =3D "fsl,mpc8360-qe-pario-bank-a" compatible =3D "fsl,mpc8360-qe-pario-bank-b" compatible =3D "fsl,mpc8360-qe-pario-bank-c" compatible =3D "fsl,mpc8360-qe-pario-bank-d" compatible =3D "fsl,mpc8360-qe-pario-bank-e" compatible =3D "fsl,mpc8360-qe-pario-bank-f" compatible =3D "fsl,mpc8360-qe-pario-bank-g" compatible =3D "fsl,mpc8568-qe-pario-bank-a" compatible =3D "fsl,mpc8568-qe-pario-bank-b" compatible =3D "fsl,mpc8568-qe-pario-bank-c" compatible =3D "fsl,mpc8568-qe-pario-bank-d" compatible =3D "fsl,mpc8568-qe-pario-bank-e" compatible =3D "fsl,mpc8568-qe-pario-bank-f" When not using IRQ and for banks having no IRQ (like bank D on mpc8323) the origin compatible =3D "fsl,mpc8323-qe-pario-bank" is still valid. Signed-off-by: Christophe Leroy --- v5: Changed to DT schema --- .../fsl/cpm_qe/fsl,mpc8323-qe-pario-bank.yaml | 27 +++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,mpc8323-q= e-pario-bank.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,mp= c8323-qe-pario-bank.yaml index e6ba319a75c1..80f93914c779 100644 --- a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,mpc8323-qe-pario= -bank.yaml +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,mpc8323-qe-pario= -bank.yaml @@ -17,6 +17,22 @@ properties: items: - enum: - fsl,chip-qe-pario-bank + - fsl,mpc8323-qe-pario-bank-a + - fsl,mpc8323-qe-pario-bank-b + - fsl,mpc8323-qe-pario-bank-c + - fsl,mpc8360-qe-pario-bank-a + - fsl,mpc8360-qe-pario-bank-b + - fsl,mpc8360-qe-pario-bank-c + - fsl,mpc8360-qe-pario-bank-d + - fsl,mpc8360-qe-pario-bank-e + - fsl,mpc8360-qe-pario-bank-f + - fsl,mpc8360-qe-pario-bank-g + - fsl,mpc8568-qe-pario-bank-a + - fsl,mpc8568-qe-pario-bank-b + - fsl,mpc8568-qe-pario-bank-c + - fsl,mpc8568-qe-pario-bank-d + - fsl,mpc8568-qe-pario-bank-e + - fsl,mpc8568-qe-pario-bank-f - const: fsl,mpc8323-qe-pario-bank =20 reg: @@ -28,6 +44,9 @@ properties: '#gpio-cells': const: 2 =20 + interrupts: + description: List of interrupts for lines of the port that trigger int= errupts on change. + required: - compatible - reg @@ -39,15 +58,19 @@ additionalProperties: false examples: - | qe_pio_a: gpio-controller@1400 { - compatible =3D "fsl,mpc8360-qe-pario-bank", "fsl,mpc8323-qe-pario-= bank"; + compatible =3D "fsl,mpc8360-qe-pario-bank-a", "fsl,mpc8323-qe-pari= o-bank"; reg =3D <0x1400 0x18>; gpio-controller; #gpio-cells =3D <2>; + interrupts =3D <0 1 2 3>; + interrupt-parent =3D <&qepic>; }; =20 qe_pio_e: gpio-controller@1460 { - compatible =3D "fsl,mpc8360-qe-pario-bank", "fsl,mpc8323-qe-pario-= bank"; + compatible =3D "fsl,mpc8360-qe-pario-bank-e", "fsl,mpc8323-qe-pari= o-bank"; reg =3D <0x1460 0x18>; gpio-controller; #gpio-cells =3D <2>; + interrupts =3D <19 20 21 22 23 24 25>; + interrupt-parent =3D <&qepic>; }; --=20 2.49.0