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charset="utf-8" Previously, the AD4030 driver was using the number of scan realbits for the voltage channel to derive the scale to millivolts. Though, when sample averaging is enabled (oversampling_ratio > 1), the number of scan realbits for the channel is set to 30 and doesn't match the amount of conversion precision bits. Due to that, the calculated channel scale did not correctly scale raw sample data to millivolt units in those cases. Use chip specific precision bits to derive the correct channel _scale on every and all channel configuration. Fixes: dc78e71d7c15 ("iio: adc: ad4030: remove some duplicate code") Signed-off-by: Marcelo Schmitt --- This was probalby buggy since=20 commit 949abd1ca5a4 ("iio: adc: ad4030: add averaging support") but I decided to set the fixes tag with dc78e71d7c15 because this patch will not apply cleanly over 949abd1ca5a4. drivers/iio/adc/ad4030.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/iio/adc/ad4030.c b/drivers/iio/adc/ad4030.c index 1bc2f9a22470..82784593f976 100644 --- a/drivers/iio/adc/ad4030.c +++ b/drivers/iio/adc/ad4030.c @@ -394,7 +394,14 @@ static int ad4030_get_chan_scale(struct iio_dev *indio= _dev, else *val =3D st->vref_uv / MILLI; =20 - *val2 =3D scan_type->realbits; + /* + * Even though the sample data comes in a 30-bit chunk when the ADC + * is averaging samples, the conversion precision is still 16-bit or + * 24-bit depending on the device. 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Fri, 29 Aug 2025 20:40:55 -0400 From: Marcelo Schmitt To: , , , , CC: , , , , , , , , , , , , , , Subject: [PATCH 02/15] dt-bindings: iio: adc: adi,ad4030: Reference spi-peripheral-props Date: Fri, 29 Aug 2025 21:40:52 -0300 Message-ID: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-GUID: ttkmjPW7qcttfgyXYED3Zuc_-nEExwnW X-Proofpoint-ORIG-GUID: hrLtIgTqPLjk2a4uw4cKGg1OGxTr3z2a X-Authority-Analysis: v=2.4 cv=J6Wq7BnS c=1 sm=1 tr=0 ts=68b248a7 cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=2OwXVqhp2XgA:10 a=gAnH3GRIAAAA:8 a=IgjcDGkmi_FApCPpklgA:9 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODI5MDA3NCBTYWx0ZWRfX7LEgkhvDVG/I +PGu0xAUaeSnEG9pVfvAt+RQf+jaY2+R6MRzfFfQTGehzjZ/wpMxFTC97YJ+3Gw1apJjL/fQ+lG cGkoKE1z7eHqDd6iNiirLj+cX5zCnxAw2WJn/I/Or7L0JbCJtntCtVThDWsnitFUWv5zuReIe7b Bxqed3JS5kPduSsr6/yeS+/HoJVsEC9bYiuNUy58LnmPKGzC8lsSqXmsJoytKVmmkoZyN5etsUk IComX+/FDzH1JF+EC7CTXd6pZgWtympbHLMZnGT42/gF9Xsfq3WiqOogohlJtbNzKoT/3BSU8Xg yoE1YpxX3hcRSWr06paOA4sq6k0vV5X8rz8oPUTK8a2y6TeUoAkiTBXW4NzJc6vt+8PqMhF7pGI sVtX/wVE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-29_07,2025-08-28_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 adultscore=0 spamscore=0 clxscore=1011 suspectscore=0 bulkscore=0 malwarescore=0 impostorscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508290074 Content-Type: text/plain; charset="utf-8" AD4030 and similar devices all connect to the system as SPI peripherals. Reference spi-peripheral-props so common SPI peripheral can be used from ad4030 dt-binding. Signed-off-by: Marcelo Schmitt --- Not sure if it is worth applying this patch since it doesn't seem to cause = any practical effect to the binding. Though, sending it in case it might be wor= th it. Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad4030.yaml index 54e7349317b7..a8fee4062d0e 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml @@ -20,6 +20,8 @@ description: | * https://www.analog.com/media/en/technical-documentation/data-sheets/ad= 4630-24_ad4632-24.pdf * https://www.analog.com/media/en/technical-documentation/data-sheets/ad= 4630-16-4632-16.pdf =20 +$ref: /schemas/spi/spi-peripheral-props.yaml# + properties: compatible: enum: --=20 2.39.2 From nobody Fri Oct 3 13:21:33 2025 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E468B2E403; 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charset="utf-8" Document double PWM setup SPI offload wiring schema. Signed-off-by: Marcelo Schmitt --- Documentation/iio/ad4030.rst | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/Documentation/iio/ad4030.rst b/Documentation/iio/ad4030.rst index b57424b650a8..dc3ac253ef66 100644 --- a/Documentation/iio/ad4030.rst +++ b/Documentation/iio/ad4030.rst @@ -92,6 +92,35 @@ Interleaved mode In this mode, both channels conversion results are bit interleaved one SDO= line. As such the wiring is the same as `One lane mode`_. =20 +SPI offload wiring +^^^^^^^^^^^^^^^^^^ + +.. code-block:: + + +-------------+ +-------------+ + | CNV |<-----+--| GPIO | + | | +--| PWM1 | + | | | | + | | +--| PWM0 | + | | | +-------------+ + | | +->| TRIGGER | + | CS |<--------| CS | + | | | | + | ADC | | SPI | + | | | | + | SDI |<--------| SDO | + | SDO |-------->| SDI | + | SCLK |<--------| SCLK | + +-------------+ +-------------+ + +In this mode, both the ``cnv-gpios`` and a ``pwms`` properties are require= d. +The ``pwms`` property specifies the PWM that is connected to the ADC CNV p= in. +The SPI offload will have a ``trigger-sources`` property to indicate the S= PI +offload (PWM) trigger source. The IIO device driver synchronizes the PWMs = to do +ADC transfer zone 2 data capture. + +.. seealso:: `SPI offload support`_ + SPI Clock mode -------------- =20 --=20 2.39.2 From nobody Fri Oct 3 13:21:33 2025 Received: from mx0b-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 11C6E16DC28; Sat, 30 Aug 2025 00:41:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756514520; cv=none; b=jFjcubjF0aYLg1oIIT65eQlWWuKqJ2qAqm93xVzBAaznhxUP2pTpluKSbwacyQLU+iRU0C+exS1Y0mBuTSAVyf1dCoRpf8c49dLARz2udukSGoTkkoJo1Bt35Pp3qBAXCI+n7qYz8meSpELJj0M5PFgvJ/Soa75UtyBomqLhK2E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756514520; c=relaxed/simple; bh=QGdJODPCkQCmSaEsXd5uIQEp43dw+5ue/xsF7FmmkNc=; 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charset="utf-8" In setups designed for high speed data rate capture, a PWM is used to generate the CNV signal that issues data captures from the ADC. Document the use of a PWM for AD4030 and similar devices. Signed-off-by: Marcelo Schmitt --- Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad4030.yaml index a8fee4062d0e..564b6f67a96e 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml @@ -64,6 +64,10 @@ properties: The Reset Input (/RST). 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charset="utf-8" From: Axel Haslam Add an offset parameter that can be passed in the periodic trigger. This is useful for example when adc drivers implement a separate periodic signal to trigger conversion and need offload to read the result with some delay. Signed-off-by: Axel Haslam Signed-off-by: Marcelo Schmitt --- include/linux/spi/offload/types.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/spi/offload/types.h b/include/linux/spi/offload/= types.h index 6f7892347871..0170fd1f42e5 100644 --- a/include/linux/spi/offload/types.h +++ b/include/linux/spi/offload/types.h @@ -59,6 +59,7 @@ enum spi_offload_trigger_type { =20 struct spi_offload_trigger_periodic { u64 frequency_hz; + u64 offset_ns; }; =20 struct spi_offload_trigger_config { --=20 2.39.2 From nobody Fri Oct 3 13:21:33 2025 Received: from mx0b-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AD87226281; Sat, 30 Aug 2025 00:42:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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charset="utf-8" From: Axel Haslam Pass the duty offset to the waveform pwm. Signed-off-by: Axel Haslam Signed-off-by: Marcelo Schmitt --- drivers/spi/spi-offload-trigger-pwm.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-offload-trigger-pwm.c b/drivers/spi/spi-offloa= d-trigger-pwm.c index 805ed41560df..8413aeb3689d 100644 --- a/drivers/spi/spi-offload-trigger-pwm.c +++ b/drivers/spi/spi-offload-trigger-pwm.c @@ -51,13 +51,13 @@ static int spi_offload_trigger_pwm_validate(struct spi_= offload_trigger *trigger, wf.period_length_ns =3D DIV_ROUND_UP_ULL(NSEC_PER_SEC, periodic->frequenc= y_hz); /* REVISIT: 50% duty-cycle for now - may add config parameter later */ wf.duty_length_ns =3D wf.period_length_ns / 2; - + wf.duty_offset_ns =3D periodic->offset_ns; ret =3D pwm_round_waveform_might_sleep(st->pwm, &wf); if (ret < 0) return ret; =20 periodic->frequency_hz =3D DIV_ROUND_UP_ULL(NSEC_PER_SEC, wf.period_lengt= h_ns); - + periodic->offset_ns =3D wf.duty_offset_ns; return 0; } =20 @@ -77,6 +77,7 @@ static int spi_offload_trigger_pwm_enable(struct spi_offl= oad_trigger *trigger, wf.period_length_ns =3D DIV_ROUND_UP_ULL(NSEC_PER_SEC, periodic->frequenc= y_hz); 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charset="utf-8" AD4030 and similar ADCs can capture data at sample rates up to 2 mega samples per second (MSPS). Not all SPI controllers are able to achieve such high throughputs and even when the controller is fast enough to run transfers at the required speed, it may be costly to the CPU to handle transfer data at such high sample rates. Add SPI offload support for AD4030 and similar ADCs so to enable ADC data capture at maximum sample rates. Cc: Sergiu Cuciurean Cc: Nuno Sa Cc: Trevor Gamblin Cc: Axel Haslam Cc: David Lechner Co-developed-by: Sergiu Cuciurean Signed-off-by: Sergiu Cuciurean Co-developed-by: Nuno Sa Signed-off-by: Nuno Sa Co-developed-by: Trevor Gamblin Signed-off-by: Trevor Gamblin Co-developed-by: Axel Haslam Signed-off-by: Axel Haslam Signed-off-by: Marcelo Schmitt --- Most of the code in this patch is based on work from Sergiu Cuciurean, Nuno= Sa, Axel Haslam, and Trevor Gamblin, hence the many co-developed-by tags. I also draw inspiration from other drivers supporting SPI offload, many of them wr= itten by David Lechner. drivers/iio/adc/Kconfig | 2 + drivers/iio/adc/ad4030.c | 400 ++++++++++++++++++++++++++++++++++++--- 2 files changed, 378 insertions(+), 24 deletions(-) diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 6de2abad0197..7cfbc07e7f77 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -49,6 +49,8 @@ config AD4030 depends on GPIOLIB select REGMAP select IIO_BUFFER + select IIO_BUFFER_DMA + select IIO_BUFFER_DMAENGINE select IIO_TRIGGERED_BUFFER help Say yes here to build support for Analog Devices AD4030 and AD4630 high= speed diff --git a/drivers/iio/adc/ad4030.c b/drivers/iio/adc/ad4030.c index 82784593f976..68f76432dbfd 100644 --- a/drivers/iio/adc/ad4030.c +++ b/drivers/iio/adc/ad4030.c @@ -15,11 +15,15 @@ =20 #include #include +#include +#include #include #include #include +#include #include #include +#include #include #include #include @@ -111,6 +115,8 @@ #define AD4632_TCYC_NS 2000 #define AD4632_TCYC_ADJUSTED_NS (AD4632_TCYC_NS - AD4030_TCNVL_NS) #define AD4030_TRESET_COM_DELAY_MS 750 +/* Datasheet says 9.8ns, so use the closest integer value */ +#define AD4030_TQUIET_CNV_DELAY_NS 10 =20 enum ad4030_out_mode { AD4030_OUT_DATA_MD_DIFF, @@ -120,7 +126,7 @@ enum ad4030_out_mode { AD4030_OUT_DATA_MD_32_PATTERN, }; =20 -enum { +enum ad4030_lane_mode { AD4030_LANE_MD_1_PER_CH, AD4030_LANE_MD_2_PER_CH, AD4030_LANE_MD_4_PER_CH, @@ -130,17 +136,21 @@ enum { enum { AD4030_SCAN_TYPE_NORMAL, AD4030_SCAN_TYPE_AVG, + AD4030_OFFLOAD_SCAN_TYPE_NORMAL, + AD4030_OFFLOAD_SCAN_TYPE_AVG, }; =20 struct ad4030_chip_info { const char *name; const unsigned long *available_masks; const struct iio_chan_spec channels[AD4030_MAX_IIO_CHANNEL_NB]; + const struct iio_chan_spec offload_channels[AD4030_MAX_IIO_CHANNEL_NB]; u8 grade; u8 precision_bits; /* Number of hardware channels */ int num_voltage_inputs; unsigned int tcyc_ns; + unsigned int max_sample_rate_hz; }; =20 struct ad4030_state { @@ -148,11 +158,20 @@ struct ad4030_state { struct regmap *regmap; const struct ad4030_chip_info *chip; struct gpio_desc *cnv_gpio; + struct pwm_device *conv_trigger; + struct pwm_waveform conv_wf; int vref_uv; int vio_uv; int offset_avail[3]; unsigned int avg_log2; enum ad4030_out_mode mode; + enum ad4030_lane_mode lane_mode; + /* offload sampling spi message */ + struct spi_transfer offload_xfer; + struct spi_message offload_msg; + struct spi_offload *offload; + struct spi_offload_trigger *offload_trigger; + struct spi_offload_trigger_config offload_trigger_config; =20 /* * DMA (thus cache coherency maintenance) requires the transfer buffers @@ -209,12 +228,13 @@ struct ad4030_state { * - voltage0-voltage1 * - voltage2-voltage3 */ -#define AD4030_CHAN_DIFF(_idx, _scan_type) { \ +#define __AD4030_CHAN_DIFF(_idx, _scan_type, _offload) { \ .info_mask_shared_by_all =3D \ BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ .info_mask_shared_by_all_available =3D \ BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ .info_mask_separate =3D BIT(IIO_CHAN_INFO_SCALE) | \ + (_offload ? BIT(IIO_CHAN_INFO_SAMP_FREQ) : 0) | \ BIT(IIO_CHAN_INFO_CALIBSCALE) | \ BIT(IIO_CHAN_INFO_CALIBBIAS) | \ BIT(IIO_CHAN_INFO_RAW), \ @@ -232,12 +252,23 @@ struct ad4030_state { .num_ext_scan_type =3D ARRAY_SIZE(_scan_type), \ } =20 +#define AD4030_CHAN_DIFF(_idx, _scan_type) \ + __AD4030_CHAN_DIFF(_idx, _scan_type, 0) + +#define AD4030_OFFLOAD_CHAN_DIFF(_idx, _scan_type) \ + __AD4030_CHAN_DIFF(_idx, _scan_type, 1) + static const int ad4030_average_modes[] =3D { 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536, }; =20 +static const struct spi_offload_config ad4030_offload_config =3D { + .capability_flags =3D SPI_OFFLOAD_CAP_TRIGGER | + SPI_OFFLOAD_CAP_RX_STREAM_DMA, +}; + static int ad4030_enter_config_mode(struct ad4030_state *st) { st->tx_data[0] =3D AD4030_REG_ACCESS; @@ -385,7 +416,7 @@ static int ad4030_get_chan_scale(struct iio_dev *indio_= dev, struct ad4030_state *st =3D iio_priv(indio_dev); const struct iio_scan_type *scan_type; =20 - scan_type =3D iio_get_current_scan_type(indio_dev, st->chip->channels); + scan_type =3D iio_get_current_scan_type(indio_dev, chan); if (IS_ERR(scan_type)) return PTR_ERR(scan_type); =20 @@ -458,6 +489,96 @@ static int ad4030_get_chan_calibbias(struct iio_dev *i= ndio_dev, } } =20 +static void ad4030_get_sampling_freq(const struct ad4030_state *st, int *f= req) +{ + *freq =3D DIV_ROUND_CLOSEST_ULL(NANO, st->conv_wf.period_length_ns); +} + +static int __ad4030_set_sampling_freq(struct ad4030_state *st, unsigned in= t freq) +{ + struct spi_offload_trigger_config *config =3D &st->offload_trigger_config; + struct pwm_waveform conv_wf =3D { }; + u64 offload_period_ns; + u64 offload_offset_ns; + u32 mode; + int ret; + u64 target =3D AD4030_TCNVH_NS; + + conv_wf.period_length_ns =3D DIV_ROUND_CLOSEST(NSEC_PER_SEC, freq); + /* + * The datasheet lists a minimum time of 9.8 ns, but no maximum. If the + * rounded PWM's value is less than 10, increase the target value by 10 + * and attempt to round the waveform again, until the value is at least + * 10 ns. Use a separate variable to represent the target in case the + * rounding is severe enough to keep putting the first few results under + * the minimum 10ns condition checked by the while loop. + */ + do { + conv_wf.duty_length_ns =3D target; + ret =3D pwm_round_waveform_might_sleep(st->conv_trigger, &conv_wf); + if (ret) + return ret; + target +=3D 10; + } while (conv_wf.duty_length_ns < 10); + + offload_period_ns =3D conv_wf.period_length_ns; + + ret =3D regmap_read(st->regmap, AD4030_REG_MODES, &mode); + if (ret) + return ret; + if (FIELD_GET(AD4030_REG_MODES_MASK_OUT_DATA_MODE, mode) =3D=3D AD4030_OU= T_DATA_MD_30_AVERAGED_DIFF) { + u32 avg; + + ret =3D regmap_read(st->regmap, AD4030_REG_AVG, &avg); + if (ret) + return ret; + + offload_period_ns <<=3D FIELD_GET(AD4030_REG_AVG_MASK_AVG_VAL, avg); + } + + config->periodic.frequency_hz =3D DIV_ROUND_UP_ULL(NSEC_PER_SEC, + offload_period_ns); + + /* + * The hardware does the capture on zone 2 (when spi trigger PWM + * is used). This means that the spi trigger signal should happen at + * tsync + tquiet_con_delay being tsync the conversion signal period + * and tquiet_con_delay 9.8ns. Hence set the PWM phase accordingly. + * + * The PWM waveform API only supports nanosecond resolution right now, + * so round this setting to the closest available value. + */ + offload_offset_ns =3D AD4030_TQUIET_CNV_DELAY_NS; + do { + config->periodic.offset_ns =3D offload_offset_ns; + ret =3D spi_offload_trigger_validate(st->offload_trigger, config); + if (ret) + return ret; + offload_offset_ns +=3D 10; + + } while (config->periodic.offset_ns < AD4030_TQUIET_CNV_DELAY_NS); + + st->conv_wf =3D conv_wf; + + return 0; +} + +static int ad4030_set_sampling_freq(struct iio_dev *indio_dev, unsigned in= t freq) +{ + struct ad4030_state *st =3D iio_priv(indio_dev); + int ret; + + if (PTR_ERR_OR_ZERO(st->offload)) + return -EINVAL; + + if (!freq || freq > st->chip->max_sample_rate_hz) + return -EINVAL; + + ret =3D __ad4030_set_sampling_freq(st, freq); + iio_device_release_direct(indio_dev); + + return ret; +} static int ad4030_set_chan_calibscale(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int gain_int, @@ -618,7 +739,7 @@ static int ad4030_conversion(struct iio_dev *indio_dev) unsigned int i; int ret; =20 - scan_type =3D iio_get_current_scan_type(indio_dev, st->chip->channels); + scan_type =3D iio_get_current_scan_type(indio_dev, &indio_dev->channels[0= ]); if (IS_ERR(scan_type)) return PTR_ERR(scan_type); =20 @@ -774,6 +895,13 @@ static int ad4030_read_raw_dispatch(struct iio_dev *in= dio_dev, *val =3D BIT(st->avg_log2); return IIO_VAL_INT; =20 + case IIO_CHAN_INFO_SAMP_FREQ: + if (PTR_ERR_OR_ZERO(st->offload)) + return -EINVAL; + + ad4030_get_sampling_freq(st, val); + return IIO_VAL_INT; + default: return -EINVAL; } @@ -814,6 +942,9 @@ static int ad4030_write_raw_dispatch(struct iio_dev *in= dio_dev, case IIO_CHAN_INFO_OVERSAMPLING_RATIO: return ad4030_set_avg_frame_len(indio_dev, val); =20 + case IIO_CHAN_INFO_SAMP_FREQ: + return ad4030_set_sampling_freq(indio_dev, val); + default: return -EINVAL; } @@ -868,7 +999,11 @@ static int ad4030_get_current_scan_type(const struct i= io_dev *indio_dev, { struct ad4030_state *st =3D iio_priv(indio_dev); =20 - return st->avg_log2 ? AD4030_SCAN_TYPE_AVG : AD4030_SCAN_TYPE_NORMAL; + if (PTR_ERR_OR_ZERO(st->offload)) + return st->avg_log2 ? AD4030_SCAN_TYPE_AVG : AD4030_SCAN_TYPE_NORMAL; + else + return st->avg_log2 ? AD4030_OFFLOAD_SCAN_TYPE_AVG : + AD4030_OFFLOAD_SCAN_TYPE_NORMAL; } =20 static int ad4030_update_scan_mode(struct iio_dev *indio_dev, @@ -903,6 +1038,67 @@ static const struct iio_buffer_setup_ops ad4030_buffe= r_setup_ops =3D { .validate_scan_mask =3D ad4030_validate_scan_mask, }; =20 +static int ad4030_offload_buffer_postenable(struct iio_dev *indio_dev) +{ + struct ad4030_state *st =3D iio_priv(indio_dev); + int ret; + + ret =3D regmap_write(st->regmap, AD4030_REG_EXIT_CFG_MODE, BIT(0)); + if (ret) + return ret; + + st->offload_msg.offload =3D st->offload; + ret =3D spi_optimize_message(st->spi, &st->offload_msg); + if (ret < 0) + goto out_reset_mode; + + ret =3D pwm_set_waveform_might_sleep(st->conv_trigger, &st->conv_wf, fals= e); + if (ret) + goto out_unoptimize; + + ret =3D spi_offload_trigger_enable(st->offload, st->offload_trigger, + &st->offload_trigger_config); + if (ret) + goto out_pwm_disable; + return 0; +out_pwm_disable: + pwm_disable(st->conv_trigger); +out_unoptimize: + spi_unoptimize_message(&st->offload_msg); +out_reset_mode: + /* reenter register configuration mode */ + ret =3D ad4030_enter_config_mode(st); + if (ret) + dev_warn(&st->spi->dev, + "couldn't reenter register configuration mode\n"); + return ret; +} + +static int ad4030_offload_buffer_predisable(struct iio_dev *indio_dev) +{ + struct ad4030_state *st =3D iio_priv(indio_dev); + int ret; + + pwm_disable(st->conv_trigger); + + spi_offload_trigger_disable(st->offload, st->offload_trigger); + + spi_unoptimize_message(&st->offload_msg); + + /* reenter register configuration mode */ + ret =3D ad4030_enter_config_mode(st); + if (ret) + dev_warn(&st->spi->dev, + "couldn't reenter register configuration mode\n"); + + return ret; +} + +static const struct iio_buffer_setup_ops ad4030_offload_buffer_setup_ops = =3D { + .postenable =3D &ad4030_offload_buffer_postenable, + .predisable =3D &ad4030_offload_buffer_predisable, +}; + static int ad4030_regulators_get(struct ad4030_state *st) { struct device *dev =3D &st->spi->dev; @@ -972,6 +1168,44 @@ static int ad4030_detect_chip_info(const struct ad403= 0_state *st) return 0; } =20 +static int ad4030_pwm_get(struct ad4030_state *st) +{ + struct device *dev =3D &st->spi->dev; + + st->conv_trigger =3D devm_pwm_get(dev, "cnv"); + if (IS_ERR(st->conv_trigger)) + return dev_err_probe(dev, PTR_ERR(st->conv_trigger), + "Failed to get cnv pwm\n"); + + /* + * Preemptively disable the PWM, since we only want to enable it with + * the buffer + */ + pwm_disable(st->conv_trigger); + + return 0; +} + +static void ad4030_prepare_offload_msg(struct ad4030_state *st) +{ + u8 data_width =3D st->chip->precision_bits; + u8 offload_bpw; + + if (st->lane_mode =3D=3D AD4030_LANE_MD_INTERLEAVED) + /* + * This means all channels on 1 lane. + */ + offload_bpw =3D data_width * st->chip->num_voltage_inputs; + else + offload_bpw =3D data_width; + + st->offload_xfer.speed_hz =3D AD4030_SPI_MAX_REG_XFER_SPEED; + st->offload_xfer.bits_per_word =3D offload_bpw; + st->offload_xfer.len =3D roundup_pow_of_two(BITS_TO_BYTES(offload_bpw)); + st->offload_xfer.offload_flags =3D SPI_OFFLOAD_XFER_RX_STREAM; + spi_message_init_with_transfers(&st->offload_msg, &st->offload_xfer, 1); +} + static int ad4030_config(struct ad4030_state *st) { int ret; @@ -982,11 +1216,11 @@ static int ad4030_config(struct ad4030_state *st) st->offset_avail[2] =3D BIT(st->chip->precision_bits - 1) - 1; =20 if (st->chip->num_voltage_inputs > 1) - reg_modes =3D FIELD_PREP(AD4030_REG_MODES_MASK_LANE_MODE, - AD4030_LANE_MD_INTERLEAVED); + st->lane_mode =3D AD4030_LANE_MD_INTERLEAVED; else - reg_modes =3D FIELD_PREP(AD4030_REG_MODES_MASK_LANE_MODE, - AD4030_LANE_MD_1_PER_CH); + st->lane_mode =3D AD4030_LANE_MD_1_PER_CH; + + reg_modes =3D FIELD_PREP(AD4030_REG_MODES_MASK_LANE_MODE, st->lane_mode); =20 ret =3D regmap_write(st->regmap, AD4030_REG_MODES, reg_modes); if (ret) @@ -999,6 +1233,31 @@ static int ad4030_config(struct ad4030_state *st) return 0; } =20 +static int ad4030_spi_offload_setup(struct iio_dev *indio_dev, + struct ad4030_state *st) +{ + struct device *dev =3D &st->spi->dev; + struct dma_chan *rx_dma; + + indio_dev->setup_ops =3D &ad4030_offload_buffer_setup_ops; + + st->offload_trigger =3D devm_spi_offload_trigger_get(dev, st->offload, + SPI_OFFLOAD_TRIGGER_PERIODIC); + if (IS_ERR(st->offload_trigger)) + return dev_err_probe(dev, PTR_ERR(st->offload_trigger), + "failed to get offload trigger\n"); + + st->offload_trigger_config.type =3D SPI_OFFLOAD_TRIGGER_PERIODIC; + + rx_dma =3D devm_spi_offload_rx_stream_request_dma_chan(dev, st->offload); + if (IS_ERR(rx_dma)) + return dev_err_probe(dev, PTR_ERR(rx_dma), + "failed to get offload RX DMA\n"); + + return devm_iio_dmaengine_buffer_setup_with_handle(dev, indio_dev, rx_dma, + IIO_BUFFER_DIRECTION_IN); +} + static int ad4030_probe(struct spi_device *spi) { struct device *dev =3D &spi->dev; @@ -1050,24 +1309,55 @@ static int ad4030_probe(struct spi_device *spi) return dev_err_probe(dev, PTR_ERR(st->cnv_gpio), "Failed to get cnv gpio\n"); =20 - /* - * One hardware channel is split in two software channels when using - * common byte mode. Add one more channel for the timestamp. - */ - indio_dev->num_channels =3D 2 * st->chip->num_voltage_inputs + 1; indio_dev->name =3D st->chip->name; indio_dev->modes =3D INDIO_DIRECT_MODE; indio_dev->info =3D &ad4030_iio_info; - indio_dev->channels =3D st->chip->channels; - indio_dev->available_scan_masks =3D st->chip->available_masks; =20 - ret =3D devm_iio_triggered_buffer_setup(dev, indio_dev, - iio_pollfunc_store_time, - ad4030_trigger_handler, - &ad4030_buffer_setup_ops); - if (ret) - return dev_err_probe(dev, ret, - "Failed to setup triggered buffer\n"); + st->offload =3D devm_spi_offload_get(dev, spi, &ad4030_offload_config); + ret =3D PTR_ERR_OR_ZERO(st->offload); + if (ret && ret !=3D -ENODEV) + return dev_err_probe(dev, ret, "failed to get offload\n"); + + /* Fall back to low speed usage when no SPI offload available. */ + if (ret =3D=3D -ENODEV) { + /* + * One hardware channel is split in two software channels when + * using common byte mode. Add one more channel for the timestamp. + */ + indio_dev->num_channels =3D 2 * st->chip->num_voltage_inputs + 1; + indio_dev->channels =3D st->chip->channels; + indio_dev->available_scan_masks =3D st->chip->available_masks; + + ret =3D devm_iio_triggered_buffer_setup(dev, indio_dev, + iio_pollfunc_store_time, + ad4030_trigger_handler, + &ad4030_buffer_setup_ops); + if (ret) + return dev_err_probe(dev, ret, + "Failed to setup triggered buffer\n"); + + } else { + /* + * One hardware channel is split in two software channels when + * using common byte mode. Offloaded SPI transfers can't support + * software timestamp so no additional timestamp channel is added. + */ + indio_dev->num_channels =3D 2 * st->chip->num_voltage_inputs; + indio_dev->channels =3D st->chip->offload_channels; + indio_dev->available_scan_masks =3D st->chip->available_masks; + ret =3D ad4030_spi_offload_setup(indio_dev, st); + if (ret) + return dev_err_probe(dev, ret, + "Failed to setup SPI offload\n"); + + ret =3D ad4030_pwm_get(st); + if (ret) + return dev_err_probe(&spi->dev, ret, + "Failed to get PWM: %d\n", ret); + + ret =3D __ad4030_set_sampling_freq(st, st->chip->max_sample_rate_hz); + ad4030_prepare_offload_msg(st); + } =20 return devm_iio_device_register(dev, indio_dev); } @@ -1103,6 +1393,20 @@ static const struct iio_scan_type ad4030_24_scan_typ= es[] =3D { .shift =3D 2, .endianness =3D IIO_BE, }, + [AD4030_OFFLOAD_SCAN_TYPE_NORMAL] =3D { + .sign =3D 's', + .storagebits =3D 32, + .realbits =3D 24, + .shift =3D 0, + .endianness =3D IIO_CPU, + }, + [AD4030_OFFLOAD_SCAN_TYPE_AVG] =3D { + .sign =3D 's', + .storagebits =3D 32, + .realbits =3D 30, + .shift =3D 2, + .endianness =3D IIO_CPU, + }, }; =20 static const struct iio_scan_type ad4030_16_scan_types[] =3D { @@ -1119,7 +1423,21 @@ static const struct iio_scan_type ad4030_16_scan_typ= es[] =3D { .realbits =3D 30, .shift =3D 2, .endianness =3D IIO_BE, - } + }, + [AD4030_OFFLOAD_SCAN_TYPE_NORMAL] =3D { + .sign =3D 's', + .storagebits =3D 32, + .realbits =3D 16, + .shift =3D 0, + .endianness =3D IIO_CPU, + }, + [AD4030_OFFLOAD_SCAN_TYPE_AVG] =3D { + .sign =3D 's', + .storagebits =3D 32, + .realbits =3D 30, + .shift =3D 2, + .endianness =3D IIO_CPU, + }, }; =20 static const struct ad4030_chip_info ad4030_24_chip_info =3D { @@ -1130,10 +1448,15 @@ static const struct ad4030_chip_info ad4030_24_chip= _info =3D { AD4030_CHAN_CMO(1, 0), IIO_CHAN_SOFT_TIMESTAMP(2), }, + .offload_channels =3D { + AD4030_OFFLOAD_CHAN_DIFF(0, ad4030_24_scan_types), + AD4030_CHAN_CMO(1, 0), + }, .grade =3D AD4030_REG_CHIP_GRADE_AD4030_24_GRADE, .precision_bits =3D 24, .num_voltage_inputs =3D 1, .tcyc_ns =3D AD4030_TCYC_ADJUSTED_NS, + .max_sample_rate_hz =3D 2 * MEGA, }; =20 static const struct ad4030_chip_info ad4630_16_chip_info =3D { @@ -1146,10 +1469,17 @@ static const struct ad4030_chip_info ad4630_16_chip= _info =3D { AD4030_CHAN_CMO(3, 1), IIO_CHAN_SOFT_TIMESTAMP(4), }, + .offload_channels =3D { + AD4030_OFFLOAD_CHAN_DIFF(0, ad4030_16_scan_types), + AD4030_OFFLOAD_CHAN_DIFF(1, ad4030_16_scan_types), + AD4030_CHAN_CMO(2, 0), + AD4030_CHAN_CMO(3, 1), + }, .grade =3D AD4030_REG_CHIP_GRADE_AD4630_16_GRADE, .precision_bits =3D 16, .num_voltage_inputs =3D 2, .tcyc_ns =3D AD4030_TCYC_ADJUSTED_NS, + .max_sample_rate_hz =3D 2 * MEGA, }; =20 static const struct ad4030_chip_info ad4630_24_chip_info =3D { @@ -1162,10 +1492,17 @@ static const struct ad4030_chip_info ad4630_24_chip= _info =3D { AD4030_CHAN_CMO(3, 1), IIO_CHAN_SOFT_TIMESTAMP(4), }, + .offload_channels =3D { + AD4030_OFFLOAD_CHAN_DIFF(0, ad4030_24_scan_types), + AD4030_OFFLOAD_CHAN_DIFF(1, ad4030_24_scan_types), + AD4030_CHAN_CMO(2, 0), + AD4030_CHAN_CMO(3, 1), + }, .grade =3D AD4030_REG_CHIP_GRADE_AD4630_24_GRADE, .precision_bits =3D 24, .num_voltage_inputs =3D 2, .tcyc_ns =3D AD4030_TCYC_ADJUSTED_NS, + .max_sample_rate_hz =3D 2 * MEGA, }; =20 static const struct ad4030_chip_info ad4632_16_chip_info =3D { @@ -1178,10 +1515,17 @@ static const struct ad4030_chip_info ad4632_16_chip= _info =3D { AD4030_CHAN_CMO(3, 1), IIO_CHAN_SOFT_TIMESTAMP(4), }, + .offload_channels =3D { + AD4030_OFFLOAD_CHAN_DIFF(0, ad4030_16_scan_types), + AD4030_OFFLOAD_CHAN_DIFF(1, ad4030_16_scan_types), + AD4030_CHAN_CMO(2, 0), + AD4030_CHAN_CMO(3, 1), + }, .grade =3D AD4030_REG_CHIP_GRADE_AD4632_16_GRADE, .precision_bits =3D 16, .num_voltage_inputs =3D 2, .tcyc_ns =3D AD4632_TCYC_ADJUSTED_NS, + .max_sample_rate_hz =3D 500 * KILO, }; =20 static const struct ad4030_chip_info ad4632_24_chip_info =3D { @@ -1194,10 +1538,17 @@ static const struct ad4030_chip_info ad4632_24_chip= _info =3D { AD4030_CHAN_CMO(3, 1), IIO_CHAN_SOFT_TIMESTAMP(4), }, + .offload_channels =3D { + AD4030_OFFLOAD_CHAN_DIFF(0, ad4030_24_scan_types), + AD4030_OFFLOAD_CHAN_DIFF(1, ad4030_24_scan_types), + AD4030_CHAN_CMO(2, 0), + AD4030_CHAN_CMO(3, 1), + }, .grade =3D AD4030_REG_CHIP_GRADE_AD4632_24_GRADE, .precision_bits =3D 24, .num_voltage_inputs =3D 2, .tcyc_ns =3D AD4632_TCYC_ADJUSTED_NS, + .max_sample_rate_hz =3D 500 * KILO, }; =20 static const struct spi_device_id ad4030_id_table[] =3D { @@ -1233,3 +1584,4 @@ module_spi_driver(ad4030_driver); MODULE_AUTHOR("Esteban Blanc "); MODULE_DESCRIPTION("Analog Devices AD4630 ADC family driver"); MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("IIO_DMAENGINE_BUFFER"); --=20 2.39.2 From nobody Fri Oct 3 13:21:33 2025 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B00B16DC28; Sat, 30 Aug 2025 00:43:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756514615; cv=none; b=PkFUN5zo/9h8iLj1H9QlNDFDLY6PfkXFLnJZYjIS4BSS5DMd1ARwdi3FcO6JP61gKUSBJ04137J32hNjsiCrQHo0pM/nk2CTLExZ8+OtVncBaDYj6H7P5uucMNc1RyS5BkkgCV6zYdOp4m8joCZAE+9EL9k9ywRqSBhFun0F1Q4= ARC-Message-Signature: i=1; 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Fri, 29 Aug 2025 20:43:13 -0400 From: Marcelo Schmitt To: , , , , CC: , , , , , , , , , , , , , , Subject: [PATCH 08/15] dt-bindings: iio: adc: adi,ad4030: Add 4-lane per channel bus width option Date: Fri, 29 Aug 2025 21:43:10 -0300 Message-ID: <8011cd2b2f2fe6fd162bc4b4b75ec64255516a87.1756511030.git.marcelo.schmitt@analog.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODI1MDA3NSBTYWx0ZWRfXxqhY9BBUQb0M Qo61sUskWsxUYpPy86xKNOj3fmjc31msUCyr42/o2ZSRp2vVD9AgFnpUZQbkfpzJBpp5Js8VpZ/ xD89Kz9A4EIXjWkjq9VOqXI5W/1Zcrh0bInW78Njxt4k1yoOOK0CcHZoMnZzF3Wdva05c+qqLq6 FDUZsdQTXd/NEatkDtBMEfG1ZaLr/dg/cgwQDGq0GG78dCNNy3J6qKM68/M/gwEflccyhPsjZ6u /r1WwgKzm5DaHFuOkEEa0mGLQeg7tQSnkww6c7dfNC8wCZvN6P6SI9uXz7XK2YzoP9ElXB5SL1i t+MUutP5+A1PbFteuW8lMI4pYZq7IuD8El3oKsgBFQA77QNNrDDFrbVV1uIgULzWE0eO+Ci2+VN FNPr9/bM X-Proofpoint-ORIG-GUID: VPSe03N6ByXMQDltH_3iNVdd7zzpcyvD X-Proofpoint-GUID: _Vs8m2Vt4ag-jTHQUsmDJqdOkdEACasO X-Authority-Analysis: v=2.4 cv=AoXu3P9P c=1 sm=1 tr=0 ts=68b24931 cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=2OwXVqhp2XgA:10 a=gAnH3GRIAAAA:8 a=lK7_pbyzKmk9y7L_IogA:9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-29_07,2025-08-28_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 priorityscore=1501 malwarescore=0 clxscore=1015 adultscore=0 bulkscore=0 phishscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508250075 Content-Type: text/plain; charset="utf-8" AD4630 has two input channels and each of them can have it's data output in 4 dedicated lines, resulting in a total of 8 data lines used by the device. Document the option that specifies the case where AD4630 and similar ADCs provide data through 8 SPI lines. Signed-off-by: Marcelo Schmitt --- Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad4030.yaml index 564b6f67a96e..bee85087a7b2 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml @@ -39,7 +39,7 @@ properties: maximum: 102040816 =20 spi-rx-bus-width: - enum: [1, 2, 4] + enum: [1, 2, 4, 8] =20 vdd-5v-supply: true vdd-1v8-supply: true --=20 2.39.2 From nobody Fri Oct 3 13:21:33 2025 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0801C1AF0A7; Sat, 30 Aug 2025 00:43:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; 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charset="utf-8" AD4030 and similar chips can output ADC sample data through 1, 2, or 4 lines per channel. The number of SPI lines the device uses to output data is specified in firmware. Parse SPI read bus width setting from firmware and configure the device to use that amount of lines to output data. Co-developed-by: Sergiu Cuciurean Signed-off-by: Sergiu Cuciurean Signed-off-by: Marcelo Schmitt --- drivers/iio/adc/ad4030.c | 33 ++++++++++++++++++++++++++++++--- 1 file changed, 30 insertions(+), 3 deletions(-) diff --git a/drivers/iio/adc/ad4030.c b/drivers/iio/adc/ad4030.c index 68f76432dbfd..e6c1c9be1632 100644 --- a/drivers/iio/adc/ad4030.c +++ b/drivers/iio/adc/ad4030.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -258,6 +259,10 @@ struct ad4030_state { #define AD4030_OFFLOAD_CHAN_DIFF(_idx, _scan_type) \ __AD4030_CHAN_DIFF(_idx, _scan_type, 1) =20 +static const int ad4030_rx_bus_width[] =3D { + 1, 2, 4, 8, +}; + static const int ad4030_average_modes[] =3D { 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, @@ -1197,7 +1202,7 @@ static void ad4030_prepare_offload_msg(struct ad4030_= state *st) */ offload_bpw =3D data_width * st->chip->num_voltage_inputs; else - offload_bpw =3D data_width; + offload_bpw =3D data_width / (1 << st->lane_mode); =20 st->offload_xfer.speed_hz =3D AD4030_SPI_MAX_REG_XFER_SPEED; st->offload_xfer.bits_per_word =3D offload_bpw; @@ -1208,6 +1213,10 @@ static void ad4030_prepare_offload_msg(struct ad4030= _state *st) =20 static int ad4030_config(struct ad4030_state *st) { + struct device *dev =3D &st->spi->dev; + const char *propname; + u32 rx_bus_width; + unsigned int i; int ret; u8 reg_modes; =20 @@ -1215,10 +1224,28 @@ static int ad4030_config(struct ad4030_state *st) st->offset_avail[1] =3D 1; st->offset_avail[2] =3D BIT(st->chip->precision_bits - 1) - 1; =20 - if (st->chip->num_voltage_inputs > 1) + /* Optional property specifying the number of lanes to read ADC data */ + propname =3D "spi-rx-bus-width"; + rx_bus_width =3D ad4030_rx_bus_width[0]; /* Default to 1 rx lane. */ + device_property_read_u32(dev, propname, &rx_bus_width); + /* Check the rx bus width is valid */ + for (i =3D 0; i < ARRAY_SIZE(ad4030_rx_bus_width); i++) + if (ad4030_rx_bus_width[i] =3D=3D rx_bus_width) + break; + + if (i >=3D ARRAY_SIZE(ad4030_rx_bus_width)) + return dev_err_probe(dev, -EINVAL, "Invalid %s: %u\n", + propname, rx_bus_width); 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charset="utf-8" AD4030 and similar designs support three different options for the clock that frames ADC output data. Each option implies a different hardware configuration for reading ADC data. Document AD4030 clock mode options. Co-developed-by: Sergiu Cuciurean Signed-off-by: Sergiu Cuciurean Signed-off-by: Marcelo Schmitt --- .../devicetree/bindings/iio/adc/adi,ad4030.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad4030.yaml index bee85087a7b2..1e4e025b835f 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml @@ -78,6 +78,18 @@ properties: interrupt-names: const: busy =20 + adi,clock-mode: + $ref: /schemas/types.yaml#/definitions/string + enum: [ spi, echo, host ] + default: spi + description: + Describes how the clock that frames ADC data output is setup. + spi - Spi-compatible. Normal SPI operation clocking. + echo - Echo-clock. Synchronous clock echoing to ease timing requirem= ents + when using isolation on the digital interface. + host - Host. The Host clock mode uses an internal oscillator to cloc= k out + the data bits. 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charset="utf-8" AD4030 series of ADCs support three different options for the clock that frames data output. Since each clock option implies a different hardware setup, the clock mode to use is specified in firmware. Read the designated clock option from firmware and configure the device to work accordingly. Co-developed-by: Sergiu Cuciurean Signed-off-by: Sergiu Cuciurean Signed-off-by: Marcelo Schmitt --- drivers/iio/adc/ad4030.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/iio/adc/ad4030.c b/drivers/iio/adc/ad4030.c index e6c1c9be1632..a5931056936a 100644 --- a/drivers/iio/adc/ad4030.c +++ b/drivers/iio/adc/ad4030.c @@ -74,6 +74,7 @@ (AD4030_REG_GAIN_X0_MSB + (AD4030_REG_GAIN_BYTES_NB * (ch))) #define AD4030_REG_MODES 0x20 #define AD4030_REG_MODES_MASK_OUT_DATA_MODE GENMASK(2, 0) +#define AD4030_REG_MODES_MASK_CLOCK_MODE GENMASK(5, 4) #define AD4030_REG_MODES_MASK_LANE_MODE GENMASK(7, 6) #define AD4030_REG_OSCILATOR 0x21 #define AD4030_REG_IO 0x22 @@ -127,6 +128,12 @@ enum ad4030_out_mode { AD4030_OUT_DATA_MD_32_PATTERN, }; =20 +enum ad4030_clock_mode { + AD4030_SPI_CLOCK_MODE, + AD4030_ECHO_CLOCK_MODE, + AD4030_CLOCK_HOST_MODE, +}; + enum ad4030_lane_mode { AD4030_LANE_MD_1_PER_CH, AD4030_LANE_MD_2_PER_CH, @@ -167,6 +174,7 @@ struct ad4030_state { unsigned int avg_log2; enum ad4030_out_mode mode; enum ad4030_lane_mode lane_mode; + enum ad4030_clock_mode clock_mode; /* offload sampling spi message */ struct spi_transfer offload_xfer; struct spi_message offload_msg; @@ -263,6 +271,12 @@ static const int ad4030_rx_bus_width[] =3D { 1, 2, 4, 8, }; =20 +static const char * const ad4030_clock_mode_str[] =3D { + [AD4030_SPI_CLOCK_MODE] =3D "spi", + [AD4030_ECHO_CLOCK_MODE] =3D "echo", + [AD4030_CLOCK_HOST_MODE] =3D "host", +}; + static const int ad4030_average_modes[] =3D { 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, @@ -1249,6 +1263,14 @@ static int ad4030_config(struct ad4030_state *st) =20 reg_modes =3D FIELD_PREP(AD4030_REG_MODES_MASK_LANE_MODE, st->lane_mode); =20 + /* Optional data clock mode */ + ret =3D device_property_match_property_string(dev, "adi,clock-mode", + ad4030_clock_mode_str, + ARRAY_SIZE(ad4030_clock_mode_str)); + /* Default to SPI clock mode. */ + reg_modes |=3D FIELD_PREP(AD4030_REG_MODES_MASK_CLOCK_MODE, + ret >=3D 0 ? ret : AD4030_SPI_CLOCK_MODE); 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Fri, 29 Aug 2025 20:44:48 -0400 From: Marcelo Schmitt To: , , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH 12/15] dt-bindings: iio: adc: adi,ad4030: Add adi,dual-data-rate Date: Fri, 29 Aug 2025 21:44:45 -0300 Message-ID: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODI3MDAwMCBTYWx0ZWRfXxLxlqBlzcVd3 e2FKf9TB7v9EO1WHG4RhfgR561OeP7HHOeufy/tXfQpTmN7qo09bRzmpPQ0CeHObbBZ/RWbqCda c4aaaFmY0bDjp1LDuurqtt1xXfFkx6vz3ow7bp5XmNly3sFVMlZcLs4C60lQH1lVhgWqVYB6DqS fivYMWoEkTHgMahr133MA67EwnuL5VEQqBNkIZJOc+eOAnWm/1xvcPmFh1qccmlMWI+W4cf4L+X uTJQZ8uLbVHjveikqevPCGPCPY6BQ6JDQPbmim7UsrGuUd3+8wQUM0yegqs1SVSpdbZgATBps6w aA0wzEnIGB3BzwYEuR8VePPjVvKtZoWULu0XtK/GVTLBxHSj465RxB/zD6XViaa851/SuJHByzj Efj5kZ86 X-Authority-Analysis: v=2.4 cv=Z4bsHGRA c=1 sm=1 tr=0 ts=68b24994 cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=2OwXVqhp2XgA:10 a=gAnH3GRIAAAA:8 a=1jY0wEZUOeTI3omRP7QA:9 X-Proofpoint-ORIG-GUID: OxnmGFVBwnGd_lZgDvt7oLT8O1lu6LnJ X-Proofpoint-GUID: xJrPRKIPNI6YFN_o5XeHG2O3Dja_HPxh X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-29_07,2025-08-28_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 clxscore=1015 malwarescore=0 bulkscore=0 adultscore=0 priorityscore=1501 impostorscore=0 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508270000 Content-Type: text/plain; charset="utf-8" On echo and host clock modes, AD4030 and similar devices can do two data bit transitions per clock cycle per active lane. Document how to specify dual data rate (DDR) feature for AD4030 series devices in device tree. Co-developed-by: Sergiu Cuciurean Signed-off-by: Sergiu Cuciurean Signed-off-by: Marcelo Schmitt --- .../bindings/iio/adc/adi,ad4030.yaml | 27 +++++++++++++++---- 1 file changed, 22 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad4030.yaml index 1e4e025b835f..9adb60629631 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml @@ -90,6 +90,13 @@ properties: host - Host. The Host clock mode uses an internal oscillator to cloc= k out the data bits. In this mode, the spi controller is not drivin= g SCLK. =20 + adi,dual-data-rate: + description: + Enable dual data rate (DDR) in which two bits (per active lane) are + transmitted in one clock cycle. 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charset="utf-8" Set AD4030 series device to do two data bit transitions per clock cycle per active lane when specified by firmware. The dual data rate (DDR) feature is available only for host clock mode and echo clock mode. Co-developed-by: Sergiu Cuciurean Signed-off-by: Sergiu Cuciurean Signed-off-by: Marcelo Schmitt --- drivers/iio/adc/ad4030.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/iio/adc/ad4030.c b/drivers/iio/adc/ad4030.c index a5931056936a..37ba00097efe 100644 --- a/drivers/iio/adc/ad4030.c +++ b/drivers/iio/adc/ad4030.c @@ -74,6 +74,7 @@ (AD4030_REG_GAIN_X0_MSB + (AD4030_REG_GAIN_BYTES_NB * (ch))) #define AD4030_REG_MODES 0x20 #define AD4030_REG_MODES_MASK_OUT_DATA_MODE GENMASK(2, 0) +#define AD4030_REG_MODES_MASK_DDR_MODE BIT(3) #define AD4030_REG_MODES_MASK_CLOCK_MODE GENMASK(5, 4) #define AD4030_REG_MODES_MASK_LANE_MODE GENMASK(7, 6) #define AD4030_REG_OSCILATOR 0x21 @@ -175,6 +176,7 @@ struct ad4030_state { enum ad4030_out_mode mode; enum ad4030_lane_mode lane_mode; enum ad4030_clock_mode clock_mode; + bool ddr; /* offload sampling spi message */ struct spi_transfer offload_xfer; struct spi_message offload_msg; @@ -1218,6 +1220,9 @@ static void ad4030_prepare_offload_msg(struct ad4030_= state *st) else offload_bpw =3D data_width / (1 << st->lane_mode); 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charset="utf-8" ADAQ4216 and ADAQ4224 are similar to AD4030 except ADAQ devices have a PGA (programmable gain amplifier) that scales the input signal prior to it reaching the ADC inputs. The PGA is controlled through a couple of pins (A0 and A1) that set one of four possible signal gain. Signed-off-by: Marcelo Schmitt --- The PGA doc was inspired on ad7191 dt-binding and uses the same properies (= but with different values) to describe the hardware. .../bindings/iio/adc/adi,ad4030.yaml | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad4030.yaml index 9adb60629631..36fd2aa51922 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4030.yaml @@ -19,6 +19,8 @@ description: | * https://www.analog.com/media/en/technical-documentation/data-sheets/ad= 4030-24-4032-24.pdf * https://www.analog.com/media/en/technical-documentation/data-sheets/ad= 4630-24_ad4632-24.pdf * https://www.analog.com/media/en/technical-documentation/data-sheets/ad= 4630-16-4632-16.pdf + * https://www.analog.com/media/en/technical-documentation/data-sheets/ad= aq4216.pdf + * https://www.analog.com/media/en/technical-documentation/data-sheets/ad= aq4224.pdf =20 $ref: /schemas/spi/spi-peripheral-props.yaml# =20 @@ -31,6 +33,8 @@ properties: - adi,ad4630-24 - adi,ad4632-16 - adi,ad4632-24 + - adi,adaq4216 + - adi,adaq4224 =20 reg: maxItems: 1 @@ -64,6 +68,27 @@ properties: The Reset Input (/RST). Used for asynchronous device reset. maxItems: 1 =20 + pga-gpios: + description: + A0 and A1 pins for gain selection. For devices that have PGA configu= ration + input pins, pga-gpios should be defined if adi,gain-milli is absent. + minItems: 2 + maxItems: 2 + + adi,pga-value: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Should be present if PGA control inputs are pin-strapped. The values + specify the gain per mille. For example, 333 means the input signal = is + scaled by a 0.333 factor (i.e. attenuated to one third of it's origi= nal + magnitude). Possible values: + Gain 333 (A1=3D0, A0=3D0) + Gain 556 (A1=3D0, A0=3D1) + Gain 2222 (A1=3D1, A0=3D0) + Gain 6667 (A1=3D1, A0=3D1) + If defined, pga-gpios must be absent. + enum: [333, 556, 2222, 6667] + pwms: description: PWM signal connected to the CNV pin. maxItems: 1 @@ -120,6 +145,20 @@ allOf: then: properties: adi,dual-data-rate: false + # ADAQ devices require a gain property to indicate how hardware PGA is s= et + - if: + properties: + compatible: + contains: + enum: + - adi,adaq4216 + - adi,adaq4224 + then: + oneOf: + - required: + - adi,pga-value + - required: + - pga-gpios =20 unevaluatedProperties: false =20 --=20 2.39.2 From nobody Fri Oct 3 13:21:33 2025 Received: from mx0b-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0511D1A9FBC; Sat, 30 Aug 2025 00:46:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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The PGA is controlled through a pair of pins (A0 and A1) whose state define the gain that is applied to the input signal. Add support for ADAQ4216 and ADAQ4224. Provide a list of PGA options through the IIO device channel scale available interface and enable control of the PGA through the channel scale interface. Signed-off-by: Marcelo Schmitt --- drivers/iio/adc/ad4030.c | 239 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 235 insertions(+), 4 deletions(-) diff --git a/drivers/iio/adc/ad4030.c b/drivers/iio/adc/ad4030.c index 37ba00097efe..32157b3a0420 100644 --- a/drivers/iio/adc/ad4030.c +++ b/drivers/iio/adc/ad4030.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -42,6 +43,8 @@ #define AD4030_REG_CHIP_GRADE_AD4630_24_GRADE 0x00 #define AD4030_REG_CHIP_GRADE_AD4632_16_GRADE 0x05 #define AD4030_REG_CHIP_GRADE_AD4632_24_GRADE 0x02 +#define AD4030_REG_CHIP_GRADE_ADAQ4216_GRADE 0x1E +#define AD4030_REG_CHIP_GRADE_ADAQ4224_GRADE 0x1C #define AD4030_REG_CHIP_GRADE_MASK_CHIP_GRADE GENMASK(7, 3) #define AD4030_REG_SCRATCH_PAD 0x0A #define AD4030_REG_SPI_REVISION 0x0B @@ -121,6 +124,10 @@ /* Datasheet says 9.8ns, so use the closest integer value */ #define AD4030_TQUIET_CNV_DELAY_NS 10 =20 +/* HARDWARE_GAIN */ +#define ADAQ4616_PGA_PINS 2 +#define ADAQ4616_GAIN_MAX_NANO 6666666667 + enum ad4030_out_mode { AD4030_OUT_DATA_MD_DIFF, AD4030_OUT_DATA_MD_16_DIFF_8_COM, @@ -149,6 +156,20 @@ enum { AD4030_OFFLOAD_SCAN_TYPE_AVG, }; =20 +/* + * Gains computed as fractions of 1000 so they can be expressed by integer= s. + */ +static const int ad4030_hw_gains[] =3D { + 333, 556, 2222, 6667, +}; + +static const int ad4030_hw_gains_frac[4][2] =3D { + { 1, 3 }, /* 1/3 gain */ + { 5, 9 }, /* 5/9 gain */ + { 20, 9 }, /* 20/9 gain */ + { 20, 3 }, /* 20/3 gain */ +}; + struct ad4030_chip_info { const char *name; const unsigned long *available_masks; @@ -160,6 +181,7 @@ struct ad4030_chip_info { int num_voltage_inputs; unsigned int tcyc_ns; unsigned int max_sample_rate_hz; + unsigned int num_pga_pins; }; =20 struct ad4030_state { @@ -183,6 +205,10 @@ struct ad4030_state { struct spi_offload *offload; struct spi_offload_trigger *offload_trigger; struct spi_offload_trigger_config offload_trigger_config; + struct gpio_descs *pga_gpios; + int pga_index; + unsigned int scale_avail[ARRAY_SIZE(ad4030_hw_gains)][2]; + size_t scale_avail_size; =20 /* * DMA (thus cache coherency maintenance) requires the transfer buffers @@ -239,7 +265,7 @@ struct ad4030_state { * - voltage0-voltage1 * - voltage2-voltage3 */ -#define __AD4030_CHAN_DIFF(_idx, _scan_type, _offload) { \ +#define __AD4030_CHAN_DIFF(_idx, _scan_type, _offload, _pga) { \ .info_mask_shared_by_all =3D \ BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ .info_mask_shared_by_all_available =3D \ @@ -250,6 +276,7 @@ struct ad4030_state { BIT(IIO_CHAN_INFO_CALIBBIAS) | \ BIT(IIO_CHAN_INFO_RAW), \ .info_mask_separate_available =3D BIT(IIO_CHAN_INFO_CALIBBIAS) | \ + (_pga ? BIT(IIO_CHAN_INFO_SCALE) : 0) | \ BIT(IIO_CHAN_INFO_CALIBSCALE), \ .type =3D IIO_VOLTAGE, \ .indexed =3D 1, \ @@ -264,10 +291,16 @@ struct ad4030_state { } =20 #define AD4030_CHAN_DIFF(_idx, _scan_type) \ - __AD4030_CHAN_DIFF(_idx, _scan_type, 0) + __AD4030_CHAN_DIFF(_idx, _scan_type, 0, 0) =20 #define AD4030_OFFLOAD_CHAN_DIFF(_idx, _scan_type) \ - __AD4030_CHAN_DIFF(_idx, _scan_type, 1) + __AD4030_CHAN_DIFF(_idx, _scan_type, 1, 0) + +#define ADAQ4216_CHAN_DIFF(_idx, _scan_type) \ + __AD4030_CHAN_DIFF(_idx, _scan_type, 0, 1) + +#define ADAQ4216_OFFLOAD_CHAN_DIFF(_idx, _scan_type) \ + __AD4030_CHAN_DIFF(_idx, _scan_type, 1, 1) =20 static const int ad4030_rx_bus_width[] =3D { 1, 2, 4, 8, @@ -429,6 +462,74 @@ static const struct regmap_config ad4030_regmap_config= =3D { .max_register =3D AD4030_REG_DIG_ERR, }; =20 +static void ad4030_fill_scale_avail(struct ad4030_state *st) +{ + unsigned int mag_bits, tmp0, tmp1, i; + u64 range; + + /* + * The maximum precision of differential channels is retrieved from the + * chip properties. The output code of differential channels is in two's + * complement format (i.e. signed), so the MSB is the sign bit and only + * (precision_bits - 1) bits express voltage magnitude. + */ + mag_bits =3D st->chip->precision_bits - 1; + + for (i =3D 0; i < ARRAY_SIZE(ad4030_hw_gains); i++) { + range =3D mult_frac(st->vref_uv, ad4030_hw_gains_frac[i][1], + ad4030_hw_gains_frac[i][0]); + /* + * If range were in mV, we would multiply it by NANO below. + * Though, range is in =C2=B5V so multiply it by MICRO only so the + * result after right shift and division scales output codes to + * millivolts. + */ + tmp0 =3D div_u64_rem(((u64)range * MICRO) >> mag_bits, NANO, &tmp1); + st->scale_avail[i][0] =3D tmp0; /* Integer part */ + st->scale_avail[i][1] =3D tmp1; /* Fractional part */ + } +} + +static int ad4030_set_pga_gain(struct ad4030_state *st) +{ + DECLARE_BITMAP(bitmap, ADAQ4616_PGA_PINS) =3D { }; + + bitmap_write(bitmap, st->pga_index, 0, 2); + + return gpiod_multi_set_value_cansleep(st->pga_gpios, bitmap); +} + +static int ad4030_set_pga(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int gain_int, + int gain_fract) +{ + struct ad4030_state *st =3D iio_priv(indio_dev); + const struct iio_scan_type *scan_type; + unsigned int mag_bits; + u64 gain_nano, tmp; + + if (!st->pga_gpios) + return -EINVAL; + + scan_type =3D iio_get_current_scan_type(indio_dev, chan); + if (scan_type->sign =3D=3D 's') + mag_bits =3D st->chip->precision_bits - 1; + else + mag_bits =3D st->chip->precision_bits; + + gain_nano =3D gain_int * NANO + gain_fract; + + if (!in_range(gain_nano, 0, ADAQ4616_GAIN_MAX_NANO)) + return -EINVAL; + + tmp =3D DIV_ROUND_CLOSEST_ULL(gain_nano << mag_bits, NANO); + gain_nano =3D DIV_ROUND_CLOSEST_ULL(st->vref_uv, tmp); + st->pga_index =3D find_closest(gain_nano, ad4030_hw_gains, + ARRAY_SIZE(ad4030_hw_gains)); + + return ad4030_set_pga_gain(st); +} + static int ad4030_get_chan_scale(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, @@ -455,7 +556,14 @@ static int ad4030_get_chan_scale(struct iio_dev *indio= _dev, *val2 =3D scan_type->realbits =3D=3D 30 ? st->chip->precision_bits : scan_type->realbits; =20 - return IIO_VAL_FRACTIONAL_LOG2; + /* The LSB of the 8-bit common-mode data is always vref/256. */ + if (scan_type->realbits =3D=3D 8 || !st->chip->num_pga_pins) + return IIO_VAL_FRACTIONAL_LOG2; + + *val =3D st->scale_avail[st->pga_index][0]; + *val2 =3D st->scale_avail[st->pga_index][1]; + + return IIO_VAL_INT_PLUS_NANO; } =20 static int ad4030_get_chan_calibscale(struct iio_dev *indio_dev, @@ -654,6 +762,19 @@ static int ad4030_set_chan_calibbias(struct iio_dev *i= ndio_dev, st->tx_data, AD4030_REG_OFFSET_BYTES_NB); } =20 +static int ad4030_write_raw_get_fmt(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, long mask) +{ + switch (mask) { + case IIO_CHAN_INFO_SCALE: + return IIO_VAL_INT_PLUS_NANO; + default: + return IIO_VAL_INT_PLUS_MICRO; + } + + return -EINVAL; +} + static int ad4030_set_avg_frame_len(struct iio_dev *dev, int avg_val) { struct ad4030_state *st =3D iio_priv(dev); @@ -891,6 +1012,15 @@ static int ad4030_read_avail(struct iio_dev *indio_de= v, *length =3D ARRAY_SIZE(ad4030_average_modes); return IIO_AVAIL_LIST; =20 + case IIO_CHAN_INFO_SCALE: + if (!st->pga_gpios) + *vals =3D (int *)st->scale_avail[st->pga_index]; + else + *vals =3D (int *)st->scale_avail; + *length =3D st->scale_avail_size * 2; /* print int and nano part */ + *type =3D IIO_VAL_INT_PLUS_NANO; + return IIO_AVAIL_LIST; + default: return -EINVAL; } @@ -966,6 +1096,9 @@ static int ad4030_write_raw_dispatch(struct iio_dev *i= ndio_dev, case IIO_CHAN_INFO_SAMP_FREQ: return ad4030_set_sampling_freq(indio_dev, val); =20 + case IIO_CHAN_INFO_SCALE: + return ad4030_set_pga(indio_dev, chan, val, val2); + default: return -EINVAL; } @@ -1037,6 +1170,7 @@ static const struct iio_info ad4030_iio_info =3D { .read_avail =3D ad4030_read_avail, .read_raw =3D ad4030_read_raw, .write_raw =3D ad4030_write_raw, + .write_raw_get_fmt =3D &ad4030_write_raw_get_fmt, .debugfs_reg_access =3D ad4030_reg_access, .read_label =3D ad4030_read_label, .get_current_scan_type =3D ad4030_get_current_scan_type, @@ -1318,6 +1452,51 @@ static int ad4030_spi_offload_setup(struct iio_dev *= indio_dev, IIO_BUFFER_DIRECTION_IN); } =20 +static int ad4030_setup_pga(struct device *dev, struct iio_dev *indio_dev, + struct ad4030_state *st) +{ + unsigned int i; + int pga_value; + int ret; + + ret =3D device_property_read_u32(dev, "adi,pga-value", &pga_value); + if (ret && ret !=3D -EINVAL) + return dev_err_probe(dev, ret, "Failed to get PGA value.\n"); + + if (ret =3D=3D -EINVAL) { + /* Setup GPIOs for PGA control */ + st->pga_gpios =3D devm_gpiod_get_array(dev, "pga", GPIOD_OUT_LOW); + if (IS_ERR(st->pga_gpios)) + return dev_err_probe(dev, PTR_ERR(st->pga_gpios), + "Failed to get PGA gpios.\n"); + + if (st->pga_gpios->ndescs !=3D 2) + return dev_err_probe(dev, -EINVAL, + "Expected 2 GPIOs for PGA control.\n"); + + st->scale_avail_size =3D ARRAY_SIZE(ad4030_hw_gains); + st->pga_index =3D 0; + return ad4030_set_pga_gain(st); + } + + /* Set ADC driver to handle pin-strapped PGA pins setup */ + for (i =3D 0; i < ARRAY_SIZE(ad4030_hw_gains); i++) { + if (pga_value !=3D ad4030_hw_gains[i]) + continue; + + st->pga_index =3D i; + break; + } + if (i =3D=3D ARRAY_SIZE(ad4030_hw_gains)) + return dev_err_probe(dev, -EINVAL, "Invalid PGA value: %d.\n", + pga_value); + + st->scale_avail_size =3D 1; + st->pga_gpios =3D NULL; + + return 0; +} + static int ad4030_probe(struct spi_device *spi) { struct device *dev =3D &spi->dev; @@ -1360,6 +1539,14 @@ static int ad4030_probe(struct spi_device *spi) if (ret) return ret; =20 + if (st->chip->num_pga_pins > 0) { + ret =3D ad4030_setup_pga(dev, indio_dev, st); + if (ret) + return ret; + + ad4030_fill_scale_avail(st); + } + ret =3D ad4030_config(st); if (ret) return ret; @@ -1611,12 +1798,54 @@ static const struct ad4030_chip_info ad4632_24_chip= _info =3D { .max_sample_rate_hz =3D 500 * KILO, }; =20 +static const struct ad4030_chip_info adaq4216_chip_info =3D { + .name =3D "adaq4216", + .available_masks =3D ad4030_channel_masks, + .channels =3D { + ADAQ4216_CHAN_DIFF(0, ad4030_16_scan_types), + AD4030_CHAN_CMO(1, 0), + IIO_CHAN_SOFT_TIMESTAMP(2), + }, + .offload_channels =3D { + ADAQ4216_OFFLOAD_CHAN_DIFF(0, ad4030_16_scan_types), + AD4030_CHAN_CMO(1, 0), + }, + .grade =3D AD4030_REG_CHIP_GRADE_ADAQ4216_GRADE, + .precision_bits =3D 16, + .num_voltage_inputs =3D 1, + .tcyc_ns =3D AD4030_TCYC_ADJUSTED_NS, + .max_sample_rate_hz =3D 2 * MEGA, + .num_pga_pins =3D ADAQ4616_PGA_PINS, +}; + +static const struct ad4030_chip_info adaq4224_chip_info =3D { + .name =3D "adaq4224", + .available_masks =3D ad4030_channel_masks, + .channels =3D { + ADAQ4216_CHAN_DIFF(0, ad4030_24_scan_types), + AD4030_CHAN_CMO(1, 0), + IIO_CHAN_SOFT_TIMESTAMP(2), + }, + .offload_channels =3D { + ADAQ4216_OFFLOAD_CHAN_DIFF(0, ad4030_24_scan_types), + AD4030_CHAN_CMO(1, 0), + }, + .grade =3D AD4030_REG_CHIP_GRADE_ADAQ4224_GRADE, + .precision_bits =3D 24, + .num_voltage_inputs =3D 1, + .tcyc_ns =3D AD4030_TCYC_ADJUSTED_NS, + .max_sample_rate_hz =3D 2 * MEGA, + .num_pga_pins =3D ADAQ4616_PGA_PINS, +}; + static const struct spi_device_id ad4030_id_table[] =3D { { "ad4030-24", (kernel_ulong_t)&ad4030_24_chip_info }, { "ad4630-16", (kernel_ulong_t)&ad4630_16_chip_info }, { "ad4630-24", (kernel_ulong_t)&ad4630_24_chip_info }, { "ad4632-16", (kernel_ulong_t)&ad4632_16_chip_info }, { "ad4632-24", (kernel_ulong_t)&ad4632_24_chip_info }, + { "adaq4216", (kernel_ulong_t)&adaq4216_chip_info }, + { "adaq4224", (kernel_ulong_t)&adaq4224_chip_info }, { } }; MODULE_DEVICE_TABLE(spi, ad4030_id_table); @@ -1627,6 +1856,8 @@ static const struct of_device_id ad4030_of_match[] = =3D { { .compatible =3D "adi,ad4630-24", .data =3D &ad4630_24_chip_info }, { .compatible =3D "adi,ad4632-16", .data =3D &ad4632_16_chip_info }, { .compatible =3D "adi,ad4632-24", .data =3D &ad4632_24_chip_info }, + { .compatible =3D "adi,adaq4216", .data =3D &adaq4216_chip_info }, + { .compatible =3D "adi,adaq4224", .data =3D &adaq4224_chip_info }, { } }; MODULE_DEVICE_TABLE(of, ad4030_of_match); --=20 2.39.2