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Tue, 26 Aug 2025 09:38:06 -0700 (PDT) Date: Tue, 26 Aug 2025 19:38:03 +0300 From: Dan Carpenter To: Srinivas Kandagatla Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ciprian Costea , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, NXP S32 Linux Team , linaro-s32@linaro.org Subject: [PATCH V2 1/3] dt-bindings: nvmem: Add the nxp,s32g-ocotp yaml file Message-ID: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Ciprian Costea Add bindings to expose the On Chip One-Time Programmable Controller (OCOTP) for the NXP s32g chipset. There are three versions of this chip but they're compatible so we can fall back to the nxp,s32g2-ocotp compatible. Signed-off-by: Ciprian Costea Signed-off-by: Dan Carpenter Reviewed-by: Conor Dooley --- v2: dt_binding_check DT_SCHEMA_FILES=3Dnxp,s32g-ocotp-nvmem.yaml is clean make CHECK_DTBS=3Dy freescale/*.dtb is clean. Particularly the freescale/s32g274a-evb.dtb file which Rob mentioned. remove bogus include file remove redundant "reg" description remove #address-cells and #size-cells since they are already in nvmem.yaml Fix email From header .../bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 Documentation/devicetree/bindings/nvmem/nxp,s32g-ocotp-= nvmem.yaml diff --git a/Documentation/devicetree/bindings/nvmem/nxp,s32g-ocotp-nvmem.y= aml b/Documentation/devicetree/bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml new file mode 100644 index 000000000000..01adc6093c68 --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/nxp,s32g-ocotp-nvmem.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP S32G OCOTP NVMEM driver + +maintainers: + - Ciprian Costea + +description: | + The drivers provides an interface to access One Time + Programmable memory pages, such as TMU fuse values. + +allOf: + - $ref: nvmem.yaml# + +properties: + compatible: + oneOf: + - enum: + - nxp,s32g2-ocotp + - items: + - enum: + - nxp,s32r45-ocotp + - nxp,s32g3-ocotp + - const: nxp,s32g2-ocotp + reg: + maxItems: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + ocotp: nvmem@400a4000 { + compatible =3D "nxp,s32g2-ocotp"; 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Tue, 26 Aug 2025 09:38:14 -0700 (PDT) Date: Tue, 26 Aug 2025 19:38:10 +0300 From: Dan Carpenter To: Srinivas Kandagatla Cc: NXP S32 Linux Team , linaro-s32@linaro.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH V2 2/3] nvmem: s32g-ocotp: Add driver for S32G OCOTP Message-ID: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Ciprian Costea Provide access to the On Chip One-Time Programmable Controller (OCOTP) pages on the NXP S32G platform. Signed-off-by: Ciprian Costea Co-developed-by: Ghennadi Procopciuc Signed-off-by: Ghennadi Procopciuc Co-developed-by: Larisa Grigore Signed-off-by: Larisa Grigore Signed-off-by: Dan Carpenter --- v2: Add S-o-b tags for Ghennadi and Larisa. Use keepouts instead of the s32g_map[] table. This allows a bunch of code to be deleted. Version 1 only let one word (S32G_OCOTP_WORD_SIZE or 4) to be read at a time, but now the driver allows larger reads. Set the .word_size in s32g_ocotp_nvmem_config to be 4 instead. Krzysztof asked for some changes in the probe() function but that code was deleted instead. drivers/nvmem/Kconfig | 10 +++ drivers/nvmem/Makefile | 2 + drivers/nvmem/s32g-ocotp-nvmem.c | 101 +++++++++++++++++++++++++++++++ 3 files changed, 113 insertions(+) create mode 100644 drivers/nvmem/s32g-ocotp-nvmem.c diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig index 0bdd86d74f62..55016f803492 100644 --- a/drivers/nvmem/Kconfig +++ b/drivers/nvmem/Kconfig @@ -240,6 +240,16 @@ config NVMEM_NINTENDO_OTP This driver can also be built as a module. If so, the module will be called nvmem-nintendo-otp. =20 +config NVMEM_S32G_OCOTP + tristate "S32G SoC OCOTP support" + depends on ARCH_S32 + help + This is a driver for the 'OCOTP' peripheral available on S32G + platforms. + + If you say Y here, you will get support for the One Time + Programmable memory pages. + config NVMEM_QCOM_QFPROM tristate "QCOM QFPROM Support" depends on ARCH_QCOM || COMPILE_TEST diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile index 84fef48b7ff6..e01bb4ad612a 100644 --- a/drivers/nvmem/Makefile +++ b/drivers/nvmem/Makefile @@ -79,6 +79,8 @@ obj-$(CONFIG_NVMEM_SUNPLUS_OCOTP) +=3D nvmem_sunplus_ocot= p.o nvmem_sunplus_ocotp-y :=3D sunplus-ocotp.o obj-$(CONFIG_NVMEM_SUNXI_SID) +=3D nvmem_sunxi_sid.o nvmem_sunxi_sid-y :=3D sunxi_sid.o +obj-$(CONFIG_NVMEM_S32G_OCOTP) +=3D nvmem-s32g-ocotp-nvmem.o +nvmem-s32g-ocotp-nvmem-y :=3D s32g-ocotp-nvmem.o obj-$(CONFIG_NVMEM_U_BOOT_ENV) +=3D nvmem_u-boot-env.o nvmem_u-boot-env-y :=3D u-boot-env.o obj-$(CONFIG_NVMEM_UNIPHIER_EFUSE) +=3D nvmem-uniphier-efuse.o diff --git a/drivers/nvmem/s32g-ocotp-nvmem.c b/drivers/nvmem/s32g-ocotp-nv= mem.c new file mode 100644 index 000000000000..dce092c0fc52 --- /dev/null +++ b/drivers/nvmem/s32g-ocotp-nvmem.c @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2023-2025 NXP + */ + +#include +#include +#include +#include +#include +#include +#include + +struct s32g_ocotp_priv { + struct device *dev; + void __iomem *base; +}; + +static int s32g_ocotp_read(void *context, unsigned int offset, + void *val, size_t bytes) +{ + struct s32g_ocotp_priv *s32g_data =3D context; + u32 *dst =3D val; + + while (bytes >=3D sizeof(u32)) { + *dst++ =3D ioread32(s32g_data->base + offset); + + bytes -=3D sizeof(u32); + offset +=3D sizeof(u32); + } + + return 0; +} + +static struct nvmem_keepout s32g_keepouts[] =3D { + { .start =3D 0, .end =3D 520 }, + { .start =3D 540, .end =3D 564 }, + { .start =3D 596, .end =3D 664 }, + { .start =3D 668, .end =3D 676 }, + { .start =3D 684, .end =3D 732 }, + { .start =3D 744, .end =3D 864 }, + { .start =3D 908, .end =3D 924 }, + { .start =3D 928, .end =3D 936 }, + { .start =3D 948, .end =3D 964 }, + { .start =3D 968, .end =3D 976 }, + { .start =3D 984, .end =3D 1012 }, +}; + +static struct nvmem_config s32g_ocotp_nvmem_config =3D { + .name =3D "s32g-ocotp", + .add_legacy_fixed_of_cells =3D true, + .read_only =3D true, + .word_size =3D 4, + .reg_read =3D s32g_ocotp_read, + .keepout =3D s32g_keepouts, + .nkeepout =3D ARRAY_SIZE(s32g_keepouts), +}; + +static const struct of_device_id ocotp_of_match[] =3D { + { .compatible =3D "nxp,s32g2-ocotp" }, + { /* sentinel */ } +}; + +static int s32g_ocotp_probe(struct platform_device *pdev) +{ + struct s32g_ocotp_priv *s32g_data; + struct device *dev =3D &pdev->dev; + struct nvmem_device *nvmem; + struct resource *res; + + s32g_data =3D devm_kzalloc(dev, sizeof(*s32g_data), GFP_KERNEL); + if (!s32g_data) + return -ENOMEM; + + s32g_data->base =3D devm_platform_get_and_ioremap_resource(pdev, 0, &res); + if (IS_ERR(s32g_data->base)) { + dev_err(dev, "Cannot map OCOTP device.\n"); + return PTR_ERR(s32g_data->base); + } + + s32g_data->dev =3D dev; + s32g_ocotp_nvmem_config.dev =3D dev; + s32g_ocotp_nvmem_config.priv =3D s32g_data; + s32g_ocotp_nvmem_config.size =3D resource_size(res); + + nvmem =3D devm_nvmem_register(dev, &s32g_ocotp_nvmem_config); + + return PTR_ERR_OR_ZERO(nvmem); +} + +static struct platform_driver s32g_ocotp_driver =3D { + .probe =3D s32g_ocotp_probe, + .driver =3D { + .name =3D "s32g-ocotp", + .of_match_table =3D ocotp_of_match, + }, +}; +module_platform_driver(s32g_ocotp_driver); +MODULE_AUTHOR("NXP"); +MODULE_DESCRIPTION("S32G OCOTP driver"); +MODULE_LICENSE("GPL"); --=20 2.47.2 From nobody Fri Oct 3 18:06:08 2025 Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6F47136C087 for ; Tue, 26 Aug 2025 16:38:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756226302; cv=none; b=Xp9XucKYWk43Wfz1Zwqsf5PHY4BlmQiNkHVMss0Hxt3Yxg+3I03YiipEILpIRy5EfJKTjVBAmDkEXnfTwYUCuI8ytv4IChOxjLcGVwGZPdYG6SQqKmUDsxQdrc+MMEvO+CEIjY28TUpu+d6Ucigca60Gf/2lz4LqxPQzRvpGmLo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756226302; c=relaxed/simple; bh=809NI1CN0NNuV9uuoAaLx43aJ5mdVRKJJ2h/czEopkE=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; 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Tue, 26 Aug 2025 09:38:18 -0700 (PDT) Date: Tue, 26 Aug 2025 19:38:15 +0300 From: Dan Carpenter To: Chester Lin Cc: Matthias Brugger , Ghennadi Procopciuc , NXP S32 Linux Team , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linaro-s32@linaro.org Subject: [PATCH V2 3/3] arm64: dts: s32g: Add device tree information for the OCOTP driver Message-ID: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the device tree information for the S32G On Chip One-Time Programmable Controller (OCOTP) chip. Signed-off-by: Dan Carpenter --- v2: change "ocotp: ocotp@400a4000 {" to "ocotp: nvmem@400a4000 {" arch/arm64/boot/dts/freescale/s32g2.dtsi | 7 +++++++ arch/arm64/boot/dts/freescale/s32g3.dtsi | 7 +++++++ 2 files changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts= /freescale/s32g2.dtsi index 6a7cc7b33754..e8cfddabfc24 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -701,5 +701,12 @@ gic: interrupt-controller@50800000 { interrupt-controller; #interrupt-cells =3D <3>; }; + + ocotp: nvmem@400a4000 { + compatible =3D "nxp,s32g2-ocotp"; + reg =3D <0x400a4000 0x400>; + #address-cells =3D <1>; + #size-cells =3D <1>; + }; }; }; diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts= /freescale/s32g3.dtsi index 61ee08f0cfdc..8fe1fa35e9ac 100644 --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi @@ -765,6 +765,13 @@ gic: interrupt-controller@50800000 { <0x50420000 0x2000>; interrupts =3D ; }; + + ocotp: nvmem@400a4000 { + compatible =3D "nxp,s32g3-ocotp", "nxp,s32g2-ocotp"; + reg =3D <0x400a4000 0x400>; + #address-cells =3D <1>; + #size-cells =3D <1>; + }; }; =20 timer { --=20 2.47.2