From nobody Fri Oct 3 23:08:33 2025 Received: from pidgin.makrotopia.org (pidgin.makrotopia.org [185.142.180.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C996727AC41; Fri, 22 Aug 2025 16:11:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.142.180.65 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755879106; cv=none; b=c49mdrAREDC/vcYcFmt6a45UwKfMVn0SzNer1HVKR6Qa9inef7XyB7IW1EchJsMQpSEBI3RNDOGRQbW379084QYWd3dB+KL1p6TF+wOhUWxhDOaaq7Zb7f80SUfcJmsg+2UYBRRCl6a9V65cBsQKzoDyXWzw73J1xuMUwux0vxo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755879106; c=relaxed/simple; bh=LQ/g51PR0KOdhHRIGfdUs4T3UPUrAcV0u/JeQBR2/Qo=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=o3s/HQMzUyevoPmmHVIhw+U02LNxHQoGhuGucPL8uFuUXh9kyotNo8T2fklIKT0wPsQn8bMvE/Brr/oibI9/Dwplj9m5UuAE8DbCF0sbBGDvMwLDFDJ8qyc083jclwKWz3XyiXM4+MiN/yFTej+P9Qa/3eib3xDWYouICCsJEf8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org; spf=pass smtp.mailfrom=makrotopia.org; arc=none smtp.client-ip=185.142.180.65 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=makrotopia.org Received: from local by pidgin.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.98.2) (envelope-from ) id 1upUMX-000000006nb-2gMb; Fri, 22 Aug 2025 16:11:33 +0000 Date: Fri, 22 Aug 2025 17:11:30 +0100 From: Daniel Golle To: Hauke Mehrtens , Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Philipp Zabel , Russell King , linux-kernel@vger.kernel.org, netdev@vger.kernel.org Cc: Andreas Schirm , Lukas Stockmann , Alexander Sverdlin , Peter Christen , Avinash Jayaraman , Bing tao Xu , Liang Xu , Juraj Povazanec , "Fanni (Fang-Yi) Chan" , "Benny (Ying-Tsan) Weng" , "Livia M. Rosu" , John Crispin Subject: [PATCH net-next v4 1/7] net: dsa: lantiq_gswip: deduplicate dsa_switch_ops Message-ID: <03d72eceeb3faecdbe03ce58aab40861cf6b77c1.1755878232.git.daniel@makrotopia.org> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The two instances of struct dsa_switch_ops differ only by their .phylink_get_caps op. Instead of having two instances of dsa_switch_ops, rather just have a pointer to the phylink_get_caps function in struct gswip_hw_info. Signed-off-by: Daniel Golle Reviewed-by: Andrew Lunn Reviewed-by: Vladimir Oltean --- v4: no changes v3: no changes v2: no changes drivers/net/dsa/lantiq_gswip.c | 44 ++++++++++++---------------------- 1 file changed, 15 insertions(+), 29 deletions(-) diff --git a/drivers/net/dsa/lantiq_gswip.c b/drivers/net/dsa/lantiq_gswip.c index 6eb3140d4044..1cff938a87ef 100644 --- a/drivers/net/dsa/lantiq_gswip.c +++ b/drivers/net/dsa/lantiq_gswip.c @@ -254,7 +254,8 @@ struct gswip_hw_info { int max_ports; int cpu_port; - const struct dsa_switch_ops *ops; + void (*phylink_get_caps)(struct dsa_switch *ds, int port, + struct phylink_config *config); }; =20 struct xway_gphy_match_data { @@ -1554,6 +1555,14 @@ static void gswip_xrx300_phylink_get_caps(struct dsa= _switch *ds, int port, MAC_10 | MAC_100 | MAC_1000; } =20 +static void gswip_phylink_get_caps(struct dsa_switch *ds, int port, + struct phylink_config *config) +{ + struct gswip_priv *priv =3D ds->priv; + + priv->hw_info->phylink_get_caps(ds, port, config); +} + static void gswip_port_set_link(struct gswip_priv *priv, int port, bool li= nk) { u32 mdio_phy; @@ -1826,30 +1835,7 @@ static const struct phylink_mac_ops gswip_phylink_ma= c_ops =3D { .mac_link_up =3D gswip_phylink_mac_link_up, }; =20 -static const struct dsa_switch_ops gswip_xrx200_switch_ops =3D { - .get_tag_protocol =3D gswip_get_tag_protocol, - .setup =3D gswip_setup, - .port_enable =3D gswip_port_enable, - .port_disable =3D gswip_port_disable, - .port_bridge_join =3D gswip_port_bridge_join, - .port_bridge_leave =3D gswip_port_bridge_leave, - .port_fast_age =3D gswip_port_fast_age, - .port_vlan_filtering =3D gswip_port_vlan_filtering, - .port_vlan_add =3D gswip_port_vlan_add, - .port_vlan_del =3D gswip_port_vlan_del, - .port_stp_state_set =3D gswip_port_stp_state_set, - .port_fdb_add =3D gswip_port_fdb_add, - .port_fdb_del =3D gswip_port_fdb_del, - .port_fdb_dump =3D gswip_port_fdb_dump, - .port_change_mtu =3D gswip_port_change_mtu, - .port_max_mtu =3D gswip_port_max_mtu, - .phylink_get_caps =3D gswip_xrx200_phylink_get_caps, - .get_strings =3D gswip_get_strings, - .get_ethtool_stats =3D gswip_get_ethtool_stats, - .get_sset_count =3D gswip_get_sset_count, -}; - -static const struct dsa_switch_ops gswip_xrx300_switch_ops =3D { +static const struct dsa_switch_ops gswip_switch_ops =3D { .get_tag_protocol =3D gswip_get_tag_protocol, .setup =3D gswip_setup, .port_enable =3D gswip_port_enable, @@ -1866,7 +1852,7 @@ static const struct dsa_switch_ops gswip_xrx300_switc= h_ops =3D { .port_fdb_dump =3D gswip_port_fdb_dump, .port_change_mtu =3D gswip_port_change_mtu, .port_max_mtu =3D gswip_port_max_mtu, - .phylink_get_caps =3D gswip_xrx300_phylink_get_caps, + .phylink_get_caps =3D gswip_phylink_get_caps, .get_strings =3D gswip_get_strings, .get_ethtool_stats =3D gswip_get_ethtool_stats, .get_sset_count =3D gswip_get_sset_count, @@ -2129,7 +2115,7 @@ static int gswip_probe(struct platform_device *pdev) priv->ds->dev =3D dev; priv->ds->num_ports =3D priv->hw_info->max_ports; priv->ds->priv =3D priv; - priv->ds->ops =3D priv->hw_info->ops; + priv->ds->ops =3D &gswip_switch_ops; priv->ds->phylink_mac_ops =3D &gswip_phylink_mac_ops; priv->dev =3D dev; mutex_init(&priv->pce_table_lock); @@ -2230,13 +2216,13 @@ static void gswip_shutdown(struct platform_device *= pdev) static const struct gswip_hw_info gswip_xrx200 =3D { .max_ports =3D 7, .cpu_port =3D 6, - .ops =3D &gswip_xrx200_switch_ops, + .phylink_get_caps =3D gswip_xrx200_phylink_get_caps, }; =20 static const struct gswip_hw_info gswip_xrx300 =3D { .max_ports =3D 7, .cpu_port =3D 6, - .ops =3D &gswip_xrx300_switch_ops, + .phylink_get_caps =3D gswip_xrx300_phylink_get_caps, }; =20 static const struct of_device_id gswip_of_match[] =3D { --=20 2.50.1 From nobody Fri Oct 3 23:08:33 2025 Received: from pidgin.makrotopia.org (pidgin.makrotopia.org [185.142.180.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 85E2427AC41; Fri, 22 Aug 2025 16:11:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.142.180.65 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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Fri, 22 Aug 2025 16:11:42 +0000 Date: Fri, 22 Aug 2025 17:11:39 +0100 From: Daniel Golle To: Hauke Mehrtens , Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Philipp Zabel , Russell King , linux-kernel@vger.kernel.org, netdev@vger.kernel.org Cc: Andreas Schirm , Lukas Stockmann , Alexander Sverdlin , Peter Christen , Avinash Jayaraman , Bing tao Xu , Liang Xu , Juraj Povazanec , "Fanni (Fang-Yi) Chan" , "Benny (Ying-Tsan) Weng" , "Livia M. Rosu" , John Crispin Subject: [PATCH net-next v4 2/7] net: dsa: lantiq_gswip: prepare for more CPU port options Message-ID: <879c66672d26fe49c1f5d9aa40d8ebc0f31885ab.1755878232.git.daniel@makrotopia.org> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The MaxLinear GSW1xx series of switches support using either the (R)(G)MII interface on port 5 or the SGMII interface on port 4 to be used as CPU port. Prepare for supporting them by defining a mask of allowed CPU ports instead of a single port. Signed-off-by: Daniel Golle Reviewed-by: Andrew Lunn Reviewed-by: Vladimir Oltean --- v4: no changes v3: no changes v2: no changes drivers/net/dsa/lantiq_gswip.c | 79 +++++++++++++++++++++------------- 1 file changed, 50 insertions(+), 29 deletions(-) diff --git a/drivers/net/dsa/lantiq_gswip.c b/drivers/net/dsa/lantiq_gswip.c index 1cff938a87ef..a36b31f7d30b 100644 --- a/drivers/net/dsa/lantiq_gswip.c +++ b/drivers/net/dsa/lantiq_gswip.c @@ -253,7 +253,7 @@ =20 struct gswip_hw_info { int max_ports; - int cpu_port; + unsigned int allowed_cpu_ports; void (*phylink_get_caps)(struct dsa_switch *ds, int port, struct phylink_config *config); }; @@ -655,7 +655,6 @@ static int gswip_add_single_port_br(struct gswip_priv *= priv, int port, bool add) { struct gswip_pce_table_entry vlan_active =3D {0,}; struct gswip_pce_table_entry vlan_mapping =3D {0,}; - unsigned int cpu_port =3D priv->hw_info->cpu_port; int err; =20 vlan_active.index =3D port + 1; @@ -675,7 +674,7 @@ static int gswip_add_single_port_br(struct gswip_priv *= priv, int port, bool add) vlan_mapping.index =3D port + 1; vlan_mapping.table =3D GSWIP_TABLE_VLAN_MAPPING; vlan_mapping.val[0] =3D 0 /* vid */; - vlan_mapping.val[1] =3D BIT(port) | BIT(cpu_port); + vlan_mapping.val[1] =3D BIT(port) | dsa_cpu_ports(priv->ds); vlan_mapping.val[2] =3D 0; err =3D gswip_pce_table_entry_write(priv, &vlan_mapping); if (err) { @@ -805,10 +804,10 @@ static int gswip_port_vlan_filtering(struct dsa_switc= h *ds, int port, =20 static int gswip_setup(struct dsa_switch *ds) { + unsigned int cpu_ports =3D dsa_cpu_ports(ds); struct gswip_priv *priv =3D ds->priv; - unsigned int cpu_port =3D priv->hw_info->cpu_port; - int i; - int err; + struct dsa_port *cpu_dp; + int err, i; =20 gswip_switch_w(priv, GSWIP_SWRES_R0, GSWIP_SWRES); usleep_range(5000, 10000); @@ -830,9 +829,9 @@ static int gswip_setup(struct dsa_switch *ds) } =20 /* Default unknown Broadcast/Multicast/Unicast port maps */ - gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP1); - gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP2); - gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP3); + gswip_switch_w(priv, cpu_ports, GSWIP_PCE_PMAP1); + gswip_switch_w(priv, cpu_ports, GSWIP_PCE_PMAP2); + gswip_switch_w(priv, cpu_ports, GSWIP_PCE_PMAP3); =20 /* Deactivate MDIO PHY auto polling. Some PHYs as the AR8030 have an * interoperability problem with this auto polling mechanism because @@ -861,13 +860,15 @@ static int gswip_setup(struct dsa_switch *ds) GSWIP_MII_CFG_EN | GSWIP_MII_CFG_ISOLATE, 0, i); =20 - /* enable special tag insertion on cpu port */ - gswip_switch_mask(priv, 0, GSWIP_FDMA_PCTRL_STEN, - GSWIP_FDMA_PCTRLp(cpu_port)); + dsa_switch_for_each_cpu_port(cpu_dp, ds) { + /* enable special tag insertion on cpu port */ + gswip_switch_mask(priv, 0, GSWIP_FDMA_PCTRL_STEN, + GSWIP_FDMA_PCTRLp(cpu_dp->index)); =20 - /* accept special tag in ingress direction */ - gswip_switch_mask(priv, 0, GSWIP_PCE_PCTRL_0_INGRESS, - GSWIP_PCE_PCTRL_0p(cpu_port)); + /* accept special tag in ingress direction */ + gswip_switch_mask(priv, 0, GSWIP_PCE_PCTRL_0_INGRESS, + GSWIP_PCE_PCTRL_0p(cpu_dp->index)); + } =20 gswip_switch_mask(priv, 0, GSWIP_BM_QUEUE_GCTRL_GL_MOD, GSWIP_BM_QUEUE_GCTRL); @@ -963,7 +964,6 @@ static int gswip_vlan_add_unaware(struct gswip_priv *pr= iv, { struct gswip_pce_table_entry vlan_mapping =3D {0,}; unsigned int max_ports =3D priv->hw_info->max_ports; - unsigned int cpu_port =3D priv->hw_info->cpu_port; bool active_vlan_created =3D false; int idx =3D -1; int i; @@ -1003,7 +1003,7 @@ static int gswip_vlan_add_unaware(struct gswip_priv *= priv, } =20 /* Update the VLAN mapping entry and write it to the switch */ - vlan_mapping.val[1] |=3D BIT(cpu_port); + vlan_mapping.val[1] |=3D dsa_cpu_ports(priv->ds); vlan_mapping.val[1] |=3D BIT(port); err =3D gswip_pce_table_entry_write(priv, &vlan_mapping); if (err) { @@ -1025,7 +1025,7 @@ static int gswip_vlan_add_aware(struct gswip_priv *pr= iv, { struct gswip_pce_table_entry vlan_mapping =3D {0,}; unsigned int max_ports =3D priv->hw_info->max_ports; - unsigned int cpu_port =3D priv->hw_info->cpu_port; + unsigned int cpu_ports =3D dsa_cpu_ports(priv->ds); bool active_vlan_created =3D false; int idx =3D -1; int fid =3D -1; @@ -1072,8 +1072,8 @@ static int gswip_vlan_add_aware(struct gswip_priv *pr= iv, =20 vlan_mapping.val[0] =3D vid; /* Update the VLAN mapping entry and write it to the switch */ - vlan_mapping.val[1] |=3D BIT(cpu_port); - vlan_mapping.val[2] |=3D BIT(cpu_port); + vlan_mapping.val[1] |=3D cpu_ports; + vlan_mapping.val[2] |=3D cpu_ports; vlan_mapping.val[1] |=3D BIT(port); if (untagged) vlan_mapping.val[2] &=3D ~BIT(port); @@ -1100,7 +1100,6 @@ static int gswip_vlan_remove(struct gswip_priv *priv, { struct gswip_pce_table_entry vlan_mapping =3D {0,}; unsigned int max_ports =3D priv->hw_info->max_ports; - unsigned int cpu_port =3D priv->hw_info->cpu_port; int idx =3D -1; int i; int err; @@ -1136,7 +1135,7 @@ static int gswip_vlan_remove(struct gswip_priv *priv, } =20 /* In case all ports are removed from the bridge, remove the VLAN */ - if ((vlan_mapping.val[1] & ~BIT(cpu_port)) =3D=3D 0) { + if (!(vlan_mapping.val[1] & ~dsa_cpu_ports(priv->ds))) { err =3D gswip_vlan_active_remove(priv, idx); if (err) { dev_err(priv->dev, "failed to write active VLAN: %d\n", @@ -2079,6 +2078,30 @@ static int gswip_gphy_fw_list(struct gswip_priv *pri= v, return err; } =20 +static int gswip_validate_cpu_port(struct dsa_switch *ds) +{ + struct gswip_priv *priv =3D ds->priv; + struct dsa_port *cpu_dp; + int cpu_port =3D -1; + + dsa_switch_for_each_cpu_port(cpu_dp, ds) { + if (cpu_port !=3D -1) + return dev_err_probe(ds->dev, -EINVAL, + "only a single CPU port is supported\n"); + + cpu_port =3D cpu_dp->index; + } + + if (cpu_port =3D=3D -1) + return dev_err_probe(ds->dev, -EINVAL, "no CPU port defined\n"); + + if (BIT(cpu_port) & ~priv->hw_info->allowed_cpu_ports) + return dev_err_probe(ds->dev, -EINVAL, + "unsupported CPU port defined\n"); + + return 0; +} + static int gswip_probe(struct platform_device *pdev) { struct device_node *np, *gphy_fw_np; @@ -2161,12 +2184,10 @@ static int gswip_probe(struct platform_device *pdev) dev_err_probe(dev, err, "dsa switch registration failed\n"); goto gphy_fw_remove; } - if (!dsa_is_cpu_port(priv->ds, priv->hw_info->cpu_port)) { - err =3D dev_err_probe(dev, -EINVAL, - "wrong CPU port defined, HW only supports port: %i\n", - priv->hw_info->cpu_port); + + err =3D gswip_validate_cpu_port(priv->ds); + if (err) goto disable_switch; - } =20 platform_set_drvdata(pdev, priv); =20 @@ -2215,13 +2236,13 @@ static void gswip_shutdown(struct platform_device *= pdev) =20 static const struct gswip_hw_info gswip_xrx200 =3D { .max_ports =3D 7, - .cpu_port =3D 6, + .allowed_cpu_ports =3D BIT(6), .phylink_get_caps =3D gswip_xrx200_phylink_get_caps, }; =20 static const struct gswip_hw_info gswip_xrx300 =3D { .max_ports =3D 7, - .cpu_port =3D 6, + .allowed_cpu_ports =3D BIT(6), .phylink_get_caps =3D gswip_xrx300_phylink_get_caps, }; =20 --=20 2.50.1 From nobody Fri Oct 3 23:08:33 2025 Received: from pidgin.makrotopia.org (pidgin.makrotopia.org [185.142.180.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 94147265623; Fri, 22 Aug 2025 16:11:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.142.180.65 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755879119; 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Fri, 22 Aug 2025 16:11:51 +0000 Date: Fri, 22 Aug 2025 17:11:48 +0100 From: Daniel Golle To: Hauke Mehrtens , Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Philipp Zabel , Russell King , linux-kernel@vger.kernel.org, netdev@vger.kernel.org Cc: Andreas Schirm , Lukas Stockmann , Alexander Sverdlin , Peter Christen , Avinash Jayaraman , Bing tao Xu , Liang Xu , Juraj Povazanec , "Fanni (Fang-Yi) Chan" , "Benny (Ying-Tsan) Weng" , "Livia M. Rosu" , John Crispin Subject: [PATCH net-next v4 3/7] net: dsa: lantiq_gswip: move definitions to header Message-ID: <551c72c93131cd200b38340741e68ff21793ba0b.1755878232.git.daniel@makrotopia.org> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce header file and move register definitions as well as the definitions struct gswip_hw_info and struct gswip_priv there. Signed-off-by: Daniel Golle Reviewed-by: Andrew Lunn Reviewed-by: Vladimir Oltean --- v4: no changes v3: remove accidentally added VAL1_VALID bit definition v2: no changes drivers/net/dsa/lantiq_gswip.c | 250 +------------------------------- drivers/net/dsa/lantiq_gswip.h | 252 +++++++++++++++++++++++++++++++++ 2 files changed, 255 insertions(+), 247 deletions(-) create mode 100644 drivers/net/dsa/lantiq_gswip.h diff --git a/drivers/net/dsa/lantiq_gswip.c b/drivers/net/dsa/lantiq_gswip.c index a36b31f7d30b..b1b250fc4f61 100644 --- a/drivers/net/dsa/lantiq_gswip.c +++ b/drivers/net/dsa/lantiq_gswip.c @@ -25,7 +25,9 @@ * between all LAN ports by default. */ =20 -#include +#include "lantiq_gswip.h" +#include "lantiq_pce.h" + #include #include #include @@ -39,259 +41,13 @@ #include #include #include -#include -#include -#include -#include #include =20 -#include "lantiq_pce.h" - -/* GSWIP MDIO Registers */ -#define GSWIP_MDIO_GLOB 0x00 -#define GSWIP_MDIO_GLOB_ENABLE BIT(15) -#define GSWIP_MDIO_CTRL 0x08 -#define GSWIP_MDIO_CTRL_BUSY BIT(12) -#define GSWIP_MDIO_CTRL_RD BIT(11) -#define GSWIP_MDIO_CTRL_WR BIT(10) -#define GSWIP_MDIO_CTRL_PHYAD_MASK 0x1f -#define GSWIP_MDIO_CTRL_PHYAD_SHIFT 5 -#define GSWIP_MDIO_CTRL_REGAD_MASK 0x1f -#define GSWIP_MDIO_READ 0x09 -#define GSWIP_MDIO_WRITE 0x0A -#define GSWIP_MDIO_MDC_CFG0 0x0B -#define GSWIP_MDIO_MDC_CFG1 0x0C -#define GSWIP_MDIO_PHYp(p) (0x15 - (p)) -#define GSWIP_MDIO_PHY_LINK_MASK 0x6000 -#define GSWIP_MDIO_PHY_LINK_AUTO 0x0000 -#define GSWIP_MDIO_PHY_LINK_DOWN 0x4000 -#define GSWIP_MDIO_PHY_LINK_UP 0x2000 -#define GSWIP_MDIO_PHY_SPEED_MASK 0x1800 -#define GSWIP_MDIO_PHY_SPEED_AUTO 0x1800 -#define GSWIP_MDIO_PHY_SPEED_M10 0x0000 -#define GSWIP_MDIO_PHY_SPEED_M100 0x0800 -#define GSWIP_MDIO_PHY_SPEED_G1 0x1000 -#define GSWIP_MDIO_PHY_FDUP_MASK 0x0600 -#define GSWIP_MDIO_PHY_FDUP_AUTO 0x0000 -#define GSWIP_MDIO_PHY_FDUP_EN 0x0200 -#define GSWIP_MDIO_PHY_FDUP_DIS 0x0600 -#define GSWIP_MDIO_PHY_FCONTX_MASK 0x0180 -#define GSWIP_MDIO_PHY_FCONTX_AUTO 0x0000 -#define GSWIP_MDIO_PHY_FCONTX_EN 0x0100 -#define GSWIP_MDIO_PHY_FCONTX_DIS 0x0180 -#define GSWIP_MDIO_PHY_FCONRX_MASK 0x0060 -#define GSWIP_MDIO_PHY_FCONRX_AUTO 0x0000 -#define GSWIP_MDIO_PHY_FCONRX_EN 0x0020 -#define GSWIP_MDIO_PHY_FCONRX_DIS 0x0060 -#define GSWIP_MDIO_PHY_ADDR_MASK 0x001f -#define GSWIP_MDIO_PHY_MASK (GSWIP_MDIO_PHY_ADDR_MASK | \ - GSWIP_MDIO_PHY_FCONRX_MASK | \ - GSWIP_MDIO_PHY_FCONTX_MASK | \ - GSWIP_MDIO_PHY_LINK_MASK | \ - GSWIP_MDIO_PHY_SPEED_MASK | \ - GSWIP_MDIO_PHY_FDUP_MASK) - -/* GSWIP MII Registers */ -#define GSWIP_MII_CFGp(p) (0x2 * (p)) -#define GSWIP_MII_CFG_RESET BIT(15) -#define GSWIP_MII_CFG_EN BIT(14) -#define GSWIP_MII_CFG_ISOLATE BIT(13) -#define GSWIP_MII_CFG_LDCLKDIS BIT(12) -#define GSWIP_MII_CFG_RGMII_IBS BIT(8) -#define GSWIP_MII_CFG_RMII_CLK BIT(7) -#define GSWIP_MII_CFG_MODE_MIIP 0x0 -#define GSWIP_MII_CFG_MODE_MIIM 0x1 -#define GSWIP_MII_CFG_MODE_RMIIP 0x2 -#define GSWIP_MII_CFG_MODE_RMIIM 0x3 -#define GSWIP_MII_CFG_MODE_RGMII 0x4 -#define GSWIP_MII_CFG_MODE_GMII 0x9 -#define GSWIP_MII_CFG_MODE_MASK 0xf -#define GSWIP_MII_CFG_RATE_M2P5 0x00 -#define GSWIP_MII_CFG_RATE_M25 0x10 -#define GSWIP_MII_CFG_RATE_M125 0x20 -#define GSWIP_MII_CFG_RATE_M50 0x30 -#define GSWIP_MII_CFG_RATE_AUTO 0x40 -#define GSWIP_MII_CFG_RATE_MASK 0x70 -#define GSWIP_MII_PCDU0 0x01 -#define GSWIP_MII_PCDU1 0x03 -#define GSWIP_MII_PCDU5 0x05 -#define GSWIP_MII_PCDU_TXDLY_MASK GENMASK(2, 0) -#define GSWIP_MII_PCDU_RXDLY_MASK GENMASK(9, 7) - -/* GSWIP Core Registers */ -#define GSWIP_SWRES 0x000 -#define GSWIP_SWRES_R1 BIT(1) /* GSWIP Software reset */ -#define GSWIP_SWRES_R0 BIT(0) /* GSWIP Hardware reset */ -#define GSWIP_VERSION 0x013 -#define GSWIP_VERSION_REV_SHIFT 0 -#define GSWIP_VERSION_REV_MASK GENMASK(7, 0) -#define GSWIP_VERSION_MOD_SHIFT 8 -#define GSWIP_VERSION_MOD_MASK GENMASK(15, 8) -#define GSWIP_VERSION_2_0 0x100 -#define GSWIP_VERSION_2_1 0x021 -#define GSWIP_VERSION_2_2 0x122 -#define GSWIP_VERSION_2_2_ETC 0x022 - -#define GSWIP_BM_RAM_VAL(x) (0x043 - (x)) -#define GSWIP_BM_RAM_ADDR 0x044 -#define GSWIP_BM_RAM_CTRL 0x045 -#define GSWIP_BM_RAM_CTRL_BAS BIT(15) -#define GSWIP_BM_RAM_CTRL_OPMOD BIT(5) -#define GSWIP_BM_RAM_CTRL_ADDR_MASK GENMASK(4, 0) -#define GSWIP_BM_QUEUE_GCTRL 0x04A -#define GSWIP_BM_QUEUE_GCTRL_GL_MOD BIT(10) -/* buffer management Port Configuration Register */ -#define GSWIP_BM_PCFGp(p) (0x080 + ((p) * 2)) -#define GSWIP_BM_PCFG_CNTEN BIT(0) /* RMON Counter Enable */ -#define GSWIP_BM_PCFG_IGCNT BIT(1) /* Ingres Special Tag RMON count */ -/* buffer management Port Control Register */ -#define GSWIP_BM_RMON_CTRLp(p) (0x81 + ((p) * 2)) -#define GSWIP_BM_CTRL_RMON_RAM1_RES BIT(0) /* Software Reset for RMON RAM= 1 */ -#define GSWIP_BM_CTRL_RMON_RAM2_RES BIT(1) /* Software Reset for RMON RAM= 2 */ - -/* PCE */ -#define GSWIP_PCE_TBL_KEY(x) (0x447 - (x)) -#define GSWIP_PCE_TBL_MASK 0x448 -#define GSWIP_PCE_TBL_VAL(x) (0x44D - (x)) -#define GSWIP_PCE_TBL_ADDR 0x44E -#define GSWIP_PCE_TBL_CTRL 0x44F -#define GSWIP_PCE_TBL_CTRL_BAS BIT(15) -#define GSWIP_PCE_TBL_CTRL_TYPE BIT(13) -#define GSWIP_PCE_TBL_CTRL_VLD BIT(12) -#define GSWIP_PCE_TBL_CTRL_KEYFORM BIT(11) -#define GSWIP_PCE_TBL_CTRL_GMAP_MASK GENMASK(10, 7) -#define GSWIP_PCE_TBL_CTRL_OPMOD_MASK GENMASK(6, 5) -#define GSWIP_PCE_TBL_CTRL_OPMOD_ADRD 0x00 -#define GSWIP_PCE_TBL_CTRL_OPMOD_ADWR 0x20 -#define GSWIP_PCE_TBL_CTRL_OPMOD_KSRD 0x40 -#define GSWIP_PCE_TBL_CTRL_OPMOD_KSWR 0x60 -#define GSWIP_PCE_TBL_CTRL_ADDR_MASK GENMASK(4, 0) -#define GSWIP_PCE_PMAP1 0x453 /* Monitoring port map */ -#define GSWIP_PCE_PMAP2 0x454 /* Default Multicast port map */ -#define GSWIP_PCE_PMAP3 0x455 /* Default Unknown Unicast port map */ -#define GSWIP_PCE_GCTRL_0 0x456 -#define GSWIP_PCE_GCTRL_0_MTFL BIT(0) /* MAC Table Flushing */ -#define GSWIP_PCE_GCTRL_0_MC_VALID BIT(3) -#define GSWIP_PCE_GCTRL_0_VLAN BIT(14) /* VLAN aware Switching */ -#define GSWIP_PCE_GCTRL_1 0x457 -#define GSWIP_PCE_GCTRL_1_MAC_GLOCK BIT(2) /* MAC Address table lock */ -#define GSWIP_PCE_GCTRL_1_MAC_GLOCK_MOD BIT(3) /* Mac address table lock = forwarding mode */ -#define GSWIP_PCE_PCTRL_0p(p) (0x480 + ((p) * 0xA)) -#define GSWIP_PCE_PCTRL_0_TVM BIT(5) /* Transparent VLAN mode */ -#define GSWIP_PCE_PCTRL_0_VREP BIT(6) /* VLAN Replace Mode */ -#define GSWIP_PCE_PCTRL_0_INGRESS BIT(11) /* Accept special tag in ingres= s */ -#define GSWIP_PCE_PCTRL_0_PSTATE_LISTEN 0x0 -#define GSWIP_PCE_PCTRL_0_PSTATE_RX 0x1 -#define GSWIP_PCE_PCTRL_0_PSTATE_TX 0x2 -#define GSWIP_PCE_PCTRL_0_PSTATE_LEARNING 0x3 -#define GSWIP_PCE_PCTRL_0_PSTATE_FORWARDING 0x7 -#define GSWIP_PCE_PCTRL_0_PSTATE_MASK GENMASK(2, 0) -#define GSWIP_PCE_VCTRL(p) (0x485 + ((p) * 0xA)) -#define GSWIP_PCE_VCTRL_UVR BIT(0) /* Unknown VLAN Rule */ -#define GSWIP_PCE_VCTRL_VIMR BIT(3) /* VLAN Ingress Member violation rul= e */ -#define GSWIP_PCE_VCTRL_VEMR BIT(4) /* VLAN Egress Member violation rule= */ -#define GSWIP_PCE_VCTRL_VSR BIT(5) /* VLAN Security */ -#define GSWIP_PCE_VCTRL_VID0 BIT(6) /* Priority Tagged Rule */ -#define GSWIP_PCE_DEFPVID(p) (0x486 + ((p) * 0xA)) - -#define GSWIP_MAC_FLEN 0x8C5 -#define GSWIP_MAC_CTRL_0p(p) (0x903 + ((p) * 0xC)) -#define GSWIP_MAC_CTRL_0_PADEN BIT(8) -#define GSWIP_MAC_CTRL_0_FCS_EN BIT(7) -#define GSWIP_MAC_CTRL_0_FCON_MASK 0x0070 -#define GSWIP_MAC_CTRL_0_FCON_AUTO 0x0000 -#define GSWIP_MAC_CTRL_0_FCON_RX 0x0010 -#define GSWIP_MAC_CTRL_0_FCON_TX 0x0020 -#define GSWIP_MAC_CTRL_0_FCON_RXTX 0x0030 -#define GSWIP_MAC_CTRL_0_FCON_NONE 0x0040 -#define GSWIP_MAC_CTRL_0_FDUP_MASK 0x000C -#define GSWIP_MAC_CTRL_0_FDUP_AUTO 0x0000 -#define GSWIP_MAC_CTRL_0_FDUP_EN 0x0004 -#define GSWIP_MAC_CTRL_0_FDUP_DIS 0x000C -#define GSWIP_MAC_CTRL_0_GMII_MASK 0x0003 -#define GSWIP_MAC_CTRL_0_GMII_AUTO 0x0000 -#define GSWIP_MAC_CTRL_0_GMII_MII 0x0001 -#define GSWIP_MAC_CTRL_0_GMII_RGMII 0x0002 -#define GSWIP_MAC_CTRL_2p(p) (0x905 + ((p) * 0xC)) -#define GSWIP_MAC_CTRL_2_LCHKL BIT(2) /* Frame Length Check Long Enable */ -#define GSWIP_MAC_CTRL_2_MLEN BIT(3) /* Maximum Untagged Frame Lnegth */ - -/* Ethernet Switch Fetch DMA Port Control Register */ -#define GSWIP_FDMA_PCTRLp(p) (0xA80 + ((p) * 0x6)) -#define GSWIP_FDMA_PCTRL_EN BIT(0) /* FDMA Port Enable */ -#define GSWIP_FDMA_PCTRL_STEN BIT(1) /* Special Tag Insertion Enable */ -#define GSWIP_FDMA_PCTRL_VLANMOD_MASK GENMASK(4, 3) /* VLAN Modification = Control */ -#define GSWIP_FDMA_PCTRL_VLANMOD_SHIFT 3 /* VLAN Modification Control */ -#define GSWIP_FDMA_PCTRL_VLANMOD_DIS (0x0 << GSWIP_FDMA_PCTRL_VLANMOD_SHI= FT) -#define GSWIP_FDMA_PCTRL_VLANMOD_PRIO (0x1 << GSWIP_FDMA_PCTRL_VLANMOD_SH= IFT) -#define GSWIP_FDMA_PCTRL_VLANMOD_ID (0x2 << GSWIP_FDMA_PCTRL_VLANMOD_SHIF= T) -#define GSWIP_FDMA_PCTRL_VLANMOD_BOTH (0x3 << GSWIP_FDMA_PCTRL_VLANMOD_SH= IFT) - -/* Ethernet Switch Store DMA Port Control Register */ -#define GSWIP_SDMA_PCTRLp(p) (0xBC0 + ((p) * 0x6)) -#define GSWIP_SDMA_PCTRL_EN BIT(0) /* SDMA Port Enable */ -#define GSWIP_SDMA_PCTRL_FCEN BIT(1) /* Flow Control Enable */ -#define GSWIP_SDMA_PCTRL_PAUFWD BIT(3) /* Pause Frame Forwarding */ - -#define GSWIP_TABLE_ACTIVE_VLAN 0x01 -#define GSWIP_TABLE_VLAN_MAPPING 0x02 -#define GSWIP_TABLE_MAC_BRIDGE 0x0b -#define GSWIP_TABLE_MAC_BRIDGE_KEY3_FID GENMASK(5, 0) /* Filtering identi= fier */ -#define GSWIP_TABLE_MAC_BRIDGE_VAL0_PORT GENMASK(7, 4) /* Port on learned= entries */ -#define GSWIP_TABLE_MAC_BRIDGE_VAL1_STATIC BIT(0) /* Static, non-aging e= ntry */ - -#define XRX200_GPHY_FW_ALIGN (16 * 1024) - -/* Maximum packet size supported by the switch. In theory this should be 1= 0240, - * but long packets currently cause lock-ups with an MTU of over 2526. Med= ium - * packets are sometimes dropped (e.g. TCP over 2477, UDP over 2516-2519, = ICMP - * over 2526), hence an MTU value of 2400 seems safe. This issue only affe= cts - * packet reception. This is probably caused by the PPA engine, which is o= n the - * RX part of the device. Packet transmission works properly up to 10240. - */ -#define GSWIP_MAX_PACKET_LENGTH 2400 - -struct gswip_hw_info { - int max_ports; - unsigned int allowed_cpu_ports; - void (*phylink_get_caps)(struct dsa_switch *ds, int port, - struct phylink_config *config); -}; - struct xway_gphy_match_data { char *fe_firmware_name; char *ge_firmware_name; }; =20 -struct gswip_gphy_fw { - struct clk *clk_gate; - struct reset_control *reset; - u32 fw_addr_offset; - char *fw_name; -}; - -struct gswip_vlan { - struct net_device *bridge; - u16 vid; - u8 fid; -}; - -struct gswip_priv { - __iomem void *gswip; - __iomem void *mdio; - __iomem void *mii; - const struct gswip_hw_info *hw_info; - const struct xway_gphy_match_data *gphy_fw_name_cfg; - struct dsa_switch *ds; - struct device *dev; - struct regmap *rcu_regmap; - struct gswip_vlan vlans[64]; - int num_gphy_fw; - struct gswip_gphy_fw *gphy_fw; - u32 port_vlan_filter; - struct mutex pce_table_lock; -}; - struct gswip_pce_table_entry { u16 index; // PCE_TBL_ADDR.ADDR =3D pData->table_index u16 table; // PCE_TBL_CTRL.ADDR =3D pData->table diff --git a/drivers/net/dsa/lantiq_gswip.h b/drivers/net/dsa/lantiq_gswip.h new file mode 100644 index 000000000000..8703c947028a --- /dev/null +++ b/drivers/net/dsa/lantiq_gswip.h @@ -0,0 +1,252 @@ +// SPDX-License-Identifier: GPL-2.0 +#ifndef __LANTIQ_GSWIP_H +#define __LANTIQ_GSWIP_H + +#include +#include +#include +#include +#include +#include + +/* GSWIP MDIO Registers */ +#define GSWIP_MDIO_GLOB 0x00 +#define GSWIP_MDIO_GLOB_ENABLE BIT(15) +#define GSWIP_MDIO_CTRL 0x08 +#define GSWIP_MDIO_CTRL_BUSY BIT(12) +#define GSWIP_MDIO_CTRL_RD BIT(11) +#define GSWIP_MDIO_CTRL_WR BIT(10) +#define GSWIP_MDIO_CTRL_PHYAD_MASK 0x1f +#define GSWIP_MDIO_CTRL_PHYAD_SHIFT 5 +#define GSWIP_MDIO_CTRL_REGAD_MASK 0x1f +#define GSWIP_MDIO_READ 0x09 +#define GSWIP_MDIO_WRITE 0x0A +#define GSWIP_MDIO_MDC_CFG0 0x0B +#define GSWIP_MDIO_MDC_CFG1 0x0C +#define GSWIP_MDIO_PHYp(p) (0x15 - (p)) +#define GSWIP_MDIO_PHY_LINK_MASK 0x6000 +#define GSWIP_MDIO_PHY_LINK_AUTO 0x0000 +#define GSWIP_MDIO_PHY_LINK_DOWN 0x4000 +#define GSWIP_MDIO_PHY_LINK_UP 0x2000 +#define GSWIP_MDIO_PHY_SPEED_MASK 0x1800 +#define GSWIP_MDIO_PHY_SPEED_AUTO 0x1800 +#define GSWIP_MDIO_PHY_SPEED_M10 0x0000 +#define GSWIP_MDIO_PHY_SPEED_M100 0x0800 +#define GSWIP_MDIO_PHY_SPEED_G1 0x1000 +#define GSWIP_MDIO_PHY_FDUP_MASK 0x0600 +#define GSWIP_MDIO_PHY_FDUP_AUTO 0x0000 +#define GSWIP_MDIO_PHY_FDUP_EN 0x0200 +#define GSWIP_MDIO_PHY_FDUP_DIS 0x0600 +#define GSWIP_MDIO_PHY_FCONTX_MASK 0x0180 +#define GSWIP_MDIO_PHY_FCONTX_AUTO 0x0000 +#define GSWIP_MDIO_PHY_FCONTX_EN 0x0100 +#define GSWIP_MDIO_PHY_FCONTX_DIS 0x0180 +#define GSWIP_MDIO_PHY_FCONRX_MASK 0x0060 +#define GSWIP_MDIO_PHY_FCONRX_AUTO 0x0000 +#define GSWIP_MDIO_PHY_FCONRX_EN 0x0020 +#define GSWIP_MDIO_PHY_FCONRX_DIS 0x0060 +#define GSWIP_MDIO_PHY_ADDR_MASK 0x001f +#define GSWIP_MDIO_PHY_MASK (GSWIP_MDIO_PHY_ADDR_MASK | \ + GSWIP_MDIO_PHY_FCONRX_MASK | \ + GSWIP_MDIO_PHY_FCONTX_MASK | \ + GSWIP_MDIO_PHY_LINK_MASK | \ + GSWIP_MDIO_PHY_SPEED_MASK | \ + GSWIP_MDIO_PHY_FDUP_MASK) + +/* GSWIP MII Registers */ +#define GSWIP_MII_CFGp(p) (0x2 * (p)) +#define GSWIP_MII_CFG_RESET BIT(15) +#define GSWIP_MII_CFG_EN BIT(14) +#define GSWIP_MII_CFG_ISOLATE BIT(13) +#define GSWIP_MII_CFG_LDCLKDIS BIT(12) +#define GSWIP_MII_CFG_RGMII_IBS BIT(8) +#define GSWIP_MII_CFG_RMII_CLK BIT(7) +#define GSWIP_MII_CFG_MODE_MIIP 0x0 +#define GSWIP_MII_CFG_MODE_MIIM 0x1 +#define GSWIP_MII_CFG_MODE_RMIIP 0x2 +#define GSWIP_MII_CFG_MODE_RMIIM 0x3 +#define GSWIP_MII_CFG_MODE_RGMII 0x4 +#define GSWIP_MII_CFG_MODE_GMII 0x9 +#define GSWIP_MII_CFG_MODE_MASK 0xf +#define GSWIP_MII_CFG_RATE_M2P5 0x00 +#define GSWIP_MII_CFG_RATE_M25 0x10 +#define GSWIP_MII_CFG_RATE_M125 0x20 +#define GSWIP_MII_CFG_RATE_M50 0x30 +#define GSWIP_MII_CFG_RATE_AUTO 0x40 +#define GSWIP_MII_CFG_RATE_MASK 0x70 +#define GSWIP_MII_PCDU0 0x01 +#define GSWIP_MII_PCDU1 0x03 +#define GSWIP_MII_PCDU5 0x05 +#define GSWIP_MII_PCDU_TXDLY_MASK GENMASK(2, 0) +#define GSWIP_MII_PCDU_RXDLY_MASK GENMASK(9, 7) + +/* GSWIP Core Registers */ +#define GSWIP_SWRES 0x000 +#define GSWIP_SWRES_R1 BIT(1) /* GSWIP Software reset */ +#define GSWIP_SWRES_R0 BIT(0) /* GSWIP Hardware reset */ +#define GSWIP_VERSION 0x013 +#define GSWIP_VERSION_REV_SHIFT 0 +#define GSWIP_VERSION_REV_MASK GENMASK(7, 0) +#define GSWIP_VERSION_MOD_SHIFT 8 +#define GSWIP_VERSION_MOD_MASK GENMASK(15, 8) +#define GSWIP_VERSION_2_0 0x100 +#define GSWIP_VERSION_2_1 0x021 +#define GSWIP_VERSION_2_2 0x122 +#define GSWIP_VERSION_2_2_ETC 0x022 + +#define GSWIP_BM_RAM_VAL(x) (0x043 - (x)) +#define GSWIP_BM_RAM_ADDR 0x044 +#define GSWIP_BM_RAM_CTRL 0x045 +#define GSWIP_BM_RAM_CTRL_BAS BIT(15) +#define GSWIP_BM_RAM_CTRL_OPMOD BIT(5) +#define GSWIP_BM_RAM_CTRL_ADDR_MASK GENMASK(4, 0) +#define GSWIP_BM_QUEUE_GCTRL 0x04A +#define GSWIP_BM_QUEUE_GCTRL_GL_MOD BIT(10) +/* buffer management Port Configuration Register */ +#define GSWIP_BM_PCFGp(p) (0x080 + ((p) * 2)) +#define GSWIP_BM_PCFG_CNTEN BIT(0) /* RMON Counter Enable */ +#define GSWIP_BM_PCFG_IGCNT BIT(1) /* Ingres Special Tag RMON count */ +/* buffer management Port Control Register */ +#define GSWIP_BM_RMON_CTRLp(p) (0x81 + ((p) * 2)) +#define GSWIP_BM_CTRL_RMON_RAM1_RES BIT(0) /* Software Reset for RMON RAM= 1 */ +#define GSWIP_BM_CTRL_RMON_RAM2_RES BIT(1) /* Software Reset for RMON RAM= 2 */ + +/* PCE */ +#define GSWIP_PCE_TBL_KEY(x) (0x447 - (x)) +#define GSWIP_PCE_TBL_MASK 0x448 +#define GSWIP_PCE_TBL_VAL(x) (0x44D - (x)) +#define GSWIP_PCE_TBL_ADDR 0x44E +#define GSWIP_PCE_TBL_CTRL 0x44F +#define GSWIP_PCE_TBL_CTRL_BAS BIT(15) +#define GSWIP_PCE_TBL_CTRL_TYPE BIT(13) +#define GSWIP_PCE_TBL_CTRL_VLD BIT(12) +#define GSWIP_PCE_TBL_CTRL_KEYFORM BIT(11) +#define GSWIP_PCE_TBL_CTRL_GMAP_MASK GENMASK(10, 7) +#define GSWIP_PCE_TBL_CTRL_OPMOD_MASK GENMASK(6, 5) +#define GSWIP_PCE_TBL_CTRL_OPMOD_ADRD 0x00 +#define GSWIP_PCE_TBL_CTRL_OPMOD_ADWR 0x20 +#define GSWIP_PCE_TBL_CTRL_OPMOD_KSRD 0x40 +#define GSWIP_PCE_TBL_CTRL_OPMOD_KSWR 0x60 +#define GSWIP_PCE_TBL_CTRL_ADDR_MASK GENMASK(4, 0) +#define GSWIP_PCE_PMAP1 0x453 /* Monitoring port map */ +#define GSWIP_PCE_PMAP2 0x454 /* Default Multicast port map */ +#define GSWIP_PCE_PMAP3 0x455 /* Default Unknown Unicast port map */ +#define GSWIP_PCE_GCTRL_0 0x456 +#define GSWIP_PCE_GCTRL_0_MTFL BIT(0) /* MAC Table Flushing */ +#define GSWIP_PCE_GCTRL_0_MC_VALID BIT(3) +#define GSWIP_PCE_GCTRL_0_VLAN BIT(14) /* VLAN aware Switching */ +#define GSWIP_PCE_GCTRL_1 0x457 +#define GSWIP_PCE_GCTRL_1_MAC_GLOCK BIT(2) /* MAC Address table lock */ +#define GSWIP_PCE_GCTRL_1_MAC_GLOCK_MOD BIT(3) /* Mac address table lock = forwarding mode */ +#define GSWIP_PCE_PCTRL_0p(p) (0x480 + ((p) * 0xA)) +#define GSWIP_PCE_PCTRL_0_TVM BIT(5) /* Transparent VLAN mode */ +#define GSWIP_PCE_PCTRL_0_VREP BIT(6) /* VLAN Replace Mode */ +#define GSWIP_PCE_PCTRL_0_INGRESS BIT(11) /* Accept special tag in ingres= s */ +#define GSWIP_PCE_PCTRL_0_PSTATE_LISTEN 0x0 +#define GSWIP_PCE_PCTRL_0_PSTATE_RX 0x1 +#define GSWIP_PCE_PCTRL_0_PSTATE_TX 0x2 +#define GSWIP_PCE_PCTRL_0_PSTATE_LEARNING 0x3 +#define GSWIP_PCE_PCTRL_0_PSTATE_FORWARDING 0x7 +#define GSWIP_PCE_PCTRL_0_PSTATE_MASK GENMASK(2, 0) +#define GSWIP_PCE_VCTRL(p) (0x485 + ((p) * 0xA)) +#define GSWIP_PCE_VCTRL_UVR BIT(0) /* Unknown VLAN Rule */ +#define GSWIP_PCE_VCTRL_VIMR BIT(3) /* VLAN Ingress Member violation rul= e */ +#define GSWIP_PCE_VCTRL_VEMR BIT(4) /* VLAN Egress Member violation rule= */ +#define GSWIP_PCE_VCTRL_VSR BIT(5) /* VLAN Security */ +#define GSWIP_PCE_VCTRL_VID0 BIT(6) /* Priority Tagged Rule */ +#define GSWIP_PCE_DEFPVID(p) (0x486 + ((p) * 0xA)) + +#define GSWIP_MAC_FLEN 0x8C5 +#define GSWIP_MAC_CTRL_0p(p) (0x903 + ((p) * 0xC)) +#define GSWIP_MAC_CTRL_0_PADEN BIT(8) +#define GSWIP_MAC_CTRL_0_FCS_EN BIT(7) +#define GSWIP_MAC_CTRL_0_FCON_MASK 0x0070 +#define GSWIP_MAC_CTRL_0_FCON_AUTO 0x0000 +#define GSWIP_MAC_CTRL_0_FCON_RX 0x0010 +#define GSWIP_MAC_CTRL_0_FCON_TX 0x0020 +#define GSWIP_MAC_CTRL_0_FCON_RXTX 0x0030 +#define GSWIP_MAC_CTRL_0_FCON_NONE 0x0040 +#define GSWIP_MAC_CTRL_0_FDUP_MASK 0x000C +#define GSWIP_MAC_CTRL_0_FDUP_AUTO 0x0000 +#define GSWIP_MAC_CTRL_0_FDUP_EN 0x0004 +#define GSWIP_MAC_CTRL_0_FDUP_DIS 0x000C +#define GSWIP_MAC_CTRL_0_GMII_MASK 0x0003 +#define GSWIP_MAC_CTRL_0_GMII_AUTO 0x0000 +#define GSWIP_MAC_CTRL_0_GMII_MII 0x0001 +#define GSWIP_MAC_CTRL_0_GMII_RGMII 0x0002 +#define GSWIP_MAC_CTRL_2p(p) (0x905 + ((p) * 0xC)) +#define GSWIP_MAC_CTRL_2_LCHKL BIT(2) /* Frame Length Check Long Enable */ +#define GSWIP_MAC_CTRL_2_MLEN BIT(3) /* Maximum Untagged Frame Lnegth */ + +/* Ethernet Switch Fetch DMA Port Control Register */ +#define GSWIP_FDMA_PCTRLp(p) (0xA80 + ((p) * 0x6)) +#define GSWIP_FDMA_PCTRL_EN BIT(0) /* FDMA Port Enable */ +#define GSWIP_FDMA_PCTRL_STEN BIT(1) /* Special Tag Insertion Enable */ +#define GSWIP_FDMA_PCTRL_VLANMOD_MASK GENMASK(4, 3) /* VLAN Modification = Control */ +#define GSWIP_FDMA_PCTRL_VLANMOD_SHIFT 3 /* VLAN Modification Control */ +#define GSWIP_FDMA_PCTRL_VLANMOD_DIS (0x0 << GSWIP_FDMA_PCTRL_VLANMOD_SHI= FT) +#define GSWIP_FDMA_PCTRL_VLANMOD_PRIO (0x1 << GSWIP_FDMA_PCTRL_VLANMOD_SH= IFT) +#define GSWIP_FDMA_PCTRL_VLANMOD_ID (0x2 << GSWIP_FDMA_PCTRL_VLANMOD_SHIF= T) +#define GSWIP_FDMA_PCTRL_VLANMOD_BOTH (0x3 << GSWIP_FDMA_PCTRL_VLANMOD_SH= IFT) + +/* Ethernet Switch Store DMA Port Control Register */ +#define GSWIP_SDMA_PCTRLp(p) (0xBC0 + ((p) * 0x6)) +#define GSWIP_SDMA_PCTRL_EN BIT(0) /* SDMA Port Enable */ +#define GSWIP_SDMA_PCTRL_FCEN BIT(1) /* Flow Control Enable */ +#define GSWIP_SDMA_PCTRL_PAUFWD BIT(3) /* Pause Frame Forwarding */ + +#define GSWIP_TABLE_ACTIVE_VLAN 0x01 +#define GSWIP_TABLE_VLAN_MAPPING 0x02 +#define GSWIP_TABLE_MAC_BRIDGE 0x0b +#define GSWIP_TABLE_MAC_BRIDGE_KEY3_FID GENMASK(5, 0) /* Filtering identi= fier */ +#define GSWIP_TABLE_MAC_BRIDGE_VAL0_PORT GENMASK(7, 4) /* Port on learned= entries */ +#define GSWIP_TABLE_MAC_BRIDGE_VAL1_STATIC BIT(0) /* Static, non-aging e= ntry */ + +#define XRX200_GPHY_FW_ALIGN (16 * 1024) + +/* Maximum packet size supported by the switch. In theory this should be 1= 0240, + * but long packets currently cause lock-ups with an MTU of over 2526. Med= ium + * packets are sometimes dropped (e.g. TCP over 2477, UDP over 2516-2519, = ICMP + * over 2526), hence an MTU value of 2400 seems safe. This issue only affe= cts + * packet reception. This is probably caused by the PPA engine, which is o= n the + * RX part of the device. Packet transmission works properly up to 10240. + */ +#define GSWIP_MAX_PACKET_LENGTH 2400 + +struct gswip_hw_info { + int max_ports; + unsigned int allowed_cpu_ports; + void (*phylink_get_caps)(struct dsa_switch *ds, int port, + struct phylink_config *config); +}; + +struct gswip_gphy_fw { + struct clk *clk_gate; + struct reset_control *reset; + u32 fw_addr_offset; + char *fw_name; +}; + +struct gswip_vlan { + struct net_device *bridge; + u16 vid; + u8 fid; +}; + +struct gswip_priv { + __iomem void *gswip; + __iomem void *mdio; + __iomem void *mii; + const struct gswip_hw_info *hw_info; + const struct xway_gphy_match_data *gphy_fw_name_cfg; + struct dsa_switch *ds; + struct device *dev; + struct regmap *rcu_regmap; + struct gswip_vlan vlans[64]; + int num_gphy_fw; + struct gswip_gphy_fw *gphy_fw; + u32 port_vlan_filter; + struct mutex pce_table_lock; +}; + +#endif /* __LANTIQ_GSWIP_H */ --=20 2.50.1 From nobody Fri Oct 3 23:08:33 2025 Received: from pidgin.makrotopia.org (pidgin.makrotopia.org [185.142.180.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C1E0B286D53; Fri, 22 Aug 2025 16:12:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.142.180.65 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755879127; cv=none; b=TAeZWq2WKzpziRqCULiN5mk3G13tzymK1i2LlBlV+9aLb7eo4hPqaCqx7useETUwzdPTzLQBlTVA2ZGhxb7REcMu3EmQ/+LYT2r9clrFSFgVSBleFBZoE/kGqjdbEmXmWm3qKtTuhofy8xCHWjbt8Xv7Pvfbs/lWhE2v88rSiNk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755879127; c=relaxed/simple; bh=xXiKD0VrPC7ZiS3o5VbC7gFbGWEB7qIrO+VYO2W8wFw=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=nXrbWQO9WTrN0vtS9Nj7vy9q9Vjz5ZNKsjjcn1H2+UqXczHPsCBBz7NIgZokm+KJaFvGHbyZ0tDhk4cMMryYDbemCK0cb+O2yX99ryeEYOu3TUIs7JHgmOhwkVCjIkeOWEetlGLtc6qacYY3f7a2EXVy2xCddz7xpBBwkDcJVxM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org; spf=pass smtp.mailfrom=makrotopia.org; arc=none smtp.client-ip=185.142.180.65 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=makrotopia.org Received: from local by pidgin.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.98.2) (envelope-from ) id 1upUMy-000000006oP-3eOj; Fri, 22 Aug 2025 16:12:00 +0000 Date: Fri, 22 Aug 2025 17:11:57 +0100 From: Daniel Golle To: Hauke Mehrtens , Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Philipp Zabel , Russell King , linux-kernel@vger.kernel.org, netdev@vger.kernel.org Cc: Andreas Schirm , Lukas Stockmann , Alexander Sverdlin , Peter Christen , Avinash Jayaraman , Bing tao Xu , Liang Xu , Juraj Povazanec , "Fanni (Fang-Yi) Chan" , "Benny (Ying-Tsan) Weng" , "Livia M. Rosu" , John Crispin Subject: [PATCH net-next v4 4/7] net: dsa: lantiq_gswip: introduce bitmap for MII ports Message-ID: <019fc8ed06f2317976eac143320d1dc046e8f392.1755878232.git.daniel@makrotopia.org> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Instead of relying on hard-coded numbers for MII ports, introduce a bitmap for MII ports. This is done in order to prepare for supporting MaxLinear GSW1xx ICs which got a different layout of ports. Signed-off-by: Daniel Golle Reviewed-by: Vladimir Oltean --- v4: no changes v3: no changes v2: - move comment before 'if' statement - don't add unused sgmii_ports and phy_ports - correct bitmask for XRX200 and XRX300 (they were swapped in v1/RFC) drivers/net/dsa/lantiq_gswip.c | 14 +++++++++++--- drivers/net/dsa/lantiq_gswip.h | 1 + 2 files changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/net/dsa/lantiq_gswip.c b/drivers/net/dsa/lantiq_gswip.c index b1b250fc4f61..d988839dce2f 100644 --- a/drivers/net/dsa/lantiq_gswip.c +++ b/drivers/net/dsa/lantiq_gswip.c @@ -183,14 +183,20 @@ static void gswip_mii_mask(struct gswip_priv *priv, u= 32 clear, u32 set, static void gswip_mii_mask_cfg(struct gswip_priv *priv, u32 clear, u32 set, int port) { - /* There's no MII_CFG register for the CPU port */ - if (!dsa_is_cpu_port(priv->ds, port)) - gswip_mii_mask(priv, clear, set, GSWIP_MII_CFGp(port)); + /* MII_CFG register only exists for MII ports */ + if (!(priv->hw_info->mii_ports & BIT(port))) + return; + + gswip_mii_mask(priv, clear, set, GSWIP_MII_CFGp(port)); } =20 static void gswip_mii_mask_pcdu(struct gswip_priv *priv, u32 clear, u32 se= t, int port) { + /* MII_PCDU register only exists for MII ports */ + if (!(priv->hw_info->mii_ports & BIT(port))) + return; + switch (port) { case 0: gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU0); @@ -1993,12 +1999,14 @@ static void gswip_shutdown(struct platform_device *= pdev) static const struct gswip_hw_info gswip_xrx200 =3D { .max_ports =3D 7, .allowed_cpu_ports =3D BIT(6), + .mii_ports =3D BIT(0) | BIT(1) | BIT(5), .phylink_get_caps =3D gswip_xrx200_phylink_get_caps, }; =20 static const struct gswip_hw_info gswip_xrx300 =3D { .max_ports =3D 7, .allowed_cpu_ports =3D BIT(6), + .mii_ports =3D BIT(0) | BIT(5), .phylink_get_caps =3D gswip_xrx300_phylink_get_caps, }; =20 diff --git a/drivers/net/dsa/lantiq_gswip.h b/drivers/net/dsa/lantiq_gswip.h index 8703c947028a..1bd05348f1e1 100644 --- a/drivers/net/dsa/lantiq_gswip.h +++ b/drivers/net/dsa/lantiq_gswip.h @@ -216,6 +216,7 @@ struct gswip_hw_info { int max_ports; unsigned int allowed_cpu_ports; + unsigned int mii_ports; void (*phylink_get_caps)(struct dsa_switch *ds, int port, struct phylink_config *config); }; --=20 2.50.1 From nobody Fri Oct 3 23:08:33 2025 Received: from pidgin.makrotopia.org (pidgin.makrotopia.org [185.142.180.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B9829265623; Fri, 22 Aug 2025 16:12:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.142.180.65 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755879138; cv=none; b=KAWIaTnfyclNpcZZXp9C+QILVhA5R5YbrmGDU2acv1N8ppQmwgf1MzmCBW62pKOjESs4oIMY/4tI3UP/5tTN8Sn+gaT+gE0E4zN6kgqs+gSmELuZr4SBffa3I2JMOhF/XZG94I50NDL44eaGqKxQHb9zCUik4X7X1eZChNqME4Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755879138; c=relaxed/simple; bh=eNoIFVY6U+NP1Z0Xd9ECqCHAlqCEIyEIhrLyYEjyR5c=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=W7f23pM3Z0wMdBh0hpMJHWSBDJMgzGiCUIzDS5kzG8oM2HzpS5LtUv/HyW9S2L+vj77kxRGTNtQUzTS+E+hgpRcGDb0+yuptLBs6pTqoJvlaZCOlS19HYFEOIZUqEODoM1miRvnQiSDC+OTPdPXMNGcuYfV4R8Z1TurwpnYsCbs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org; spf=pass smtp.mailfrom=makrotopia.org; arc=none smtp.client-ip=185.142.180.65 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=makrotopia.org Received: from local by pidgin.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.98.2) (envelope-from ) id 1upUN7-000000006og-1sg9; Fri, 22 Aug 2025 16:12:09 +0000 Date: Fri, 22 Aug 2025 17:12:06 +0100 From: Daniel Golle To: Hauke Mehrtens , Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Philipp Zabel , Russell King , linux-kernel@vger.kernel.org, netdev@vger.kernel.org Cc: Andreas Schirm , Lukas Stockmann , Alexander Sverdlin , Peter Christen , Avinash Jayaraman , Bing tao Xu , Liang Xu , Juraj Povazanec , "Fanni (Fang-Yi) Chan" , "Benny (Ying-Tsan) Weng" , "Livia M. Rosu" , John Crispin Subject: [PATCH net-next v4 5/7] net: dsa: lantiq_gswip: load model-specific microcode Message-ID: <486d95c085913d506745fbe4a0ab5d1ebdc3ed63.1755878232.git.daniel@makrotopia.org> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Load microcode as specified in struct hw_info instead of relying on a single array of instructions. This is done in preparation to allow loading different microcode for the MaxLinear GSW1xx family. Signed-off-by: Daniel Golle Reviewed-by: Vladimir Oltean --- v4: no changes v3: no changes v2: no changes drivers/net/dsa/lantiq_gswip.c | 14 +++++++++----- drivers/net/dsa/lantiq_gswip.h | 9 +++++++++ drivers/net/dsa/lantiq_pce.h | 9 ++------- 3 files changed, 20 insertions(+), 12 deletions(-) diff --git a/drivers/net/dsa/lantiq_gswip.c b/drivers/net/dsa/lantiq_gswip.c index d988839dce2f..1ce9ef425082 100644 --- a/drivers/net/dsa/lantiq_gswip.c +++ b/drivers/net/dsa/lantiq_gswip.c @@ -500,15 +500,15 @@ static int gswip_pce_load_microcode(struct gswip_priv= *priv) GSWIP_PCE_TBL_CTRL_OPMOD_ADWR, GSWIP_PCE_TBL_CTRL); gswip_switch_w(priv, 0, GSWIP_PCE_TBL_MASK); =20 - for (i =3D 0; i < ARRAY_SIZE(gswip_pce_microcode); i++) { + for (i =3D 0; i < priv->hw_info->pce_microcode_size; i++) { gswip_switch_w(priv, i, GSWIP_PCE_TBL_ADDR); - gswip_switch_w(priv, gswip_pce_microcode[i].val_0, + gswip_switch_w(priv, (*priv->hw_info->pce_microcode)[i].val_0, GSWIP_PCE_TBL_VAL(0)); - gswip_switch_w(priv, gswip_pce_microcode[i].val_1, + gswip_switch_w(priv, (*priv->hw_info->pce_microcode)[i].val_1, GSWIP_PCE_TBL_VAL(1)); - gswip_switch_w(priv, gswip_pce_microcode[i].val_2, + gswip_switch_w(priv, (*priv->hw_info->pce_microcode)[i].val_2, GSWIP_PCE_TBL_VAL(2)); - gswip_switch_w(priv, gswip_pce_microcode[i].val_3, + gswip_switch_w(priv, (*priv->hw_info->pce_microcode)[i].val_3, GSWIP_PCE_TBL_VAL(3)); =20 /* start the table access: */ @@ -2001,6 +2001,8 @@ static const struct gswip_hw_info gswip_xrx200 =3D { .allowed_cpu_ports =3D BIT(6), .mii_ports =3D BIT(0) | BIT(1) | BIT(5), .phylink_get_caps =3D gswip_xrx200_phylink_get_caps, + .pce_microcode =3D &gswip_pce_microcode, + .pce_microcode_size =3D ARRAY_SIZE(gswip_pce_microcode), }; =20 static const struct gswip_hw_info gswip_xrx300 =3D { @@ -2008,6 +2010,8 @@ static const struct gswip_hw_info gswip_xrx300 =3D { .allowed_cpu_ports =3D BIT(6), .mii_ports =3D BIT(0) | BIT(5), .phylink_get_caps =3D gswip_xrx300_phylink_get_caps, + .pce_microcode =3D &gswip_pce_microcode, + .pce_microcode_size =3D ARRAY_SIZE(gswip_pce_microcode), }; =20 static const struct of_device_id gswip_of_match[] =3D { diff --git a/drivers/net/dsa/lantiq_gswip.h b/drivers/net/dsa/lantiq_gswip.h index 1bd05348f1e1..3c60f14673a7 100644 --- a/drivers/net/dsa/lantiq_gswip.h +++ b/drivers/net/dsa/lantiq_gswip.h @@ -213,10 +213,19 @@ */ #define GSWIP_MAX_PACKET_LENGTH 2400 =20 +struct gswip_pce_microcode { + u16 val_3; + u16 val_2; + u16 val_1; + u16 val_0; +}; + struct gswip_hw_info { int max_ports; unsigned int allowed_cpu_ports; unsigned int mii_ports; + const struct gswip_pce_microcode (*pce_microcode)[]; + size_t pce_microcode_size; void (*phylink_get_caps)(struct dsa_switch *ds, int port, struct phylink_config *config); }; diff --git a/drivers/net/dsa/lantiq_pce.h b/drivers/net/dsa/lantiq_pce.h index e2be31f3672a..659f9a0638d9 100644 --- a/drivers/net/dsa/lantiq_pce.h +++ b/drivers/net/dsa/lantiq_pce.h @@ -7,6 +7,8 @@ * Copyright (C) 2017 - 2018 Hauke Mehrtens */ =20 +#include "lantiq_gswip.h" + enum { OUT_MAC0 =3D 0, OUT_MAC1, @@ -74,13 +76,6 @@ enum { FLAG_NO, /*13*/ }; =20 -struct gswip_pce_microcode { - u16 val_3; - u16 val_2; - u16 val_1; - u16 val_0; -}; - #define MC_ENTRY(val, msk, ns, out, len, type, flags, ipv4_len) \ { val, msk, ((ns) << 10 | (out) << 4 | (len) >> 1),\ ((len) & 1) << 15 | (type) << 13 | (flags) << 9 | (ipv4_len) << 8 } --=20 2.50.1 From nobody Fri Oct 3 23:08:33 2025 Received: from pidgin.makrotopia.org (pidgin.makrotopia.org [185.142.180.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9E4A72882D4; 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dmarc=none (p=none dis=none) header.from=makrotopia.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=makrotopia.org Received: from local by pidgin.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.98.2) (envelope-from ) id 1upUNF-000000006ou-1vzV; Fri, 22 Aug 2025 16:12:17 +0000 Date: Fri, 22 Aug 2025 17:12:13 +0100 From: Daniel Golle To: Hauke Mehrtens , Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Philipp Zabel , Russell King , linux-kernel@vger.kernel.org, netdev@vger.kernel.org Cc: Andreas Schirm , Lukas Stockmann , Alexander Sverdlin , Peter Christen , Avinash Jayaraman , Bing tao Xu , Liang Xu , Juraj Povazanec , "Fanni (Fang-Yi) Chan" , "Benny (Ying-Tsan) Weng" , "Livia M. Rosu" , John Crispin Subject: [PATCH net-next v4 6/7] net: dsa: lantiq_gswip: make DSA tag protocol model-specific Message-ID: <841281b62fdb472048fa98fbad6c88dfbf512825.1755878232.git.daniel@makrotopia.org> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" While the older Lantiq / Intel which are currently supported all use the DSA_TAG_GSWIP tagging protocol, newer MaxLinear GSW1xx modules use another 8-byte tagging protocol. Move the tag protocol information to struct gswip_hw_info to make it possible for new models to specify a different tagging protocol. Signed-off-by: Daniel Golle Reviewed-by: Andrew Lunn Reviewed-by: Vladimir Oltean --- v4: no changes v3: no changes v2: no changes drivers/net/dsa/lantiq_gswip.c | 6 +++++- drivers/net/dsa/lantiq_gswip.h | 1 + 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/net/dsa/lantiq_gswip.c b/drivers/net/dsa/lantiq_gswip.c index 1ce9ef425082..f8a43c351649 100644 --- a/drivers/net/dsa/lantiq_gswip.c +++ b/drivers/net/dsa/lantiq_gswip.c @@ -659,7 +659,9 @@ static enum dsa_tag_protocol gswip_get_tag_protocol(str= uct dsa_switch *ds, int port, enum dsa_tag_protocol mp) { - return DSA_TAG_PROTO_GSWIP; + struct gswip_priv *priv =3D ds->priv; + + return priv->hw_info->tag_protocol; } =20 static int gswip_vlan_active_create(struct gswip_priv *priv, @@ -2003,6 +2005,7 @@ static const struct gswip_hw_info gswip_xrx200 =3D { .phylink_get_caps =3D gswip_xrx200_phylink_get_caps, .pce_microcode =3D &gswip_pce_microcode, .pce_microcode_size =3D ARRAY_SIZE(gswip_pce_microcode), + .tag_protocol =3D DSA_TAG_PROTO_GSWIP, }; =20 static const struct gswip_hw_info gswip_xrx300 =3D { @@ -2012,6 +2015,7 @@ static const struct gswip_hw_info gswip_xrx300 =3D { .phylink_get_caps =3D gswip_xrx300_phylink_get_caps, .pce_microcode =3D &gswip_pce_microcode, .pce_microcode_size =3D ARRAY_SIZE(gswip_pce_microcode), + .tag_protocol =3D DSA_TAG_PROTO_GSWIP, }; =20 static const struct of_device_id gswip_of_match[] =3D { diff --git a/drivers/net/dsa/lantiq_gswip.h b/drivers/net/dsa/lantiq_gswip.h index 3c60f14673a7..0b7b6db4eab9 100644 --- a/drivers/net/dsa/lantiq_gswip.h +++ b/drivers/net/dsa/lantiq_gswip.h @@ -226,6 +226,7 @@ struct gswip_hw_info { unsigned int mii_ports; const struct gswip_pce_microcode (*pce_microcode)[]; size_t pce_microcode_size; + enum dsa_tag_protocol tag_protocol; void (*phylink_get_caps)(struct dsa_switch *ds, int port, struct phylink_config *config); }; --=20 2.50.1 From nobody Fri Oct 3 23:08:33 2025 Received: from pidgin.makrotopia.org (pidgin.makrotopia.org [185.142.180.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 59BB1281525; Fri, 22 Aug 2025 16:12:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.142.180.65 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755879151; cv=none; b=iImEaDsrgmNK9P/4a7lgOPRLUoFjlLveUO1oxUGjSWkcQTivUbuYPZ3IEdV9oe/Rsw0iLmfV+Zy10pQB+r1NFQKkNT6M6OgFi6Ff3Z0HoO10dzo3Jyg0lXkg95UCVWiD96QAib2GEbVNEvJrLwChcSuGrQGcoA0HpzwGbccJmAw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755879151; c=relaxed/simple; bh=v43CVOfdATmGLdEU2YvxTHCWbyWikT9BQFV6cJxMbUY=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=atqW0KF9RUhD3R7jObE04L46geLPGoNlbdTPH962Ho9LiSubZrAYAXcuvXubdLvPNk8OggguF3Br1j22YKrWY0W6NC7a2Nl8R9F2KrTz6nlK95aOmwPeb+UtGskWYhSJ7e1hf5Idn4Y/keiq067cktU0GE4uvi1dIdV4aVOEM48= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org; spf=pass smtp.mailfrom=makrotopia.org; arc=none smtp.client-ip=185.142.180.65 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=makrotopia.org Received: from local by pidgin.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.98.2) (envelope-from ) id 1upUNN-000000006pC-16Fr; Fri, 22 Aug 2025 16:12:25 +0000 Date: Fri, 22 Aug 2025 17:12:21 +0100 From: Daniel Golle To: Hauke Mehrtens , Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Philipp Zabel , Russell King , linux-kernel@vger.kernel.org, netdev@vger.kernel.org Cc: Andreas Schirm , Lukas Stockmann , Alexander Sverdlin , Peter Christen , Avinash Jayaraman , Bing tao Xu , Liang Xu , Juraj Povazanec , "Fanni (Fang-Yi) Chan" , "Benny (Ying-Tsan) Weng" , "Livia M. Rosu" , John Crispin Subject: [PATCH net-next v4 7/7] net: dsa: lantiq_gswip: store switch API version in priv Message-ID: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Store the switch API version in struct gswip_priv. As the hardware has the 'major/minor' version bytes in the wrong order preventing numerical comparisons the version to be stored in gswip_priv is constructed in such a way that the REV field is the most significant byte and the MOD field the least significant byte. Also provide a conveniance macro to allow comparing the stored version of the hardware against the already defined GSWIP_VERSION_* macros. This is done in order to prepare supporting newer features such as 4096 VLANs and per-port configurable learning which are only available starting from specific hardware versions. Signed-off-by: Daniel Golle --- v4: use FIELD_GET accessor macro to construct version to be stored, add comments and postpone adding the for now unused GSWIP_VERSION_2_3 macro v3: use __force for version field endian exception (__le16 __force) to fix sparse warning. v2: no changes drivers/net/dsa/lantiq_gswip.c | 13 +++++++++++-- drivers/net/dsa/lantiq_gswip.h | 13 +++++++++++-- 2 files changed, 22 insertions(+), 4 deletions(-) diff --git a/drivers/net/dsa/lantiq_gswip.c b/drivers/net/dsa/lantiq_gswip.c index f8a43c351649..638f9a42f218 100644 --- a/drivers/net/dsa/lantiq_gswip.c +++ b/drivers/net/dsa/lantiq_gswip.c @@ -1908,6 +1908,16 @@ static int gswip_probe(struct platform_device *pdev) mutex_init(&priv->pce_table_lock); version =3D gswip_switch_r(priv, GSWIP_VERSION); =20 + /* The hardware has the 'major/minor' version bytes in the wrong order + * preventing numerical comparisons. Construct a 16-bit unsigned integer + * having the REV field as most significant byte and the MOD field as + * least significant byte. This is effectively swapping the two bytes of + * the version variable, but other than using swab16 it doesn't affect + * the source variable. + */ + priv->version =3D GSWIP_VERSION_REV(version) << 8 | + GSWIP_VERSION_MOD(version); + np =3D dev->of_node; switch (version) { case GSWIP_VERSION_2_0: @@ -1956,8 +1966,7 @@ static int gswip_probe(struct platform_device *pdev) platform_set_drvdata(pdev, priv); =20 dev_info(dev, "probed GSWIP version %lx mod %lx\n", - (version & GSWIP_VERSION_REV_MASK) >> GSWIP_VERSION_REV_SHIFT, - (version & GSWIP_VERSION_MOD_MASK) >> GSWIP_VERSION_MOD_SHIFT); + GSWIP_VERSION_REV(version), GSWIP_VERSION_MOD(version)); return 0; =20 disable_switch: diff --git a/drivers/net/dsa/lantiq_gswip.h b/drivers/net/dsa/lantiq_gswip.h index 0b7b6db4eab9..620c2d560cbe 100644 --- a/drivers/net/dsa/lantiq_gswip.h +++ b/drivers/net/dsa/lantiq_gswip.h @@ -7,6 +7,7 @@ #include #include #include +#include #include =20 /* GSWIP MDIO Registers */ @@ -85,14 +86,21 @@ #define GSWIP_SWRES_R1 BIT(1) /* GSWIP Software reset */ #define GSWIP_SWRES_R0 BIT(0) /* GSWIP Hardware reset */ #define GSWIP_VERSION 0x013 -#define GSWIP_VERSION_REV_SHIFT 0 #define GSWIP_VERSION_REV_MASK GENMASK(7, 0) -#define GSWIP_VERSION_MOD_SHIFT 8 #define GSWIP_VERSION_MOD_MASK GENMASK(15, 8) +#define GSWIP_VERSION_REV(v) FIELD_GET(GSWIP_VERSION_REV_MASK, v) +#define GSWIP_VERSION_MOD(v) FIELD_GET(GSWIP_VERSION_MOD_MASK, v) #define GSWIP_VERSION_2_0 0x100 #define GSWIP_VERSION_2_1 0x021 #define GSWIP_VERSION_2_2 0x122 #define GSWIP_VERSION_2_2_ETC 0x022 +/* The hardware has the 'major/minor' version bytes in the wrong order + * preventing numerical comparisons. Swap the bytes of the 16-bit value + * to end up with REV being the most significant byte and MOD being the + * least significant byte, which then allows comparing it with the + * value stored in struct gswip_priv. + */ +#define GSWIP_VERSION_GE(priv, ver) ((priv)->version >=3D swab16(ver)) =20 #define GSWIP_BM_RAM_VAL(x) (0x043 - (x)) #define GSWIP_BM_RAM_ADDR 0x044 @@ -258,6 +266,7 @@ struct gswip_priv { struct gswip_gphy_fw *gphy_fw; u32 port_vlan_filter; struct mutex pce_table_lock; + u16 version; }; =20 #endif /* __LANTIQ_GSWIP_H */ --=20 2.50.1