From nobody Sat Oct 4 00:27:01 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 096723451DE; Thu, 21 Aug 2025 18:23:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755800620; cv=none; b=d3MUpPTSSlH9puIePc5l1lEOLGslzF+bF7qiGEseEpdeTAj1TZZIpQg6Oq+aDy4V/5dy3zmmH4/H9f5etBr6OUWPdgfU1aCYYVptWmq3l6wRDfR6Yb4M34Z44jtXF6ogZXSvrrisxHzJdrpvkRe2tkKqUrLQwnOF75QU/21Ip18= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755800620; c=relaxed/simple; bh=+bsXqjrbjdk0kUQXXL1WrzIRuzrIEx7IY5OrHK70vXo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ovMqvYNa9u49jwYpkmIdO3In/Q10aDJ5uAUCu2UizJvcWMHa+s4YP6EiYDEuIZ9UjrKZIVjzZDGQ01XzAInvJM79Uf/uL1hUg8+mFFlCnAkBU+lkv8hALvBntUQfR2/MsUu+SbW52vqBmQ/t7k6j5/qNPy6sHRDp7Be73OE1QsE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=gXOFFeCL; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="gXOFFeCL" Received: by smtp.kernel.org (Postfix) with ESMTPSA id EB229C4CEEB; Thu, 21 Aug 2025 18:23:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755800618; bh=+bsXqjrbjdk0kUQXXL1WrzIRuzrIEx7IY5OrHK70vXo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=gXOFFeCLTTNqCVCKZ0JTD61qLiaW/lEaolroVnAs/+nklhVjQCH/tfdoABvL2Qzv+ ezddI3EL4PH5IYkaB4Dx/bUpNXhbrHBGkmVFCzivk00BPFClyCQSFV/X+9Dg8z/dgK hd0cfxb2J6VdDHtG+Cb3JfrxJlukh/xBA6XgX8Ue1VPqs/n4J0CmZ0CK0J2J1JPQ/r hxvemuevxPO/8q8eHt9NreQ8rErznyJB6oEVThnsKxlugPvnoPKPf4uiHArzjrjXs1 KZHNFdBDFYPg7G//Z0fCCva1J4KqY6olsoqdx9HKLEiQOsBUsbavKcdcHoOP2dcWbh 0lgV+g6o+tJKw== From: "Naveen N Rao (AMD)" To: Sean Christopherson , Paolo Bonzini Cc: , , Suravee Suthikulpanit , Vasant Hegde , Pankaj Gupta , Alejandro Jimenez , Joao Martins , Nikunj A Dadhania Subject: [PATCH v4 1/7] KVM: SVM: Limit AVIC physical max index based on configured max_vcpu_ids Date: Thu, 21 Aug 2025 23:48:32 +0530 Message-ID: <471e9725e5f10a4d609910c684152de4689c09f2.1755797611.git.naveen@kernel.org> X-Mailer: git-send-email 2.50.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" KVM allows VMMs to specify the maximum possible APIC ID for a virtual machine through KVM_CAP_MAX_VCPU_ID capability so as to limit data structures related to APIC/x2APIC. Utilize the same to set the AVIC physical max index in the VMCB, similar to VMX. This helps hardware limit the number of entries to be scanned in the physical APIC ID table speeding up IPI broadcasts for virtual machines with smaller number of vCPUs. Unlike VMX, SVM AVIC requires a single page to be allocated for the Physical APIC ID table and the Logical APIC ID table, so retain the existing approach of allocating those during VM init. Signed-off-by: Naveen N Rao (AMD) --- arch/x86/kvm/svm/avic.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index a34c5c3b164e..a6908ac5298d 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -82,6 +82,7 @@ bool x2avic_enabled; static void avic_activate_vmcb(struct vcpu_svm *svm) { struct vmcb *vmcb =3D svm->vmcb01.ptr; + struct kvm *kvm =3D svm->vcpu.kvm; =20 vmcb->control.int_ctl &=3D ~(AVIC_ENABLE_MASK | X2APIC_MODE_MASK); vmcb->control.avic_physical_id &=3D ~AVIC_PHYSICAL_MAX_INDEX_MASK; @@ -97,7 +98,8 @@ static void avic_activate_vmcb(struct vcpu_svm *svm) */ if (x2avic_enabled && apic_x2apic_mode(svm->vcpu.arch.apic)) { vmcb->control.int_ctl |=3D X2APIC_MODE_MASK; - vmcb->control.avic_physical_id |=3D X2AVIC_MAX_PHYSICAL_ID; + vmcb->control.avic_physical_id |=3D min(kvm->arch.max_vcpu_ids - 1, + X2AVIC_MAX_PHYSICAL_ID); /* Disabling MSR intercept for x2APIC registers */ svm_set_x2apic_msr_interception(svm, false); } else { @@ -108,7 +110,8 @@ static void avic_activate_vmcb(struct vcpu_svm *svm) kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, &svm->vcpu); =20 /* For xAVIC and hybrid-xAVIC modes */ - vmcb->control.avic_physical_id |=3D AVIC_MAX_PHYSICAL_ID; + vmcb->control.avic_physical_id |=3D min(kvm->arch.max_vcpu_ids - 1, + AVIC_MAX_PHYSICAL_ID); /* Enabling MSR intercept for x2APIC registers */ svm_set_x2apic_msr_interception(svm, true); } --=20 2.50.1 From nobody Sat Oct 4 00:27:01 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E42EF2C21C3; Thu, 21 Aug 2025 18:22:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755800580; cv=none; b=KU5YAT1P+kiO1uUYdwMXeMnFyFxEmMvohd1ptSaSuXlkB2cQtxuf9R1vjTHKXDVMCiRZN4bllCw3cbKs/9Rah066U/NtKONtYPUYJcYgSrcNCwsINVv9Y0s7UVBhdSo0jeBEpMDnMp3o6joxEefYBklzuFiQr6t1oiG8qR21oNM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755800580; c=relaxed/simple; bh=trQVciou02BhqLI+wLFz+BJzOyksrkiGATsW4fd67aE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=fZ3+6pLxnUqxRrkFNgjg3VEeLEbhWY5dpoEnIAcTlicnuomei0/cS72Fdzmd9AkvQG3goySa+LrOB8PoZKWIT0L/rlQxFMZEVsUbBaJsRBfHlkVVIsPUpqibdsgVwnQsXSunNDsp+C6obnM7nwyZW2MJ4z+SAjk5cjqrByhpIH0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=b7s/L6+5; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="b7s/L6+5" Received: by smtp.kernel.org (Postfix) with ESMTPSA id DF416C4CEEB; Thu, 21 Aug 2025 18:22:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755800579; bh=trQVciou02BhqLI+wLFz+BJzOyksrkiGATsW4fd67aE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=b7s/L6+5Fk8KOSKcdHN/llciet0ETx9ev0EY5VxZjKkU2gKZvpTpqdjCak78wc5Vw A3MhfqzgLDDTO+3XfRYBrvsKOS/K633fygH0NGlZC3HlpA6jGGCbm6lf+ZH+KBiGGv tSVunXP5T1ckJW1ENJ9BwKOiWDNjpXivyRn+PuTqGKO+Ca+8Gox+cjZcPTcR5IdRG/ Kqi8upLo7MdXDQGD8Gum1BeOeozvCH8iwvJvT4ZhUw3KYX79qnyGCIpyI00a2qzFb7 D6ggmXtl7pot7tv691m2yubkLvrjIZM//oVR4SNGbMR6JKuuS9dBOXHwxFBfDiDhrI TqiZAZQ6UMKrg== From: "Naveen N Rao (AMD)" To: Sean Christopherson , Paolo Bonzini Cc: , , Suravee Suthikulpanit , Vasant Hegde , Pankaj Gupta , Alejandro Jimenez , Joao Martins , Nikunj A Dadhania Subject: [PATCH v4 2/7] KVM: SVM: Add a helper to look up the max physical ID for AVIC Date: Thu, 21 Aug 2025 23:48:33 +0530 Message-ID: <82992eac8f3a2424373001d76526f418276532a5.1755797611.git.naveen@kernel.org> X-Mailer: git-send-email 2.50.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" To help with a future change, add a helper to look up the maximum physical ID depending on the vCPU AVIC mode. No functional change intended. Suggested-by: Sean Christopherson Signed-off-by: Naveen N Rao (AMD) --- arch/x86/kvm/svm/avic.c | 26 ++++++++++++++++++++------ 1 file changed, 20 insertions(+), 6 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index a6908ac5298d..4f00e31347c3 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -79,13 +79,31 @@ static bool next_vm_id_wrapped =3D 0; static DEFINE_SPINLOCK(svm_vm_data_hash_lock); bool x2avic_enabled; =20 +static u32 avic_get_max_physical_id(struct kvm_vcpu *vcpu) +{ + u32 arch_max; + + if (x2avic_enabled && apic_x2apic_mode(vcpu->arch.apic)) + arch_max =3D X2AVIC_MAX_PHYSICAL_ID; + else + arch_max =3D AVIC_MAX_PHYSICAL_ID; + + /* + * Despite its name, KVM_CAP_MAX_VCPU_ID represents the maximum APIC ID p= lus one, + * so the max possible APIC ID is one less than that. + */ + return min(vcpu->kvm->arch.max_vcpu_ids - 1, arch_max); +} + static void avic_activate_vmcb(struct vcpu_svm *svm) { struct vmcb *vmcb =3D svm->vmcb01.ptr; - struct kvm *kvm =3D svm->vcpu.kvm; + struct kvm_vcpu *vcpu =3D &svm->vcpu; =20 vmcb->control.int_ctl &=3D ~(AVIC_ENABLE_MASK | X2APIC_MODE_MASK); + vmcb->control.avic_physical_id &=3D ~AVIC_PHYSICAL_MAX_INDEX_MASK; + vmcb->control.avic_physical_id |=3D avic_get_max_physical_id(vcpu); =20 vmcb->control.int_ctl |=3D AVIC_ENABLE_MASK; =20 @@ -98,8 +116,7 @@ static void avic_activate_vmcb(struct vcpu_svm *svm) */ if (x2avic_enabled && apic_x2apic_mode(svm->vcpu.arch.apic)) { vmcb->control.int_ctl |=3D X2APIC_MODE_MASK; - vmcb->control.avic_physical_id |=3D min(kvm->arch.max_vcpu_ids - 1, - X2AVIC_MAX_PHYSICAL_ID); + /* Disabling MSR intercept for x2APIC registers */ svm_set_x2apic_msr_interception(svm, false); } else { @@ -109,9 +126,6 @@ static void avic_activate_vmcb(struct vcpu_svm *svm) */ kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, &svm->vcpu); =20 - /* For xAVIC and hybrid-xAVIC modes */ - vmcb->control.avic_physical_id |=3D min(kvm->arch.max_vcpu_ids - 1, - AVIC_MAX_PHYSICAL_ID); /* Enabling MSR intercept for x2APIC registers */ svm_set_x2apic_msr_interception(svm, true); } --=20 2.50.1 From nobody Sat Oct 4 00:27:01 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0DF4E2C21C3; Thu, 21 Aug 2025 18:23:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755800585; cv=none; b=aeifQBxr+Lb8PzbvYOUbH6vzvFnEyTQSFtpZ6L27PaRod6nzz6nsJQgvZDhQBGDMBJ4Q2mNUFSP5gI+pB8c3SLQMhHSPp2SpIp+Oy1FSvyljYMrjA3KhywPjPtHw1vzaAvmiAf+UxFFC57q88ru0sSBHr6/hePzoFGUOX0ZmAXU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755800585; c=relaxed/simple; bh=5JJUhuDphwQRDsn4xnJY27gsjgfY8NFDiTRQ6+7yP0M=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=F0TKfONlPZyEul+Rmm6jyatMCwkQ87YkHZBvKah3Mz8p6bAj+bzKyo4ILPnsAXzaHNc2Q3CEfHuYRmyTUyoEwtqO2wS6cnZcg3aBXuIhJ6J7p93Wguf2vC7MYV9jyiX5MgHjxnT9e5xrCmaoQgWlyPtdIDz5phVn1kme+uvQ5PA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=aLHcGYUV; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="aLHcGYUV" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B600FC4CEEB; Thu, 21 Aug 2025 18:23:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755800584; bh=5JJUhuDphwQRDsn4xnJY27gsjgfY8NFDiTRQ6+7yP0M=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=aLHcGYUVh1Uws9fQU2a29hdWyOEz84qe0KdKj4feiGRolLAD/yUgGPn9GtGwY36cG 64Ql66g0W5cSloYO2+gKBW1HNyZWFSkwU+XDmn8tWacI/qCU4+dpXVcrhm04z3w4gB qeVwJ67FsVS0y4zu9k1hHgBABUybTtHDdnPI/wI2m9p98Vs9pZi21yFSxP1uqRlu3h foRVTGtewD17Ny5dMl+EPRNnRrHBIZ5e397FzMTZ+f0mVOnj3yymKs+3d+DTBhkLZY qdAdfFMED1jK/zcWAI59NiukTv68zMgOHiwnIVDzAIvR+yz9zTM/4QubaP/bGt/4jy vbEBSSE+BBkZQ== From: "Naveen N Rao (AMD)" To: Sean Christopherson , Paolo Bonzini Cc: , , Suravee Suthikulpanit , Vasant Hegde , Pankaj Gupta , Alejandro Jimenez , Joao Martins , Nikunj A Dadhania Subject: [PATCH v4 3/7] KVM: SVM: Replace hard-coded value 0x1FF with the corresponding macro Date: Thu, 21 Aug 2025 23:48:34 +0530 Message-ID: <2ea3769ddd3178dd7144e8364f8cffe68b37dd83.1755797611.git.naveen@kernel.org> X-Mailer: git-send-email 2.50.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The lower 9-bit field in EXITINFO2 represents an index into the AVIC Physical/Logical APIC ID table for a AVIC_INCOMPLETE_IPI #VMEXIT. Since the index into the Logical APIC ID table is just 8 bits, this field is actually bound by the bit-width of the index into the AVIC Physical ID table which is represented by AVIC_PHYSICAL_MAX_INDEX_MASK. So, use that macro to mask EXITINFO2.Index instead of hard coding 0x1FF in avic_incomplete_ipi_interception(). Co-developed-by: Suravee Suthikulpanit Signed-off-by: Suravee Suthikulpanit Signed-off-by: Naveen N Rao (AMD) --- arch/x86/kvm/svm/avic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index 4f00e31347c3..d00b8f34e8d3 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -500,7 +500,7 @@ int avic_incomplete_ipi_interception(struct kvm_vcpu *v= cpu) u32 icrh =3D svm->vmcb->control.exit_info_1 >> 32; u32 icrl =3D svm->vmcb->control.exit_info_1; u32 id =3D svm->vmcb->control.exit_info_2 >> 32; - u32 index =3D svm->vmcb->control.exit_info_2 & 0x1FF; + u32 index =3D svm->vmcb->control.exit_info_2 & AVIC_PHYSICAL_MAX_INDEX_MA= SK; struct kvm_lapic *apic =3D vcpu->arch.apic; =20 trace_kvm_avic_incomplete_ipi(vcpu->vcpu_id, icrh, icrl, id, index); --=20 2.50.1 From nobody Sat Oct 4 00:27:01 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F792343D82; Thu, 21 Aug 2025 18:23:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755800590; cv=none; b=J4ht90YivgdC34QG8OYpjyeR0J0vZ5aES8ipiFul+0erwI+cryew+uo+Hw64ONtw9zW9nQgiVRV6q9Z/S3LlT4nlEw8/G4ib0SXEHn6QHnhjifEMQtdnKNg5YmCVY4lxGEL+6C9zf9yu0OmZy0vgbj1ZPx8Dmjfa3nXBcJucQ/A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755800590; c=relaxed/simple; bh=FJElYwFWMkHBmKZmwX5ZW0wOgAGaF8KcxGG+//Rl2Dw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=HJAlPyOvQWd1GbNcO8mjE4nzM/X3X8ZAe3s1ClRkuy/XWrrRKYchjlfBnpLebs2K065qN33hcwMTsEFGzyBOHLrg8KRQW3nqI9jZ3bAJstNzFwR+YJvJe2OSXZBcay+h/vFah7MUh9eRtLTHBAzshVjzItNRWnvjD+DZWzq8VoU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=lNoLslh3; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="lNoLslh3" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D1D51C4CEEB; Thu, 21 Aug 2025 18:23:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755800589; bh=FJElYwFWMkHBmKZmwX5ZW0wOgAGaF8KcxGG+//Rl2Dw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lNoLslh3T0lXIAOdCatK5wSh7IrThadZeDBkN2PXdGFwGS0uxzXA5KMJ7yNeaxCdI goIX2UnCOVpnTvKfOf8ZDB4hqLlTQ6AFgQ4fCMWFJUznvWnJb1PZDsAsPTfwa9y1SR llNEjDr0BWOUZF/FfHDowGe50d8a+TGnkxv1lOHphyJDXMk0zY7v51pAgpaj3rJfXH QzZkCVfFj7q+pyIn7h0+CKXLfVV/0A9OC90lnGvMMk0YPysWEcAWaVuEqazFvwj6lI 3yu9vyCcSbf5N0qAD1/BHqGvYsTRaS6FvLdwKMIRaa6McRkxWECxXCbXaPX3SiECPn QGT3Uyyyt/SZA== From: "Naveen N Rao (AMD)" To: Sean Christopherson , Paolo Bonzini Cc: , , Suravee Suthikulpanit , Vasant Hegde , Pankaj Gupta , Alejandro Jimenez , Joao Martins , Nikunj A Dadhania Subject: [PATCH v4 4/7] KVM: SVM: Expand AVIC_PHYSICAL_MAX_INDEX_MASK to be a 12-bit field Date: Thu, 21 Aug 2025 23:48:35 +0530 Message-ID: X-Mailer: git-send-email 2.50.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In the latest APM describing AVIC support for 4k vCPUs, VMCB AVIC_PHYSICAL_MAX_INDEX (Offset 0xF8) and EXITINFO2.Index are both updated from 9-bit wide to 12-bit wide fields unconditionally (i.e., regardless of AVIC support for 4k vCPUs). Expand AVIC_PHYSICAL_MAX_INDEX_MASK accordingly. While AVIC_PHYSICAL_MAX_INDEX_MASK is updated to a 12-bit field, KVM will limit the max vCPU/APIC ID based on the maximum supported on a specific processor and enforce that limit during vCPU creation. I.e., we don't need to rely on the mask to ensure that the max APIC ID being programmed in the VMCB is in range. The additional bits (11:9) were previously marked reserved and were never set/read by older processors. Signed-off-by: Naveen N Rao (AMD) --- arch/x86/include/asm/svm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/include/asm/svm.h b/arch/x86/include/asm/svm.h index ffc27f676243..58c10991521c 100644 --- a/arch/x86/include/asm/svm.h +++ b/arch/x86/include/asm/svm.h @@ -279,7 +279,7 @@ enum avic_ipi_failure_cause { AVIC_IPI_FAILURE_INVALID_IPI_VECTOR, }; =20 -#define AVIC_PHYSICAL_MAX_INDEX_MASK GENMASK_ULL(8, 0) +#define AVIC_PHYSICAL_MAX_INDEX_MASK GENMASK_ULL(11, 0) =20 /* * For AVIC, the max index allowed for physical APIC ID table is 0xfe (254= ), as --=20 2.50.1 From nobody Sat Oct 4 00:27:01 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 81EEB2E62B3; Thu, 21 Aug 2025 18:23:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755800600; cv=none; b=bLiaLOl9P+FADvj2GutLZ5Jo1Fo5PypBc4H/yx33K8lEof2jBRIFv0M9LNzAhUpMjs1Ts+Hg9lUonLrdgw53FgCHSsIbERKUoLaXCrVfErp0bZX7OcMxi7/dIeKLKRYwBpJJqVFgywmkwCTNuOKgkY2FYe1SEC92daLR4jDPtF8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755800600; c=relaxed/simple; bh=n/UG1uEWyVosv/9nhjgReWzsttl/974c80BSLHMkfb4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Hy7SiD9BNVrh14ok+CIqxLCOnqbKzwOV9fOZm60yD/ouLtDImVOgy/AWfLVIfBH6rE/YYBMuLUsUOsZt0xg30hFr3veys3uh++us1c+DPQB2wrPWpGPtEiQtccr7/UeQRcHpU4oFcySBUv/xjNp2tJSDJVn8ZCi4UUL+LEK2srk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=SwWUAZ/X; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="SwWUAZ/X" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 50003C4CEEB; Thu, 21 Aug 2025 18:23:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755800600; bh=n/UG1uEWyVosv/9nhjgReWzsttl/974c80BSLHMkfb4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SwWUAZ/Xp543KQ1EST1hyVkt9ReqApRTOulqWlgA5iCyMT8t23/YjnVdSBuJQnjzR wAttMsXm8N2wGZXzlvvOd0eIdWQmtnms09xEa1nFKPOcSOpAdMgnCU4ceG01I8JORi YcUeWE9tuMPwpCJKneDnXR+WQDRRVm2SB2UcrbIqxDAmX4WH9YrmpVHmXFiEOexPdE +w0KgmW78x6xRSLUJQ9e4L3o8EXIKSVhwSYbcpOdQTal4bLmu93GNuvJ5YGPyydC0o 11XDys4llVk8sdzPPwTV7NvlCfYFLXUN6VITtZpZubKXo8iG4DuzcrcAaByuVpI1Wi G8abx4uh5gDag== From: "Naveen N Rao (AMD)" To: Sean Christopherson , Paolo Bonzini Cc: , , Suravee Suthikulpanit , Vasant Hegde , Pankaj Gupta , Alejandro Jimenez , Joao Martins , Nikunj A Dadhania Subject: [PATCH v4 5/7] KVM: SVM: Move AVIC Physical ID table allocation to vcpu_precreate() Date: Thu, 21 Aug 2025 23:48:36 +0530 Message-ID: <14f291111be8f32fdd49e37f1466dc4a4b2f7872.1755797611.git.naveen@kernel.org> X-Mailer: git-send-email 2.50.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" With support for 4k vCPUs in x2AVIC, the size of the AVIC Physical ID table is expanded from a single 4k page to a maximum of 8 contiguous 4k pages. The actual number of pages allocated depends on the maximum possible APIC ID in the guest, which is only known by the time the first vCPU is created. In preparation for supporting a dynamic AVIC Physical ID table size, move its allocation to vcpu_precreate(). Suggested-by: Sean Christopherson Signed-off-by: Naveen N Rao (AMD) --- arch/x86/kvm/svm/svm.h | 1 + arch/x86/kvm/svm/avic.c | 18 ++++++++++++++---- arch/x86/kvm/svm/svm.c | 9 +++++++++ 3 files changed, 24 insertions(+), 4 deletions(-) diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index 58b9d168e0c8..58d13b418734 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -803,6 +803,7 @@ extern struct kvm_x86_nested_ops svm_nested_ops; =20 bool avic_hardware_setup(void); int avic_ga_log_notifier(u32 ga_tag); +int avic_alloc_physical_id_table(struct kvm *kvm); void avic_vm_destroy(struct kvm *kvm); int avic_vm_init(struct kvm *kvm); void avic_init_vmcb(struct vcpu_svm *svm, struct vmcb *vmcb); diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index d00b8f34e8d3..b5a397b7c684 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -185,6 +185,20 @@ int avic_ga_log_notifier(u32 ga_tag) return 0; } =20 +int avic_alloc_physical_id_table(struct kvm *kvm) +{ + struct kvm_svm *kvm_svm =3D to_kvm_svm(kvm); + + if (kvm_svm->avic_physical_id_table || !enable_apicv || !irqchip_in_kerne= l(kvm)) + return 0; + + kvm_svm->avic_physical_id_table =3D (void *)get_zeroed_page(GFP_KERNEL_AC= COUNT); + if (!kvm_svm->avic_physical_id_table) + return -ENOMEM; + + return 0; +} + void avic_vm_destroy(struct kvm *kvm) { unsigned long flags; @@ -212,10 +226,6 @@ int avic_vm_init(struct kvm *kvm) if (!enable_apicv) return 0; =20 - kvm_svm->avic_physical_id_table =3D (void *)get_zeroed_page(GFP_KERNEL_AC= COUNT); - if (!kvm_svm->avic_physical_id_table) - goto free_avic; - kvm_svm->avic_logical_id_table =3D (void *)get_zeroed_page(GFP_KERNEL_ACC= OUNT); if (!kvm_svm->avic_logical_id_table) goto free_avic; diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 7e7821ee8ee1..949cc9e76007 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -1271,6 +1271,14 @@ void svm_switch_vmcb(struct vcpu_svm *svm, struct kv= m_vmcb_info *target_vmcb) svm->vmcb =3D target_vmcb->ptr; } =20 +static int svm_vcpu_precreate(struct kvm *kvm) +{ + if (enable_apicv) + return avic_alloc_physical_id_table(kvm); + + return 0; +} + static int svm_vcpu_create(struct kvm_vcpu *vcpu) { struct vcpu_svm *svm; @@ -5063,6 +5071,7 @@ static struct kvm_x86_ops svm_x86_ops __initdata =3D { .emergency_disable_virtualization_cpu =3D svm_emergency_disable_virtualiz= ation_cpu, .has_emulated_msr =3D svm_has_emulated_msr, =20 + .vcpu_precreate =3D svm_vcpu_precreate, .vcpu_create =3D svm_vcpu_create, .vcpu_free =3D svm_vcpu_free, .vcpu_reset =3D svm_vcpu_reset, --=20 2.50.1 From nobody Sat Oct 4 00:27:01 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 108342E62B3; Thu, 21 Aug 2025 18:23:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755800606; cv=none; b=TuoIpZgy5PVDgvdGltvQ0AJ4WwQjBUAyrO6SRKbcmanlinnBkz81XtTCdKWH6Vk4j6RmpVUPpH9BX07W6O091MhBm9QTSReT+DRv/+jYhNouERNKO43yj0MdtRmemSJUipN4pqzsQ7q4flZtk1S378EGMDAZNVaJrhN0KkVPTc0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755800606; c=relaxed/simple; bh=0Yj5JZHjaWiDqMSbt1goY4h+cOWdrnslXbKQElQVKlw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=najsLoZMkmO2r274Si+BHzLUzq/g4HYqmHcgh9uNLaglZOu3GtgysXhwMmn7IFsoc7z3PCtuQSR2aPBXsfrjHVtpAqfIEoHCEcjrnNivCa1su68bWa2sWOxRB4DQFI8cvNosOzPGUW4lej/X9xYQe2G99qbKcccJTxjcFD2y2GM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=YlQ3VuCb; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="YlQ3VuCb" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B5E13C4CEEB; Thu, 21 Aug 2025 18:23:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755800605; bh=0Yj5JZHjaWiDqMSbt1goY4h+cOWdrnslXbKQElQVKlw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=YlQ3VuCbfpU49jDZop9TSOTAWVHLDsoakVzrq6slMV4Ey8rDWxJYDcZL3qKTO/anU lYpuyjVSBf3HBb9Glu3VDqrsGWDHeUMZEsbqi0kDJGUSFrj8Qvv+4RvETrH5RzCOwu thO8CTwZwogDwwaMlBJLiM502Pe7G+qCeAQnVuSCvpHD2oOeF9bXv7ua6HhdSRRCx5 03VVNw96zJUW4kap+HklKSdZsHi6Kr2dd/7LPtmNrFZPIzqWvcDKA2yKh87OBJ7x9m 9N7dresuXVdYd0Boopdc9xEACBQkdc7Q5vWXuzt2IkKqcoDfXipNY6NKrYMm3kyZ8h oBsZGYYBTIzeQ== From: "Naveen N Rao (AMD)" To: Sean Christopherson , Paolo Bonzini Cc: , , Suravee Suthikulpanit , Vasant Hegde , Pankaj Gupta , Alejandro Jimenez , Joao Martins , Nikunj A Dadhania Subject: [PATCH v4 6/7] x86/cpufeatures: Add X86_FEATURE_X2AVIC_EXT Date: Thu, 21 Aug 2025 23:48:37 +0530 Message-ID: X-Mailer: git-send-email 2.50.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add CPUID feature bit for x2AVIC extension that enables AMD SVM to support up to 4096 vCPUs in x2AVIC mode. The primary change is in the size of the AVIC Physical ID table, which can now go up to 8 contiguous 4k pages. The number of pages allocated is controlled by the maximum APIC ID for a guest, and that controls the number of pages to allocate for the AVIC Physical ID table. AVIC hardware is enhanced to look up Physical ID table entries for vCPUs > 512 for locating the target APIC backing page and the host APIC ID of the physical core on which the guest vCPU is running. Signed-off-by: Naveen N Rao (AMD) --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/scattered.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index eb859299d514..9ba97459579f 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -496,6 +496,7 @@ #define X86_FEATURE_TSA_L1_NO (21*32+12) /* AMD CPU not vulnerable to TSA= -L1 */ #define X86_FEATURE_CLEAR_CPU_BUF_VM (21*32+13) /* Clear CPU buffers using= VERW before VMRUN */ #define X86_FEATURE_MSR_IMM (21*32+14) /* MSR immediate form instructions= */ +#define X86_FEATURE_X2AVIC_EXT (21*32+15) /* AMD SVM x2AVIC support for 4= k vCPUs */ =20 /* * BUG word(s) diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattere= d.c index cf4ae822bcc0..c6908c08aa55 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -49,6 +49,7 @@ static const struct cpuid_bit cpuid_bits[] =3D { { X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 }, { X86_FEATURE_AMD_FAST_CPPC, CPUID_EDX, 15, 0x80000007, 0 }, { X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 }, + { X86_FEATURE_X2AVIC_EXT, CPUID_ECX, 6, 0x8000000a, 0 }, { X86_FEATURE_COHERENCY_SFW_NO, CPUID_EBX, 31, 0x8000001f, 0 }, { X86_FEATURE_SMBA, CPUID_EBX, 2, 0x80000020, 0 }, { X86_FEATURE_BMEC, CPUID_EBX, 3, 0x80000020, 0 }, --=20 2.50.1 From nobody Sat Oct 4 00:27:01 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4D217343D66; Thu, 21 Aug 2025 18:23:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755800611; cv=none; b=Uw8nf2LChtl/dvf4qEKf1u51NAeRpqyws5Gcj/PI4ZDOt8c+muRMUZ9da05uO6Tewx7VAk+UL44ko60wOyAGP9FmiXOljzDGXBZ0ReUMuO7P7HIgF0JSeO17adC1HgIao7mTmODr+aStdz5T7wzDLeeLHPlEKxQug+PSNy9/8jg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755800611; c=relaxed/simple; bh=Jz4K02/DkA+KjN4qPfqmXopJA34UvBEt2w0g5HHD59M=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ltZsvObR7nw3kmmyUx2ahgLF0gBUsywGpVolSoG8eeO80mxN8XhgAaFbCFlScfHH54bTFGbfceMi9VeF7b6FJzDZ72b3ZEsXNYOug6uRp+F9mA0TpA9rNKQCuleIsdqvED2n30bXu7JYrEmznjQQAdr9CgoFB6sBL2DUzTKblak= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=runX6P2n; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="runX6P2n" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 38409C4CEEB; Thu, 21 Aug 2025 18:23:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755800610; bh=Jz4K02/DkA+KjN4qPfqmXopJA34UvBEt2w0g5HHD59M=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=runX6P2nYn1iaWZr7MetT29pQAO4T3bAw3MRE0DrClqKqZ5JBxOAjTacU5OymOi09 bnV38F604/eGIaNC9fS71cjAaSTpFM0ok4M2CzmzTXHOw2A97JQQP7LLEV7EUGCvY+ TMEViUqd6MWrw8w2MRYa168g1mg1wVvUVZh6lw/5kyouoRzn8O/BqraeYyoaIwKMBA TqpWqkdQxTi1oIsmOVSm7CrVG/PX4B+wOu4ONEi9mxRTClyXz2m+9WxxakkaEvvm1c YUNydNiYEw3t+XgsHzWSuC7/3GngxnwMxD2GnkaRZK1+rTvvW8nqoPuwSbzc92OcWy hyYfYfXiL1IVg== From: "Naveen N Rao (AMD)" To: Sean Christopherson , Paolo Bonzini Cc: , , Suravee Suthikulpanit , Vasant Hegde , Pankaj Gupta , Alejandro Jimenez , Joao Martins , Nikunj A Dadhania Subject: [PATCH v4 7/7] KVM: SVM: Add AVIC support for 4k vCPUs in x2AVIC mode Date: Thu, 21 Aug 2025 23:48:38 +0530 Message-ID: <69a5a2958b6aa111d36881a1d58d56bb20c43cac.1755797611.git.naveen@kernel.org> X-Mailer: git-send-email 2.50.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" With AVIC support for 4k vCPUs, the maximum supported physical ID in x2AVIC mode is 4095. Since this is no longer fixed, introduce a variable (x2avic_max_physical_id) to capture the maximum supported physical ID on the current platform and use that in place of the existing macro (X2AVIC_MAX_PHYSICAL_ID). With AVIC support for 4k vCPUs, the AVIC Physical ID table is no longer a single page and can occupy up to 8 contiguous 4k pages. Since AVIC hardware accesses of the physical ID table are limited by the physical max index programmed in the VMCB, it is sufficient to allocate only as many pages as are required to have a physical table entry for the max guest APIC ID. Since the guest APIC mode is not available at this point, provision for the maximum possible x2AVIC ID. For this purpose, add a variant of avic_get_max_physical_id() that works with a NULL vCPU pointer and returns the max x2AVIC ID. Wrap this in a new helper for obtaining the allocation order. To make it easy to identify support for 4k vCPUs in x2AVIC mode, update the message printed to the kernel log to print the maximum number of vCPUs supported. Do this on all platforms supporting x2AVIC since it is useful to know what is supported on a specific platform. Co-developed-by: Suravee Suthikulpanit Signed-off-by: Suravee Suthikulpanit Signed-off-by: Naveen N Rao (AMD) --- arch/x86/include/asm/svm.h | 3 +++ arch/x86/kvm/svm/avic.c | 43 ++++++++++++++++++++++++++++---------- 2 files changed, 35 insertions(+), 11 deletions(-) diff --git a/arch/x86/include/asm/svm.h b/arch/x86/include/asm/svm.h index 58c10991521c..16d71752606b 100644 --- a/arch/x86/include/asm/svm.h +++ b/arch/x86/include/asm/svm.h @@ -289,11 +289,14 @@ enum avic_ipi_failure_cause { =20 /* * For x2AVIC, the max index allowed for physical APIC ID table is 0x1ff (= 511). + * With X86_FEATURE_X2AVIC_EXT, the max index is increased to 0xfff (4095). */ #define X2AVIC_MAX_PHYSICAL_ID 0x1FFUL +#define X2AVIC_4K_MAX_PHYSICAL_ID 0xFFFUL =20 static_assert((AVIC_MAX_PHYSICAL_ID & AVIC_PHYSICAL_MAX_INDEX_MASK) =3D=3D= AVIC_MAX_PHYSICAL_ID); static_assert((X2AVIC_MAX_PHYSICAL_ID & AVIC_PHYSICAL_MAX_INDEX_MASK) =3D= =3D X2AVIC_MAX_PHYSICAL_ID); +static_assert((X2AVIC_4K_MAX_PHYSICAL_ID & AVIC_PHYSICAL_MAX_INDEX_MASK) = =3D=3D X2AVIC_4K_MAX_PHYSICAL_ID); =20 #define SVM_SEV_FEAT_SNP_ACTIVE BIT(0) #define SVM_SEV_FEAT_RESTRICTED_INJECTION BIT(3) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index b5a397b7c684..1dda90d29f4e 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -78,13 +78,14 @@ static u32 next_vm_id =3D 0; static bool next_vm_id_wrapped =3D 0; static DEFINE_SPINLOCK(svm_vm_data_hash_lock); bool x2avic_enabled; +static u64 x2avic_max_physical_id; =20 -static u32 avic_get_max_physical_id(struct kvm_vcpu *vcpu) +static u32 __avic_get_max_physical_id(struct kvm *kvm, struct kvm_vcpu *vc= pu) { u32 arch_max; =20 - if (x2avic_enabled && apic_x2apic_mode(vcpu->arch.apic)) - arch_max =3D X2AVIC_MAX_PHYSICAL_ID; + if (x2avic_enabled && (!vcpu || apic_x2apic_mode(vcpu->arch.apic))) + arch_max =3D x2avic_max_physical_id; else arch_max =3D AVIC_MAX_PHYSICAL_ID; =20 @@ -92,7 +93,12 @@ static u32 avic_get_max_physical_id(struct kvm_vcpu *vcp= u) * Despite its name, KVM_CAP_MAX_VCPU_ID represents the maximum APIC ID p= lus one, * so the max possible APIC ID is one less than that. */ - return min(vcpu->kvm->arch.max_vcpu_ids - 1, arch_max); + return min(kvm->arch.max_vcpu_ids - 1, arch_max); +} + +static u32 avic_get_max_physical_id(struct kvm_vcpu *vcpu) +{ + return __avic_get_max_physical_id(vcpu->kvm, vcpu); } =20 static void avic_activate_vmcb(struct vcpu_svm *svm) @@ -185,6 +191,12 @@ int avic_ga_log_notifier(u32 ga_tag) return 0; } =20 +static int avic_get_physical_id_table_order(struct kvm *kvm) +{ + /* Provision for the maximum physical ID supported in x2avic mode */ + return get_order((__avic_get_max_physical_id(kvm, NULL) + 1) * sizeof(u64= )); +} + int avic_alloc_physical_id_table(struct kvm *kvm) { struct kvm_svm *kvm_svm =3D to_kvm_svm(kvm); @@ -192,7 +204,8 @@ int avic_alloc_physical_id_table(struct kvm *kvm) if (kvm_svm->avic_physical_id_table || !enable_apicv || !irqchip_in_kerne= l(kvm)) return 0; =20 - kvm_svm->avic_physical_id_table =3D (void *)get_zeroed_page(GFP_KERNEL_AC= COUNT); + kvm_svm->avic_physical_id_table =3D (void *)__get_free_pages(GFP_KERNEL_A= CCOUNT | __GFP_ZERO, + avic_get_physical_id_table_order(kvm)); if (!kvm_svm->avic_physical_id_table) return -ENOMEM; =20 @@ -208,7 +221,8 @@ void avic_vm_destroy(struct kvm *kvm) return; =20 free_page((unsigned long)kvm_svm->avic_logical_id_table); - free_page((unsigned long)kvm_svm->avic_physical_id_table); + free_pages((unsigned long)kvm_svm->avic_physical_id_table, + avic_get_physical_id_table_order(kvm)); =20 spin_lock_irqsave(&svm_vm_data_hash_lock, flags); hash_del(&kvm_svm->hnode); @@ -290,7 +304,7 @@ static int avic_init_backing_page(struct kvm_vcpu *vcpu) * fully initialized AVIC. */ if ((!x2avic_enabled && id > AVIC_MAX_PHYSICAL_ID) || - (id > X2AVIC_MAX_PHYSICAL_ID)) { + (id > x2avic_max_physical_id)) { kvm_set_apicv_inhibit(vcpu->kvm, APICV_INHIBIT_REASON_PHYSICAL_ID_TOO_BI= G); vcpu->arch.apic->apicv_active =3D false; return 0; @@ -910,7 +924,8 @@ static void __avic_vcpu_load(struct kvm_vcpu *vcpu, int= cpu, if (WARN_ON(h_physical_id & ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK= )) return; =20 - if (WARN_ON_ONCE(vcpu->vcpu_id * sizeof(entry) >=3D PAGE_SIZE)) + if (WARN_ON_ONCE(vcpu->vcpu_id * sizeof(entry) >=3D + PAGE_SIZE << avic_get_physical_id_table_order(vcpu->kvm))) return; =20 /* @@ -972,7 +987,8 @@ static void __avic_vcpu_put(struct kvm_vcpu *vcpu, enum= avic_vcpu_action action) =20 lockdep_assert_preemption_disabled(); =20 - if (WARN_ON_ONCE(vcpu->vcpu_id * sizeof(entry) >=3D PAGE_SIZE)) + if (WARN_ON_ONCE(vcpu->vcpu_id * sizeof(entry) >=3D + PAGE_SIZE << avic_get_physical_id_table_order(vcpu->kvm))) return; =20 /* @@ -1156,8 +1172,13 @@ bool avic_hardware_setup(void) =20 /* AVIC is a prerequisite for x2AVIC. */ x2avic_enabled =3D boot_cpu_has(X86_FEATURE_X2AVIC); - if (x2avic_enabled) - pr_info("x2AVIC enabled\n"); + if (x2avic_enabled) { + if (cpu_feature_enabled(X86_FEATURE_X2AVIC_EXT)) + x2avic_max_physical_id =3D X2AVIC_4K_MAX_PHYSICAL_ID; + else + x2avic_max_physical_id =3D X2AVIC_MAX_PHYSICAL_ID; + pr_info("x2AVIC enabled (max %lld vCPUs)\n", x2avic_max_physical_id + 1); + } =20 /* * Disable IPI virtualization for AMD Family 17h CPUs (Zen1 and Zen2) --=20 2.50.1