From nobody Sat Oct 4 09:38:04 2025 Received: from pegase2.c-s.fr (pegase2.c-s.fr [93.17.235.10]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 640702D7D42; Mon, 18 Aug 2025 09:20:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=93.17.235.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755508843; cv=none; b=jFv2m7qmspVhs4DdNjA3Uv2grW0WgscJSx9N0ewoL5hv9YyKGi0V/lsD9Zh38Li7bn/nOKkcg0ye8xU0boCgxgNjcPJr1Ocz/vQo5XC+TVF+h4XieQQLd3xl9VBCEuY4Y+IC2/cUBhvsAiVPxi9lgmbuc8STI89RM9NnCtyEfC4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755508843; c=relaxed/simple; bh=ES8U2Yx+S0pmkhw2rCUU5KQ7Jju8hSUnIJwJ46d0Jxo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=c2ULPJHNI1VbDUgUqGv9dqDl7KnRq8IkCo/ikfYPhgrTmAu6xeVUanjVeMp2KQW55GhJPjZMzGupSh3UVyO1sUbHPcOPMgPJbAfunPPLoYkTw0mM9B3N7n93idKTm7bc7U9A0M4sAa2vhRAvPuPdQr5lDC+UVadEWOwC91qpLus= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=csgroup.eu; spf=pass smtp.mailfrom=csgroup.eu; arc=none smtp.client-ip=93.17.235.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=csgroup.eu Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=csgroup.eu Received: from localhost (mailhub4.si.c-s.fr [172.26.127.67]) by localhost (Postfix) with ESMTP id 4c55sZ1CVfz9sWq; Mon, 18 Aug 2025 10:46:10 +0200 (CEST) X-Virus-Scanned: amavisd-new at c-s.fr Received: from pegase2.c-s.fr ([172.26.127.65]) by localhost (pegase2.c-s.fr [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 82XmJ-8e-6-P; Mon, 18 Aug 2025 10:46:10 +0200 (CEST) Received: from messagerie.si.c-s.fr (messagerie.si.c-s.fr [192.168.25.192]) by pegase2.c-s.fr (Postfix) with ESMTP id 4c55sY5Dydz9sWh; Mon, 18 Aug 2025 10:46:09 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by messagerie.si.c-s.fr (Postfix) with ESMTP id A0D0E8B765; Mon, 18 Aug 2025 10:46:09 +0200 (CEST) X-Virus-Scanned: amavisd-new at c-s.fr Received: from messagerie.si.c-s.fr ([127.0.0.1]) by localhost (messagerie.si.c-s.fr [127.0.0.1]) (amavisd-new, port 10023) with ESMTP id UF1PVajMXdU5; Mon, 18 Aug 2025 10:46:09 +0200 (CEST) Received: from PO20335.idsi0.si.c-s.fr (unknown [10.25.207.160]) by messagerie.si.c-s.fr (Postfix) with ESMTP id 6D9C48B764; Mon, 18 Aug 2025 10:46:09 +0200 (CEST) From: Christophe Leroy To: Qiang Zhao , Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Christophe Leroy , linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 1/5] soc: fsl: qe: Add an interrupt controller for QUICC Engine Ports Date: Mon, 18 Aug 2025 10:45:54 +0200 Message-ID: <9a0405e10f70f747e75840967ea55193e6c75bb3.1755506608.git.christophe.leroy@csgroup.eu> X-Mailer: git-send-email 2.49.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755506759; l=5277; i=christophe.leroy@csgroup.eu; s=20211009; h=from:subject:message-id; bh=ES8U2Yx+S0pmkhw2rCUU5KQ7Jju8hSUnIJwJ46d0Jxo=; b=yEn3iA7/GSe11JG0mGudkpVm3yiX7e0kIL8k113EotyPIHQjRCrs3JWRP8eldWsHfmenSsIgQ APCpXYy8KMUByRkn1u3bff9krR1OsJVKzqonAyQ4+b8dibYLnBMW5Sa X-Developer-Key: i=christophe.leroy@csgroup.eu; a=ed25519; pk=HIzTzUj91asvincQGOFx6+ZF5AoUuP9GdOtQChs7Mm0= Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The QUICC Engine provides interrupts for a few I/O ports. This is handled via a separate interrupt ID and managed via a triplet of dedicated registers hosted by the SoC. Implement an interrupt driver for it for that those IRQs can then be linked to the related GPIOs. The number of ports for which interrupts are supported depends on the microcontroller: - mpc8323 has 10 interrupts - mpc8360 has 28 interrupts - mpc8568 has 18 interrupts So add this information as data of the compatible. Signed-off-by: Christophe Leroy --- v2: Properly cast (void *) to long instead of int to enable warning-free bu= ild on PPC64 --- drivers/soc/fsl/qe/Makefile | 2 +- drivers/soc/fsl/qe/qe_ports_ic.c | 156 +++++++++++++++++++++++++++++++ 2 files changed, 157 insertions(+), 1 deletion(-) create mode 100644 drivers/soc/fsl/qe/qe_ports_ic.c diff --git a/drivers/soc/fsl/qe/Makefile b/drivers/soc/fsl/qe/Makefile index ec8506e13113..901a9c40d5eb 100644 --- a/drivers/soc/fsl/qe/Makefile +++ b/drivers/soc/fsl/qe/Makefile @@ -11,4 +11,4 @@ obj-$(CONFIG_UCC_SLOW) +=3D ucc_slow.o obj-$(CONFIG_UCC_FAST) +=3D ucc_fast.o obj-$(CONFIG_QE_TDM) +=3D qe_tdm.o obj-$(CONFIG_QE_USB) +=3D usb.o -obj-$(CONFIG_QE_GPIO) +=3D gpio.o +obj-$(CONFIG_QE_GPIO) +=3D gpio.o qe_ports_ic.o diff --git a/drivers/soc/fsl/qe/qe_ports_ic.c b/drivers/soc/fsl/qe/qe_ports= _ic.c new file mode 100644 index 000000000000..9715643d36a6 --- /dev/null +++ b/drivers/soc/fsl/qe/qe_ports_ic.c @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * QUICC ENGINE I/O Ports Interrupt Controller + * + * Copyright (c) 2025 Christophe Leroy CS GROUP France (christophe.leroy@c= sgroup.eu) + */ + +#include +#include +#include + +/* QE IC registers offset */ +#define CEPIER 0x0c +#define CEPIMR 0x10 +#define CEPICR 0x14 + +struct qepic_data { + void __iomem *reg; + struct irq_domain *host; +}; + +static void qepic_mask(struct irq_data *d) +{ + struct qepic_data *data =3D irq_data_get_irq_chip_data(d); + + clrbits32(data->reg + CEPIMR, 1 << (31 - irqd_to_hwirq(d))); +} + +static void qepic_unmask(struct irq_data *d) +{ + struct qepic_data *data =3D irq_data_get_irq_chip_data(d); + + setbits32(data->reg + CEPIMR, 1 << (31 - irqd_to_hwirq(d))); +} + +static void qepic_end(struct irq_data *d) +{ + struct qepic_data *data =3D irq_data_get_irq_chip_data(d); + + out_be32(data->reg + CEPIER, 1 << (31 - irqd_to_hwirq(d))); +} + +static int qepic_set_type(struct irq_data *d, unsigned int flow_type) +{ + struct qepic_data *data =3D irq_data_get_irq_chip_data(d); + unsigned int vec =3D (unsigned int)irqd_to_hwirq(d); + + switch (flow_type & IRQ_TYPE_SENSE_MASK) { + case IRQ_TYPE_EDGE_FALLING: + setbits32(data->reg + CEPICR, 1 << (31 - vec)); + return 0; + case IRQ_TYPE_EDGE_BOTH: + case IRQ_TYPE_NONE: + clrbits32(data->reg + CEPICR, 1 << (31 - vec)); + return 0; + } + return -EINVAL; +} + +static struct irq_chip qepic =3D { + .name =3D "QEPIC", + .irq_mask =3D qepic_mask, + .irq_unmask =3D qepic_unmask, + .irq_eoi =3D qepic_end, + .irq_set_type =3D qepic_set_type, +}; + +static int qepic_get_irq(struct irq_desc *desc) +{ + struct qepic_data *data =3D irq_desc_get_handler_data(desc); + u32 event =3D in_be32(data->reg + CEPIER); + + if (!event) + return -1; + + return irq_find_mapping(data->host, 32 - ffs(event)); +} + +static void qepic_cascade(struct irq_desc *desc) +{ + generic_handle_irq(qepic_get_irq(desc)); +} + +static int qepic_host_map(struct irq_domain *h, unsigned int virq, irq_hw_= number_t hw) +{ + irq_set_chip_data(virq, h->host_data); + irq_set_chip_and_handler(virq, &qepic, handle_fasteoi_irq); + return 0; +} + +static const struct irq_domain_ops qepic_host_ops =3D { + .map =3D qepic_host_map, +}; + +static int qepic_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct qepic_data *data; + unsigned long nb; + int irq; + + nb =3D (unsigned long)of_device_get_match_data(dev); + if (nb < 1 || nb > 32) + return -EINVAL; + + data =3D devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->reg =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(data->reg)) + return PTR_ERR(data->reg); + + irq =3D platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + data->host =3D irq_domain_add_linear(dev->of_node, nb, &qepic_host_ops, d= ata); + if (!data->host) + return -ENODEV; + + irq_set_handler_data(irq, data); + irq_set_chained_handler(irq, qepic_cascade); + + return 0; +} + +static const struct of_device_id qepic_match[] =3D { + { + .compatible =3D "fsl,mpc8323-qe-ports-ic", + .data =3D (void *)10, + }, + { + .compatible =3D "fsl,mpc8360-qe-ports-ic", + .data =3D (void *)28, + }, + { + .compatible =3D "fsl,mpc8568-qe-ports-ic", + .data =3D (void *)18, + }, + {}, +}; + +static struct platform_driver qepic_driver =3D { + .driver =3D { + .name =3D "qe_ports_ic", + .of_match_table =3D qepic_match, + }, + .probe =3D qepic_probe, +}; + +static int __init qepic_init(void) +{ + return platform_driver_register(&qepic_driver); +} +arch_initcall(qepic_init); --=20 2.49.0 From nobody Sat Oct 4 09:38:04 2025 Received: from pegase2.c-s.fr (pegase2.c-s.fr [93.17.235.10]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2AC572D7D42; Mon, 18 Aug 2025 09:20:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=93.17.235.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755508859; cv=none; b=lvqZzQYqkF3i0ZMcglY5FzngrY6g783ASHVNZ+ztqN6IE9ZWkiAUv9yZkAozAJEZHstFKrsQiHYTgMW8cqeHGhMmxUlnHCIiCkbjv6fdNEm1f7WonGmfSzn0bmF8KieaIm+llcGph0WtRZEzY50WJZdETg4Tf3/Ae4P8Yh57CxY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755508859; c=relaxed/simple; bh=1uL2LicwjOlUIYno54f8JBgI5fU0qjg/pfIcjSsv9gk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=fsWGSCn//jdoTSexFplCvFzqHX++t06+pKReqU0f6XFtPbHNCkqj45cu/UruU7ehB2I7Aa1b9hBcHkMRBgVGEB3LzIzGubnaNDe6axmb/fWG9WCIGmujs5qzBZLUox83WMe76Cvf9dQvThoDKalPYgMUZIRum1p1lbLSGUWIw1A= ARC-Authentication-Results: i=1; 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Mon, 18 Aug 2025 10:46:09 +0200 (CEST) X-Virus-Scanned: amavisd-new at c-s.fr Received: from messagerie.si.c-s.fr ([127.0.0.1]) by localhost (messagerie.si.c-s.fr [127.0.0.1]) (amavisd-new, port 10023) with ESMTP id mZjBc2RFevRD; Mon, 18 Aug 2025 10:46:09 +0200 (CEST) Received: from PO20335.idsi0.si.c-s.fr (unknown [10.25.207.160]) by messagerie.si.c-s.fr (Postfix) with ESMTP id 8D79A8B763; Mon, 18 Aug 2025 10:46:09 +0200 (CEST) From: Christophe Leroy To: Qiang Zhao , Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Christophe Leroy , linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, Bartosz Golaszewski Subject: [PATCH v2 2/5] soc: fsl: qe: Change GPIO driver to a proper platform driver Date: Mon, 18 Aug 2025 10:45:55 +0200 Message-ID: <0f534668e05631c9786c9d0382af470daeedecfd.1755506608.git.christophe.leroy@csgroup.eu> X-Mailer: git-send-email 2.49.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755506759; l=3217; i=christophe.leroy@csgroup.eu; s=20211009; h=from:subject:message-id; bh=1uL2LicwjOlUIYno54f8JBgI5fU0qjg/pfIcjSsv9gk=; b=a3iAS5SgWnFLGYzcAQP1Hs3aUPLiJ9Kb6EOXH0JUUnDSmJHxVLljVaQVp+INS8wdONuBiGT33 T7zp17hda7cDS7eaYSg9UP/mTKJg2K6761bTFD7ruRa5i7O145Kk9AO X-Developer-Key: i=christophe.leroy@csgroup.eu; a=ed25519; pk=HIzTzUj91asvincQGOFx6+ZF5AoUuP9GdOtQChs7Mm0= Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In order to be able to add interrupts to the GPIOs, first change the QE GPIO driver to the proper platform driver in order to allow initialisation to be done in the right order, otherwise the GPIOs get added before the interrupts are registered. Signed-off-by: Christophe Leroy Reviewed-by: Bartosz Golaszewski --- v2: Use devm_kzalloc() instead of kzalloc() --- drivers/soc/fsl/qe/gpio.c | 86 +++++++++++++++++++++------------------ 1 file changed, 47 insertions(+), 39 deletions(-) diff --git a/drivers/soc/fsl/qe/gpio.c b/drivers/soc/fsl/qe/gpio.c index 8df1e8fa86a5..93fcc6d85ac7 100644 --- a/drivers/soc/fsl/qe/gpio.c +++ b/drivers/soc/fsl/qe/gpio.c @@ -19,6 +19,7 @@ #include #include #include +#include =20 #include =20 @@ -295,45 +296,52 @@ void qe_pin_set_gpio(struct qe_pin *qe_pin) } EXPORT_SYMBOL(qe_pin_set_gpio); =20 -static int __init qe_add_gpiochips(void) +static int qe_gpio_probe(struct platform_device *ofdev) { - struct device_node *np; - - for_each_compatible_node(np, NULL, "fsl,mpc8323-qe-pario-bank") { - int ret; - struct qe_gpio_chip *qe_gc; - struct of_mm_gpio_chip *mm_gc; - struct gpio_chip *gc; - - qe_gc =3D kzalloc(sizeof(*qe_gc), GFP_KERNEL); - if (!qe_gc) { - ret =3D -ENOMEM; - goto err; - } + struct device *dev =3D &ofdev->dev; + struct device_node *np =3D dev->of_node; + struct qe_gpio_chip *qe_gc; + struct of_mm_gpio_chip *mm_gc; + struct gpio_chip *gc; =20 - spin_lock_init(&qe_gc->lock); - - mm_gc =3D &qe_gc->mm_gc; - gc =3D &mm_gc->gc; - - mm_gc->save_regs =3D qe_gpio_save_regs; - gc->ngpio =3D QE_PIO_PINS; - gc->direction_input =3D qe_gpio_dir_in; - gc->direction_output =3D qe_gpio_dir_out; - gc->get =3D qe_gpio_get; - gc->set =3D qe_gpio_set; - gc->set_multiple =3D qe_gpio_set_multiple; - - ret =3D of_mm_gpiochip_add_data(np, mm_gc, qe_gc); - if (ret) - goto err; - continue; -err: - pr_err("%pOF: registration failed with status %d\n", - np, ret); - kfree(qe_gc); - /* try others anyway */ - } - return 0; + qe_gc =3D devm_kzalloc(dev, sizeof(*qe_gc), GFP_KERNEL); + if (!qe_gc) + return -ENOMEM; + + spin_lock_init(&qe_gc->lock); + + mm_gc =3D &qe_gc->mm_gc; + gc =3D &mm_gc->gc; + + mm_gc->save_regs =3D qe_gpio_save_regs; + gc->ngpio =3D QE_PIO_PINS; + gc->direction_input =3D qe_gpio_dir_in; + gc->direction_output =3D qe_gpio_dir_out; + gc->get =3D qe_gpio_get; + gc->set =3D qe_gpio_set; + gc->set_multiple =3D qe_gpio_set_multiple; + + return of_mm_gpiochip_add_data(np, mm_gc, qe_gc); +} + +static const struct of_device_id qe_gpio_match[] =3D { + { + .compatible =3D "fsl,mpc8323-qe-pario-bank", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, qe_gpio_match); + +static struct platform_driver qe_gpio_driver =3D { + .probe =3D qe_gpio_probe, + .driver =3D { + .name =3D "qe-gpio", + .of_match_table =3D qe_gpio_match, + }, +}; + +static int __init qe_gpio_init(void) +{ + return platform_driver_register(&qe_gpio_driver); } -arch_initcall(qe_add_gpiochips); +arch_initcall(qe_gpio_init); --=20 2.49.0 From nobody Sat Oct 4 09:38:04 2025 Received: from pegase2.c-s.fr (pegase2.c-s.fr [93.17.235.10]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E4D282D7D42; Mon, 18 Aug 2025 09:20:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=93.17.235.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Mon, 18 Aug 2025 10:46:12 +0200 (CEST) X-Virus-Scanned: amavisd-new at c-s.fr Received: from pegase2.c-s.fr ([172.26.127.65]) by localhost (pegase2.c-s.fr [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 5yhzdcCd9cYr; Mon, 18 Aug 2025 10:46:12 +0200 (CEST) Received: from messagerie.si.c-s.fr (messagerie.si.c-s.fr [192.168.25.192]) by pegase2.c-s.fr (Postfix) with ESMTP id 4c55sZ07nwz9sWm; Mon, 18 Aug 2025 10:46:10 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by messagerie.si.c-s.fr (Postfix) with ESMTP id E2A588B765; Mon, 18 Aug 2025 10:46:09 +0200 (CEST) X-Virus-Scanned: amavisd-new at c-s.fr Received: from messagerie.si.c-s.fr ([127.0.0.1]) by localhost (messagerie.si.c-s.fr [127.0.0.1]) (amavisd-new, port 10023) with ESMTP id vns69XugoAlV; Mon, 18 Aug 2025 10:46:09 +0200 (CEST) Received: from PO20335.idsi0.si.c-s.fr (unknown [10.25.207.160]) by messagerie.si.c-s.fr (Postfix) with ESMTP id AFEEF8B764; Mon, 18 Aug 2025 10:46:09 +0200 (CEST) From: Christophe Leroy To: Qiang Zhao , Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Christophe Leroy , linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 3/5] soc: fsl: qe: Drop legacy-of-mm-gpiochip.h header from GPIO driver Date: Mon, 18 Aug 2025 10:45:56 +0200 Message-ID: X-Mailer: git-send-email 2.49.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755506759; l=7343; i=christophe.leroy@csgroup.eu; s=20211009; h=from:subject:message-id; bh=71KPdI4+YFoLm/OfDlnRkk1s5xf+3TgUC7cT9RMRHUM=; b=uLPKXf9NshSiWxr6TU/TtnUKKebgXkRyN2MxNbWt7oMRNnZJNZ08ev4AXPWTa3SwmAwFMervp iJhwzk0GN49BE+t4v0u0UDf53h0vc4dJRBybudsYRBREJNV9K81yyCz X-Developer-Key: i=christophe.leroy@csgroup.eu; a=ed25519; pk=HIzTzUj91asvincQGOFx6+ZF5AoUuP9GdOtQChs7Mm0= Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Remove legacy-of-mm-gpiochip.h header file. The above mentioned file provides an OF API that's deprecated. There is no agnostic alternatives to it and we have to open code the logic which was hidden behind of_mm_gpiochip_add_data(). Note, most of the GPIO drivers are using their own labeling schemas and resource retrieval that only a few may gain of the code deduplication, so whenever alternative is appear we can move drivers again to use that one. As a side effect this change fixes a potential memory leak on an error path, if of_mm_gpiochip_add_data() fails. [Text copied from commit 34064c8267a6 ("powerpc/8xx: Drop legacy-of-mm-gpiochip.h header")] Suggested-by: Bartosz Golaszewski Signed-off-by: Christophe Leroy --- v2: New --- arch/powerpc/platforms/Kconfig | 1 - drivers/soc/fsl/qe/gpio.c | 51 ++++++++++++++++++---------------- 2 files changed, 27 insertions(+), 25 deletions(-) diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig index fea3766eac0f..5b689bd3ddf4 100644 --- a/arch/powerpc/platforms/Kconfig +++ b/arch/powerpc/platforms/Kconfig @@ -232,7 +232,6 @@ config QE_GPIO bool "QE GPIO support" depends on QUICC_ENGINE select GPIOLIB - select OF_GPIO_MM_GPIOCHIP help Say Y here if you're going to use hardware that connects to the QE GPIOs. diff --git a/drivers/soc/fsl/qe/gpio.c b/drivers/soc/fsl/qe/gpio.c index 93fcc6d85ac7..a338469cebe4 100644 --- a/drivers/soc/fsl/qe/gpio.c +++ b/drivers/soc/fsl/qe/gpio.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include @@ -24,7 +23,8 @@ #include =20 struct qe_gpio_chip { - struct of_mm_gpio_chip mm_gc; + struct gpio_chip gc; + void __iomem *regs; spinlock_t lock; =20 /* shadowed data register to clear/set bits safely */ @@ -34,11 +34,9 @@ struct qe_gpio_chip { struct qe_pio_regs saved_regs; }; =20 -static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_gc) +static void qe_gpio_save_regs(struct qe_gpio_chip *qe_gc) { - struct qe_gpio_chip *qe_gc =3D - container_of(mm_gc, struct qe_gpio_chip, mm_gc); - struct qe_pio_regs __iomem *regs =3D mm_gc->regs; + struct qe_pio_regs __iomem *regs =3D qe_gc->regs; =20 qe_gc->cpdata =3D ioread32be(®s->cpdata); qe_gc->saved_regs.cpdata =3D qe_gc->cpdata; @@ -51,8 +49,8 @@ static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_= gc) =20 static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio) { - struct of_mm_gpio_chip *mm_gc =3D to_of_mm_gpio_chip(gc); - struct qe_pio_regs __iomem *regs =3D mm_gc->regs; + struct qe_gpio_chip *qe_gc =3D gpiochip_get_data(gc); + struct qe_pio_regs __iomem *regs =3D qe_gc->regs; u32 pin_mask =3D 1 << (QE_PIO_PINS - 1 - gpio); =20 return !!(ioread32be(®s->cpdata) & pin_mask); @@ -60,9 +58,8 @@ static int qe_gpio_get(struct gpio_chip *gc, unsigned int= gpio) =20 static int qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) { - struct of_mm_gpio_chip *mm_gc =3D to_of_mm_gpio_chip(gc); struct qe_gpio_chip *qe_gc =3D gpiochip_get_data(gc); - struct qe_pio_regs __iomem *regs =3D mm_gc->regs; + struct qe_pio_regs __iomem *regs =3D qe_gc->regs; unsigned long flags; u32 pin_mask =3D 1 << (QE_PIO_PINS - 1 - gpio); =20 @@ -83,9 +80,8 @@ static int qe_gpio_set(struct gpio_chip *gc, unsigned int= gpio, int val) static int qe_gpio_set_multiple(struct gpio_chip *gc, unsigned long *mask, unsigned long *bits) { - struct of_mm_gpio_chip *mm_gc =3D to_of_mm_gpio_chip(gc); struct qe_gpio_chip *qe_gc =3D gpiochip_get_data(gc); - struct qe_pio_regs __iomem *regs =3D mm_gc->regs; + struct qe_pio_regs __iomem *regs =3D qe_gc->regs; unsigned long flags; int i; =20 @@ -111,13 +107,12 @@ static int qe_gpio_set_multiple(struct gpio_chip *gc, =20 static int qe_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio) { - struct of_mm_gpio_chip *mm_gc =3D to_of_mm_gpio_chip(gc); struct qe_gpio_chip *qe_gc =3D gpiochip_get_data(gc); unsigned long flags; =20 spin_lock_irqsave(&qe_gc->lock, flags); =20 - __par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_IN, 0, 0, 0); + __par_io_config_pin(qe_gc->regs, gpio, QE_PIO_DIR_IN, 0, 0, 0); =20 spin_unlock_irqrestore(&qe_gc->lock, flags); =20 @@ -126,7 +121,6 @@ static int qe_gpio_dir_in(struct gpio_chip *gc, unsigne= d int gpio) =20 static int qe_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int va= l) { - struct of_mm_gpio_chip *mm_gc =3D to_of_mm_gpio_chip(gc); struct qe_gpio_chip *qe_gc =3D gpiochip_get_data(gc); unsigned long flags; =20 @@ -134,7 +128,7 @@ static int qe_gpio_dir_out(struct gpio_chip *gc, unsign= ed int gpio, int val) =20 spin_lock_irqsave(&qe_gc->lock, flags); =20 - __par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_OUT, 0, 0, 0); + __par_io_config_pin(qe_gc->regs, gpio, QE_PIO_DIR_OUT, 0, 0, 0); =20 spin_unlock_irqrestore(&qe_gc->lock, flags); =20 @@ -240,7 +234,7 @@ EXPORT_SYMBOL(qe_pin_free); void qe_pin_set_dedicated(struct qe_pin *qe_pin) { struct qe_gpio_chip *qe_gc =3D qe_pin->controller; - struct qe_pio_regs __iomem *regs =3D qe_gc->mm_gc.regs; + struct qe_pio_regs __iomem *regs =3D qe_gc->regs; struct qe_pio_regs *sregs =3D &qe_gc->saved_regs; int pin =3D qe_pin->num; u32 mask1 =3D 1 << (QE_PIO_PINS - (pin + 1)); @@ -269,7 +263,6 @@ void qe_pin_set_dedicated(struct qe_pin *qe_pin) =20 iowrite32be(qe_gc->cpdata, ®s->cpdata); qe_clrsetbits_be32(®s->cpodr, mask1, sregs->cpodr & mask1); - spin_unlock_irqrestore(&qe_gc->lock, flags); } EXPORT_SYMBOL(qe_pin_set_dedicated); @@ -284,7 +277,7 @@ EXPORT_SYMBOL(qe_pin_set_dedicated); void qe_pin_set_gpio(struct qe_pin *qe_pin) { struct qe_gpio_chip *qe_gc =3D qe_pin->controller; - struct qe_pio_regs __iomem *regs =3D qe_gc->mm_gc.regs; + struct qe_pio_regs __iomem *regs =3D qe_gc->regs; unsigned long flags; =20 spin_lock_irqsave(&qe_gc->lock, flags); @@ -301,7 +294,6 @@ static int qe_gpio_probe(struct platform_device *ofdev) struct device *dev =3D &ofdev->dev; struct device_node *np =3D dev->of_node; struct qe_gpio_chip *qe_gc; - struct of_mm_gpio_chip *mm_gc; struct gpio_chip *gc; =20 qe_gc =3D devm_kzalloc(dev, sizeof(*qe_gc), GFP_KERNEL); @@ -310,18 +302,29 @@ static int qe_gpio_probe(struct platform_device *ofde= v) =20 spin_lock_init(&qe_gc->lock); =20 - mm_gc =3D &qe_gc->mm_gc; - gc =3D &mm_gc->gc; + gc =3D &qe_gc->gc; =20 - mm_gc->save_regs =3D qe_gpio_save_regs; + gc->base =3D -1; gc->ngpio =3D QE_PIO_PINS; gc->direction_input =3D qe_gpio_dir_in; gc->direction_output =3D qe_gpio_dir_out; gc->get =3D qe_gpio_get; gc->set =3D qe_gpio_set; gc->set_multiple =3D qe_gpio_set_multiple; + gc->parent =3D dev; + gc->owner =3D THIS_MODULE; + + gc->label =3D devm_kasprintf(dev, GFP_KERNEL, "%pOF", np); + if (!gc->label) + return -ENOMEM; + + qe_gc->regs =3D devm_of_iomap(dev, np, 0, NULL); + if (IS_ERR(qe_gc->regs)) + return PTR_ERR(qe_gc->regs); + + qe_gpio_save_regs(qe_gc); =20 - return of_mm_gpiochip_add_data(np, mm_gc, qe_gc); + return devm_gpiochip_add_data(dev, gc, qe_gc); } =20 static const struct of_device_id qe_gpio_match[] =3D { --=20 2.49.0 From nobody Sat Oct 4 09:38:04 2025 Received: from pegase2.c-s.fr (pegase2.c-s.fr [93.17.235.10]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E30692D7D42; Mon, 18 Aug 2025 09:20:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=93.17.235.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755508855; cv=none; b=Fpw4s6If237wLFpbW2NutRGI868X2JFlBXRJQdhafVoaFdtTCi2WqeCPeaoaJMdXNanQk31zcHTeuoAPAp+mYc7zzfqZ60mXuVkpt6BRpgtxkH4q91VnoIPwPHqJDPsR43mHBTqW8NI7hqlWCadlWNYyEQRi89PSjdhHYAZT3x0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755508855; c=relaxed/simple; bh=KAXI/UdG1uKmQEqjT0xzFF6ZLrXwXMHk7giEW1/cpwI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=iCwZqQZn0QgEghEM2vrUfU9VC7JfawFGnyB9gYE7i6xTYnuqzgghZ+VH8ez61+EzjWnfkXj7HaZ8o3lUi1XRD8H6M9BXa02u+BM77VaaNztkkNANueneyPJHJbtQT35SvtOHbramZGudEoc0CmTGKOIsoJpkcoaamd/PX9jF/qc= ARC-Authentication-Results: i=1; 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Mon, 18 Aug 2025 10:46:10 +0200 (CEST) X-Virus-Scanned: amavisd-new at c-s.fr Received: from messagerie.si.c-s.fr ([127.0.0.1]) by localhost (messagerie.si.c-s.fr [127.0.0.1]) (amavisd-new, port 10023) with ESMTP id YFmZUm584ZmT; Mon, 18 Aug 2025 10:46:09 +0200 (CEST) Received: from PO20335.idsi0.si.c-s.fr (unknown [10.25.207.160]) by messagerie.si.c-s.fr (Postfix) with ESMTP id CF60C8B763; Mon, 18 Aug 2025 10:46:09 +0200 (CEST) From: Christophe Leroy To: Qiang Zhao , Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Christophe Leroy , linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 4/5] soc: fsl: qe: Add support of IRQ in QE GPIO Date: Mon, 18 Aug 2025 10:45:57 +0200 Message-ID: X-Mailer: git-send-email 2.49.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755506759; l=4414; i=christophe.leroy@csgroup.eu; s=20211009; h=from:subject:message-id; bh=KAXI/UdG1uKmQEqjT0xzFF6ZLrXwXMHk7giEW1/cpwI=; b=MW/ze3K9TK2iL0/rORULbghAvqryKWrfqy6TLbLvD5VVeZnLqeWtR7lBIzwSXSaoZHM8JT18w /wsaAaaP1BTDABTihOHtotOGJXdkcCKIOkhkfqAHIOgpIegdhqYENi+ X-Developer-Key: i=christophe.leroy@csgroup.eu; a=ed25519; pk=HIzTzUj91asvincQGOFx6+ZF5AoUuP9GdOtQChs7Mm0= Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In the QE, a few GPIOs are IRQ capable. Similarly to commit 726bd223105c ("powerpc/8xx: Adding support of IRQ in MPC8xx GPIO"), add IRQ support to QE GPIO. Add property 'fsl,qe-gpio-irq-mask' similar to 'fsl,cpm1-gpio-irq-mask' that define which of the GPIOs have IRQs. Here is an exemple for port B of mpc8323 which has IRQs for GPIOs PB7, PB9, PB25 and PB27. qe_pio_b: gpio-controller@1418 { #gpio-cells =3D <2>; compatible =3D "fsl,mpc8323-qe-pario-bank"; reg =3D <0x1418 0x18>; interrupts =3D <4 5 6 7>; fsl,qe-gpio-irq-mask =3D <0x01400050>; interrupt-parent =3D <&qepic>; gpio-controller; }; Signed-off-by: Christophe Leroy --- v2: Document fsl,qe-gpio-irq-mask --- .../bindings/soc/fsl/cpm_qe/qe/par_io.txt | 19 ++++++++++++++++++ drivers/soc/fsl/qe/gpio.c | 20 +++++++++++++++++++ 2 files changed, 39 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/par_io.txt= b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/par_io.txt index 09b1b05fa677..9cd6e5ac2a7b 100644 --- a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/par_io.txt +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/par_io.txt @@ -32,6 +32,15 @@ Required properties: "fsl,mpc8323-qe-pario-bank". - reg : offset to the register set and its length. - gpio-controller : node to identify gpio controllers. +Optional properties: +- fsl,qe-gpio-irq-mask : For banks having interrupt capability this item t= ells + which ports have an associated interrupt (ports are listed in the same o= rder + QE ports registers) +- interrupts : This property provides the list of interrupt for each GPIO = having + one as described by the fsl,cpm1-gpio-irq-mask property. There should be= as + many interrupts as number of ones in the mask property. The first interr= upt in + the list corresponds to the most significant bit of the mask. +- interrupt-parent : Parent for the above interrupt property. =20 Example: qe_pio_a: gpio-controller@1400 { @@ -42,6 +51,16 @@ Example: gpio-controller; }; =20 + qe_pio_b: gpio-controller@1418 { + #gpio-cells =3D <2>; + compatible =3D "fsl,mpc8323-qe-pario-bank"; + reg =3D <0x1418 0x18>; + interrupts =3D <4 5 6 7>; + fsl,qe-gpio-irq-mask =3D <0x01400050>; + interrupt-parent =3D <&qepic>; + gpio-controller; + }; + qe_pio_e: gpio-controller@1460 { #gpio-cells =3D <2>; compatible =3D "fsl,mpc8360-qe-pario-bank", diff --git a/drivers/soc/fsl/qe/gpio.c b/drivers/soc/fsl/qe/gpio.c index a338469cebe4..91d469403126 100644 --- a/drivers/soc/fsl/qe/gpio.c +++ b/drivers/soc/fsl/qe/gpio.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -32,6 +33,8 @@ struct qe_gpio_chip { =20 /* saved_regs used to restore dedicated functions */ struct qe_pio_regs saved_regs; + + int irq[32]; }; =20 static void qe_gpio_save_regs(struct qe_gpio_chip *qe_gc) @@ -135,6 +138,13 @@ static int qe_gpio_dir_out(struct gpio_chip *gc, unsig= ned int gpio, int val) return 0; } =20 +static int qe_gpio_to_irq(struct gpio_chip *gc, unsigned int gpio) +{ + struct qe_gpio_chip *qe_gc =3D gpiochip_get_data(gc); + + return qe_gc->irq[gpio] ? : -ENXIO; +} + struct qe_pin { /* * The qe_gpio_chip name is unfortunate, we should change that to @@ -295,6 +305,7 @@ static int qe_gpio_probe(struct platform_device *ofdev) struct device_node *np =3D dev->of_node; struct qe_gpio_chip *qe_gc; struct gpio_chip *gc; + u32 mask; =20 qe_gc =3D devm_kzalloc(dev, sizeof(*qe_gc), GFP_KERNEL); if (!qe_gc) @@ -302,6 +313,14 @@ static int qe_gpio_probe(struct platform_device *ofdev) =20 spin_lock_init(&qe_gc->lock); =20 + if (!of_property_read_u32(np, "fsl,qe-gpio-irq-mask", &mask)) { + int i, j; + + for (i =3D 0, j =3D 0; i < ARRAY_SIZE(qe_gc->irq); i++) + if (mask & (1 << (31 - i))) + qe_gc->irq[i] =3D irq_of_parse_and_map(np, j++); + } + gc =3D &qe_gc->gc; =20 gc->base =3D -1; @@ -311,6 +330,7 @@ static int qe_gpio_probe(struct platform_device *ofdev) gc->get =3D qe_gpio_get; gc->set =3D qe_gpio_set; gc->set_multiple =3D qe_gpio_set_multiple; + gc->to_irq =3D qe_gpio_to_irq; gc->parent =3D dev; gc->owner =3D THIS_MODULE; =20 --=20 2.49.0 From nobody Sat Oct 4 09:38:04 2025 Received: from pegase2.c-s.fr (pegase2.c-s.fr [93.17.235.10]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C5E372D7D42; Mon, 18 Aug 2025 09:20:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=93.17.235.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755508847; cv=none; b=TOqprEdY7ZJOxt12EVKmpZspLSSCzlYO7/IWNyKnPK+IQV98KuaWpwCzIs/oIgquQ/FczJaTIYGJQmoQYqffMny3aabYNwqwfljPiD9Q40aCy5ne7DWlXCRhvNHr4SeNkbOkNsEL2KbHMqyBYunD4pf6ubGb1CCGtFCBtKAxDAo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755508847; c=relaxed/simple; bh=FsJjFzo97CaIj8ecmEYrlheS4JZRtCwCquhmLdyFc7U=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=XqkU5ePIkXtFKyOwIEFPyMXmJb5ykZRPnfMoGJHEMFLQaSFTtonEkMFwINQCoVMdownpSzatzBBua7JkJA9mLBengS4GzCwv8mrZ3rprMVtsxcCemkaVHUzAtJwy7Q3x0zxmywO7K3TQt/n+OKTgaY2Wa3SLgMAUN1fKJHbpkzY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=csgroup.eu; spf=pass smtp.mailfrom=csgroup.eu; arc=none smtp.client-ip=93.17.235.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=csgroup.eu Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=csgroup.eu Received: from localhost (mailhub4.si.c-s.fr [172.26.127.67]) by localhost (Postfix) with ESMTP id 4c55sf33SKz9sX4; Mon, 18 Aug 2025 10:46:14 +0200 (CEST) X-Virus-Scanned: amavisd-new at c-s.fr Received: from pegase2.c-s.fr ([172.26.127.65]) by localhost (pegase2.c-s.fr [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id rx4zHsvHPdak; Mon, 18 Aug 2025 10:46:14 +0200 (CEST) Received: from messagerie.si.c-s.fr (messagerie.si.c-s.fr [192.168.25.192]) by pegase2.c-s.fr (Postfix) with ESMTP id 4c55sZ1ZzKz9sWh; Mon, 18 Aug 2025 10:46:10 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by messagerie.si.c-s.fr (Postfix) with ESMTP id 217968B763; Mon, 18 Aug 2025 10:46:10 +0200 (CEST) X-Virus-Scanned: amavisd-new at c-s.fr Received: from messagerie.si.c-s.fr ([127.0.0.1]) by localhost (messagerie.si.c-s.fr [127.0.0.1]) (amavisd-new, port 10023) with ESMTP id giALWGHkvImb; Mon, 18 Aug 2025 10:46:10 +0200 (CEST) Received: from PO20335.idsi0.si.c-s.fr (unknown [10.25.207.160]) by messagerie.si.c-s.fr (Postfix) with ESMTP id EDCBB8B764; Mon, 18 Aug 2025 10:46:09 +0200 (CEST) From: Christophe Leroy To: Qiang Zhao , Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Christophe Leroy , linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 5/5] dt-bindings: soc: fsl: qe: Add an interrupt controller for QUICC Engine Ports Date: Mon, 18 Aug 2025 10:45:58 +0200 Message-ID: X-Mailer: git-send-email 2.49.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755506759; l=2392; i=christophe.leroy@csgroup.eu; s=20211009; h=from:subject:message-id; bh=FsJjFzo97CaIj8ecmEYrlheS4JZRtCwCquhmLdyFc7U=; b=hFHnrqREIMbLuXYAIGjkJ3D28meiD7b8MHSCYawlfY+LlUHthVv1wORv0SDpFEM2Ka+xgcy44 ih8BI2ai0K2Dpx8Wvzs9qmU5X2t5EZKhQym3hoV6sJGw8lmJpxLC2XS X-Developer-Key: i=christophe.leroy@csgroup.eu; a=ed25519; pk=HIzTzUj91asvincQGOFx6+ZF5AoUuP9GdOtQChs7Mm0= Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The QUICC Engine provides interrupts for a few I/O ports. This is handled via a separate interrupt ID and managed via a triplet of dedicated registers hosted by the SoC. Implement an interrupt driver for it for that those IRQs can then be linked to the related GPIOs. Signed-off-by: Christophe Leroy Acked-by: Conor Dooley --- v2: Fixed problems reported by 'make dt_binding_check' --- .../soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe= -ports-ic.yaml diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-= ic.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-ic.= yaml new file mode 100644 index 000000000000..b7c74c66347c --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale QUICC Engine I/O Ports Interrupt Controller + +maintainers: + - Christophe Leroy + +description: + Interrupt controller for the QUICC Engine I/O ports found on some Freesc= ale/NXP PowerQUICC and QorIQ SoCs. + +properties: + compatible: + enum: + - fsl,mpc8323-qe-ports-ic + - fsl,mpc8360-qe-ports-ic + - fsl,mpc8568-qe-ports-ic + + reg: + maxItems: 1 + description: Base address and size of the QE I/O Ports Interrupt Contr= oller registers. + + interrupt-controller: true + + '#address-cells': + const: 0 + + '#interrupt-cells': + const: 1 + + interrupts: + maxItems: 1 + description: Interrupt line to which the QE I/O Ports controller is co= nnected. + +required: + - compatible + - reg + - interrupt-controller + - '#address-cells' + - '#interrupt-cells' + - interrupts + +additionalProperties: false + +examples: + - | + interrupt-controller@c00 { + interrupt-controller; + compatible =3D "fsl,mpc8323-qe-ports-ic"; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + reg =3D <0xc00 0x18>; + interrupts =3D <74 0x8>; + interrupt-parent =3D <&ipic>; + }; --=20 2.49.0