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Sat, 16 Aug 2025 03:47:06 -0700 (PDT) From: Ciprian Costea X-Google-Original-From: Ciprian Costea Date: Sat, 16 Aug 2025 13:47:03 +0300 To: Srinivas Kandagatla Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ciprian Costea , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linaro-s32@linaro.org, NXP S32 Linux Team , Srinivas Kandagatla Subject: [PATCH 1/3] dt-bindings: nvmem: Add the nxp,s32g-ocotp yaml file Message-ID: <7d0e025ed3fdc9e545f1d0b84f6a1cbb9dfb4e91.1755341000.git.dan.carpenter@linaro.org> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add bindings to expose the On Chip One-Time Programmable Controller (OCOTP) for the NXP s32g chipset. There are three versions of this chip but they're compatible so we can fall back to the nxp,s32g2-ocotp compatible. Signed-off-by: Ciprian Costea Signed-off-by: Dan Carpenter --- .../bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml | 57 +++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100644 Documentation/devicetree/bindings/nvmem/nxp,s32g-ocotp-= nvmem.yaml diff --git a/Documentation/devicetree/bindings/nvmem/nxp,s32g-ocotp-nvmem.y= aml b/Documentation/devicetree/bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml new file mode 100644 index 000000000000..19f3bb6b7eb0 --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/nxp,s32g-ocotp-nvmem.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP S32G OCOTP NVMEM driver + +maintainers: + - Ciprian Costea + +description: | + The drivers provides an interface to access One Time + Programmable memory pages, such as TMU fuse values. + +allOf: + - $ref: nvmem.yaml# + +properties: + compatible: + oneOf: + - items: + - enum: + - nxp,s32g3-ocotp + - nxp,s32r45-ocotp + - const: nxp,s32g2-ocotp + + reg: + description: + Address and Size of the fuse bank to be read. + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + +required: + - compatible + - reg + - '#address-cells' + - '#size-cells' + +unevaluatedProperties: false + +examples: + - | + #include + + ocotp: ocotp@400a4000 { + compatible =3D "nxp,s32g2-ocotp"; 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Sat, 16 Aug 2025 03:47:11 -0700 (PDT) From: Ciprian Costea X-Google-Original-From: Ciprian Costea Date: Sat, 16 Aug 2025 13:47:08 +0300 To: Srinivas Kandagatla Cc: linaro-s32@linaro.org, NXP S32 Linux Team , linux-kernel@vger.kernel.org Subject: [PATCH 2/3] nvmem: s32g-ocotp: Add driver for S32G OCOTP Message-ID: <7e1f16bf09e77afef4cc5fa609a6c3ad820bb14c.1755341000.git.dan.carpenter@linaro.org> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Provide access to the On Chip One-Time Programmable Controller (OCOTP) pages on the NXP S32G platform. Signed-off-by: Ciprian Costea Co-developed-by: Ghennadi Procopciuc Co-developed-by: Larisa Grigore Signed-off-by: Dan Carpenter --- drivers/nvmem/Kconfig | 10 ++ drivers/nvmem/Makefile | 2 + drivers/nvmem/s32g-ocotp-nvmem.c | 171 +++++++++++++++++++++++++++++++ 3 files changed, 183 insertions(+) create mode 100644 drivers/nvmem/s32g-ocotp-nvmem.c diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig index edd811444ce5..6a1cafa74e36 100644 --- a/drivers/nvmem/Kconfig +++ b/drivers/nvmem/Kconfig @@ -314,6 +314,16 @@ config NVMEM_ROCKCHIP_OTP This driver can also be built as a module. If so, the module will be called nvmem_rockchip_otp. =20 +config NVMEM_S32G_OCOTP + tristate "S32G SoC OCOTP support" + depends on ARCH_S32 + help + This is a driver for the On Chip One-Time Programmable controller + (OCOTP) available on S32G platforms. + + If you say Y here, you will get support for the One Time + Programmable memory pages. + config NVMEM_SC27XX_EFUSE tristate "Spreadtrum SC27XX eFuse Support" depends on MFD_SC27XX_PMIC || COMPILE_TEST diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile index 2021d59688db..b7bfa78af8f3 100644 --- a/drivers/nvmem/Makefile +++ b/drivers/nvmem/Makefile @@ -64,6 +64,8 @@ obj-$(CONFIG_NVMEM_ROCKCHIP_EFUSE) +=3D nvmem_rockchip_ef= use.o nvmem_rockchip_efuse-y :=3D rockchip-efuse.o obj-$(CONFIG_NVMEM_ROCKCHIP_OTP) +=3D nvmem-rockchip-otp.o nvmem-rockchip-otp-y :=3D rockchip-otp.o +obj-$(CONFIG_NVMEM_S32G_OCOTP) +=3D nvmem-s32g-ocotp-nvmem.o +nvmem-s32g-ocotp-nvmem-y :=3D s32g-ocotp-nvmem.o obj-$(CONFIG_NVMEM_SC27XX_EFUSE) +=3D nvmem-sc27xx-efuse.o nvmem-sc27xx-efuse-y :=3D sc27xx-efuse.o obj-$(CONFIG_NVMEM_SNVS_LPGPR) +=3D nvmem_snvs_lpgpr.o diff --git a/drivers/nvmem/s32g-ocotp-nvmem.c b/drivers/nvmem/s32g-ocotp-nv= mem.c new file mode 100644 index 000000000000..37355bd83b17 --- /dev/null +++ b/drivers/nvmem/s32g-ocotp-nvmem.c @@ -0,0 +1,171 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2023-2025 NXP + */ + +#include +#include +#include +#include +#include +#include +#include + +#define S32G_OCOTP_BANK_OFFSET 512u +#define S32G_OCOTP_BANK_SIZE 32u +#define S32G_OCOTP_WORD_SIZE 4u + +struct s32g_fuse { + u8 bank; + u8 words_mask; +}; + +struct s32g_fuse_map { + const struct s32g_fuse *map; + size_t n_entries; +}; + +struct s32g_ocotp_priv { + struct device *dev; + void __iomem *base; + const struct s32g_fuse_map *fuse; +}; + +static const struct s32g_fuse s32g_map[] =3D { + { .bank =3D 0, .words_mask =3D GENMASK(6, 2) }, + { .bank =3D 1, .words_mask =3D GENMASK(7, 5) }, + { .bank =3D 2, .words_mask =3D GENMASK(1, 0) }, + { .bank =3D 2, .words_mask =3D GENMASK(4, 2) }, + { .bank =3D 4, .words_mask =3D BIT(6) }, + { .bank =3D 5, .words_mask =3D BIT(1) }, + { .bank =3D 5, .words_mask =3D BIT(2) }, + { .bank =3D 6, .words_mask =3D BIT(7) }, + { .bank =3D 7, .words_mask =3D GENMASK(1, 0) }, + { .bank =3D 11, .words_mask =3D GENMASK(5, 0) }, + { .bank =3D 11, .words_mask =3D GENMASK(7, 6) }, + { .bank =3D 12, .words_mask =3D GENMASK(2, 0) }, + { .bank =3D 12, .words_mask =3D BIT(7) }, + { .bank =3D 13, .words_mask =3D GENMASK(4, 2) }, + { .bank =3D 14, .words_mask =3D BIT(1) | BIT(4) | BIT(5) }, + { .bank =3D 15, .words_mask =3D GENMASK(7, 5) }, +}; + +static const struct s32g_fuse_map s32g_fuse_map =3D { + .map =3D s32g_map, + .n_entries =3D ARRAY_SIZE(s32g_map), +}; + +static const struct of_device_id ocotp_of_match[] =3D { + { .compatible =3D "nxp,s32g2-ocotp", .data =3D &s32g_fuse_map}, + { /* sentinel */ } +}; + +static u32 get_bank_index(unsigned int offset) +{ + return (offset - S32G_OCOTP_BANK_OFFSET) / S32G_OCOTP_BANK_SIZE; +} + +static u32 get_word_index(unsigned int offset) +{ + return offset % S32G_OCOTP_BANK_SIZE / S32G_OCOTP_WORD_SIZE; +} + +static bool is_valid_word(struct s32g_ocotp_priv *s32g_data, + unsigned int offset, int bytes) +{ + const struct s32g_fuse_map *fuse =3D s32g_data->fuse; + u32 bank, word; + size_t i; + + if (offset < S32G_OCOTP_BANK_OFFSET) + return false; + + if (bytes !=3D S32G_OCOTP_WORD_SIZE) + return false; + + bank =3D get_bank_index(offset); + word =3D get_word_index(offset); + if (bank >=3D fuse->n_entries) + return false; + + for (i =3D 0; i < fuse->n_entries; i++) { + if (fuse->map[i].bank =3D=3D bank && + fuse->map[i].words_mask & BIT(word)) + return true; + } + return false; +} + +static int s32g_ocotp_read(void *context, unsigned int offset, + void *val, size_t bytes) +{ + struct s32g_ocotp_priv *s32g_data =3D context; + + if (!is_valid_word(s32g_data, offset, bytes)) + return -EINVAL; + + /* Read from Fuse OCOTP Shadow registers */ + *(u32 *)val =3D ioread32(s32g_data->base + offset); + + return 0; +} + +static struct nvmem_config s32g_ocotp_nvmem_config =3D { + .name =3D "s32g-ocotp", + .add_legacy_fixed_of_cells =3D true, + .read_only =3D true, + .word_size =3D S32G_OCOTP_WORD_SIZE, + .reg_read =3D s32g_ocotp_read, +}; + +static int s32g_ocotp_probe(struct platform_device *pdev) +{ + const struct of_device_id *of_matched_dt_id; + struct s32g_ocotp_priv *s32g_data; + struct device *dev =3D &pdev->dev; + struct nvmem_device *nvmem; + struct resource *res; + + of_matched_dt_id =3D of_match_device(ocotp_of_match, dev); + if (!of_matched_dt_id) { + dev_err(dev, "Unable to find driver data.\n"); + return -ENODEV; + } + + s32g_data =3D devm_kzalloc(dev, sizeof(*s32g_data), GFP_KERNEL); + if (!s32g_data) + return -ENOMEM; + + s32g_data->fuse =3D of_device_get_match_data(dev); + if (!s32g_data->fuse) { + dev_err(dev, "Cannot find platform device data.\n"); + return -ENODEV; + } + + s32g_data->base =3D devm_platform_get_and_ioremap_resource(pdev, 0, &res); + if (IS_ERR(s32g_data->base)) { + dev_err(dev, "Cannot map OCOTP device.\n"); + return PTR_ERR(s32g_data->base); + } + + s32g_data->dev =3D dev; + s32g_ocotp_nvmem_config.dev =3D dev; + s32g_ocotp_nvmem_config.priv =3D s32g_data; + s32g_ocotp_nvmem_config.size =3D resource_size(res); + + nvmem =3D devm_nvmem_register(dev, &s32g_ocotp_nvmem_config); + + return PTR_ERR_OR_ZERO(nvmem); +} + +static struct platform_driver s32g_ocotp_driver =3D { + .probe =3D s32g_ocotp_probe, + .driver =3D { + .name =3D "s32g-ocotp", + .of_match_table =3D ocotp_of_match, + }, +}; +module_platform_driver(s32g_ocotp_driver); +MODULE_AUTHOR("NXP"); +MODULE_DESCRIPTION("S32G OCOTP driver"); +MODULE_LICENSE("GPL"); --=20 2.47.2 From nobody Sat Oct 4 12:45:48 2025 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 36EE629AAF6 for ; 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Sat, 16 Aug 2025 03:47:16 -0700 (PDT) Received: from localhost ([196.207.164.177]) by smtp.gmail.com with UTF8SMTPSA id 5b1f17b1804b1-45a1c6be10esm96169425e9.3.2025.08.16.03.47.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Aug 2025 03:47:16 -0700 (PDT) Date: Sat, 16 Aug 2025 13:47:13 +0300 From: Dan Carpenter To: Chester Lin Cc: Matthias Brugger , Ghennadi Procopciuc , NXP S32 Linux Team , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linaro-s32@linaro.org, Srinivas Kandagatla Subject: [PATCH 3/3] arm64: dts: s32g: Add device tree information for the OCOTP driver Message-ID: <9b3874c6aedf87f78cc6438fe840433162b06445.1755341000.git.dan.carpenter@linaro.org> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the device tree information for the S32G On Chip One-Time Programmable Controller (OCOTP) chip. Signed-off-by: Dan Carpenter --- arch/arm64/boot/dts/freescale/s32g2.dtsi | 7 +++++++ arch/arm64/boot/dts/freescale/s32g3.dtsi | 7 +++++++ 2 files changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts= /freescale/s32g2.dtsi index 09d2fbbe1d8c..e58ea0d3b083 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -612,5 +612,12 @@ gic: interrupt-controller@50800000 { interrupt-controller; #interrupt-cells =3D <3>; }; + + ocotp: ocotp@400a4000 { + compatible =3D "nxp,s32g2-ocotp"; + reg =3D <0x400a4000 0x400>; + #address-cells =3D <1>; + #size-cells =3D <1>; + }; }; }; diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts= /freescale/s32g3.dtsi index 39effbe8217c..184a29dea184 100644 --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi @@ -681,6 +681,13 @@ gic: interrupt-controller@50800000 { <0x50420000 0x2000>; interrupts =3D ; }; + + ocotp: ocotp@400a4000 { + compatible =3D "nxp,s32g3-ocotp", "nxp,s32g2-ocotp"; + reg =3D <0x400a4000 0x400>; + #address-cells =3D <1>; + #size-cells =3D <1>; + }; }; =20 timer { --=20 2.47.2