From nobody Sat Oct 4 19:14:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 77792291864; Wed, 13 Aug 2025 17:01:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755104492; cv=none; b=CEIc7Z39d00PYVLfX+UgZCArNxaDqi6IALNWYXTLeMgDA246lN7Mfp6zfHGWs5yIulFqIHsrdzONxoeuj2PiktXoZ4EjZaYfqf6n4+R13oo0xFL0X2m0qojSGzIL/htg0UhdoH9DiZnLoA3DvOhkmRoyVZDop1ALgMHCJgKe/SU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755104492; c=relaxed/simple; bh=nvDCjI8G+B+H5gCrY6OJ5M1oTNHiic2SypXf3MT+n2Y=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Om6o1in8HrtjIE4jS4SWeg0OI+sgPVVtPJtLGwROr5fI7LoeA2ku4dZEq5nZ+6IM2DOHIwHZck6rgT6qyp8uPf71oUKqW8scqtfeccQmPNTja6WZZEdiMiqgtC73+prGA/0kGmmKL3cp7dZDfajKzEA8wJ/7JdBzAPEFdYsb2UM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8977914BF; Wed, 13 Aug 2025 10:01:21 -0700 (PDT) Received: from e121345-lin.cambridge.arm.com (e121345-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 704653F738; Wed, 13 Aug 2025 10:01:25 -0700 (PDT) From: Robin Murphy To: peterz@infradead.org, mingo@redhat.com, will@kernel.org, mark.rutland@arm.com, acme@kernel.org, namhyung@kernel.org, alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, adrian.hunter@intel.com, kan.liang@linux.intel.com Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-alpha@vger.kernel.org, linux-snps-arc@lists.infradead.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, linux-csky@vger.kernel.org, loongarch@lists.linux.dev, linux-mips@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, linux-pm@vger.kernel.org, linux-rockchip@lists.infradead.org, dmaengine@vger.kernel.org, linux-fpga@vger.kernel.org, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, coresight@lists.linaro.org, iommu@lists.linux.dev, linux-amlogic@lists.infradead.org, linux-cxl@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH 01/19] perf/arm-cmn: Fix event validation Date: Wed, 13 Aug 2025 18:00:53 +0100 Message-Id: <0716da3e77065f005ef6ea0d10ddf67fc53e76cb.1755096883.git.robin.murphy@arm.com> X-Mailer: git-send-email 2.39.2.101.g768bb238c484.dirty In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In the hypothetical case where a CMN event is opened with a software group leader that already has some other hardware sibling, currently arm_cmn_val_add_event() could try to interpret the other event's data as an arm_cmn_hw_event, which is not great since we dereference a pointer from there... Thankfully the way to be more robust is to be less clever - stop trying to special-case software events and simply skip any event that isn't for our PMU. Signed-off-by: Robin Murphy --- drivers/perf/arm-cmn.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/perf/arm-cmn.c b/drivers/perf/arm-cmn.c index 11fb2234b10f..f8c9be9fa6c0 100644 --- a/drivers/perf/arm-cmn.c +++ b/drivers/perf/arm-cmn.c @@ -1652,7 +1652,7 @@ static void arm_cmn_val_add_event(struct arm_cmn *cmn= , struct arm_cmn_val *val, enum cmn_node_type type; int i; =20 - if (is_software_event(event)) + if (event->pmu !=3D &cmn->pmu) return; =20 type =3D CMN_EVENT_TYPE(event); @@ -1693,9 +1693,6 @@ static int arm_cmn_validate_group(struct arm_cmn *cmn= , struct perf_event *event) if (leader =3D=3D event) return 0; =20 - if (event->pmu !=3D leader->pmu && !is_software_event(leader)) - return -EINVAL; - val =3D kzalloc(sizeof(*val), GFP_KERNEL); if (!val) return -ENOMEM; --=20 2.39.2.101.g768bb238c484.dirty From nobody Sat Oct 4 19:14:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B110522DF9E; Wed, 13 Aug 2025 17:01:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755104496; cv=none; b=UkZ1tGRFmozAYqDGdCdgv5hRDHGHRGydnfNul6Vp4fr9GYem5kobxZAsU3Sj0MCgc6YKLf8QHpnwNMTXbEFOn68eJITGK2PJaRz8ZdOmjR9WPSbQBaYLo22aGZcfOtaxXMMgt3plqSk9sKPGgWCQU2n/AGY2JjUWpYKyZ7PIydM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755104496; c=relaxed/simple; bh=0oyjzVYktsArPH0QHqPqYIaxRU0EWejtBLkJtie6tpI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=e4SE5F6lSAidDFAmGK1ZLqJKeQsYzbi+650NeTAAOchornIBRBwq1AnHUEuOWtxMSfuVxOfSPpzuy/jmWXs/W2XMMC9Ci6w3vO0XWm9zTpjNmgW6DOiUlhilWHWq0ywCV2dW2RtSgE11F4Von7AZ3cc73IyRKy1O8yHEUJRO1/8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 128701BCB; Wed, 13 Aug 2025 10:01:26 -0700 (PDT) Received: from e121345-lin.cambridge.arm.com (e121345-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id EEB253F738; Wed, 13 Aug 2025 10:01:29 -0700 (PDT) From: Robin Murphy To: peterz@infradead.org, mingo@redhat.com, will@kernel.org, mark.rutland@arm.com, acme@kernel.org, namhyung@kernel.org, alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, adrian.hunter@intel.com, kan.liang@linux.intel.com Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-alpha@vger.kernel.org, linux-snps-arc@lists.infradead.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, linux-csky@vger.kernel.org, loongarch@lists.linux.dev, linux-mips@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, linux-pm@vger.kernel.org, linux-rockchip@lists.infradead.org, dmaengine@vger.kernel.org, linux-fpga@vger.kernel.org, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, coresight@lists.linaro.org, iommu@lists.linux.dev, linux-amlogic@lists.infradead.org, linux-cxl@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH 02/19] perf/hisilicon: Fix group validation Date: Wed, 13 Aug 2025 18:00:54 +0100 Message-Id: X-Mailer: git-send-email 2.39.2.101.g768bb238c484.dirty In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The group validation logic shared by the HiSilicon HNS3/PCIe drivers is a bit off, in that given a software group leader, it will consider that event *in place of* the actual new event being opened. At worst this could theoretically allow an unschedulable group if the software event config happens to look like one of the hardware siblings. The uncore framework avoids that particular issue, but all 3 also share the common issue of not preventing racy access to the sibling list, and some redundant checks which can be cleaned up. Signed-off-by: Robin Murphy --- drivers/perf/hisilicon/hisi_pcie_pmu.c | 17 ++++++----------- drivers/perf/hisilicon/hisi_uncore_pmu.c | 23 +++++++---------------- drivers/perf/hisilicon/hns3_pmu.c | 17 ++++++----------- 3 files changed, 19 insertions(+), 38 deletions(-) diff --git a/drivers/perf/hisilicon/hisi_pcie_pmu.c b/drivers/perf/hisilico= n/hisi_pcie_pmu.c index c5394d007b61..3b0b2f7197d0 100644 --- a/drivers/perf/hisilicon/hisi_pcie_pmu.c +++ b/drivers/perf/hisilicon/hisi_pcie_pmu.c @@ -338,21 +338,16 @@ static bool hisi_pcie_pmu_validate_event_group(struct= perf_event *event) int counters =3D 1; int num; =20 - event_group[0] =3D leader; - if (!is_software_event(leader)) { - if (leader->pmu !=3D event->pmu) - return false; + if (leader =3D=3D event) + return true; =20 - if (leader !=3D event && !hisi_pcie_pmu_cmp_event(leader, event)) - event_group[counters++] =3D event; - } + event_group[0] =3D event; + if (leader->pmu =3D=3D event->pmu && !hisi_pcie_pmu_cmp_event(leader, eve= nt)) + event_group[counters++] =3D leader; =20 for_each_sibling_event(sibling, event->group_leader) { - if (is_software_event(sibling)) - continue; - if (sibling->pmu !=3D event->pmu) - return false; + continue; =20 for (num =3D 0; num < counters; num++) { /* diff --git a/drivers/perf/hisilicon/hisi_uncore_pmu.c b/drivers/perf/hisili= con/hisi_uncore_pmu.c index a449651f79c9..3c531b36cf25 100644 --- a/drivers/perf/hisilicon/hisi_uncore_pmu.c +++ b/drivers/perf/hisilicon/hisi_uncore_pmu.c @@ -101,26 +101,17 @@ static bool hisi_validate_event_group(struct perf_eve= nt *event) /* Include count for the event */ int counters =3D 1; =20 - if (!is_software_event(leader)) { - /* - * We must NOT create groups containing mixed PMUs, although - * software events are acceptable - */ - if (leader->pmu !=3D event->pmu) - return false; + if (leader =3D=3D event) + return true; =20 - /* Increment counter for the leader */ - if (leader !=3D event) - counters++; - } + /* Increment counter for the leader */ + if (leader->pmu =3D=3D event->pmu) + counters++; =20 for_each_sibling_event(sibling, event->group_leader) { - if (is_software_event(sibling)) - continue; - if (sibling->pmu !=3D event->pmu) - return false; /* Increment counter for each sibling */ - counters++; + if (sibling->pmu =3D=3D event->pmu) + counters++; } =20 /* The group can not count events more than the counters in the HW */ diff --git a/drivers/perf/hisilicon/hns3_pmu.c b/drivers/perf/hisilicon/hns= 3_pmu.c index c157f3572cae..382e469257f9 100644 --- a/drivers/perf/hisilicon/hns3_pmu.c +++ b/drivers/perf/hisilicon/hns3_pmu.c @@ -1058,21 +1058,16 @@ static bool hns3_pmu_validate_event_group(struct pe= rf_event *event) int counters =3D 1; int num; =20 - event_group[0] =3D leader; - if (!is_software_event(leader)) { - if (leader->pmu !=3D event->pmu) - return false; + if (leader =3D=3D event) + return true; =20 - if (leader !=3D event && !hns3_pmu_cmp_event(leader, event)) - event_group[counters++] =3D event; - } + event_group[0] =3D event; + if (leader->pmu =3D=3D event->pmu && !hns3_pmu_cmp_event(leader, event)) + event_group[counters++] =3D leader; =20 for_each_sibling_event(sibling, event->group_leader) { - if (is_software_event(sibling)) - continue; - if (sibling->pmu !=3D event->pmu) - return false; + continue; =20 for (num =3D 0; num < counters; num++) { /* --=20 2.39.2.101.g768bb238c484.dirty From nobody Sat Oct 4 19:14:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 75CC828D8FB; Wed, 13 Aug 2025 17:01:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755104501; cv=none; b=AZx3skclHk2BdMP0SaPMKh1oYbC+KAW6UyU7gpYff3pW9UU/AJPT9N3jtPDW7rSUnUG3NCCouKya1PMku+wKjDjuw75bB8m0kgBINks5t4kKfAyCt13CLVu8oQukC43DzPNLPvB2fEBUr4gFqiMoSyiV3xNAdPiuYWvJBlBwTJM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755104501; c=relaxed/simple; bh=Yxo8fR9zuH8qiDRz3yj+dgc/ztJ9AMTU5oV+Xlaqlro=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=WxyluK0vWcB++xmdQ8tRH8JEbzPCmRxmfHce8phLBguAiy3TIgeipmABnapEMZXsiQv8McjV5FyBu+H27FHiHsAoLTGPhs7mIrn1LiImg3P1GsS+DGxmTSOrDlI7kfYAhIO9HM97NH1a54Hu515xe1C3Pchfzwgt01vDo0Vcg+A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 901F71BD0; Wed, 13 Aug 2025 10:01:30 -0700 (PDT) Received: from e121345-lin.cambridge.arm.com (e121345-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 776713F738; Wed, 13 Aug 2025 10:01:34 -0700 (PDT) From: Robin Murphy To: peterz@infradead.org, mingo@redhat.com, will@kernel.org, mark.rutland@arm.com, acme@kernel.org, namhyung@kernel.org, alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, adrian.hunter@intel.com, kan.liang@linux.intel.com Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-alpha@vger.kernel.org, linux-snps-arc@lists.infradead.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, linux-csky@vger.kernel.org, loongarch@lists.linux.dev, linux-mips@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, linux-pm@vger.kernel.org, linux-rockchip@lists.infradead.org, dmaengine@vger.kernel.org, linux-fpga@vger.kernel.org, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, coresight@lists.linaro.org, iommu@lists.linux.dev, linux-amlogic@lists.infradead.org, linux-cxl@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH 03/19] perf/imx8_ddr: Fix group validation Date: Wed, 13 Aug 2025 18:00:55 +0100 Message-Id: X-Mailer: git-send-email 2.39.2.101.g768bb238c484.dirty In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The group validation here is erroneously inspecting software events, as well as other hardware siblings, which are only checked for *after* they've already been misinterpreted. Once again, just ignore events which don't belong to our PMU, and don't duplicate what perf_event_open() will already check for us. Signed-off-by: Robin Murphy --- drivers/perf/fsl_imx8_ddr_perf.c | 21 +++++---------------- 1 file changed, 5 insertions(+), 16 deletions(-) diff --git a/drivers/perf/fsl_imx8_ddr_perf.c b/drivers/perf/fsl_imx8_ddr_p= erf.c index b989ffa95d69..56fe281974d2 100644 --- a/drivers/perf/fsl_imx8_ddr_perf.c +++ b/drivers/perf/fsl_imx8_ddr_perf.c @@ -331,6 +331,9 @@ static u32 ddr_perf_filter_val(struct perf_event *event) static bool ddr_perf_filters_compatible(struct perf_event *a, struct perf_event *b) { + /* Ignore grouped events that aren't ours */ + if (a->pmu !=3D b->pmu) + return true; if (!ddr_perf_is_filtered(a)) return true; if (!ddr_perf_is_filtered(b)) @@ -409,16 +412,8 @@ static int ddr_perf_event_init(struct perf_event *even= t) return -EOPNOTSUPP; } =20 - /* - * We must NOT create groups containing mixed PMUs, although software - * events are acceptable (for example to create a CCN group - * periodically read when a hrtimer aka cpu-clock leader triggers). - */ - if (event->group_leader->pmu !=3D event->pmu && - !is_software_event(event->group_leader)) - return -EINVAL; - - if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER) { + if (event !=3D event->group_leader && + pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER) { if (!ddr_perf_filters_compatible(event, event->group_leader)) return -EINVAL; for_each_sibling_event(sibling, event->group_leader) { @@ -427,12 +422,6 @@ static int ddr_perf_event_init(struct perf_event *even= t) } } =20 - for_each_sibling_event(sibling, event->group_leader) { - if (sibling->pmu !=3D event->pmu && - !is_software_event(sibling)) - return -EINVAL; - } - event->cpu =3D pmu->cpu; hwc->idx =3D -1; =20 --=20 2.39.2.101.g768bb238c484.dirty From nobody Sat Oct 4 19:14:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id DBA01347DD; Wed, 13 Aug 2025 17:01:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755104505; cv=none; b=mpzc3zMEtyfFdSqvasP+nB3AZrTUicn+DILEjWDI6hCmDOEchCErOMNNIBxSrT95nP00qBtVh/GJ05TGlLzWhFRw3nTDS7ZYIrGl3ausGIYhzrYuoZLGYNGoXl1SizbhWLYgJDGP8D6a9a+yezuOVkAAUM6sk4quH1QmXURpi0o= ARC-Message-Signature: i=1; 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Wed, 13 Aug 2025 10:01:38 -0700 (PDT) From: Robin Murphy To: peterz@infradead.org, mingo@redhat.com, will@kernel.org, mark.rutland@arm.com, acme@kernel.org, namhyung@kernel.org, alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, adrian.hunter@intel.com, kan.liang@linux.intel.com Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-alpha@vger.kernel.org, linux-snps-arc@lists.infradead.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, linux-csky@vger.kernel.org, loongarch@lists.linux.dev, linux-mips@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, linux-pm@vger.kernel.org, linux-rockchip@lists.infradead.org, dmaengine@vger.kernel.org, linux-fpga@vger.kernel.org, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, coresight@lists.linaro.org, iommu@lists.linux.dev, linux-amlogic@lists.infradead.org, linux-cxl@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH 04/19] perf/starfive: Fix group validation Date: Wed, 13 Aug 2025 18:00:56 +0100 Message-Id: <6b9c9cf887c102c9154a1f28aea643a66787858f.1755096883.git.robin.murphy@arm.com> X-Mailer: git-send-email 2.39.2.101.g768bb238c484.dirty In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The group validation code here is superficially the right shape, but is failing to count the group leader, while also erroneously counting software siblings. Just correctly count the events which belong to our PMU, and let perf core worry about the rest. Signed-off-by: Robin Murphy --- drivers/perf/starfive_starlink_pmu.c | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/drivers/perf/starfive_starlink_pmu.c b/drivers/perf/starfive_s= tarlink_pmu.c index 5e5a672b4229..e185f307e639 100644 --- a/drivers/perf/starfive_starlink_pmu.c +++ b/drivers/perf/starfive_starlink_pmu.c @@ -347,19 +347,15 @@ static bool starlink_pmu_validate_event_group(struct = perf_event *event) struct perf_event *sibling; int counter =3D 1; =20 - /* - * Ensure hardware events in the group are on the same PMU, - * software events are acceptable. - */ - if (event->group_leader->pmu !=3D event->pmu && - !is_software_event(event->group_leader)) - return false; + if (leader =3D=3D event) + return true; + + if (leader->pmu =3D=3D event->pmu) + counter++; =20 for_each_sibling_event(sibling, leader) { - if (sibling->pmu !=3D event->pmu && !is_software_event(sibling)) - return false; - - counter++; + if (sibling->pmu =3D=3D event->pmu) + counter++; } =20 return counter <=3D STARLINK_PMU_NUM_COUNTERS; --=20 2.39.2.101.g768bb238c484.dirty From nobody Sat Oct 4 19:14:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2564F242927; Wed, 13 Aug 2025 17:01:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755104509; cv=none; b=RVxnQU+/F5C/YW1N3ob7Sxsa/deicsL4/3/iQI8sS9yVXK7zbt0U/1AgZMmShvxllun8KS0lHThaPgDs09lKoRDRyRJruPMCvMydHfSakC//NePXBpNZlQF+nx4gESNkkGPhvI3AXQcTp4UOkXACeocdRRvGzG9aEuAwLxJyKqs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755104509; c=relaxed/simple; bh=xhd+T4zZccQK+ZVtI7yALpBdwFrYaFDIIq0aIZk/RoQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=UrY0o2ej5+9ZD5AxTGyIFYF+kRlC/kDwCs2GJqm8uTp6j2r/GcHekWv33kEb7jH3gTmU6/9oMGrSxSWgvIdh9v8L4CQAkha2dTbnqr7QUXmMPvRui9EcZp7jZC4IAovenCllzXkMKgpyYIB+AZFQB/icWSsUH2++xAyiEl5w6+w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 93BEC1C00; Wed, 13 Aug 2025 10:01:39 -0700 (PDT) Received: from e121345-lin.cambridge.arm.com (e121345-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 7CB223F738; Wed, 13 Aug 2025 10:01:43 -0700 (PDT) From: Robin Murphy To: peterz@infradead.org, mingo@redhat.com, will@kernel.org, mark.rutland@arm.com, acme@kernel.org, namhyung@kernel.org, alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, adrian.hunter@intel.com, kan.liang@linux.intel.com Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-alpha@vger.kernel.org, linux-snps-arc@lists.infradead.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, linux-csky@vger.kernel.org, loongarch@lists.linux.dev, linux-mips@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, linux-pm@vger.kernel.org, linux-rockchip@lists.infradead.org, dmaengine@vger.kernel.org, linux-fpga@vger.kernel.org, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, coresight@lists.linaro.org, iommu@lists.linux.dev, linux-amlogic@lists.infradead.org, linux-cxl@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH 05/19] iommu/vt-d: Fix perfmon group validation Date: Wed, 13 Aug 2025 18:00:57 +0100 Message-Id: X-Mailer: git-send-email 2.39.2.101.g768bb238c484.dirty In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The group validation here has a few issues to fix: firstly, failing to count the group leader or the event being opened itself. Secondly it appears wrong not to count disabled sibling events given that they could be enabled later. Finally there's the subtlety that we should avoid racy access to the sibling list when the event is its own group leader. Signed-off-by: Robin Murphy --- drivers/iommu/intel/perfmon.c | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/drivers/iommu/intel/perfmon.c b/drivers/iommu/intel/perfmon.c index 75f493bcb353..c3a1ac14cb2b 100644 --- a/drivers/iommu/intel/perfmon.c +++ b/drivers/iommu/intel/perfmon.c @@ -258,21 +258,25 @@ static int iommu_pmu_validate_group(struct perf_event= *event) { struct iommu_pmu *iommu_pmu =3D iommu_event_to_pmu(event); struct perf_event *sibling; - int nr =3D 0; + int nr =3D 1; =20 + if (event =3D=3D event->group_leader) + return 0; /* * All events in a group must be scheduled simultaneously. * Check whether there is enough counters for all the events. */ - for_each_sibling_event(sibling, event->group_leader) { - if (!is_iommu_pmu_event(iommu_pmu, sibling) || - sibling->state <=3D PERF_EVENT_STATE_OFF) - continue; + if (is_iommu_pmu_event(iommu_pmu, event->group_leader)) + ++nr; =20 - if (++nr > iommu_pmu->num_cntr) - return -EINVAL; + for_each_sibling_event(sibling, event->group_leader) { + if (is_iommu_pmu_event(iommu_pmu, sibling)) + ++nr; } =20 + if (nr > iommu_pmu->num_cntr) + return -EINVAL; + return 0; } =20 --=20 2.39.2.101.g768bb238c484.dirty From nobody Sat Oct 4 19:14:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D73DF295D91; Wed, 13 Aug 2025 17:01:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755104514; cv=none; b=oqtaZsRJrpFZCYxQJeux/7yKywP7rUlschiUxPZ7lxh66rvAJk6J+BUd8rHnhv8v8XtXLY3ZegTlrjdjcu9eSucWyzvixoNM7CK8OHZw4/jrEbW/3DzhTFXSojwI7HEBL5DWFRt7u0RLNreMdzJ5fqqS/TpewxI+FhEh45L91Fc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755104514; c=relaxed/simple; bh=uo848j2DZMuYEFuAQ16GeCSN3LjjQmRdst0t3ttkAVc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=EoaoIYB7gml2jBFWpafRFD3vvIf7wh+9lQ5ZzgHx//2F4udwdFVB9GxH6EHwN8Th5gCY3l/+Gd2oOiJem1m4eIQPFI6fnnilBTrPs+TMAvFFHHNctiYmJ04urn0P/b/PL0xHz4TNtl5Gv45p2qNbm2I9Y5wvEKpcLyV+yM9wg74= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 29D641C01; Wed, 13 Aug 2025 10:01:44 -0700 (PDT) Received: from e121345-lin.cambridge.arm.com (e121345-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 074E03F738; Wed, 13 Aug 2025 10:01:47 -0700 (PDT) From: Robin Murphy To: peterz@infradead.org, mingo@redhat.com, will@kernel.org, mark.rutland@arm.com, acme@kernel.org, namhyung@kernel.org, alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, adrian.hunter@intel.com, kan.liang@linux.intel.com Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-alpha@vger.kernel.org, linux-snps-arc@lists.infradead.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, linux-csky@vger.kernel.org, loongarch@lists.linux.dev, linux-mips@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, linux-pm@vger.kernel.org, linux-rockchip@lists.infradead.org, dmaengine@vger.kernel.org, linux-fpga@vger.kernel.org, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, coresight@lists.linaro.org, iommu@lists.linux.dev, linux-amlogic@lists.infradead.org, linux-cxl@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH 06/19] ARM: l2x0: Fix group validation Date: Wed, 13 Aug 2025 18:00:58 +0100 Message-Id: <925c34a4b7f0defc3582a9fcccb6af1c21279a86.1755096883.git.robin.murphy@arm.com> X-Mailer: git-send-email 2.39.2.101.g768bb238c484.dirty In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The group validation here is almost right, but fails to count the new event itself. While we fix that, also adopt the standard pattern to avoid racy access the sibling list and drop checks that are redundant with core code. Signed-off-by: Robin Murphy --- arch/arm/mm/cache-l2x0-pmu.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/arch/arm/mm/cache-l2x0-pmu.c b/arch/arm/mm/cache-l2x0-pmu.c index 93ef0502b7ff..6fc1171031a8 100644 --- a/arch/arm/mm/cache-l2x0-pmu.c +++ b/arch/arm/mm/cache-l2x0-pmu.c @@ -274,18 +274,17 @@ static bool l2x0_pmu_group_is_valid(struct perf_event= *event) struct pmu *pmu =3D event->pmu; struct perf_event *leader =3D event->group_leader; struct perf_event *sibling; - int num_hw =3D 0; + int num_hw =3D 1; + + if (leader =3D=3D event) + return true; =20 if (leader->pmu =3D=3D pmu) num_hw++; - else if (!is_software_event(leader)) - return false; =20 for_each_sibling_event(sibling, leader) { if (sibling->pmu =3D=3D pmu) num_hw++; - else if (!is_software_event(sibling)) - return false; } =20 return num_hw <=3D PMU_NR_COUNTERS; --=20 2.39.2.101.g768bb238c484.dirty From nobody Sat Oct 4 19:14:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 8347C296BDC; Wed, 13 Aug 2025 17:01:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755104518; cv=none; b=abhdjVRjYDyKVlhE5gPvOl1T3MYbeJIb21DyYy5/vHzPTtcrcTb6uH7m9xNTIt9hjgSilo7ygk48Eg2A1GDCNifbkh3nl0fXMOKhRTQiZ8LErYsZ1pP33G6Pr7KAdH4PJRslgxc8fRtTT63vammgQFalT2SsVf85i/gcK1awYQc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755104518; c=relaxed/simple; bh=V4SASwxGPhUSUPyQKSxrF1qMcQpxHm88dZMwSEogb5s=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=rTgqDxPtV5W62YogA4ht1JjM2ChHEXMMKdp1cUmMrLZOM0SC73/5geMpBlQRmTMLx+31n3YhgixT2+ahk7Hc4dvSRxTYeaPpmCJZOL5CivVFzZaRC7UrtbJ/qMPgsu6UueZKTgAcm2x0PxlWj+Dv18HfZoFA0pZk2eTIQg0tHEs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A7DB41C14; Wed, 13 Aug 2025 10:01:48 -0700 (PDT) Received: from e121345-lin.cambridge.arm.com (e121345-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 8F4993F738; Wed, 13 Aug 2025 10:01:52 -0700 (PDT) From: Robin Murphy To: peterz@infradead.org, mingo@redhat.com, will@kernel.org, mark.rutland@arm.com, acme@kernel.org, namhyung@kernel.org, alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, adrian.hunter@intel.com, kan.liang@linux.intel.com Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-alpha@vger.kernel.org, linux-snps-arc@lists.infradead.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, linux-csky@vger.kernel.org, loongarch@lists.linux.dev, linux-mips@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, linux-pm@vger.kernel.org, linux-rockchip@lists.infradead.org, dmaengine@vger.kernel.org, linux-fpga@vger.kernel.org, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, coresight@lists.linaro.org, iommu@lists.linux.dev, linux-amlogic@lists.infradead.org, linux-cxl@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH 07/19] ARM: imx: Fix MMDC PMU group validation Date: Wed, 13 Aug 2025 18:00:59 +0100 Message-Id: <12766b2e16939ed97df8c410a994c730bede8298.1755096883.git.robin.murphy@arm.com> X-Mailer: git-send-email 2.39.2.101.g768bb238c484.dirty In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The group validation here gets the event and its group leader mixed up, such that if the group leader belongs to a different PMU, the set_bit() may go wildly out of bounds. While we fix that, also adopt the standard pattern to avoid racy access the sibling list and drop checks that are redundant with core code. Signed-off-by: Robin Murphy --- arch/arm/mach-imx/mmdc.c | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/arch/arm/mach-imx/mmdc.c b/arch/arm/mach-imx/mmdc.c index 94e4f4a2f73f..f9d432b385a2 100644 --- a/arch/arm/mach-imx/mmdc.c +++ b/arch/arm/mach-imx/mmdc.c @@ -238,11 +238,8 @@ static bool mmdc_pmu_group_event_is_valid(struct perf_= event *event, { int cfg =3D event->attr.config; =20 - if (is_software_event(event)) - return true; - if (event->pmu !=3D pmu) - return false; + return true; =20 return !test_and_set_bit(cfg, used_counters); } @@ -260,12 +257,12 @@ static bool mmdc_pmu_group_is_valid(struct perf_event= *event) struct perf_event *sibling; unsigned long counter_mask =3D 0; =20 - set_bit(leader->attr.config, &counter_mask); + if (event =3D=3D leader) + return true; =20 - if (event !=3D leader) { - if (!mmdc_pmu_group_event_is_valid(event, pmu, &counter_mask)) - return false; - } + set_bit(event->attr.config, &counter_mask); + if (!mmdc_pmu_group_event_is_valid(leader, pmu, &counter_mask)) + return false; =20 for_each_sibling_event(sibling, leader) { if (!mmdc_pmu_group_event_is_valid(sibling, pmu, &counter_mask)) --=20 2.39.2.101.g768bb238c484.dirty From nobody Sat Oct 4 19:14:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id BE9B4298CAF; Wed, 13 Aug 2025 17:02:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755104523; cv=none; b=NcjIncdnIjYs1Ihy/p6PB/kAWao1PhkFYJI/ZVgJDwXVzTd/FHgVEeou66/YPrlpgN+l5qmndd4w27USNGZYsDPdoKArC9CBHmQhGq6E/GQBzHZtjp5CoH4q2WA3D33m/VdXQwwWyfbF2U1hE/tGzbZjLhxWUdR2OB7i4vxmHMY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755104523; c=relaxed/simple; bh=tGc5odpAlI9Jc9rNn+CWgNgQ2EYb4lXXkwp3jGw2aKE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=R99qLJlja2rS49wxR2+fYzPDXo1CyBLjd4iwbsnL1/arvdzKkDEXGD0mXz/5nXMaAnVR+SMd9NRqpZlQiRxtdYQ38WbgufBheyisap0LKRac0U1nFNZUgy2bhY3L76I47ghkJIE80AFajyXn/yVFuHnhsK15De4bhDbt/6MFZpw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 35A361CDD; Wed, 13 Aug 2025 10:01:53 -0700 (PDT) Received: from e121345-lin.cambridge.arm.com (e121345-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 181F03F738; Wed, 13 Aug 2025 10:01:56 -0700 (PDT) From: Robin Murphy To: peterz@infradead.org, mingo@redhat.com, will@kernel.org, mark.rutland@arm.com, acme@kernel.org, namhyung@kernel.org, alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, adrian.hunter@intel.com, kan.liang@linux.intel.com Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-alpha@vger.kernel.org, linux-snps-arc@lists.infradead.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, linux-csky@vger.kernel.org, loongarch@lists.linux.dev, linux-mips@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, linux-pm@vger.kernel.org, linux-rockchip@lists.infradead.org, dmaengine@vger.kernel.org, linux-fpga@vger.kernel.org, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, coresight@lists.linaro.org, iommu@lists.linux.dev, linux-amlogic@lists.infradead.org, linux-cxl@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH 08/19] perf/arm_smmu_v3: Improve group validation Date: Wed, 13 Aug 2025 18:01:00 +0100 Message-Id: X-Mailer: git-send-email 2.39.2.101.g768bb238c484.dirty In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The group validation here is OK, except for the benign issue that it will double-count an event that is its own group leader. Even though it's highly unlikely we'd ever have PMCG hardware with only one counter, let's sort that out, cleaning up some reudundant checks in the process. Signed-off-by: Robin Murphy --- drivers/perf/arm_smmuv3_pmu.c | 22 +++++++++------------- 1 file changed, 9 insertions(+), 13 deletions(-) diff --git a/drivers/perf/arm_smmuv3_pmu.c b/drivers/perf/arm_smmuv3_pmu.c index 621f02a7f43b..7cac380a3528 100644 --- a/drivers/perf/arm_smmuv3_pmu.c +++ b/drivers/perf/arm_smmuv3_pmu.c @@ -377,9 +377,6 @@ static int smmu_pmu_get_event_idx(struct smmu_pmu *smmu= _pmu, static bool smmu_pmu_events_compatible(struct perf_event *curr, struct perf_event *new) { - if (new->pmu !=3D curr->pmu) - return false; - if (to_smmu_pmu(new->pmu)->global_filter && !smmu_pmu_check_global_filter(curr, new)) return false; @@ -422,15 +419,6 @@ static int smmu_pmu_event_init(struct perf_event *even= t) return -EINVAL; } =20 - /* Don't allow groups with mixed PMUs, except for s/w events */ - if (!is_software_event(event->group_leader)) { - if (!smmu_pmu_events_compatible(event->group_leader, event)) - return -EINVAL; - - if (++group_num_events > smmu_pmu->num_counters) - return -EINVAL; - } - /* * Ensure all events are on the same cpu so all events are in the * same cpu context, to avoid races on pmu_enable etc. @@ -442,8 +430,16 @@ static int smmu_pmu_event_init(struct perf_event *even= t) if (event->group_leader =3D=3D event) return 0; =20 + if (event->group_leader->pmu =3D=3D event->pmu) { + if (!smmu_pmu_events_compatible(event->group_leader, event)) + return -EINVAL; + + if (++group_num_events > smmu_pmu->num_counters) + return -EINVAL; + } + for_each_sibling_event(sibling, event->group_leader) { - if (is_software_event(sibling)) + if (sibling->pmu !=3D event->pmu) continue; =20 if (!smmu_pmu_events_compatible(sibling, event)) --=20 2.39.2.101.g768bb238c484.dirty From nobody Sat Oct 4 19:14:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 7FB0528D827; Wed, 13 Aug 2025 17:02:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755104528; cv=none; b=ZORPN5nTMEDwZFnhwsDjz6p00t+GYfHp0tibOWARsm66tTf5PqsU5eOlzpBpOw1DYOHvIQW5P9P7tgNS0tgnY3bZuijCg73NLA3JlA5VvKi1o5NBzR6XrIqqkLithisfn0XXDZ1Vkb6oo4Bwfff0150bU+bEwwBL+UjYMl2wmVc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755104528; c=relaxed/simple; bh=ZAecApf52qpQJeP4Pzp6NugpP/AqSmzwuz+kSWqmmv4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=oWW4irfTIuq08aRROc+5DNJ3BvHls3KntTeI0CQ8aQdVQOa5Rw/fxk5Dlk/A/dPoehEfl2W6/58taG/8hS+71J0yP5fiYDswjlUaNLywvkUC7Y9D2IrUzbe1b79LYysouC/9pQ7Efmvgdfvqx1rjjzwE9YYRC/GYzHFUlLmU114= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AEBB71CE0; Wed, 13 Aug 2025 10:01:57 -0700 (PDT) Received: from e121345-lin.cambridge.arm.com (e121345-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 95E5A3F738; Wed, 13 Aug 2025 10:02:01 -0700 (PDT) From: Robin Murphy To: peterz@infradead.org, mingo@redhat.com, will@kernel.org, mark.rutland@arm.com, acme@kernel.org, namhyung@kernel.org, alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, adrian.hunter@intel.com, kan.liang@linux.intel.com Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-alpha@vger.kernel.org, linux-snps-arc@lists.infradead.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, linux-csky@vger.kernel.org, loongarch@lists.linux.dev, linux-mips@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, linux-pm@vger.kernel.org, linux-rockchip@lists.infradead.org, dmaengine@vger.kernel.org, linux-fpga@vger.kernel.org, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, coresight@lists.linaro.org, iommu@lists.linux.dev, linux-amlogic@lists.infradead.org, linux-cxl@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH 09/19] perf/qcom: Improve group validation Date: Wed, 13 Aug 2025 18:01:01 +0100 Message-Id: X-Mailer: git-send-email 2.39.2.101.g768bb238c484.dirty In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The L3 driver's group validation is almost right, except for erroneously counting a software group leader - which is benign other than artificially limiting the maximum size of such a group to one less than it could be. Correct that with the now-established pattern of simply ignoring all events which do not belong to our PMU. The L2 driver gets a cleanup of some slightly suspicious logic, and both can have the same overall simplification to not duplicate things that perf core will already do, and avoid racy access to the sibling list of group leader events. Signed-off-by: Robin Murphy --- drivers/perf/qcom_l2_pmu.c | 81 +++++++++++++++----------------------- drivers/perf/qcom_l3_pmu.c | 14 +++---- 2 files changed, 37 insertions(+), 58 deletions(-) diff --git a/drivers/perf/qcom_l2_pmu.c b/drivers/perf/qcom_l2_pmu.c index ea8c85729937..9c4e1d89718d 100644 --- a/drivers/perf/qcom_l2_pmu.c +++ b/drivers/perf/qcom_l2_pmu.c @@ -468,23 +468,6 @@ static int l2_cache_event_init(struct perf_event *even= t) return -EINVAL; } =20 - /* Don't allow groups with mixed PMUs, except for s/w events */ - if (event->group_leader->pmu !=3D event->pmu && - !is_software_event(event->group_leader)) { - dev_dbg_ratelimited(&l2cache_pmu->pdev->dev, - "Can't create mixed PMU group\n"); - return -EINVAL; - } - - for_each_sibling_event(sibling, event->group_leader) { - if (sibling->pmu !=3D event->pmu && - !is_software_event(sibling)) { - dev_dbg_ratelimited(&l2cache_pmu->pdev->dev, - "Can't create mixed PMU group\n"); - return -EINVAL; - } - } - cluster =3D get_cluster_pmu(l2cache_pmu, event->cpu); if (!cluster) { /* CPU has not been initialised */ @@ -493,39 +476,6 @@ static int l2_cache_event_init(struct perf_event *even= t) return -EINVAL; } =20 - /* Ensure all events in a group are on the same cpu */ - if ((event->group_leader !=3D event) && - (cluster->on_cpu !=3D event->group_leader->cpu)) { - dev_dbg_ratelimited(&l2cache_pmu->pdev->dev, - "Can't create group on CPUs %d and %d", - event->cpu, event->group_leader->cpu); - return -EINVAL; - } - - if ((event !=3D event->group_leader) && - !is_software_event(event->group_leader) && - (L2_EVT_GROUP(event->group_leader->attr.config) =3D=3D - L2_EVT_GROUP(event->attr.config))) { - dev_dbg_ratelimited(&l2cache_pmu->pdev->dev, - "Column exclusion: conflicting events %llx %llx\n", - event->group_leader->attr.config, - event->attr.config); - return -EINVAL; - } - - for_each_sibling_event(sibling, event->group_leader) { - if ((sibling !=3D event) && - !is_software_event(sibling) && - (L2_EVT_GROUP(sibling->attr.config) =3D=3D - L2_EVT_GROUP(event->attr.config))) { - dev_dbg_ratelimited(&l2cache_pmu->pdev->dev, - "Column exclusion: conflicting events %llx %llx\n", - sibling->attr.config, - event->attr.config); - return -EINVAL; - } - } - hwc->idx =3D -1; hwc->config_base =3D event->attr.config; =20 @@ -534,6 +484,37 @@ static int l2_cache_event_init(struct perf_event *even= t) * same cpu context, to avoid races on pmu_enable etc. */ event->cpu =3D cluster->on_cpu; + if (event->cpu !=3D event->group_leader->cpu) { + dev_dbg_ratelimited(&l2cache_pmu->pdev->dev, + "Can't create group on CPUs %d and %d", + event->cpu, event->group_leader->cpu); + return -EINVAL; + } + + if (event =3D=3D event->group_leader) + return 0; + + if ((event->group_leader->pmu =3D=3D event->pmu) && + (L2_EVT_GROUP(event->group_leader->attr.config) =3D=3D + L2_EVT_GROUP(event->attr.config))) { + dev_dbg_ratelimited(&l2cache_pmu->pdev->dev, + "Column exclusion: conflicting events %llx %llx\n", + event->group_leader->attr.config, + event->attr.config); + return -EINVAL; + } + + for_each_sibling_event(sibling, event->group_leader) { + if ((sibling->pmu =3D=3D event->pmu) && + (L2_EVT_GROUP(sibling->attr.config) =3D=3D + L2_EVT_GROUP(event->attr.config))) { + dev_dbg_ratelimited(&l2cache_pmu->pdev->dev, + "Column exclusion: conflicting events %llx %llx\n", + sibling->attr.config, + event->attr.config); + return -EINVAL; + } + } =20 return 0; } diff --git a/drivers/perf/qcom_l3_pmu.c b/drivers/perf/qcom_l3_pmu.c index 66e6cabd6fff..f0cf6c33418d 100644 --- a/drivers/perf/qcom_l3_pmu.c +++ b/drivers/perf/qcom_l3_pmu.c @@ -454,18 +454,16 @@ static bool qcom_l3_cache__validate_event_group(struc= t perf_event *event) struct perf_event *sibling; int counters =3D 0; =20 - if (leader->pmu !=3D event->pmu && !is_software_event(leader)) - return false; + if (leader =3D=3D event) + return true; =20 counters =3D event_num_counters(event); - counters +=3D event_num_counters(leader); + if (leader->pmu =3D=3D event->pmu) + counters +=3D event_num_counters(leader); =20 for_each_sibling_event(sibling, leader) { - if (is_software_event(sibling)) - continue; - if (sibling->pmu !=3D event->pmu) - return false; - counters +=3D event_num_counters(sibling); + if (sibling->pmu =3D=3D event->pmu) + counters +=3D event_num_counters(sibling); } =20 /* --=20 2.39.2.101.g768bb238c484.dirty From nobody Sat Oct 4 19:14:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C02B32FABF7; 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dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3AAD71CE2; Wed, 13 Aug 2025 10:02:02 -0700 (PDT) Received: from e121345-lin.cambridge.arm.com (e121345-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 1F4713F738; Wed, 13 Aug 2025 10:02:06 -0700 (PDT) From: Robin Murphy To: peterz@infradead.org, mingo@redhat.com, will@kernel.org, mark.rutland@arm.com, acme@kernel.org, namhyung@kernel.org, alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, adrian.hunter@intel.com, kan.liang@linux.intel.com Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-alpha@vger.kernel.org, linux-snps-arc@lists.infradead.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, linux-csky@vger.kernel.org, loongarch@lists.linux.dev, linux-mips@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, linux-pm@vger.kernel.org, linux-rockchip@lists.infradead.org, dmaengine@vger.kernel.org, linux-fpga@vger.kernel.org, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, coresight@lists.linaro.org, iommu@lists.linux.dev, linux-amlogic@lists.infradead.org, linux-cxl@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH 10/19] perf/arm-ni: Improve event validation Date: Wed, 13 Aug 2025 18:01:02 +0100 Message-Id: X-Mailer: git-send-email 2.39.2.101.g768bb238c484.dirty In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Although it is entirely benign for arm_ni_val_count_event() to count any old hardware leader/sibling as an NI event (perf core will still ultimately reject the cross-PMU group), it would still be nicer if it didn't. Stop trying to special-case software events and simply skip any event which doesn't belong to our PMU. Similarly drop the early return paths since they can almost never actually return early. Signed-off-by: Robin Murphy --- drivers/perf/arm-ni.c | 29 +++++++++++++---------------- 1 file changed, 13 insertions(+), 16 deletions(-) diff --git a/drivers/perf/arm-ni.c b/drivers/perf/arm-ni.c index 1615a0564031..d6b683a0264e 100644 --- a/drivers/perf/arm-ni.c +++ b/drivers/perf/arm-ni.c @@ -271,40 +271,37 @@ static void arm_ni_pmu_disable(struct pmu *pmu) } =20 struct arm_ni_val { + const struct pmu *pmu; unsigned int evcnt; unsigned int ccnt; }; =20 -static bool arm_ni_val_count_event(struct perf_event *evt, struct arm_ni_v= al *val) +static void arm_ni_val_count_event(struct perf_event *evt, struct arm_ni_v= al *val) { - if (is_software_event(evt)) - return true; - - if (NI_EVENT_TYPE(evt) =3D=3D NI_PMU) { - val->ccnt++; - return val->ccnt <=3D 1; + if (evt->pmu =3D=3D val->pmu) { + if (NI_EVENT_TYPE(evt) =3D=3D NI_PMU) + val->ccnt++; + else + val->evcnt++; } - - val->evcnt++; - return val->evcnt <=3D NI_NUM_COUNTERS; } =20 static int arm_ni_validate_group(struct perf_event *event) { struct perf_event *sibling, *leader =3D event->group_leader; - struct arm_ni_val val =3D { 0 }; + struct arm_ni_val val =3D { .pmu =3D event->pmu }; =20 if (leader =3D=3D event) return 0; =20 arm_ni_val_count_event(event, &val); - if (!arm_ni_val_count_event(leader, &val)) + arm_ni_val_count_event(leader, &val); + for_each_sibling_event(sibling, leader) + arm_ni_val_count_event(sibling, &val); + + if (val.evcnt > NI_NUM_COUNTERS || val.ccnt > 1) return -EINVAL; =20 - for_each_sibling_event(sibling, leader) { - if (!arm_ni_val_count_event(sibling, &val)) - return -EINVAL; - } return 0; } =20 --=20 2.39.2.101.g768bb238c484.dirty From nobody Sat Oct 4 19:14:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 7175C2FF176; Wed, 13 Aug 2025 17:02:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755104537; cv=none; b=H78f8xyPtEBbhVnpBC7RaRKs9pYP65lZFT3jjHSS1lL3/1RyOw094LyoN2g4lBUWkInwWarpJqZtPliXp6DL5V8srWGimVNwqhK4g7KDL0asKvYwJi2MQHaewTbojmdVLWfgUnHllX57cVqyZohYPzSGV4sOqD2y11xDa64paoQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755104537; c=relaxed/simple; bh=U8DjL/vkHJuSW1qLVxKk7d3713WCmhYOHhUU5GUAdCs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=KOdxncNVhZNZpwFdeX3P72/EVbqZD0J+Nlq+Y051bYN4R1Z/T/TcYIw1pOv0Le4QZIERKFgWaopJUX5HJZegymVjz0LDAv+ZTHHNnN20WBp5Xc7WoxIaQ6IGfVLbhmmXCzQS9j3Vs5sIy8sVd7fJDVw4zK5Y24q8oUn0TldEp1k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B4F331D14; Wed, 13 Aug 2025 10:02:06 -0700 (PDT) Received: from e121345-lin.cambridge.arm.com (e121345-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 9DB4C3F738; Wed, 13 Aug 2025 10:02:10 -0700 (PDT) From: Robin Murphy To: peterz@infradead.org, mingo@redhat.com, will@kernel.org, mark.rutland@arm.com, acme@kernel.org, namhyung@kernel.org, alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, adrian.hunter@intel.com, kan.liang@linux.intel.com Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-alpha@vger.kernel.org, linux-snps-arc@lists.infradead.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, linux-csky@vger.kernel.org, loongarch@lists.linux.dev, linux-mips@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, linux-pm@vger.kernel.org, linux-rockchip@lists.infradead.org, dmaengine@vger.kernel.org, linux-fpga@vger.kernel.org, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, coresight@lists.linaro.org, iommu@lists.linux.dev, linux-amlogic@lists.infradead.org, linux-cxl@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH 11/19] perf/arm-cci: Tidy up event validation Date: Wed, 13 Aug 2025 18:01:03 +0100 Message-Id: X-Mailer: git-send-email 2.39.2.101.g768bb238c484.dirty In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The CCI driver only accepts events of its own type, so it is pointless to re-check the event type again further into validation. Conversely, if an event *is* for CCI but has a nonsense config, we should not return -ENOENT to potentially offer it to other PMUs. Finally it seems wrong not to count disabled events which may be enabled later. These are all artefacts left over from the original attempt to fit CCI into the arm_pmu framework; clean them up, along with the now-redundant checks for cross-PMU groups which core code will already handle (albeit not quite as the out-of-date comment says). Signed-off-by: Robin Murphy --- drivers/perf/arm-cci.c | 47 +++++++++++------------------------------- 1 file changed, 12 insertions(+), 35 deletions(-) diff --git a/drivers/perf/arm-cci.c b/drivers/perf/arm-cci.c index 1cc3214d6b6d..086d4363fcc8 100644 --- a/drivers/perf/arm-cci.c +++ b/drivers/perf/arm-cci.c @@ -333,7 +333,7 @@ static int cci400_validate_hw_event(struct cci_pmu *cci= _pmu, unsigned long hw_ev int if_type; =20 if (hw_event & ~CCI400_PMU_EVENT_MASK) - return -ENOENT; + return -EINVAL; =20 if (hw_event =3D=3D CCI400_PMU_CYCLES) return hw_event; @@ -354,14 +354,14 @@ static int cci400_validate_hw_event(struct cci_pmu *c= ci_pmu, unsigned long hw_ev if_type =3D CCI_IF_MASTER; break; default: - return -ENOENT; + return -EINVAL; } =20 if (ev_code >=3D cci_pmu->model->event_ranges[if_type].min && ev_code <=3D cci_pmu->model->event_ranges[if_type].max) return hw_event; =20 - return -ENOENT; + return -EINVAL; } =20 static int probe_cci400_revision(struct cci_pmu *cci_pmu) @@ -541,7 +541,7 @@ static int cci500_validate_hw_event(struct cci_pmu *cci= _pmu, int if_type; =20 if (hw_event & ~CCI5xx_PMU_EVENT_MASK) - return -ENOENT; + return -EINVAL; =20 switch (ev_source) { case CCI5xx_PORT_S0: @@ -565,14 +565,14 @@ static int cci500_validate_hw_event(struct cci_pmu *c= ci_pmu, if_type =3D CCI_IF_GLOBAL; break; default: - return -ENOENT; + return -EINVAL; } =20 if (ev_code >=3D cci_pmu->model->event_ranges[if_type].min && ev_code <=3D cci_pmu->model->event_ranges[if_type].max) return hw_event; =20 - return -ENOENT; + return -EINVAL; } =20 /* @@ -592,7 +592,7 @@ static int cci550_validate_hw_event(struct cci_pmu *cci= _pmu, int if_type; =20 if (hw_event & ~CCI5xx_PMU_EVENT_MASK) - return -ENOENT; + return -EINVAL; =20 switch (ev_source) { case CCI5xx_PORT_S0: @@ -617,14 +617,14 @@ static int cci550_validate_hw_event(struct cci_pmu *c= ci_pmu, if_type =3D CCI_IF_GLOBAL; break; default: - return -ENOENT; + return -EINVAL; } =20 if (ev_code >=3D cci_pmu->model->event_ranges[if_type].min && ev_code <=3D cci_pmu->model->event_ranges[if_type].max) return hw_event; =20 - return -ENOENT; + return -EINVAL; } =20 #endif /* CONFIG_ARM_CCI5xx_PMU */ @@ -801,17 +801,6 @@ static int pmu_get_event_idx(struct cci_pmu_hw_events = *hw, struct perf_event *ev return -EAGAIN; } =20 -static int pmu_map_event(struct perf_event *event) -{ - struct cci_pmu *cci_pmu =3D to_cci_pmu(event->pmu); - - if (event->attr.type < PERF_TYPE_MAX || - !cci_pmu->model->validate_hw_event) - return -ENOENT; - - return cci_pmu->model->validate_hw_event(cci_pmu, event->attr.config); -} - static int pmu_request_irq(struct cci_pmu *cci_pmu, irq_handler_t handler) { int i; @@ -1216,21 +1205,8 @@ static int validate_event(struct pmu *cci_pmu, struct cci_pmu_hw_events *hw_events, struct perf_event *event) { - if (is_software_event(event)) - return 1; - - /* - * Reject groups spanning multiple HW PMUs (e.g. CPU + CCI). The - * core perf code won't check that the pmu->ctx =3D=3D leader->ctx - * until after pmu->event_init(event). - */ + /* Ignore grouped events that aren't ours */ if (event->pmu !=3D cci_pmu) - return 0; - - if (event->state < PERF_EVENT_STATE_OFF) - return 1; - - if (event->state =3D=3D PERF_EVENT_STATE_OFF && !event->attr.enable_on_ex= ec) return 1; =20 return pmu_get_event_idx(hw_events, event) >=3D 0; @@ -1266,10 +1242,11 @@ static int validate_group(struct perf_event *event) =20 static int __hw_perf_event_init(struct perf_event *event) { + struct cci_pmu *cci_pmu =3D to_cci_pmu(event->pmu); struct hw_perf_event *hwc =3D &event->hw; int mapping; =20 - mapping =3D pmu_map_event(event); + mapping =3D cci_pmu->model->validate_hw_event(cci_pmu, event->attr.config= ); =20 if (mapping < 0) { pr_debug("event %x:%llx not supported\n", event->attr.type, --=20 2.39.2.101.g768bb238c484.dirty From nobody Sat Oct 4 19:14:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 19C8129A9D3; Wed, 13 Aug 2025 17:02:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755104542; cv=none; b=AUG5uDXX8i8e/BSo6vvPoQ5pQFYjDDKbC7NolFnajLpF1KraXg29W4GmPB3UQM0PDjl4FcXu2MgQ8sabeSnFYA9lB2RfBCVuvNorRiA2olHyAbAWemaRiyjLD8/QVgnEbdd7FQyRFCfR6xyycQb70BPdry8rQo8Ci6A7JQisnCI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755104542; c=relaxed/simple; bh=zR1/3Qwl9aQxK8T4b040jIQmNgpb5Hg7/uS53glwY50=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=liVTaSnYN4+9Ad0tG+Lm1uTDl3u77tYcH/OCaWXvrqSDtsES5EUiuFwz412jYx99544ERBBFh6AOsIZjjOSJ3j6+gvtLvAhNmjXe18/HttAf3i357Zs6IZdEBEIvRsQZ253LqoMRK1CqrC2a1ZsMdnfHXIZFEUwNtgkUWuIidc0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3C8671D15; Wed, 13 Aug 2025 10:02:11 -0700 (PDT) Received: from e121345-lin.cambridge.arm.com (e121345-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 25A5E3F738; Wed, 13 Aug 2025 10:02:15 -0700 (PDT) From: Robin Murphy To: peterz@infradead.org, mingo@redhat.com, will@kernel.org, mark.rutland@arm.com, acme@kernel.org, namhyung@kernel.org, alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, adrian.hunter@intel.com, kan.liang@linux.intel.com Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-alpha@vger.kernel.org, linux-snps-arc@lists.infradead.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, linux-csky@vger.kernel.org, loongarch@lists.linux.dev, linux-mips@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, linux-pm@vger.kernel.org, linux-rockchip@lists.infradead.org, dmaengine@vger.kernel.org, linux-fpga@vger.kernel.org, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, coresight@lists.linaro.org, iommu@lists.linux.dev, linux-amlogic@lists.infradead.org, linux-cxl@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH 12/19] perf: Ignore event state for group validation Date: Wed, 13 Aug 2025 18:01:04 +0100 Message-Id: X-Mailer: git-send-email 2.39.2.101.g768bb238c484.dirty In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" It may have been different long ago, but today it seems wrong for these drivers to skip counting disabled sibling events in group validation, given that perf_event_enable() could make them schedulable again, and thus increase the effective size of the group later. Conversely, if a sibling event is truly dead then it stands to reason that the whole group is dead, so it's not worth going to any special effort to try to squeeze in a new event that's never going to run anyway. Thus, we can simply remove all these checks. Signed-off-by: Robin Murphy --- arch/alpha/kernel/perf_event.c | 2 +- arch/powerpc/perf/core-book3s.c | 3 +-- arch/powerpc/perf/core-fsl-emb.c | 3 +-- arch/sparc/kernel/perf_event.c | 3 +-- arch/x86/events/core.c | 2 +- arch/x86/events/intel/uncore.c | 3 +-- drivers/dma/idxd/perfmon.c | 3 +-- drivers/perf/arm_pmu.c | 6 ------ 8 files changed, 7 insertions(+), 18 deletions(-) diff --git a/arch/alpha/kernel/perf_event.c b/arch/alpha/kernel/perf_event.c index a3eaab094ece..8557165e64c0 100644 --- a/arch/alpha/kernel/perf_event.c +++ b/arch/alpha/kernel/perf_event.c @@ -352,7 +352,7 @@ static int collect_events(struct perf_event *group, int= max_count, current_idx[n++] =3D PMC_NO_INDEX; } for_each_sibling_event(pe, group) { - if (!is_software_event(pe) && pe->state !=3D PERF_EVENT_STATE_OFF) { + if (!is_software_event(pe)) { if (n >=3D max_count) return -1; event[n] =3D pe; diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3= s.c index 8b0081441f85..d67f7d511f13 100644 --- a/arch/powerpc/perf/core-book3s.c +++ b/arch/powerpc/perf/core-book3s.c @@ -1602,8 +1602,7 @@ static int collect_events(struct perf_event *group, i= nt max_count, events[n++] =3D group->hw.config; } for_each_sibling_event(event, group) { - if (event->pmu->task_ctx_nr =3D=3D perf_hw_context && - event->state !=3D PERF_EVENT_STATE_OFF) { + if (event->pmu->task_ctx_nr =3D=3D perf_hw_context) { if (n >=3D max_count) return -1; ctrs[n] =3D event; diff --git a/arch/powerpc/perf/core-fsl-emb.c b/arch/powerpc/perf/core-fsl-= emb.c index 7120ab20cbfe..509932b91b75 100644 --- a/arch/powerpc/perf/core-fsl-emb.c +++ b/arch/powerpc/perf/core-fsl-emb.c @@ -261,8 +261,7 @@ static int collect_events(struct perf_event *group, int= max_count, n++; } for_each_sibling_event(event, group) { - if (!is_software_event(event) && - event->state !=3D PERF_EVENT_STATE_OFF) { + if (!is_software_event(event)) { if (n >=3D max_count) return -1; ctrs[n] =3D event; diff --git a/arch/sparc/kernel/perf_event.c b/arch/sparc/kernel/perf_event.c index cae4d33002a5..706127749c66 100644 --- a/arch/sparc/kernel/perf_event.c +++ b/arch/sparc/kernel/perf_event.c @@ -1357,8 +1357,7 @@ static int collect_events(struct perf_event *group, i= nt max_count, current_idx[n++] =3D PIC_NO_INDEX; } for_each_sibling_event(event, group) { - if (!is_software_event(event) && - event->state !=3D PERF_EVENT_STATE_OFF) { + if (!is_software_event(event)) { if (n >=3D max_count) return -1; evts[n] =3D event; diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index 7610f26dfbd9..eca5bb49aa85 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -1211,7 +1211,7 @@ static int collect_events(struct cpu_hw_events *cpuc,= struct perf_event *leader, return n; =20 for_each_sibling_event(event, leader) { - if (!is_x86_event(event) || event->state <=3D PERF_EVENT_STATE_OFF) + if (!is_x86_event(event)) continue; =20 if (collect_event(cpuc, event, max_count, n)) diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c index a762f7f5b161..297ff5adb667 100644 --- a/arch/x86/events/intel/uncore.c +++ b/arch/x86/events/intel/uncore.c @@ -406,8 +406,7 @@ uncore_collect_events(struct intel_uncore_box *box, str= uct perf_event *leader, return n; =20 for_each_sibling_event(event, leader) { - if (!is_box_event(box, event) || - event->state <=3D PERF_EVENT_STATE_OFF) + if (!is_box_event(box, event)) continue; =20 if (n >=3D max_count) diff --git a/drivers/dma/idxd/perfmon.c b/drivers/dma/idxd/perfmon.c index 4b6af2f15d8a..8c539e1f11da 100644 --- a/drivers/dma/idxd/perfmon.c +++ b/drivers/dma/idxd/perfmon.c @@ -75,8 +75,7 @@ static int perfmon_collect_events(struct idxd_pmu *idxd_p= mu, return n; =20 for_each_sibling_event(event, leader) { - if (!is_idxd_event(idxd_pmu, event) || - event->state <=3D PERF_EVENT_STATE_OFF) + if (!is_idxd_event(idxd_pmu, event)) continue; =20 if (n >=3D max_count) diff --git a/drivers/perf/arm_pmu.c b/drivers/perf/arm_pmu.c index 5c310e803dd7..e8a3c8e99da0 100644 --- a/drivers/perf/arm_pmu.c +++ b/drivers/perf/arm_pmu.c @@ -386,12 +386,6 @@ validate_event(struct pmu *pmu, struct pmu_hw_events *= hw_events, if (event->pmu !=3D pmu) return 0; =20 - if (event->state < PERF_EVENT_STATE_OFF) - return 1; - - if (event->state =3D=3D PERF_EVENT_STATE_OFF && !event->attr.enable_on_ex= ec) - return 1; - armpmu =3D to_arm_pmu(event->pmu); return armpmu->get_event_idx(hw_events, event) >=3D 0; } --=20 2.39.2.101.g768bb238c484.dirty From nobody Sat Oct 4 19:14:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 87A6D305E18; Wed, 13 Aug 2025 17:02:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755104546; cv=none; b=UEvGOjDTqaGHgTMQ48t0AYzMX90CNWB6vpD+/kKLqUuAKe/Y6BMIVGX4RCRFthc8IW4dU65mEI1f8tS+Pqdj+CKvMVT78iZW/6NMicdvp8CRDh7IogILttxu+JF1PwdETIGhKBmDyQa33nuAQFe5FPbgQZtQGO0zRkPQbkcCrnc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755104546; c=relaxed/simple; bh=rZAJzvysQNWkdQ+SdINufkykLB1u/B8zWt9sTJ/nKig=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=E9DHUnhJNJ9j2HBVpLgujRvl+C+oet6Az1YSmL3MZUSRucqRtw9JXjlX9OjKlLj+UKmgPPAQNZAg9RPHY87KBTd62VHmnTtspZA7Yg065dZbrvIzeIEkwJZI5BXLUQvQ0S55ginD8BWq5R/v6t3nX/eAQ075zSCsxNjpLW3ME/k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B6F701D6F; Wed, 13 Aug 2025 10:02:15 -0700 (PDT) Received: from e121345-lin.cambridge.arm.com (e121345-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A1A5F3F738; Wed, 13 Aug 2025 10:02:19 -0700 (PDT) From: Robin Murphy To: peterz@infradead.org, mingo@redhat.com, will@kernel.org, mark.rutland@arm.com, acme@kernel.org, namhyung@kernel.org, alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, adrian.hunter@intel.com, kan.liang@linux.intel.com Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-alpha@vger.kernel.org, linux-snps-arc@lists.infradead.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, linux-csky@vger.kernel.org, loongarch@lists.linux.dev, linux-mips@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, linux-pm@vger.kernel.org, linux-rockchip@lists.infradead.org, dmaengine@vger.kernel.org, linux-fpga@vger.kernel.org, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, coresight@lists.linaro.org, iommu@lists.linux.dev, linux-amlogic@lists.infradead.org, linux-cxl@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH 13/19] perf: Add helper for checking grouped events Date: Wed, 13 Aug 2025 18:01:05 +0100 Message-Id: X-Mailer: git-send-email 2.39.2.101.g768bb238c484.dirty In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Several drivers cannot support groups, but enforce this inconsistently (including not at all) in their event_init routines. Add a helper so that such drivers can simply and robustly check for the acceptable conditions that their event is either standalone, or the first one being added to a software-only group. In particular it took a while to see that marvell_cn10k_tad_pmu was seemingly trying to rely on the empirical behaviour of perf tool creating group leader events with disabled=3D1 and subsequent siblings with disabled=3D0. Down with this sort of thing! Signed-off-by: Robin Murphy --- arch/x86/events/amd/ibs.c | 30 ++++++--------------------- drivers/devfreq/event/rockchip-dfi.c | 3 +++ drivers/perf/alibaba_uncore_drw_pmu.c | 11 +--------- drivers/perf/arm_dmc620_pmu.c | 12 +---------- drivers/perf/dwc_pcie_pmu.c | 10 ++------- drivers/perf/marvell_cn10k_tad_pmu.c | 6 ++---- drivers/perf/marvell_pem_pmu.c | 11 ++-------- include/linux/perf_event.h | 7 +++++++ 8 files changed, 24 insertions(+), 66 deletions(-) diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index 112f43b23ebf..95de309fc7d5 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -248,27 +248,6 @@ int forward_event_to_ibs(struct perf_event *event) return -ENOENT; } =20 -/* - * Grouping of IBS events is not possible since IBS can have only - * one event active at any point in time. - */ -static int validate_group(struct perf_event *event) -{ - struct perf_event *sibling; - - if (event->group_leader =3D=3D event) - return 0; - - if (event->group_leader->pmu =3D=3D event->pmu) - return -EINVAL; - - for_each_sibling_event(sibling, event->group_leader) { - if (sibling->pmu =3D=3D event->pmu) - return -EINVAL; - } - return 0; -} - static bool perf_ibs_ldlat_event(struct perf_ibs *perf_ibs, struct perf_event *event) { @@ -309,9 +288,12 @@ static int perf_ibs_init(struct perf_event *event) event->attr.exclude_hv)) return -EINVAL; =20 - ret =3D validate_group(event); - if (ret) - return ret; + /* + * Grouping of IBS events is not possible since IBS can have only + * one event active at any point in time. + */ + if (in_hardware_group(event)) + return -EINVAL; =20 if (hwc->sample_period) { if (config & perf_ibs->cnt_mask) diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/r= ockchip-dfi.c index 0470d7c175f4..88a9ecbe96ce 100644 --- a/drivers/devfreq/event/rockchip-dfi.c +++ b/drivers/devfreq/event/rockchip-dfi.c @@ -413,6 +413,9 @@ static int rockchip_ddr_perf_event_init(struct perf_eve= nt *event) dev_warn(dfi->dev, "Can't provide per-task data!\n"); return -EINVAL; } + /* Disallow groups since we can't start/stop/read multiple counters at on= ce */ + if (in_hardware_group(event)) + return -EINVAL; =20 return 0; } diff --git a/drivers/perf/alibaba_uncore_drw_pmu.c b/drivers/perf/alibaba_u= ncore_drw_pmu.c index 99a0ef9817e0..0081618741c3 100644 --- a/drivers/perf/alibaba_uncore_drw_pmu.c +++ b/drivers/perf/alibaba_uncore_drw_pmu.c @@ -526,7 +526,6 @@ static int ali_drw_pmu_event_init(struct perf_event *ev= ent) { struct ali_drw_pmu *drw_pmu =3D to_ali_drw_pmu(event->pmu); struct hw_perf_event *hwc =3D &event->hw; - struct perf_event *sibling; struct device *dev =3D drw_pmu->pmu.dev; =20 if (event->attr.type !=3D event->pmu->type) @@ -548,19 +547,11 @@ static int ali_drw_pmu_event_init(struct perf_event *= event) return -EOPNOTSUPP; } =20 - if (event->group_leader !=3D event && - !is_software_event(event->group_leader)) { + if (in_hardware_group(event)) { dev_err(dev, "driveway only allow one event!\n"); return -EINVAL; } =20 - for_each_sibling_event(sibling, event->group_leader) { - if (sibling !=3D event && !is_software_event(sibling)) { - dev_err(dev, "driveway event not allowed!\n"); - return -EINVAL; - } - } - /* reset all the pmu counters */ writel(ALI_DRW_PMU_CNT_RST, drw_pmu->cfg_base + ALI_DRW_PMU_CNT_CTRL); =20 diff --git a/drivers/perf/arm_dmc620_pmu.c b/drivers/perf/arm_dmc620_pmu.c index 619cf937602f..24308de80246 100644 --- a/drivers/perf/arm_dmc620_pmu.c +++ b/drivers/perf/arm_dmc620_pmu.c @@ -513,7 +513,6 @@ static int dmc620_pmu_event_init(struct perf_event *eve= nt) { struct dmc620_pmu *dmc620_pmu =3D to_dmc620_pmu(event->pmu); struct hw_perf_event *hwc =3D &event->hw; - struct perf_event *sibling; =20 if (event->attr.type !=3D event->pmu->type) return -ENOENT; @@ -544,22 +543,13 @@ static int dmc620_pmu_event_init(struct perf_event *e= vent) =20 hwc->idx =3D -1; =20 - if (event->group_leader =3D=3D event) - return 0; - /* * We can't atomically disable all HW counters so only one event allowed, * although software events are acceptable. */ - if (!is_software_event(event->group_leader)) + if (in_hardware_group(event)) return -EINVAL; =20 - for_each_sibling_event(sibling, event->group_leader) { - if (sibling !=3D event && - !is_software_event(sibling)) - return -EINVAL; - } - return 0; } =20 diff --git a/drivers/perf/dwc_pcie_pmu.c b/drivers/perf/dwc_pcie_pmu.c index 146ff57813fb..78c522658d84 100644 --- a/drivers/perf/dwc_pcie_pmu.c +++ b/drivers/perf/dwc_pcie_pmu.c @@ -353,7 +353,6 @@ static int dwc_pcie_pmu_event_init(struct perf_event *e= vent) { struct dwc_pcie_pmu *pcie_pmu =3D to_dwc_pcie_pmu(event->pmu); enum dwc_pcie_event_type type =3D DWC_PCIE_EVENT_TYPE(event); - struct perf_event *sibling; u32 lane; =20 if (event->attr.type !=3D event->pmu->type) @@ -367,15 +366,10 @@ static int dwc_pcie_pmu_event_init(struct perf_event = *event) if (event->cpu < 0 || event->attach_state & PERF_ATTACH_TASK) return -EINVAL; =20 - if (event->group_leader !=3D event && - !is_software_event(event->group_leader)) + /* Disallow groups since we can't start/stop/read multiple counters at on= ce */ + if (in_hardware_group(event)) return -EINVAL; =20 - for_each_sibling_event(sibling, event->group_leader) { - if (sibling->pmu !=3D event->pmu && !is_software_event(sibling)) - return -EINVAL; - } - if (type < 0 || type >=3D DWC_PCIE_EVENT_TYPE_MAX) return -EINVAL; =20 diff --git a/drivers/perf/marvell_cn10k_tad_pmu.c b/drivers/perf/marvell_cn= 10k_tad_pmu.c index 51ccb0befa05..ee6505cb01a7 100644 --- a/drivers/perf/marvell_cn10k_tad_pmu.c +++ b/drivers/perf/marvell_cn10k_tad_pmu.c @@ -152,10 +152,8 @@ static int tad_pmu_event_init(struct perf_event *event) if (event->attr.type !=3D event->pmu->type) return -ENOENT; =20 - if (!event->attr.disabled) - return -EINVAL; - - if (event->state !=3D PERF_EVENT_STATE_OFF) + /* Disallow groups since we can't start/stop/read multiple counters at on= ce */ + if (in_hardware_group(event)) return -EINVAL; =20 event->cpu =3D tad_pmu->cpu; diff --git a/drivers/perf/marvell_pem_pmu.c b/drivers/perf/marvell_pem_pmu.c index 29fbcd1848e4..53a35a5de7f8 100644 --- a/drivers/perf/marvell_pem_pmu.c +++ b/drivers/perf/marvell_pem_pmu.c @@ -190,7 +190,6 @@ static int pem_perf_event_init(struct perf_event *event) { struct pem_pmu *pmu =3D to_pem_pmu(event->pmu); struct hw_perf_event *hwc =3D &event->hw; - struct perf_event *sibling; =20 if (event->attr.type !=3D event->pmu->type) return -ENOENT; @@ -206,16 +205,10 @@ static int pem_perf_event_init(struct perf_event *eve= nt) if (event->cpu < 0) return -EOPNOTSUPP; =20 - /* We must NOT create groups containing mixed PMUs */ - if (event->group_leader->pmu !=3D event->pmu && - !is_software_event(event->group_leader)) + /* Disallow groups since we can't start/stop/read multiple counters at on= ce */ + if (in_hardware_group(event)) return -EINVAL; =20 - for_each_sibling_event(sibling, event->group_leader) { - if (sibling->pmu !=3D event->pmu && - !is_software_event(sibling)) - return -EINVAL; - } /* * Set ownership of event to one CPU, same event can not be observed * on multiple cpus at same time. diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h index ec9d96025683..4d439c24c901 100644 --- a/include/linux/perf_event.h +++ b/include/linux/perf_event.h @@ -1556,6 +1556,13 @@ static inline int in_software_context(struct perf_ev= ent *event) return event->pmu_ctx->pmu->task_ctx_nr =3D=3D perf_sw_context; } =20 +/* True if the event has (or would have) any non-software siblings */ +static inline bool in_hardware_group(const struct perf_event *event) +{ + return event !=3D event->group_leader && + !in_software_context(event->group_leader); +} + static inline int is_exclusive_pmu(struct pmu *pmu) { return pmu->capabilities & PERF_PMU_CAP_EXCLUSIVE; --=20 2.39.2.101.g768bb238c484.dirty From nobody Sat Oct 4 19:14:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D2733307ACA; Wed, 13 Aug 2025 17:02:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755104550; cv=none; b=WZn1mcZDnicl8ECcwQAxHsMVTKjErR7WATaSSXoz70ozDfD79IaicFClHOxGvbExqx4/zzQBlBmLHIvE5dxsJFq14I+n/7llBGrybdQkUvkYqjhlEY4DXXO6RiqkBGZh063zUnWYWagyYJX7g5Sl5AIqOYIZPMzaj7BVUigCmxc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Wed, 13 Aug 2025 10:02:24 -0700 (PDT) From: Robin Murphy To: peterz@infradead.org, mingo@redhat.com, will@kernel.org, mark.rutland@arm.com, acme@kernel.org, namhyung@kernel.org, alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, adrian.hunter@intel.com, kan.liang@linux.intel.com Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-alpha@vger.kernel.org, linux-snps-arc@lists.infradead.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, linux-csky@vger.kernel.org, loongarch@lists.linux.dev, linux-mips@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, linux-pm@vger.kernel.org, linux-rockchip@lists.infradead.org, dmaengine@vger.kernel.org, linux-fpga@vger.kernel.org, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, coresight@lists.linaro.org, iommu@lists.linux.dev, linux-amlogic@lists.infradead.org, linux-cxl@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH 14/19] perf: Clean up redundant group validation Date: Wed, 13 Aug 2025 18:01:06 +0100 Message-Id: <778547b3a1c6eb907a7d775c5ac579610ea2be71.1755096883.git.robin.murphy@arm.com> X-Mailer: git-send-email 2.39.2.101.g768bb238c484.dirty In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" None of these drivers are doing anything that perf_event_open() doesn't inherently do as of commit bf480f938566 ("perf/core: Don't allow grouping events from different hw pmus"). While it's quite possible that they should be doing some actual validation of the schedulability of their own events within the given group, for now at least removing this redundant code makes it even clearer that they are not. Signed-off-by: Robin Murphy --- drivers/perf/arm-ccn.c | 16 ---------------- drivers/perf/fsl_imx9_ddr_perf.c | 16 ---------------- drivers/perf/marvell_cn10k_ddr_pmu.c | 5 ----- drivers/perf/xgene_pmu.c | 15 --------------- 4 files changed, 52 deletions(-) diff --git a/drivers/perf/arm-ccn.c b/drivers/perf/arm-ccn.c index 1a0d0e1a2263..63549aad3b99 100644 --- a/drivers/perf/arm-ccn.c +++ b/drivers/perf/arm-ccn.c @@ -708,7 +708,6 @@ static int arm_ccn_pmu_event_init(struct perf_event *ev= ent) u32 node_xp, type, event_id; int valid; int i; - struct perf_event *sibling; =20 if (event->attr.type !=3D event->pmu->type) return -ENOENT; @@ -814,21 +813,6 @@ static int arm_ccn_pmu_event_init(struct perf_event *e= vent) node_xp, type, port); } =20 - /* - * We must NOT create groups containing mixed PMUs, although software - * events are acceptable (for example to create a CCN group - * periodically read when a hrtimer aka cpu-clock leader triggers). - */ - if (event->group_leader->pmu !=3D event->pmu && - !is_software_event(event->group_leader)) - return -EINVAL; - - for_each_sibling_event(sibling, event->group_leader) { - if (sibling->pmu !=3D event->pmu && - !is_software_event(sibling)) - return -EINVAL; - } - return 0; } =20 diff --git a/drivers/perf/fsl_imx9_ddr_perf.c b/drivers/perf/fsl_imx9_ddr_p= erf.c index 267754fdf581..85874ec5ecd0 100644 --- a/drivers/perf/fsl_imx9_ddr_perf.c +++ b/drivers/perf/fsl_imx9_ddr_perf.c @@ -552,7 +552,6 @@ static int ddr_perf_event_init(struct perf_event *event) { struct ddr_pmu *pmu =3D to_ddr_pmu(event->pmu); struct hw_perf_event *hwc =3D &event->hw; - struct perf_event *sibling; =20 if (event->attr.type !=3D event->pmu->type) return -ENOENT; @@ -565,21 +564,6 @@ static int ddr_perf_event_init(struct perf_event *even= t) return -EOPNOTSUPP; } =20 - /* - * We must NOT create groups containing mixed PMUs, although software - * events are acceptable (for example to create a CCN group - * periodically read when a hrtimer aka cpu-clock leader triggers). - */ - if (event->group_leader->pmu !=3D event->pmu && - !is_software_event(event->group_leader)) - return -EINVAL; - - for_each_sibling_event(sibling, event->group_leader) { - if (sibling->pmu !=3D event->pmu && - !is_software_event(sibling)) - return -EINVAL; - } - event->cpu =3D pmu->cpu; hwc->idx =3D -1; =20 diff --git a/drivers/perf/marvell_cn10k_ddr_pmu.c b/drivers/perf/marvell_cn= 10k_ddr_pmu.c index 72ac17efd846..54e3fd206d39 100644 --- a/drivers/perf/marvell_cn10k_ddr_pmu.c +++ b/drivers/perf/marvell_cn10k_ddr_pmu.c @@ -487,11 +487,6 @@ static int cn10k_ddr_perf_event_init(struct perf_event= *event) return -EOPNOTSUPP; } =20 - /* We must NOT create groups containing mixed PMUs */ - if (event->group_leader->pmu !=3D event->pmu && - !is_software_event(event->group_leader)) - return -EINVAL; - /* Set ownership of event to one CPU, same event can not be observed * on multiple cpus at same time. */ diff --git a/drivers/perf/xgene_pmu.c b/drivers/perf/xgene_pmu.c index 33b5497bdc06..5e80ae0e692d 100644 --- a/drivers/perf/xgene_pmu.c +++ b/drivers/perf/xgene_pmu.c @@ -877,7 +877,6 @@ static int xgene_perf_event_init(struct perf_event *eve= nt) { struct xgene_pmu_dev *pmu_dev =3D to_pmu_dev(event->pmu); struct hw_perf_event *hw =3D &event->hw; - struct perf_event *sibling; =20 /* Test the event attr type check for PMU enumeration */ if (event->attr.type !=3D event->pmu->type) @@ -913,20 +912,6 @@ static int xgene_perf_event_init(struct perf_event *ev= ent) */ hw->config_base =3D event->attr.config1; =20 - /* - * We must NOT create groups containing mixed PMUs, although software - * events are acceptable - */ - if (event->group_leader->pmu !=3D event->pmu && - !is_software_event(event->group_leader)) - return -EINVAL; - - for_each_sibling_event(sibling, event->group_leader) { - if (sibling->pmu !=3D event->pmu && - !is_software_event(sibling)) - return -EINVAL; - } - return 0; } =20 --=20 2.39.2.101.g768bb238c484.dirty From nobody Sat Oct 4 19:14:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 7F52A305E3F; Wed, 13 Aug 2025 17:02:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; 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Wed, 13 Aug 2025 10:02:24 -0700 (PDT) Received: from e121345-lin.cambridge.arm.com (e121345-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A75D43F738; Wed, 13 Aug 2025 10:02:28 -0700 (PDT) From: Robin Murphy To: peterz@infradead.org, mingo@redhat.com, will@kernel.org, mark.rutland@arm.com, acme@kernel.org, namhyung@kernel.org, alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, adrian.hunter@intel.com, kan.liang@linux.intel.com Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-alpha@vger.kernel.org, linux-snps-arc@lists.infradead.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, linux-csky@vger.kernel.org, loongarch@lists.linux.dev, linux-mips@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, linux-pm@vger.kernel.org, linux-rockchip@lists.infradead.org, dmaengine@vger.kernel.org, linux-fpga@vger.kernel.org, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, coresight@lists.linaro.org, iommu@lists.linux.dev, linux-amlogic@lists.infradead.org, linux-cxl@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH 15/19] perf: Simplify group validation Date: Wed, 13 Aug 2025 18:01:07 +0100 Message-Id: <8e86d5021812c720219c8843e5179fe03e5c4de4.1755096883.git.robin.murphy@arm.com> X-Mailer: git-send-email 2.39.2.101.g768bb238c484.dirty In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" All of these drivers copy a pattern of actively policing cross-PMU groups, which is redundant since commit bf480f938566 ("perf/core: Don't allow grouping events from different hw pmus"). Clean up these checks to simplfy matters, especially for thunderx2 which can reduce right down to trivial counting. Signed-off-by: Robin Murphy --- drivers/perf/arm_cspmu/arm_cspmu.c | 7 ++----- drivers/perf/arm_dsu_pmu.c | 6 ++---- drivers/perf/arm_pmu.c | 11 ++--------- drivers/perf/thunderx2_pmu.c | 30 +++++++----------------------- 4 files changed, 13 insertions(+), 41 deletions(-) diff --git a/drivers/perf/arm_cspmu/arm_cspmu.c b/drivers/perf/arm_cspmu/ar= m_cspmu.c index efa9b229e701..7f5ea749b85c 100644 --- a/drivers/perf/arm_cspmu/arm_cspmu.c +++ b/drivers/perf/arm_cspmu/arm_cspmu.c @@ -561,12 +561,9 @@ static bool arm_cspmu_validate_event(struct pmu *pmu, struct arm_cspmu_hw_events *hw_events, struct perf_event *event) { - if (is_software_event(event)) - return true; - - /* Reject groups spanning multiple HW PMUs. */ + /* Ignore grouped events that aren't ours */ if (event->pmu !=3D pmu) - return false; + return true; =20 return (arm_cspmu_get_event_idx(hw_events, event) >=3D 0); } diff --git a/drivers/perf/arm_dsu_pmu.c b/drivers/perf/arm_dsu_pmu.c index cb4fb59fe04b..7480fd6fe377 100644 --- a/drivers/perf/arm_dsu_pmu.c +++ b/drivers/perf/arm_dsu_pmu.c @@ -492,11 +492,9 @@ static bool dsu_pmu_validate_event(struct pmu *pmu, struct dsu_hw_events *hw_events, struct perf_event *event) { - if (is_software_event(event)) - return true; - /* Reject groups spanning multiple HW PMUs. */ + /* Ignore grouped events that aren't ours */ if (event->pmu !=3D pmu) - return false; + return true; return dsu_pmu_get_event_idx(hw_events, event) >=3D 0; } =20 diff --git a/drivers/perf/arm_pmu.c b/drivers/perf/arm_pmu.c index e8a3c8e99da0..2c1af3a0207c 100644 --- a/drivers/perf/arm_pmu.c +++ b/drivers/perf/arm_pmu.c @@ -375,16 +375,9 @@ validate_event(struct pmu *pmu, struct pmu_hw_events *= hw_events, { struct arm_pmu *armpmu; =20 - if (is_software_event(event)) - return 1; - - /* - * Reject groups spanning multiple HW PMUs (e.g. CPU + CCI). The - * core perf code won't check that the pmu->ctx =3D=3D leader->ctx - * until after pmu->event_init(event). - */ + /* Ignore grouped events that aren't ours */ if (event->pmu !=3D pmu) - return 0; + return 1; =20 armpmu =3D to_arm_pmu(event->pmu); return armpmu->get_event_idx(hw_events, event) >=3D 0; diff --git a/drivers/perf/thunderx2_pmu.c b/drivers/perf/thunderx2_pmu.c index 6ed4707bd6bb..472eb4494fd1 100644 --- a/drivers/perf/thunderx2_pmu.c +++ b/drivers/perf/thunderx2_pmu.c @@ -519,19 +519,6 @@ static enum tx2_uncore_type get_tx2_pmu_type(struct ac= pi_device *adev) return (enum tx2_uncore_type)id->driver_data; } =20 -static bool tx2_uncore_validate_event(struct pmu *pmu, - struct perf_event *event, int *counters) -{ - if (is_software_event(event)) - return true; - /* Reject groups spanning multiple HW PMUs. */ - if (event->pmu !=3D pmu) - return false; - - *counters =3D *counters + 1; - return true; -} - /* * Make sure the group of events can be scheduled at once * on the PMU. @@ -539,23 +526,20 @@ static bool tx2_uncore_validate_event(struct pmu *pmu, static bool tx2_uncore_validate_event_group(struct perf_event *event, int max_counters) { - struct perf_event *sibling, *leader =3D event->group_leader; - int counters =3D 0; + struct perf_event *sibling; + int counters =3D 1; =20 if (event->group_leader =3D=3D event) return true; =20 - if (!tx2_uncore_validate_event(event->pmu, leader, &counters)) - return false; + if (event->group_leader->pmu =3D=3D event->pmu) + ++counters; =20 - for_each_sibling_event(sibling, leader) { - if (!tx2_uncore_validate_event(event->pmu, sibling, &counters)) - return false; + for_each_sibling_event(sibling, event->group_leader) { + if (sibling->pmu =3D=3D event->pmu) + ++counters; } =20 - if (!tx2_uncore_validate_event(event->pmu, event, &counters)) - return false; - /* * If the group requires more counters than the HW has, * it cannot ever be scheduled. --=20 2.39.2.101.g768bb238c484.dirty From nobody Sat Oct 4 19:14:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id CAC85309DB7; Wed, 13 Aug 2025 17:02:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; 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Wed, 13 Aug 2025 10:02:29 -0700 (PDT) Received: from e121345-lin.cambridge.arm.com (e121345-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 304C73F738; Wed, 13 Aug 2025 10:02:33 -0700 (PDT) From: Robin Murphy To: peterz@infradead.org, mingo@redhat.com, will@kernel.org, mark.rutland@arm.com, acme@kernel.org, namhyung@kernel.org, alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, adrian.hunter@intel.com, kan.liang@linux.intel.com Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-alpha@vger.kernel.org, linux-snps-arc@lists.infradead.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, linux-csky@vger.kernel.org, loongarch@lists.linux.dev, linux-mips@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, linux-pm@vger.kernel.org, linux-rockchip@lists.infradead.org, dmaengine@vger.kernel.org, linux-fpga@vger.kernel.org, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, coresight@lists.linaro.org, iommu@lists.linux.dev, linux-amlogic@lists.infradead.org, linux-cxl@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH 16/19] perf: Introduce positive capability for sampling Date: Wed, 13 Aug 2025 18:01:08 +0100 Message-Id: X-Mailer: git-send-email 2.39.2.101.g768bb238c484.dirty In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Sampling is inherently a feature for CPU PMUs, given that the thing to be sampled is a CPU context. These days, we have many more uncore/system PMUs than CPU PMUs, so it no longer makes much sense to assume sampling support by default and force the ever-growing majority of drivers to opt out of it (or erroneously fail to). Instead, let's introduce a positive opt-in capability that's more obvious and easier to maintain. Signed-off-by: Robin Murphy --- arch/alpha/kernel/perf_event.c | 3 ++- arch/arc/kernel/perf_event.c | 2 ++ arch/csky/kernel/perf_event.c | 2 ++ arch/loongarch/kernel/perf_event.c | 1 + arch/mips/kernel/perf_event_mipsxx.c | 1 + arch/powerpc/perf/core-book3s.c | 1 + arch/powerpc/perf/core-fsl-emb.c | 1 + arch/powerpc/perf/imc-pmu.c | 1 + arch/s390/kernel/perf_cpum_cf.c | 1 + arch/s390/kernel/perf_cpum_sf.c | 2 ++ arch/s390/kernel/perf_pai_crypto.c | 1 + arch/s390/kernel/perf_pai_ext.c | 1 + arch/sparc/kernel/perf_event.c | 1 + arch/x86/events/amd/ibs.c | 2 ++ arch/x86/events/core.c | 4 +++- arch/xtensa/kernel/perf_event.c | 1 + drivers/perf/arm_pmu.c | 3 ++- drivers/perf/arm_pmu_platform.c | 1 + drivers/perf/arm_spe_pmu.c | 3 ++- drivers/perf/riscv_pmu_sbi.c | 2 ++ include/linux/perf_event.h | 3 ++- kernel/events/core.c | 20 +++++++++++--------- kernel/events/hw_breakpoint.c | 1 + 23 files changed, 44 insertions(+), 14 deletions(-) diff --git a/arch/alpha/kernel/perf_event.c b/arch/alpha/kernel/perf_event.c index 8557165e64c0..4de1802d249f 100644 --- a/arch/alpha/kernel/perf_event.c +++ b/arch/alpha/kernel/perf_event.c @@ -761,7 +761,8 @@ static struct pmu pmu =3D { .start =3D alpha_pmu_start, .stop =3D alpha_pmu_stop, .read =3D alpha_pmu_read, - .capabilities =3D PERF_PMU_CAP_NO_EXCLUDE, + .capabilities =3D PERF_PMU_CAP_SAMPLING | + PERF_PMU_CAP_NO_EXCLUDE, }; =20 =20 diff --git a/arch/arc/kernel/perf_event.c b/arch/arc/kernel/perf_event.c index ed6d4f0cd621..1b99b0215027 100644 --- a/arch/arc/kernel/perf_event.c +++ b/arch/arc/kernel/perf_event.c @@ -818,6 +818,8 @@ static int arc_pmu_device_probe(struct platform_device = *pdev) =20 if (irq =3D=3D -1) arc_pmu->pmu.capabilities |=3D PERF_PMU_CAP_NO_INTERRUPT; + else + arc_pmu->pmu.capabilities |=3D PERF_PMU_CAP_SAMPLING; =20 /* * perf parser doesn't really like '-' symbol in events name, so let's diff --git a/arch/csky/kernel/perf_event.c b/arch/csky/kernel/perf_event.c index e0a36acd265b..c5ba6e235a6f 100644 --- a/arch/csky/kernel/perf_event.c +++ b/arch/csky/kernel/perf_event.c @@ -1204,6 +1204,7 @@ int init_hw_perf_events(void) } =20 csky_pmu.pmu =3D (struct pmu) { + .capabilities =3D PERF_PMU_CAP_SAMPLING, .pmu_enable =3D csky_pmu_enable, .pmu_disable =3D csky_pmu_disable, .event_init =3D csky_pmu_event_init, @@ -1314,6 +1315,7 @@ int csky_pmu_device_probe(struct platform_device *pde= v, =20 ret =3D csky_pmu_request_irq(csky_pmu_handle_irq); if (ret) { + csky_pmu.pmu.capabilities &=3D ~PERF_PMU_CAP_SAMPLING; csky_pmu.pmu.capabilities |=3D PERF_PMU_CAP_NO_INTERRUPT; pr_notice("[perf] PMU request irq fail!\n"); } diff --git a/arch/loongarch/kernel/perf_event.c b/arch/loongarch/kernel/per= f_event.c index 8ad098703488..341b17bedd0e 100644 --- a/arch/loongarch/kernel/perf_event.c +++ b/arch/loongarch/kernel/perf_event.c @@ -571,6 +571,7 @@ static int loongarch_pmu_event_init(struct perf_event *= event) } =20 static struct pmu pmu =3D { + .capabilities =3D PERF_PMU_CAP_SAMPLING, .pmu_enable =3D loongarch_pmu_enable, .pmu_disable =3D loongarch_pmu_disable, .event_init =3D loongarch_pmu_event_init, diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_e= vent_mipsxx.c index 196a070349b0..4c5d64d1158e 100644 --- a/arch/mips/kernel/perf_event_mipsxx.c +++ b/arch/mips/kernel/perf_event_mipsxx.c @@ -687,6 +687,7 @@ static int mipspmu_event_init(struct perf_event *event) } =20 static struct pmu pmu =3D { + .capabilities =3D PERF_PMU_CAP_SAMPLING, .pmu_enable =3D mipspmu_enable, .pmu_disable =3D mipspmu_disable, .event_init =3D mipspmu_event_init, diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3= s.c index d67f7d511f13..cfe7d3c120e1 100644 --- a/arch/powerpc/perf/core-book3s.c +++ b/arch/powerpc/perf/core-book3s.c @@ -2207,6 +2207,7 @@ ssize_t power_events_sysfs_show(struct device *dev, } =20 static struct pmu power_pmu =3D { + .capabilities =3D PERF_PMU_CAP_SAMPLING, .pmu_enable =3D power_pmu_enable, .pmu_disable =3D power_pmu_disable, .event_init =3D power_pmu_event_init, diff --git a/arch/powerpc/perf/core-fsl-emb.c b/arch/powerpc/perf/core-fsl-= emb.c index 509932b91b75..62038ff3663f 100644 --- a/arch/powerpc/perf/core-fsl-emb.c +++ b/arch/powerpc/perf/core-fsl-emb.c @@ -570,6 +570,7 @@ static int fsl_emb_pmu_event_init(struct perf_event *ev= ent) } =20 static struct pmu fsl_emb_pmu =3D { + .capabilities =3D PERF_PMU_CAP_SAMPLING, .pmu_enable =3D fsl_emb_pmu_enable, .pmu_disable =3D fsl_emb_pmu_disable, .event_init =3D fsl_emb_pmu_event_init, diff --git a/arch/powerpc/perf/imc-pmu.c b/arch/powerpc/perf/imc-pmu.c index 8664a7d297ad..f352dda3baf9 100644 --- a/arch/powerpc/perf/imc-pmu.c +++ b/arch/powerpc/perf/imc-pmu.c @@ -1507,6 +1507,7 @@ static int update_pmu_ops(struct imc_pmu *pmu) pmu->pmu.commit_txn =3D thread_imc_pmu_commit_txn; break; case IMC_DOMAIN_TRACE: + pmu->pmu.capabilities |=3D PERF_PMU_CAP_SAMPLING; pmu->pmu.event_init =3D trace_imc_event_init; pmu->pmu.add =3D trace_imc_event_add; pmu->pmu.del =3D trace_imc_event_del; diff --git a/arch/s390/kernel/perf_cpum_cf.c b/arch/s390/kernel/perf_cpum_c= f.c index 4d09954ebf49..7d10842d54f0 100644 --- a/arch/s390/kernel/perf_cpum_cf.c +++ b/arch/s390/kernel/perf_cpum_cf.c @@ -1861,6 +1861,7 @@ static const struct attribute_group *cfdiag_attr_grou= ps[] =3D { */ static struct pmu cf_diag =3D { .task_ctx_nr =3D perf_sw_context, + .capabilities =3D PERF_PMU_CAP_SAMPLING, .event_init =3D cfdiag_event_init, .pmu_enable =3D cpumf_pmu_enable, .pmu_disable =3D cpumf_pmu_disable, diff --git a/arch/s390/kernel/perf_cpum_sf.c b/arch/s390/kernel/perf_cpum_s= f.c index f432869f8921..3d2c400f0aaa 100644 --- a/arch/s390/kernel/perf_cpum_sf.c +++ b/arch/s390/kernel/perf_cpum_sf.c @@ -1892,6 +1892,8 @@ static const struct attribute_group *cpumsf_pmu_attr_= groups[] =3D { }; =20 static struct pmu cpumf_sampling =3D { + .capabilities =3D PERF_PMU_CAP_SAMPLING, + .pmu_enable =3D cpumsf_pmu_enable, .pmu_disable =3D cpumsf_pmu_disable, =20 diff --git a/arch/s390/kernel/perf_pai_crypto.c b/arch/s390/kernel/perf_pai= _crypto.c index f373a1009c45..a64b6b056a21 100644 --- a/arch/s390/kernel/perf_pai_crypto.c +++ b/arch/s390/kernel/perf_pai_crypto.c @@ -569,6 +569,7 @@ static const struct attribute_group *paicrypt_attr_grou= ps[] =3D { /* Performance monitoring unit for mapped counters */ static struct pmu paicrypt =3D { .task_ctx_nr =3D perf_hw_context, + .capabilities =3D PERF_PMU_CAP_SAMPLING, .event_init =3D paicrypt_event_init, .add =3D paicrypt_add, .del =3D paicrypt_del, diff --git a/arch/s390/kernel/perf_pai_ext.c b/arch/s390/kernel/perf_pai_ex= t.c index d827473e7f87..1261f80c6d52 100644 --- a/arch/s390/kernel/perf_pai_ext.c +++ b/arch/s390/kernel/perf_pai_ext.c @@ -595,6 +595,7 @@ static const struct attribute_group *paiext_attr_groups= [] =3D { /* Performance monitoring unit for mapped counters */ static struct pmu paiext =3D { .task_ctx_nr =3D perf_hw_context, + .capabilities =3D PERF_PMU_CAP_SAMPLING, .event_init =3D paiext_event_init, .add =3D paiext_add, .del =3D paiext_del, diff --git a/arch/sparc/kernel/perf_event.c b/arch/sparc/kernel/perf_event.c index 706127749c66..6ecea8e7b592 100644 --- a/arch/sparc/kernel/perf_event.c +++ b/arch/sparc/kernel/perf_event.c @@ -1573,6 +1573,7 @@ static int sparc_pmu_commit_txn(struct pmu *pmu) } =20 static struct pmu pmu =3D { + .capabilities =3D PERF_PMU_CAP_SAMPLING, .pmu_enable =3D sparc_pmu_enable, .pmu_disable =3D sparc_pmu_disable, .event_init =3D sparc_pmu_event_init, diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index 95de309fc7d5..ed07d80b6fe0 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -768,6 +768,7 @@ static struct perf_ibs perf_ibs_fetch =3D { .pmu =3D { .task_ctx_nr =3D perf_hw_context, =20 + .capabilities =3D PERF_PMU_CAP_SAMPLING, .event_init =3D perf_ibs_init, .add =3D perf_ibs_add, .del =3D perf_ibs_del, @@ -793,6 +794,7 @@ static struct perf_ibs perf_ibs_op =3D { .pmu =3D { .task_ctx_nr =3D perf_hw_context, =20 + .capabilities =3D PERF_PMU_CAP_SAMPLING, .event_init =3D perf_ibs_init, .add =3D perf_ibs_add, .del =3D perf_ibs_del, diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index eca5bb49aa85..72a4c43951ee 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -1837,7 +1837,7 @@ static void __init pmu_check_apic(void) * sample via a hrtimer based software event): */ pmu.capabilities |=3D PERF_PMU_CAP_NO_INTERRUPT; - + pmu.capabilities &=3D ~PERF_PMU_CAP_SAMPLING; } =20 static struct attribute_group x86_pmu_format_group __ro_after_init =3D { @@ -2698,6 +2698,8 @@ static bool x86_pmu_filter(struct pmu *pmu, int cpu) } =20 static struct pmu pmu =3D { + .capabilities =3D PERF_PMU_CAP_SAMPLING, + .pmu_enable =3D x86_pmu_enable, .pmu_disable =3D x86_pmu_disable, =20 diff --git a/arch/xtensa/kernel/perf_event.c b/arch/xtensa/kernel/perf_even= t.c index 223f1d452310..b03a2feb0f92 100644 --- a/arch/xtensa/kernel/perf_event.c +++ b/arch/xtensa/kernel/perf_event.c @@ -397,6 +397,7 @@ irqreturn_t xtensa_pmu_irq_handler(int irq, void *dev_i= d) } =20 static struct pmu xtensa_pmu =3D { + .capabilities =3D PERF_PMU_CAP_SAMPLING, .pmu_enable =3D xtensa_pmu_enable, .pmu_disable =3D xtensa_pmu_disable, .event_init =3D xtensa_pmu_event_init, diff --git a/drivers/perf/arm_pmu.c b/drivers/perf/arm_pmu.c index 2c1af3a0207c..72d8f38d0aa5 100644 --- a/drivers/perf/arm_pmu.c +++ b/drivers/perf/arm_pmu.c @@ -876,7 +876,8 @@ struct arm_pmu *armpmu_alloc(void) * PERF_TYPE_HARDWARE and PERF_TYPE_HW_CACHE events on a * specific PMU. */ - .capabilities =3D PERF_PMU_CAP_EXTENDED_REGS | + .capabilities =3D PERF_PMU_CAP_SAMPLING | + PERF_PMU_CAP_EXTENDED_REGS | PERF_PMU_CAP_EXTENDED_HW_TYPE, }; =20 diff --git a/drivers/perf/arm_pmu_platform.c b/drivers/perf/arm_pmu_platfor= m.c index 118170a5cede..ab7a802cd0d6 100644 --- a/drivers/perf/arm_pmu_platform.c +++ b/drivers/perf/arm_pmu_platform.c @@ -109,6 +109,7 @@ static int pmu_parse_irqs(struct arm_pmu *pmu) */ if (num_irqs =3D=3D 0) { dev_warn(dev, "no irqs for PMU, sampling events not supported\n"); + pmu->pmu.capabilities &=3D ~PERF_PMU_CAP_SAMPLING; pmu->pmu.capabilities |=3D PERF_PMU_CAP_NO_INTERRUPT; cpumask_setall(&pmu->supported_cpus); return 0; diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c index 369e77ad5f13..dbd52851f5c6 100644 --- a/drivers/perf/arm_spe_pmu.c +++ b/drivers/perf/arm_spe_pmu.c @@ -955,7 +955,8 @@ static int arm_spe_pmu_perf_init(struct arm_spe_pmu *sp= e_pmu) spe_pmu->pmu =3D (struct pmu) { .module =3D THIS_MODULE, .parent =3D &spe_pmu->pdev->dev, - .capabilities =3D PERF_PMU_CAP_EXCLUSIVE | PERF_PMU_CAP_ITRACE, + .capabilities =3D PERF_PMU_CAP_SAMPLING | + PERF_PMU_CAP_EXCLUSIVE | PERF_PMU_CAP_ITRACE, .attr_groups =3D arm_spe_pmu_attr_groups, /* * We hitch a ride on the software context here, so that diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 698de8ddf895..d185ea8c47ba 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -1361,6 +1361,8 @@ static int pmu_sbi_device_probe(struct platform_devic= e *pdev) pr_info("Perf sampling/filtering is not supported as sscof extension is = not available\n"); pmu->pmu.capabilities |=3D PERF_PMU_CAP_NO_INTERRUPT; pmu->pmu.capabilities |=3D PERF_PMU_CAP_NO_EXCLUDE; + } else { + pmu->pmu.capabilities |=3D PERF_PMU_CAP_SAMPLING; } =20 pmu->pmu.attr_groups =3D riscv_pmu_attr_groups; diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h index 4d439c24c901..bf2cfbeabba2 100644 --- a/include/linux/perf_event.h +++ b/include/linux/perf_event.h @@ -294,7 +294,7 @@ struct perf_event_pmu_context; /** * pmu::capabilities flags */ -#define PERF_PMU_CAP_NO_INTERRUPT 0x0001 +#define PERF_PMU_CAP_SAMPLING 0x0001 #define PERF_PMU_CAP_NO_NMI 0x0002 #define PERF_PMU_CAP_AUX_NO_SG 0x0004 #define PERF_PMU_CAP_EXTENDED_REGS 0x0008 @@ -305,6 +305,7 @@ struct perf_event_pmu_context; #define PERF_PMU_CAP_EXTENDED_HW_TYPE 0x0100 #define PERF_PMU_CAP_AUX_PAUSE 0x0200 #define PERF_PMU_CAP_AUX_PREFER_LARGE 0x0400 +#define PERF_PMU_CAP_NO_INTERRUPT 0x0800 =20 /** * pmu::scope diff --git a/kernel/events/core.c b/kernel/events/core.c index 8060c2857bb2..71b2a6730705 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -4359,7 +4359,7 @@ perf_adjust_freq_unthr_context(struct perf_event_cont= ext *ctx, bool unthrottle) continue; if (!perf_pmu_ctx_is_active(pmu_ctx)) continue; - if (pmu_ctx->pmu->capabilities & PERF_PMU_CAP_NO_INTERRUPT) + if (!(pmu_ctx->pmu->capabilities & PERF_PMU_CAP_SAMPLING)) continue; =20 perf_pmu_disable(pmu_ctx->pmu); @@ -10819,7 +10819,7 @@ static int perf_swevent_init(struct perf_event *eve= nt) static struct pmu perf_swevent =3D { .task_ctx_nr =3D perf_sw_context, =20 - .capabilities =3D PERF_PMU_CAP_NO_NMI, + .capabilities =3D PERF_PMU_CAP_SAMPLING | PERF_PMU_CAP_NO_NMI, =20 .event_init =3D perf_swevent_init, .add =3D perf_swevent_add, @@ -10861,6 +10861,7 @@ static int perf_tp_event_init(struct perf_event *ev= ent) static struct pmu perf_tracepoint =3D { .task_ctx_nr =3D perf_sw_context, =20 + .capabilities =3D PERF_PMU_CAP_SAMPLING, .event_init =3D perf_tp_event_init, .add =3D perf_trace_add, .del =3D perf_trace_del, @@ -11066,6 +11067,7 @@ static struct pmu perf_kprobe =3D { .stop =3D perf_swevent_stop, .read =3D perf_swevent_read, .attr_groups =3D kprobe_attr_groups, + .capabilities =3D PERF_PMU_CAP_SAMPLING, }; =20 static int perf_kprobe_event_init(struct perf_event *event) @@ -11125,6 +11127,7 @@ static struct pmu perf_uprobe =3D { .stop =3D perf_swevent_stop, .read =3D perf_swevent_read, .attr_groups =3D uprobe_attr_groups, + .capabilities =3D PERF_PMU_CAP_SAMPLING, }; =20 static int perf_uprobe_event_init(struct perf_event *event) @@ -11899,7 +11902,7 @@ static int cpu_clock_event_init(struct perf_event *= event) static struct pmu perf_cpu_clock =3D { .task_ctx_nr =3D perf_sw_context, =20 - .capabilities =3D PERF_PMU_CAP_NO_NMI, + .capabilities =3D PERF_PMU_CAP_SAMPLING | PERF_PMU_CAP_NO_NMI, .dev =3D PMU_NULL_DEV, =20 .event_init =3D cpu_clock_event_init, @@ -11982,7 +11985,7 @@ static int task_clock_event_init(struct perf_event = *event) static struct pmu perf_task_clock =3D { .task_ctx_nr =3D perf_sw_context, =20 - .capabilities =3D PERF_PMU_CAP_NO_NMI, + .capabilities =3D PERF_PMU_CAP_SAMPLING | PERF_PMU_CAP_NO_NMI, .dev =3D PMU_NULL_DEV, =20 .event_init =3D task_clock_event_init, @@ -13476,11 +13479,10 @@ SYSCALL_DEFINE5(perf_event_open, goto err_task; } =20 - if (is_sampling_event(event)) { - if (event->pmu->capabilities & PERF_PMU_CAP_NO_INTERRUPT) { - err =3D -EOPNOTSUPP; - goto err_alloc; - } + if (is_sampling_event(event) && + !(event->pmu->capabilities & PERF_PMU_CAP_SAMPLING)) { + err =3D -EOPNOTSUPP; + goto err_alloc; } =20 /* diff --git a/kernel/events/hw_breakpoint.c b/kernel/events/hw_breakpoint.c index 8ec2cb688903..604be7d7aecf 100644 --- a/kernel/events/hw_breakpoint.c +++ b/kernel/events/hw_breakpoint.c @@ -996,6 +996,7 @@ static void hw_breakpoint_stop(struct perf_event *bp, i= nt flags) static struct pmu perf_breakpoint =3D { .task_ctx_nr =3D perf_sw_context, /* could eventually get its own */ =20 + .capabilities =3D PERF_PMU_CAP_SAMPLING, .event_init =3D hw_breakpoint_event_init, .add =3D hw_breakpoint_add, .del =3D hw_breakpoint_del, --=20 2.39.2.101.g768bb238c484.dirty From nobody Sat Oct 4 19:14:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 0C2942877FA; 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dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 07FDF1E7D; Wed, 13 Aug 2025 10:02:34 -0700 (PDT) Received: from e121345-lin.cambridge.arm.com (e121345-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id AE9203F738; Wed, 13 Aug 2025 10:02:37 -0700 (PDT) From: Robin Murphy To: peterz@infradead.org, mingo@redhat.com, will@kernel.org, mark.rutland@arm.com, acme@kernel.org, namhyung@kernel.org, alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, adrian.hunter@intel.com, kan.liang@linux.intel.com Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-alpha@vger.kernel.org, linux-snps-arc@lists.infradead.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, linux-csky@vger.kernel.org, loongarch@lists.linux.dev, linux-mips@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, linux-pm@vger.kernel.org, linux-rockchip@lists.infradead.org, dmaengine@vger.kernel.org, linux-fpga@vger.kernel.org, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, coresight@lists.linaro.org, iommu@lists.linux.dev, linux-amlogic@lists.infradead.org, linux-cxl@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH 17/19] perf: Retire PERF_PMU_CAP_NO_INTERRUPT Date: Wed, 13 Aug 2025 18:01:09 +0100 Message-Id: <32bf39943eef7c7f516d814d749cdbe322eec204.1755096883.git.robin.murphy@arm.com> X-Mailer: git-send-email 2.39.2.101.g768bb238c484.dirty In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Now that we have a well-defined cap for sampling support, clean up the remains of the mildly unintuitive and inconsistently-applied PERF_PMU_CAP_NO_INTERRUPT. Not to mention the obvious redundancy of some of these drivers still checking for sampling in event_init too. Signed-off-by: Robin Murphy --- arch/arc/kernel/perf_event.c | 4 +--- arch/csky/kernel/perf_event.c | 1 - arch/powerpc/perf/8xx-pmu.c | 3 +-- arch/powerpc/perf/hv-24x7.c | 3 --- arch/powerpc/perf/hv-gpci.c | 3 --- arch/powerpc/perf/kvm-hv-pmu.c | 2 +- arch/powerpc/perf/vpa-pmu.c | 6 +----- arch/powerpc/platforms/pseries/papr_scm.c | 7 +------ arch/s390/kernel/perf_cpum_cf.c | 3 --- arch/sh/kernel/perf_event.c | 1 - arch/x86/events/amd/uncore.c | 6 +++--- arch/x86/events/core.c | 1 - arch/x86/events/intel/cstate.c | 9 +++------ arch/x86/events/msr.c | 5 +---- drivers/fpga/dfl-fme-perf.c | 6 ++---- drivers/perf/arm_cspmu/arm_cspmu.c | 14 ++------------ drivers/perf/arm_pmu_platform.c | 1 - drivers/perf/marvell_cn10k_tad_pmu.c | 3 +-- drivers/perf/riscv_pmu_legacy.c | 1 - drivers/perf/riscv_pmu_sbi.c | 1 - drivers/powercap/intel_rapl_common.c | 2 +- include/linux/perf_event.h | 1 - 22 files changed, 18 insertions(+), 65 deletions(-) diff --git a/arch/arc/kernel/perf_event.c b/arch/arc/kernel/perf_event.c index 1b99b0215027..7e154f6f0abd 100644 --- a/arch/arc/kernel/perf_event.c +++ b/arch/arc/kernel/perf_event.c @@ -816,9 +816,7 @@ static int arc_pmu_device_probe(struct platform_device = *pdev) =20 } =20 - if (irq =3D=3D -1) - arc_pmu->pmu.capabilities |=3D PERF_PMU_CAP_NO_INTERRUPT; - else + if (irq !=3D -1) arc_pmu->pmu.capabilities |=3D PERF_PMU_CAP_SAMPLING; =20 /* diff --git a/arch/csky/kernel/perf_event.c b/arch/csky/kernel/perf_event.c index c5ba6e235a6f..ecf4b2863f78 100644 --- a/arch/csky/kernel/perf_event.c +++ b/arch/csky/kernel/perf_event.c @@ -1316,7 +1316,6 @@ int csky_pmu_device_probe(struct platform_device *pde= v, ret =3D csky_pmu_request_irq(csky_pmu_handle_irq); if (ret) { csky_pmu.pmu.capabilities &=3D ~PERF_PMU_CAP_SAMPLING; - csky_pmu.pmu.capabilities |=3D PERF_PMU_CAP_NO_INTERRUPT; pr_notice("[perf] PMU request irq fail!\n"); } =20 diff --git a/arch/powerpc/perf/8xx-pmu.c b/arch/powerpc/perf/8xx-pmu.c index 1d2972229e3a..71c35bd72eae 100644 --- a/arch/powerpc/perf/8xx-pmu.c +++ b/arch/powerpc/perf/8xx-pmu.c @@ -181,8 +181,7 @@ static struct pmu mpc8xx_pmu =3D { .add =3D mpc8xx_pmu_add, .del =3D mpc8xx_pmu_del, .read =3D mpc8xx_pmu_read, - .capabilities =3D PERF_PMU_CAP_NO_INTERRUPT | - PERF_PMU_CAP_NO_NMI, + .capabilities =3D PERF_PMU_CAP_NO_NMI, }; =20 static int init_mpc8xx_pmu(void) diff --git a/arch/powerpc/perf/hv-24x7.c b/arch/powerpc/perf/hv-24x7.c index e42677cc254a..ab906616e570 100644 --- a/arch/powerpc/perf/hv-24x7.c +++ b/arch/powerpc/perf/hv-24x7.c @@ -1726,9 +1726,6 @@ static int hv_24x7_init(void) if (!hv_page_cache) return -ENOMEM; =20 - /* sampling not supported */ - h_24x7_pmu.capabilities |=3D PERF_PMU_CAP_NO_INTERRUPT; - r =3D create_events_from_catalog(&event_group.attrs, &event_desc_group.attrs, &event_long_desc_group.attrs); diff --git a/arch/powerpc/perf/hv-gpci.c b/arch/powerpc/perf/hv-gpci.c index 241551d1282f..1726690396ec 100644 --- a/arch/powerpc/perf/hv-gpci.c +++ b/arch/powerpc/perf/hv-gpci.c @@ -1008,9 +1008,6 @@ static int hv_gpci_init(void) if (r) return r; =20 - /* sampling not supported */ - h_gpci_pmu.capabilities |=3D PERF_PMU_CAP_NO_INTERRUPT; - arg =3D (void *)get_cpu_var(hv_gpci_reqb); memset(arg, 0, HGPCI_REQ_BUFFER_SIZE); =20 diff --git a/arch/powerpc/perf/kvm-hv-pmu.c b/arch/powerpc/perf/kvm-hv-pmu.c index ae264c9080ef..1c6bc65c986c 100644 --- a/arch/powerpc/perf/kvm-hv-pmu.c +++ b/arch/powerpc/perf/kvm-hv-pmu.c @@ -391,7 +391,7 @@ static struct pmu kvmppc_pmu =3D { .attr_groups =3D kvmppc_pmu_attr_groups, .type =3D -1, .scope =3D PERF_PMU_SCOPE_SYS_WIDE, - .capabilities =3D PERF_PMU_CAP_NO_EXCLUDE | PERF_PMU_CAP_NO_INTERRUPT, + .capabilities =3D PERF_PMU_CAP_NO_EXCLUDE, }; =20 static int __init kvmppc_register_pmu(void) diff --git a/arch/powerpc/perf/vpa-pmu.c b/arch/powerpc/perf/vpa-pmu.c index 840733468959..1d360b5bf67c 100644 --- a/arch/powerpc/perf/vpa-pmu.c +++ b/arch/powerpc/perf/vpa-pmu.c @@ -75,10 +75,6 @@ static int vpa_pmu_event_init(struct perf_event *event) if (event->attr.type !=3D event->pmu->type) return -ENOENT; =20 - /* it does not support event sampling mode */ - if (is_sampling_event(event)) - return -EOPNOTSUPP; - /* no branch sampling */ if (has_branch_stack(event)) return -EOPNOTSUPP; @@ -164,7 +160,7 @@ static struct pmu vpa_pmu =3D { .del =3D vpa_pmu_del, .read =3D vpa_pmu_read, .attr_groups =3D vpa_pmu_attr_groups, - .capabilities =3D PERF_PMU_CAP_NO_EXCLUDE | PERF_PMU_CAP_NO_INTERRUPT, + .capabilities =3D PERF_PMU_CAP_NO_EXCLUDE, }; =20 static int __init pseries_vpa_pmu_init(void) diff --git a/arch/powerpc/platforms/pseries/papr_scm.c b/arch/powerpc/platf= orms/pseries/papr_scm.c index f7c9271bda58..d752cdaf8422 100644 --- a/arch/powerpc/platforms/pseries/papr_scm.c +++ b/arch/powerpc/platforms/pseries/papr_scm.c @@ -379,10 +379,6 @@ static int papr_scm_pmu_event_init(struct perf_event *= event) if (event->attr.type !=3D event->pmu->type) return -ENOENT; =20 - /* it does not support event sampling mode */ - if (is_sampling_event(event)) - return -EOPNOTSUPP; - /* no branch sampling */ if (has_branch_stack(event)) return -EOPNOTSUPP; @@ -463,8 +459,7 @@ static void papr_scm_pmu_register(struct papr_scm_priv = *p) nd_pmu->pmu.add =3D papr_scm_pmu_add; nd_pmu->pmu.del =3D papr_scm_pmu_del; =20 - nd_pmu->pmu.capabilities =3D PERF_PMU_CAP_NO_INTERRUPT | - PERF_PMU_CAP_NO_EXCLUDE; + nd_pmu->pmu.capabilities =3D PERF_PMU_CAP_NO_EXCLUDE; =20 /*updating the cpumask variable */ nodeid =3D numa_map_to_online_node(dev_to_node(&p->pdev->dev)); diff --git a/arch/s390/kernel/perf_cpum_cf.c b/arch/s390/kernel/perf_cpum_c= f.c index 7d10842d54f0..1a94e0944bc5 100644 --- a/arch/s390/kernel/perf_cpum_cf.c +++ b/arch/s390/kernel/perf_cpum_cf.c @@ -760,8 +760,6 @@ static int __hw_perf_event_init(struct perf_event *even= t, unsigned int type) break; =20 case PERF_TYPE_HARDWARE: - if (is_sampling_event(event)) /* No sampling support */ - return -ENOENT; ev =3D attr->config; if (!attr->exclude_user && attr->exclude_kernel) { /* @@ -1056,7 +1054,6 @@ static void cpumf_pmu_del(struct perf_event *event, i= nt flags) /* Performance monitoring unit for s390x */ static struct pmu cpumf_pmu =3D { .task_ctx_nr =3D perf_sw_context, - .capabilities =3D PERF_PMU_CAP_NO_INTERRUPT, .pmu_enable =3D cpumf_pmu_enable, .pmu_disable =3D cpumf_pmu_disable, .event_init =3D cpumf_pmu_event_init, diff --git a/arch/sh/kernel/perf_event.c b/arch/sh/kernel/perf_event.c index 1d2507f22437..d1b534538524 100644 --- a/arch/sh/kernel/perf_event.c +++ b/arch/sh/kernel/perf_event.c @@ -352,7 +352,6 @@ int register_sh_pmu(struct sh_pmu *_pmu) * no interrupts, and are therefore unable to do sampling without * further work and timer assistance. */ - pmu.capabilities |=3D PERF_PMU_CAP_NO_INTERRUPT; =20 WARN_ON(_pmu->num_events > MAX_HWEVENTS); =20 diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c index e8b6af199c73..050a5567291a 100644 --- a/arch/x86/events/amd/uncore.c +++ b/arch/x86/events/amd/uncore.c @@ -767,7 +767,7 @@ int amd_uncore_df_ctx_init(struct amd_uncore *uncore, u= nsigned int cpu) .start =3D amd_uncore_start, .stop =3D amd_uncore_stop, .read =3D amd_uncore_read, - .capabilities =3D PERF_PMU_CAP_NO_EXCLUDE | PERF_PMU_CAP_NO_INTERRUPT, + .capabilities =3D PERF_PMU_CAP_NO_EXCLUDE, .module =3D THIS_MODULE, }; =20 @@ -903,7 +903,7 @@ int amd_uncore_l3_ctx_init(struct amd_uncore *uncore, u= nsigned int cpu) .start =3D amd_uncore_start, .stop =3D amd_uncore_stop, .read =3D amd_uncore_read, - .capabilities =3D PERF_PMU_CAP_NO_EXCLUDE | PERF_PMU_CAP_NO_INTERRUPT, + .capabilities =3D PERF_PMU_CAP_NO_EXCLUDE, .module =3D THIS_MODULE, }; =20 @@ -1068,7 +1068,7 @@ int amd_uncore_umc_ctx_init(struct amd_uncore *uncore= , unsigned int cpu) .start =3D amd_uncore_umc_start, .stop =3D amd_uncore_stop, .read =3D amd_uncore_umc_read, - .capabilities =3D PERF_PMU_CAP_NO_EXCLUDE | PERF_PMU_CAP_NO_INTERRUPT, + .capabilities =3D PERF_PMU_CAP_NO_EXCLUDE, .module =3D THIS_MODULE, }; =20 diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index 72a4c43951ee..789dfca2fa67 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -1836,7 +1836,6 @@ static void __init pmu_check_apic(void) * events (user-space has to fall back and * sample via a hrtimer based software event): */ - pmu.capabilities |=3D PERF_PMU_CAP_NO_INTERRUPT; pmu.capabilities &=3D ~PERF_PMU_CAP_SAMPLING; } =20 diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c index ec753e39b007..2a79717b898f 100644 --- a/arch/x86/events/intel/cstate.c +++ b/arch/x86/events/intel/cstate.c @@ -281,9 +281,6 @@ static int cstate_pmu_event_init(struct perf_event *eve= nt) return -ENOENT; =20 /* unsupported modes and filters */ - if (event->attr.sample_period) /* no sampling */ - return -EINVAL; - if (event->cpu < 0) return -EINVAL; =20 @@ -397,7 +394,7 @@ static struct pmu cstate_core_pmu =3D { .start =3D cstate_pmu_event_start, .stop =3D cstate_pmu_event_stop, .read =3D cstate_pmu_event_update, - .capabilities =3D PERF_PMU_CAP_NO_INTERRUPT | PERF_PMU_CAP_NO_EXCLUDE, + .capabilities =3D PERF_PMU_CAP_NO_EXCLUDE, .scope =3D PERF_PMU_SCOPE_CORE, .module =3D THIS_MODULE, }; @@ -413,7 +410,7 @@ static struct pmu cstate_pkg_pmu =3D { .start =3D cstate_pmu_event_start, .stop =3D cstate_pmu_event_stop, .read =3D cstate_pmu_event_update, - .capabilities =3D PERF_PMU_CAP_NO_INTERRUPT | PERF_PMU_CAP_NO_EXCLUDE, + .capabilities =3D PERF_PMU_CAP_NO_EXCLUDE, .scope =3D PERF_PMU_SCOPE_PKG, .module =3D THIS_MODULE, }; @@ -429,7 +426,7 @@ static struct pmu cstate_module_pmu =3D { .start =3D cstate_pmu_event_start, .stop =3D cstate_pmu_event_stop, .read =3D cstate_pmu_event_update, - .capabilities =3D PERF_PMU_CAP_NO_INTERRUPT | PERF_PMU_CAP_NO_EXCLUDE, + .capabilities =3D PERF_PMU_CAP_NO_EXCLUDE, .scope =3D PERF_PMU_SCOPE_CLUSTER, .module =3D THIS_MODULE, }; diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c index 7f5007a4752a..3285c1f3bb90 100644 --- a/arch/x86/events/msr.c +++ b/arch/x86/events/msr.c @@ -210,9 +210,6 @@ static int msr_event_init(struct perf_event *event) return -ENOENT; =20 /* unsupported modes and filters */ - if (event->attr.sample_period) /* no sampling */ - return -EINVAL; - if (cfg >=3D PERF_MSR_EVENT_MAX) return -EINVAL; =20 @@ -298,7 +295,7 @@ static struct pmu pmu_msr =3D { .start =3D msr_event_start, .stop =3D msr_event_stop, .read =3D msr_event_update, - .capabilities =3D PERF_PMU_CAP_NO_INTERRUPT | PERF_PMU_CAP_NO_EXCLUDE, + .capabilities =3D PERF_PMU_CAP_NO_EXCLUDE, .attr_update =3D attr_update, }; =20 diff --git a/drivers/fpga/dfl-fme-perf.c b/drivers/fpga/dfl-fme-perf.c index 7422d2bc6f37..a1e2e7f28a3a 100644 --- a/drivers/fpga/dfl-fme-perf.c +++ b/drivers/fpga/dfl-fme-perf.c @@ -806,9 +806,8 @@ static int fme_perf_event_init(struct perf_event *event) /* * fme counters are shared across all cores. * Therefore, it does not support per-process mode. - * Also, it does not support event sampling mode. */ - if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK) + if (event->attach_state & PERF_ATTACH_TASK) return -EINVAL; =20 if (event->cpu < 0) @@ -921,8 +920,7 @@ static int fme_perf_pmu_register(struct platform_device= *pdev, pmu->start =3D fme_perf_event_start; pmu->stop =3D fme_perf_event_stop; pmu->read =3D fme_perf_event_read; - pmu->capabilities =3D PERF_PMU_CAP_NO_INTERRUPT | - PERF_PMU_CAP_NO_EXCLUDE; + pmu->capabilities =3D PERF_PMU_CAP_NO_EXCLUDE; =20 name =3D devm_kasprintf(priv->dev, GFP_KERNEL, "dfl_fme%d", pdev->id); =20 diff --git a/drivers/perf/arm_cspmu/arm_cspmu.c b/drivers/perf/arm_cspmu/ar= m_cspmu.c index 7f5ea749b85c..761b438db231 100644 --- a/drivers/perf/arm_cspmu/arm_cspmu.c +++ b/drivers/perf/arm_cspmu/arm_cspmu.c @@ -608,12 +608,6 @@ static int arm_cspmu_event_init(struct perf_event *eve= nt) * Following other "uncore" PMUs, we do not support sampling mode or * attach to a task (per-process mode). */ - if (is_sampling_event(event)) { - dev_dbg(cspmu->pmu.dev, - "Can't support sampling events\n"); - return -EOPNOTSUPP; - } - if (event->cpu < 0 || event->attach_state & PERF_ATTACH_TASK) { dev_dbg(cspmu->pmu.dev, "Can't support per-task counters\n"); @@ -1128,7 +1122,7 @@ static int arm_cspmu_get_cpus(struct arm_cspmu *cspmu) =20 static int arm_cspmu_register_pmu(struct arm_cspmu *cspmu) { - int ret, capabilities; + int ret; =20 ret =3D arm_cspmu_alloc_attr_groups(cspmu); if (ret) @@ -1139,10 +1133,6 @@ static int arm_cspmu_register_pmu(struct arm_cspmu *= cspmu) if (ret) return ret; =20 - capabilities =3D PERF_PMU_CAP_NO_EXCLUDE; - if (cspmu->irq =3D=3D 0) - capabilities |=3D PERF_PMU_CAP_NO_INTERRUPT; - cspmu->pmu =3D (struct pmu){ .task_ctx_nr =3D perf_invalid_context, .module =3D cspmu->impl.module, @@ -1156,7 +1146,7 @@ static int arm_cspmu_register_pmu(struct arm_cspmu *c= spmu) .stop =3D arm_cspmu_stop, .read =3D arm_cspmu_read, .attr_groups =3D cspmu->attr_groups, - .capabilities =3D capabilities, + .capabilities =3D PERF_PMU_CAP_NO_EXCLUDE, }; =20 /* Hardware counter init */ diff --git a/drivers/perf/arm_pmu_platform.c b/drivers/perf/arm_pmu_platfor= m.c index ab7a802cd0d6..754dba9e4528 100644 --- a/drivers/perf/arm_pmu_platform.c +++ b/drivers/perf/arm_pmu_platform.c @@ -110,7 +110,6 @@ static int pmu_parse_irqs(struct arm_pmu *pmu) if (num_irqs =3D=3D 0) { dev_warn(dev, "no irqs for PMU, sampling events not supported\n"); pmu->pmu.capabilities &=3D ~PERF_PMU_CAP_SAMPLING; - pmu->pmu.capabilities |=3D PERF_PMU_CAP_NO_INTERRUPT; cpumask_setall(&pmu->supported_cpus); return 0; } diff --git a/drivers/perf/marvell_cn10k_tad_pmu.c b/drivers/perf/marvell_cn= 10k_tad_pmu.c index ee6505cb01a7..a162e707a639 100644 --- a/drivers/perf/marvell_cn10k_tad_pmu.c +++ b/drivers/perf/marvell_cn10k_tad_pmu.c @@ -360,8 +360,7 @@ static int tad_pmu_probe(struct platform_device *pdev) tad_pmu->pmu =3D (struct pmu) { =20 .module =3D THIS_MODULE, - .capabilities =3D PERF_PMU_CAP_NO_EXCLUDE | - PERF_PMU_CAP_NO_INTERRUPT, + .capabilities =3D PERF_PMU_CAP_NO_EXCLUDE, .task_ctx_nr =3D perf_invalid_context, =20 .event_init =3D tad_pmu_event_init, diff --git a/drivers/perf/riscv_pmu_legacy.c b/drivers/perf/riscv_pmu_legac= y.c index 93c8e0fdb589..40140e457454 100644 --- a/drivers/perf/riscv_pmu_legacy.c +++ b/drivers/perf/riscv_pmu_legacy.c @@ -123,7 +123,6 @@ static void pmu_legacy_init(struct riscv_pmu *pmu) pmu->event_mapped =3D pmu_legacy_event_mapped; pmu->event_unmapped =3D pmu_legacy_event_unmapped; pmu->csr_index =3D pmu_legacy_csr_index; - pmu->pmu.capabilities |=3D PERF_PMU_CAP_NO_INTERRUPT; pmu->pmu.capabilities |=3D PERF_PMU_CAP_NO_EXCLUDE; =20 perf_pmu_register(&pmu->pmu, "cpu", PERF_TYPE_RAW); diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index d185ea8c47ba..4fb1aab0b547 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -1359,7 +1359,6 @@ static int pmu_sbi_device_probe(struct platform_devic= e *pdev) ret =3D pmu_sbi_setup_irqs(pmu, pdev); if (ret < 0) { pr_info("Perf sampling/filtering is not supported as sscof extension is = not available\n"); - pmu->pmu.capabilities |=3D PERF_PMU_CAP_NO_INTERRUPT; pmu->pmu.capabilities |=3D PERF_PMU_CAP_NO_EXCLUDE; } else { pmu->pmu.capabilities |=3D PERF_PMU_CAP_SAMPLING; diff --git a/drivers/powercap/intel_rapl_common.c b/drivers/powercap/intel_= rapl_common.c index c7e7f9bf5313..38470351217b 100644 --- a/drivers/powercap/intel_rapl_common.c +++ b/drivers/powercap/intel_rapl_common.c @@ -2014,7 +2014,7 @@ static int rapl_pmu_update(struct rapl_package *rp) rapl_pmu.pmu.stop =3D rapl_pmu_event_stop; rapl_pmu.pmu.read =3D rapl_pmu_event_read; rapl_pmu.pmu.module =3D THIS_MODULE; - rapl_pmu.pmu.capabilities =3D PERF_PMU_CAP_NO_EXCLUDE | PERF_PMU_CAP_NO_I= NTERRUPT; + rapl_pmu.pmu.capabilities =3D PERF_PMU_CAP_NO_EXCLUDE; ret =3D perf_pmu_register(&rapl_pmu.pmu, "power", -1); if (ret) { pr_info("Failed to register PMU\n"); diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h index bf2cfbeabba2..183b7c48b329 100644 --- a/include/linux/perf_event.h +++ b/include/linux/perf_event.h @@ -305,7 +305,6 @@ struct perf_event_pmu_context; #define PERF_PMU_CAP_EXTENDED_HW_TYPE 0x0100 #define PERF_PMU_CAP_AUX_PAUSE 0x0200 #define PERF_PMU_CAP_AUX_PREFER_LARGE 0x0400 -#define PERF_PMU_CAP_NO_INTERRUPT 0x0800 =20 /** * pmu::scope --=20 2.39.2.101.g768bb238c484.dirty From nobody Sat Oct 4 19:14:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 6099330AABD; Wed, 13 Aug 2025 17:02:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 696B21E7D; Wed, 13 Aug 2025 10:02:38 -0700 (PDT) Received: from e121345-lin.cambridge.arm.com (e121345-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 520FE3F77D; Wed, 13 Aug 2025 10:02:42 -0700 (PDT) From: Robin Murphy To: peterz@infradead.org, mingo@redhat.com, will@kernel.org, mark.rutland@arm.com, acme@kernel.org, namhyung@kernel.org, alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, adrian.hunter@intel.com, kan.liang@linux.intel.com Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-alpha@vger.kernel.org, linux-snps-arc@lists.infradead.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, linux-csky@vger.kernel.org, loongarch@lists.linux.dev, linux-mips@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, linux-pm@vger.kernel.org, linux-rockchip@lists.infradead.org, dmaengine@vger.kernel.org, linux-fpga@vger.kernel.org, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, coresight@lists.linaro.org, iommu@lists.linux.dev, linux-amlogic@lists.infradead.org, linux-cxl@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH 18/19] perf: Introduce positive capability for raw events Date: Wed, 13 Aug 2025 18:01:10 +0100 Message-Id: <542787fd188ea15ef41c53d557989c962ed44771.1755096883.git.robin.murphy@arm.com> X-Mailer: git-send-email 2.39.2.101.g768bb238c484.dirty In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Only a handful of CPU PMUs accept PERF_TYPE_{RAW,HARDWARE,HW_CACHE} events without registering themselves as PERF_TYPE_RAW in the first place. Add an explicit opt-in for these special cases, so that we can make life easier for every other driver (and probably also speed up the slow-path search) by having perf_try_init_event() do the basic type checking to cover the majority of cases. Signed-off-by: Robin Murphy --- A further possibility is to automatically add the cap to PERF_TYPE_RAW PMUs in perf_pmu_register() to have a single point-of-use condition; I'm undecided... --- arch/s390/kernel/perf_cpum_cf.c | 1 + arch/s390/kernel/perf_pai_crypto.c | 2 +- arch/s390/kernel/perf_pai_ext.c | 2 +- arch/x86/events/core.c | 2 +- drivers/perf/arm_pmu.c | 1 + include/linux/perf_event.h | 1 + kernel/events/core.c | 15 +++++++++++++++ 7 files changed, 21 insertions(+), 3 deletions(-) diff --git a/arch/s390/kernel/perf_cpum_cf.c b/arch/s390/kernel/perf_cpum_c= f.c index 1a94e0944bc5..782ab755ddd4 100644 --- a/arch/s390/kernel/perf_cpum_cf.c +++ b/arch/s390/kernel/perf_cpum_cf.c @@ -1054,6 +1054,7 @@ static void cpumf_pmu_del(struct perf_event *event, i= nt flags) /* Performance monitoring unit for s390x */ static struct pmu cpumf_pmu =3D { .task_ctx_nr =3D perf_sw_context, + .capabilities =3D PERF_PMU_CAP_RAW_EVENTS, .pmu_enable =3D cpumf_pmu_enable, .pmu_disable =3D cpumf_pmu_disable, .event_init =3D cpumf_pmu_event_init, diff --git a/arch/s390/kernel/perf_pai_crypto.c b/arch/s390/kernel/perf_pai= _crypto.c index a64b6b056a21..b5b6d8b5d943 100644 --- a/arch/s390/kernel/perf_pai_crypto.c +++ b/arch/s390/kernel/perf_pai_crypto.c @@ -569,7 +569,7 @@ static const struct attribute_group *paicrypt_attr_grou= ps[] =3D { /* Performance monitoring unit for mapped counters */ static struct pmu paicrypt =3D { .task_ctx_nr =3D perf_hw_context, - .capabilities =3D PERF_PMU_CAP_SAMPLING, + .capabilities =3D PERF_PMU_CAP_SAMPLING | PERF_PMU_CAP_RAW_EVENTS, .event_init =3D paicrypt_event_init, .add =3D paicrypt_add, .del =3D paicrypt_del, diff --git a/arch/s390/kernel/perf_pai_ext.c b/arch/s390/kernel/perf_pai_ex= t.c index 1261f80c6d52..bcd28c38da70 100644 --- a/arch/s390/kernel/perf_pai_ext.c +++ b/arch/s390/kernel/perf_pai_ext.c @@ -595,7 +595,7 @@ static const struct attribute_group *paiext_attr_groups= [] =3D { /* Performance monitoring unit for mapped counters */ static struct pmu paiext =3D { .task_ctx_nr =3D perf_hw_context, - .capabilities =3D PERF_PMU_CAP_SAMPLING, + .capabilities =3D PERF_PMU_CAP_SAMPLING | PERF_PMU_CAP_RAW_EVENTS, .event_init =3D paiext_event_init, .add =3D paiext_add, .del =3D paiext_del, diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index 789dfca2fa67..764728bb80ae 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -2697,7 +2697,7 @@ static bool x86_pmu_filter(struct pmu *pmu, int cpu) } =20 static struct pmu pmu =3D { - .capabilities =3D PERF_PMU_CAP_SAMPLING, + .capabilities =3D PERF_PMU_CAP_SAMPLING | PERF_PMU_CAP_RAW_EVENTS, =20 .pmu_enable =3D x86_pmu_enable, .pmu_disable =3D x86_pmu_disable, diff --git a/drivers/perf/arm_pmu.c b/drivers/perf/arm_pmu.c index 72d8f38d0aa5..bc772a3bf411 100644 --- a/drivers/perf/arm_pmu.c +++ b/drivers/perf/arm_pmu.c @@ -877,6 +877,7 @@ struct arm_pmu *armpmu_alloc(void) * specific PMU. */ .capabilities =3D PERF_PMU_CAP_SAMPLING | + PERF_PMU_CAP_RAW_EVENTS | PERF_PMU_CAP_EXTENDED_REGS | PERF_PMU_CAP_EXTENDED_HW_TYPE, }; diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h index 183b7c48b329..c6ad036c0037 100644 --- a/include/linux/perf_event.h +++ b/include/linux/perf_event.h @@ -305,6 +305,7 @@ struct perf_event_pmu_context; #define PERF_PMU_CAP_EXTENDED_HW_TYPE 0x0100 #define PERF_PMU_CAP_AUX_PAUSE 0x0200 #define PERF_PMU_CAP_AUX_PREFER_LARGE 0x0400 +#define PERF_PMU_CAP_RAW_EVENTS 0x0800 =20 /** * pmu::scope diff --git a/kernel/events/core.c b/kernel/events/core.c index 71b2a6730705..2ecee76d2ae2 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -12556,11 +12556,26 @@ static inline bool has_extended_regs(struct perf_= event *event) (event->attr.sample_regs_intr & PERF_REG_EXTENDED_MASK); } =20 +static bool is_raw_pmu(const struct pmu *pmu) +{ + return pmu->type =3D=3D PERF_TYPE_RAW || + pmu->capabilities & PERF_PMU_CAP_RAW_EVENTS; +} + static int perf_try_init_event(struct pmu *pmu, struct perf_event *event) { struct perf_event_context *ctx =3D NULL; int ret; =20 + /* + * Before touching anything, we can safely skip: + * - any event for a specific PMU which is not this one + * - any common event if this PMU doesn't support them + */ + if (event->attr.type !=3D pmu->type && + (event->attr.type >=3D PERF_TYPE_MAX || is_raw_pmu(pmu))) + return -ENOENT; + if (!try_module_get(pmu->module)) return -ENODEV; =20 --=20 2.39.2.101.g768bb238c484.dirty From nobody Sat Oct 4 19:14:47 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 94289303C9D; Wed, 13 Aug 2025 17:02:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755104574; cv=none; b=fnxgFbIkvsqhoXfzkMoFbk5LiHVHnyKXsJ3fBbhkuzF5smpL1/zyOPB/k+dv65bc94xz+BhmucyMliUixZvmc4BRuEPkwYXDFhW3CKkuvJiv8U2TrcBIr/CV6dWPHfGSIOizaUGRwc/Qmi+6/LQh5RXs6JjZs71i6+dhbmlZRj4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755104574; c=relaxed/simple; bh=eolTxcTGSebbGJ/EgeYd+eo1ZnYvvcqd+diWOaEwadE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=HYWA5mqKhTXEB5S8khFQCOpaHBQjHJDs23kJjrN2GWWP+yqulXJenkMuoywT7UTKre+BXKAJ79Uy9oAR8AAPl5k2Kpcya//6eJ7CwMK0Z7G+VA8WFW4TPw7hE6RojRz38XninB5S2ZPRvRXEPMFzKneEHyFsLTLbAC+QgtUF38w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id ECC861E7D; Wed, 13 Aug 2025 10:02:42 -0700 (PDT) Received: from e121345-lin.cambridge.arm.com (e121345-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id CF6873F738; Wed, 13 Aug 2025 10:02:46 -0700 (PDT) From: Robin Murphy To: peterz@infradead.org, mingo@redhat.com, will@kernel.org, mark.rutland@arm.com, acme@kernel.org, namhyung@kernel.org, alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, adrian.hunter@intel.com, kan.liang@linux.intel.com Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-alpha@vger.kernel.org, linux-snps-arc@lists.infradead.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, linux-csky@vger.kernel.org, loongarch@lists.linux.dev, linux-mips@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, linux-pm@vger.kernel.org, linux-rockchip@lists.infradead.org, dmaengine@vger.kernel.org, linux-fpga@vger.kernel.org, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, coresight@lists.linaro.org, iommu@lists.linux.dev, linux-amlogic@lists.infradead.org, linux-cxl@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH 19/19] perf: Garbage-collect event_init checks Date: Wed, 13 Aug 2025 18:01:11 +0100 Message-Id: X-Mailer: git-send-email 2.39.2.101.g768bb238c484.dirty In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" All these boilerplate event_init checks are now redundant. Of course many of them were already redundant, or done in the wrong order so as to be pointless, and what we don't see here is all the ones which were missing, but have now been implicitly gained thanks to some of these new core code behaviours. In summary: - event->attr.type Now only relevant to PERF_TYPE_RAW PMUs or those advertising PERF_PMU_CAP_RAW_EVENTS. - event->cpu < 0 Already rejected by perf_event_alloc() unless a task is passed, wherein that will also set PERF_ATTACH_TASK prior to reaching perf_init_event(), so is always redundant with... - PERF_ATTACH_TASK Since at least commit bd2756811766 ("perf: Rewrite core context handling"), only relevant to PMUs using perf_hw_context or perf_sw_context; for uncore PMUs this is covered by perf_event_alloc() again, right after perf_init_event() returns, by virtue of the same non-NULL task which caused attach_state to be set in the first place. - is_sampling_event() (and variations) Now only relevant to PMUs advertising PERF_PMU_CAP_SAMPLING. - has_branch_stack() Now doubly-illogical for PMUs which never supported sampling anyway. Signed-off-by: Robin Murphy Reported-by: kernel test robot --- arch/arm/mach-imx/mmdc.c | 14 --------- arch/arm/mm/cache-l2x0-pmu.c | 10 ------- arch/powerpc/perf/hv-24x7.c | 8 ----- arch/powerpc/perf/hv-gpci.c | 8 ----- arch/powerpc/perf/imc-pmu.c | 30 ------------------- arch/powerpc/perf/kvm-hv-pmu.c | 3 -- arch/powerpc/perf/vpa-pmu.c | 7 ----- arch/powerpc/platforms/pseries/papr_scm.c | 11 ------- arch/s390/kernel/perf_cpum_cf.c | 3 +- arch/x86/events/amd/iommu.c | 15 ---------- arch/x86/events/amd/power.c | 7 ----- arch/x86/events/amd/uncore.c | 6 ---- arch/x86/events/intel/bts.c | 3 -- arch/x86/events/intel/cstate.c | 7 ----- arch/x86/events/intel/pt.c | 3 -- arch/x86/events/intel/uncore.c | 13 -------- arch/x86/events/intel/uncore_snb.c | 18 ----------- arch/x86/events/msr.c | 3 -- arch/x86/events/rapl.c | 11 ------- drivers/devfreq/event/rockchip-dfi.c | 12 -------- drivers/dma/idxd/perfmon.c | 14 --------- drivers/fpga/dfl-fme-perf.c | 14 --------- drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c | 4 --- drivers/gpu/drm/i915/i915_pmu.c | 13 -------- drivers/gpu/drm/xe/xe_pmu.c | 13 -------- .../hwtracing/coresight/coresight-etm-perf.c | 5 ---- drivers/hwtracing/ptt/hisi_ptt.c | 8 ----- drivers/iommu/intel/perfmon.c | 10 ------- drivers/perf/alibaba_uncore_drw_pmu.c | 17 ----------- drivers/perf/amlogic/meson_ddr_pmu_core.c | 9 ------ drivers/perf/arm-cci.c | 9 ------ drivers/perf/arm-ccn.c | 18 ----------- drivers/perf/arm-cmn.c | 10 ------- drivers/perf/arm-ni.c | 6 ---- drivers/perf/arm_cspmu/arm_cspmu.c | 13 -------- drivers/perf/arm_dmc620_pmu.c | 16 ---------- drivers/perf/arm_dsu_pmu.c | 20 ------------- drivers/perf/arm_smmuv3_pmu.c | 13 -------- drivers/perf/arm_spe_pmu.c | 4 --- drivers/perf/cxl_pmu.c | 6 ---- drivers/perf/dwc_pcie_pmu.c | 11 ------- drivers/perf/fsl_imx8_ddr_perf.c | 11 ------- drivers/perf/fsl_imx9_ddr_perf.c | 11 ------- drivers/perf/hisilicon/hisi_pcie_pmu.c | 8 ----- drivers/perf/hisilicon/hisi_uncore_pmu.c | 18 ----------- drivers/perf/hisilicon/hns3_pmu.c | 7 ----- drivers/perf/marvell_cn10k_ddr_pmu.c | 13 -------- drivers/perf/marvell_cn10k_tad_pmu.c | 3 -- drivers/perf/marvell_pem_pmu.c | 11 ------- drivers/perf/qcom_l2_pmu.c | 15 ---------- drivers/perf/qcom_l3_pmu.c | 19 ------------ drivers/perf/starfive_starlink_pmu.c | 14 --------- drivers/perf/thunderx2_pmu.c | 15 ---------- drivers/perf/xgene_pmu.c | 14 --------- drivers/powercap/intel_rapl_common.c | 7 ----- 55 files changed, 1 insertion(+), 590 deletions(-) diff --git a/arch/arm/mach-imx/mmdc.c b/arch/arm/mach-imx/mmdc.c index f9d432b385a2..9e3734e249a2 100644 --- a/arch/arm/mach-imx/mmdc.c +++ b/arch/arm/mach-imx/mmdc.c @@ -277,20 +277,6 @@ static int mmdc_pmu_event_init(struct perf_event *even= t) struct mmdc_pmu *pmu_mmdc =3D to_mmdc_pmu(event->pmu); int cfg =3D event->attr.config; =20 - if (event->attr.type !=3D event->pmu->type) - return -ENOENT; - - if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK) - return -EOPNOTSUPP; - - if (event->cpu < 0) { - dev_warn(pmu_mmdc->dev, "Can't provide per-task data!\n"); - return -EOPNOTSUPP; - } - - if (event->attr.sample_period) - return -EINVAL; - if (cfg < 0 || cfg >=3D MMDC_NUM_COUNTERS) return -EINVAL; =20 diff --git a/arch/arm/mm/cache-l2x0-pmu.c b/arch/arm/mm/cache-l2x0-pmu.c index 6fc1171031a8..b8753463c1c4 100644 --- a/arch/arm/mm/cache-l2x0-pmu.c +++ b/arch/arm/mm/cache-l2x0-pmu.c @@ -294,16 +294,6 @@ static int l2x0_pmu_event_init(struct perf_event *even= t) { struct hw_perf_event *hw =3D &event->hw; =20 - if (event->attr.type !=3D l2x0_pmu->type) - return -ENOENT; - - if (is_sampling_event(event) || - event->attach_state & PERF_ATTACH_TASK) - return -EINVAL; - - if (event->cpu < 0) - return -EINVAL; - if (event->attr.config & ~L2X0_EVENT_CNT_CFG_SRC_MASK) return -EINVAL; =20 diff --git a/arch/powerpc/perf/hv-24x7.c b/arch/powerpc/perf/hv-24x7.c index ab906616e570..5b03d6b34999 100644 --- a/arch/powerpc/perf/hv-24x7.c +++ b/arch/powerpc/perf/hv-24x7.c @@ -1379,10 +1379,6 @@ static int h_24x7_event_init(struct perf_event *even= t) unsigned long hret; u64 ct; =20 - /* Not our event */ - if (event->attr.type !=3D event->pmu->type) - return -ENOENT; - /* Unused areas must be 0 */ if (event_get_reserved1(event) || event_get_reserved2(event) || @@ -1397,10 +1393,6 @@ static int h_24x7_event_init(struct perf_event *even= t) return -EINVAL; } =20 - /* no branch sampling */ - if (has_branch_stack(event)) - return -EOPNOTSUPP; - /* offset must be 8 byte aligned */ if (event_get_offset(event) % 8) { pr_devel("bad alignment\n"); diff --git a/arch/powerpc/perf/hv-gpci.c b/arch/powerpc/perf/hv-gpci.c index 1726690396ec..9663aa18bc45 100644 --- a/arch/powerpc/perf/hv-gpci.c +++ b/arch/powerpc/perf/hv-gpci.c @@ -775,20 +775,12 @@ static int h_gpci_event_init(struct perf_event *event) u8 length; unsigned long ret; =20 - /* Not our event */ - if (event->attr.type !=3D event->pmu->type) - return -ENOENT; - /* config2 is unused */ if (event->attr.config2) { pr_devel("config2 set when reserved\n"); return -EINVAL; } =20 - /* no branch sampling */ - if (has_branch_stack(event)) - return -EOPNOTSUPP; - length =3D event_get_length(event); if (length < 1 || length > 8) { pr_devel("length invalid\n"); diff --git a/arch/powerpc/perf/imc-pmu.c b/arch/powerpc/perf/imc-pmu.c index f352dda3baf9..cee6390986dc 100644 --- a/arch/powerpc/perf/imc-pmu.c +++ b/arch/powerpc/perf/imc-pmu.c @@ -517,16 +517,6 @@ static int nest_imc_event_init(struct perf_event *even= t) struct imc_pmu_ref *ref; bool flag =3D false; =20 - if (event->attr.type !=3D event->pmu->type) - return -ENOENT; - - /* Sampling not supported */ - if (event->hw.sample_period) - return -EINVAL; - - if (event->cpu < 0) - return -EINVAL; - pmu =3D imc_event_to_pmu(event); =20 /* Sanity check for config (event offset) */ @@ -819,16 +809,6 @@ static int core_imc_event_init(struct perf_event *even= t) struct imc_pmu *pmu; struct imc_pmu_ref *ref; =20 - if (event->attr.type !=3D event->pmu->type) - return -ENOENT; - - /* Sampling not supported */ - if (event->hw.sample_period) - return -EINVAL; - - if (event->cpu < 0) - return -EINVAL; - event->hw.idx =3D -1; pmu =3D imc_event_to_pmu(event); =20 @@ -983,16 +963,9 @@ static int thread_imc_event_init(struct perf_event *ev= ent) struct task_struct *target; struct imc_pmu *pmu; =20 - if (event->attr.type !=3D event->pmu->type) - return -ENOENT; - if (!perfmon_capable()) return -EACCES; =20 - /* Sampling not supported */ - if (event->hw.sample_period) - return -EINVAL; - event->hw.idx =3D -1; pmu =3D imc_event_to_pmu(event); =20 @@ -1436,9 +1409,6 @@ static void trace_imc_event_del(struct perf_event *ev= ent, int flags) =20 static int trace_imc_event_init(struct perf_event *event) { - if (event->attr.type !=3D event->pmu->type) - return -ENOENT; - if (!perfmon_capable()) return -EACCES; =20 diff --git a/arch/powerpc/perf/kvm-hv-pmu.c b/arch/powerpc/perf/kvm-hv-pmu.c index 1c6bc65c986c..513f5b172ba6 100644 --- a/arch/powerpc/perf/kvm-hv-pmu.c +++ b/arch/powerpc/perf/kvm-hv-pmu.c @@ -180,9 +180,6 @@ static int kvmppc_pmu_event_init(struct perf_event *eve= nt) __func__, event, event->id, event->cpu, event->oncpu, config); =20 - if (event->attr.type !=3D event->pmu->type) - return -ENOENT; - if (config >=3D KVMPPC_EVENT_MAX) return -EINVAL; =20 diff --git a/arch/powerpc/perf/vpa-pmu.c b/arch/powerpc/perf/vpa-pmu.c index 1d360b5bf67c..35883a071360 100644 --- a/arch/powerpc/perf/vpa-pmu.c +++ b/arch/powerpc/perf/vpa-pmu.c @@ -72,13 +72,6 @@ static const struct attribute_group *vpa_pmu_attr_groups= [] =3D { =20 static int vpa_pmu_event_init(struct perf_event *event) { - if (event->attr.type !=3D event->pmu->type) - return -ENOENT; - - /* no branch sampling */ - if (has_branch_stack(event)) - return -EOPNOTSUPP; - /* Invalid event code */ if ((event->attr.config <=3D 0) || (event->attr.config > 3)) return -EINVAL; diff --git a/arch/powerpc/platforms/pseries/papr_scm.c b/arch/powerpc/platf= orms/pseries/papr_scm.c index d752cdaf8422..e6474ee0c140 100644 --- a/arch/powerpc/platforms/pseries/papr_scm.c +++ b/arch/powerpc/platforms/pseries/papr_scm.c @@ -372,17 +372,6 @@ static int papr_scm_pmu_event_init(struct perf_event *= event) struct nvdimm_pmu *nd_pmu =3D to_nvdimm_pmu(event->pmu); struct papr_scm_priv *p; =20 - if (!nd_pmu) - return -EINVAL; - - /* test the event attr type for PMU enumeration */ - if (event->attr.type !=3D event->pmu->type) - return -ENOENT; - - /* no branch sampling */ - if (has_branch_stack(event)) - return -EOPNOTSUPP; - p =3D (struct papr_scm_priv *)nd_pmu->dev->driver_data; if (!p) return -EINVAL; diff --git a/arch/s390/kernel/perf_cpum_cf.c b/arch/s390/kernel/perf_cpum_c= f.c index 782ab755ddd4..fa732e94f6e4 100644 --- a/arch/s390/kernel/perf_cpum_cf.c +++ b/arch/s390/kernel/perf_cpum_cf.c @@ -1788,8 +1788,7 @@ static int cfdiag_event_init(struct perf_event *event) struct perf_event_attr *attr =3D &event->attr; int err =3D -ENOENT; =20 - if (event->attr.config !=3D PERF_EVENT_CPUM_CF_DIAG || - event->attr.type !=3D event->pmu->type) + if (event->attr.config !=3D PERF_EVENT_CPUM_CF_DIAG) goto out; =20 /* Raw events are used to access counters directly, diff --git a/arch/x86/events/amd/iommu.c b/arch/x86/events/amd/iommu.c index a721da9987dd..8053bec14dec 100644 --- a/arch/x86/events/amd/iommu.c +++ b/arch/x86/events/amd/iommu.c @@ -209,21 +209,6 @@ static int perf_iommu_event_init(struct perf_event *ev= ent) { struct hw_perf_event *hwc =3D &event->hw; =20 - /* test the event attr type check for PMU enumeration */ - if (event->attr.type !=3D event->pmu->type) - return -ENOENT; - - /* - * IOMMU counters are shared across all cores. - * Therefore, it does not support per-process mode. - * Also, it does not support event sampling mode. - */ - if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK) - return -EINVAL; - - if (event->cpu < 0) - return -EINVAL; - /* update the hw_perf_event struct with the iommu config data */ hwc->conf =3D event->attr.config; hwc->conf1 =3D event->attr.config1; diff --git a/arch/x86/events/amd/power.c b/arch/x86/events/amd/power.c index dad42790cf7d..a5e42ee2464a 100644 --- a/arch/x86/events/amd/power.c +++ b/arch/x86/events/amd/power.c @@ -125,14 +125,7 @@ static int pmu_event_init(struct perf_event *event) { u64 cfg =3D event->attr.config & AMD_POWER_EVENT_MASK; =20 - /* Only look at AMD power events. */ - if (event->attr.type !=3D pmu_class.type) - return -ENOENT; - /* Unsupported modes and filters. */ - if (event->attr.sample_period) - return -EINVAL; - if (cfg !=3D AMD_POWER_EVENTSEL_PKG) return -EINVAL; =20 diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c index 050a5567291a..76f58c7b4c19 100644 --- a/arch/x86/events/amd/uncore.c +++ b/arch/x86/events/amd/uncore.c @@ -270,12 +270,6 @@ static int amd_uncore_event_init(struct perf_event *ev= ent) struct amd_uncore_ctx *ctx; struct hw_perf_event *hwc =3D &event->hw; =20 - if (event->attr.type !=3D event->pmu->type) - return -ENOENT; - - if (event->cpu < 0) - return -EINVAL; - pmu =3D event_to_amd_uncore_pmu(event); ctx =3D *per_cpu_ptr(pmu->ctx, event->cpu); if (!ctx) diff --git a/arch/x86/events/intel/bts.c b/arch/x86/events/intel/bts.c index 61da6b8a3d51..27e23153ba6f 100644 --- a/arch/x86/events/intel/bts.c +++ b/arch/x86/events/intel/bts.c @@ -565,9 +565,6 @@ static int bts_event_init(struct perf_event *event) { int ret; =20 - if (event->attr.type !=3D bts_pmu.type) - return -ENOENT; - /* * BTS leaks kernel addresses even when CPL0 tracing is * disabled, so disallow intel_bts driver for unprivileged diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c index 2a79717b898f..90a884d77864 100644 --- a/arch/x86/events/intel/cstate.c +++ b/arch/x86/events/intel/cstate.c @@ -277,13 +277,6 @@ static int cstate_pmu_event_init(struct perf_event *ev= ent) { u64 cfg =3D event->attr.config; =20 - if (event->attr.type !=3D event->pmu->type) - return -ENOENT; - - /* unsupported modes and filters */ - if (event->cpu < 0) - return -EINVAL; - if (event->pmu =3D=3D &cstate_core_pmu) { if (cfg >=3D PERF_CSTATE_CORE_EVENT_MAX) return -EINVAL; diff --git a/arch/x86/events/intel/pt.c b/arch/x86/events/intel/pt.c index e8cf29d2b10c..a5004dd7632b 100644 --- a/arch/x86/events/intel/pt.c +++ b/arch/x86/events/intel/pt.c @@ -1795,9 +1795,6 @@ static void pt_event_destroy(struct perf_event *event) =20 static int pt_event_init(struct perf_event *event) { - if (event->attr.type !=3D pt_pmu.pmu.type) - return -ENOENT; - if (!pt_event_valid(event)) return -EINVAL; =20 diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c index 297ff5adb667..98ffab403bb4 100644 --- a/arch/x86/events/intel/uncore.c +++ b/arch/x86/events/intel/uncore.c @@ -731,24 +731,11 @@ static int uncore_pmu_event_init(struct perf_event *e= vent) struct hw_perf_event *hwc =3D &event->hw; int ret; =20 - if (event->attr.type !=3D event->pmu->type) - return -ENOENT; - pmu =3D uncore_event_to_pmu(event); /* no device found for this pmu */ if (!pmu->registered) return -ENOENT; =20 - /* Sampling not supported yet */ - if (hwc->sample_period) - return -EINVAL; - - /* - * Place all uncore events for a particular physical package - * onto a single cpu - */ - if (event->cpu < 0) - return -EINVAL; box =3D uncore_pmu_to_box(pmu, event->cpu); if (!box || box->cpu < 0) return -EINVAL; diff --git a/arch/x86/events/intel/uncore_snb.c b/arch/x86/events/intel/unc= ore_snb.c index 807e582b8f17..8537f61bb093 100644 --- a/arch/x86/events/intel/uncore_snb.c +++ b/arch/x86/events/intel/uncore_snb.c @@ -906,29 +906,11 @@ static int snb_uncore_imc_event_init(struct perf_even= t *event) u64 cfg =3D event->attr.config & SNB_UNCORE_PCI_IMC_EVENT_MASK; int idx, base; =20 - if (event->attr.type !=3D event->pmu->type) - return -ENOENT; - pmu =3D uncore_event_to_pmu(event); /* no device found for this pmu */ if (!pmu->registered) return -ENOENT; =20 - /* Sampling not supported yet */ - if (hwc->sample_period) - return -EINVAL; - - /* unsupported modes and filters */ - if (event->attr.sample_period) /* no sampling */ - return -EINVAL; - - /* - * Place all uncore events for a particular physical package - * onto a single cpu - */ - if (event->cpu < 0) - return -EINVAL; - /* check only supported bits are set */ if (event->attr.config & ~SNB_UNCORE_PCI_IMC_EVENT_MASK) return -EINVAL; diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c index 3285c1f3bb90..cf6214849a25 100644 --- a/arch/x86/events/msr.c +++ b/arch/x86/events/msr.c @@ -206,9 +206,6 @@ static int msr_event_init(struct perf_event *event) { u64 cfg =3D event->attr.config; =20 - if (event->attr.type !=3D event->pmu->type) - return -ENOENT; - /* unsupported modes and filters */ if (cfg >=3D PERF_MSR_EVENT_MAX) return -EINVAL; diff --git a/arch/x86/events/rapl.c b/arch/x86/events/rapl.c index defd86137f12..5d298e371b28 100644 --- a/arch/x86/events/rapl.c +++ b/arch/x86/events/rapl.c @@ -370,21 +370,10 @@ static int rapl_pmu_event_init(struct perf_event *eve= nt) unsigned int rapl_pmu_idx; struct rapl_pmus *rapl_pmus; =20 - /* only look at RAPL events */ - if (event->attr.type !=3D event->pmu->type) - return -ENOENT; - - /* unsupported modes and filters */ - if (event->attr.sample_period) /* no sampling */ - return -EINVAL; - /* check only supported bits are set */ if (event->attr.config & ~RAPL_EVENT_MASK) return -EINVAL; =20 - if (event->cpu < 0) - return -EINVAL; - rapl_pmus =3D container_of(event->pmu, struct rapl_pmus, pmu); if (!rapl_pmus) return -EINVAL; diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/r= ockchip-dfi.c index 88a9ecbe96ce..87ec7bc965bd 100644 --- a/drivers/devfreq/event/rockchip-dfi.c +++ b/drivers/devfreq/event/rockchip-dfi.c @@ -401,18 +401,6 @@ static const struct attribute_group *attr_groups[] =3D= { =20 static int rockchip_ddr_perf_event_init(struct perf_event *event) { - struct rockchip_dfi *dfi =3D container_of(event->pmu, struct rockchip_dfi= , pmu); - - if (event->attr.type !=3D event->pmu->type) - return -ENOENT; - - if (event->attach_state & PERF_ATTACH_TASK) - return -EINVAL; - - if (event->cpu < 0) { - dev_warn(dfi->dev, "Can't provide per-task data!\n"); - return -EINVAL; - } /* Disallow groups since we can't start/stop/read multiple counters at on= ce */ if (in_hardware_group(event)) return -EINVAL; diff --git a/drivers/dma/idxd/perfmon.c b/drivers/dma/idxd/perfmon.c index 8c539e1f11da..4d6f1fc47685 100644 --- a/drivers/dma/idxd/perfmon.c +++ b/drivers/dma/idxd/perfmon.c @@ -171,20 +171,6 @@ static int perfmon_pmu_event_init(struct perf_event *e= vent) =20 idxd =3D event_to_idxd(event); event->hw.idx =3D -1; - - if (event->attr.type !=3D event->pmu->type) - return -ENOENT; - - /* sampling not supported */ - if (event->attr.sample_period) - return -EINVAL; - - if (event->cpu < 0) - return -EINVAL; - - if (event->pmu !=3D &idxd->idxd_pmu->pmu) - return -EINVAL; - event->hw.event_base =3D ioread64(PERFMON_TABLE_OFFSET(idxd)); event->hw.config =3D event->attr.config; =20 diff --git a/drivers/fpga/dfl-fme-perf.c b/drivers/fpga/dfl-fme-perf.c index a1e2e7f28a3a..0cc9538e0898 100644 --- a/drivers/fpga/dfl-fme-perf.c +++ b/drivers/fpga/dfl-fme-perf.c @@ -799,20 +799,6 @@ static int fme_perf_event_init(struct perf_event *even= t) struct fme_perf_event_ops *ops; u32 eventid, evtype, portid; =20 - /* test the event attr type check for PMU enumeration */ - if (event->attr.type !=3D event->pmu->type) - return -ENOENT; - - /* - * fme counters are shared across all cores. - * Therefore, it does not support per-process mode. - */ - if (event->attach_state & PERF_ATTACH_TASK) - return -EINVAL; - - if (event->cpu < 0) - return -EINVAL; - if (event->cpu !=3D priv->cpu) return -EINVAL; =20 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c b/drivers/gpu/drm/amd/= amdgpu/amdgpu_pmu.c index 6e91ea1de5aa..294a7aea9aaa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c @@ -210,10 +210,6 @@ static int amdgpu_perf_event_init(struct perf_event *e= vent) { struct hw_perf_event *hwc =3D &event->hw; =20 - /* test the event attr type check for PMU enumeration */ - if (event->attr.type !=3D event->pmu->type) - return -ENOENT; - /* update the hw_perf_event struct with config data */ hwc->config =3D event->attr.config; hwc->config_base =3D AMDGPU_PMU_PERF_TYPE_NONE; diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pm= u.c index 5bc696bfbb0f..193e96976782 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -626,19 +626,6 @@ static int i915_pmu_event_init(struct perf_event *even= t) if (!pmu->registered) return -ENODEV; =20 - if (event->attr.type !=3D event->pmu->type) - return -ENOENT; - - /* unsupported modes and filters */ - if (event->attr.sample_period) /* no sampling */ - return -EINVAL; - - if (has_branch_stack(event)) - return -EOPNOTSUPP; - - if (event->cpu < 0) - return -EINVAL; - if (is_engine_event(event)) ret =3D engine_event_init(event); else diff --git a/drivers/gpu/drm/xe/xe_pmu.c b/drivers/gpu/drm/xe/xe_pmu.c index cab51d826345..084e26728c35 100644 --- a/drivers/gpu/drm/xe/xe_pmu.c +++ b/drivers/gpu/drm/xe/xe_pmu.c @@ -238,24 +238,11 @@ static int xe_pmu_event_init(struct perf_event *event) if (!pmu->registered) return -ENODEV; =20 - if (event->attr.type !=3D event->pmu->type) - return -ENOENT; - - /* unsupported modes and filters */ - if (event->attr.sample_period) /* no sampling */ - return -EINVAL; - - if (event->cpu < 0) - return -EINVAL; - gt =3D config_to_gt_id(event->attr.config); id =3D config_to_event_id(event->attr.config); if (!event_supported(pmu, gt, id)) return -ENOENT; =20 - if (has_branch_stack(event)) - return -EOPNOTSUPP; - if (!event_param_valid(event)) return -ENOENT; =20 diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwt= racing/coresight/coresight-etm-perf.c index f1551c08ecb2..fd98eb6a1942 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -178,11 +178,6 @@ static int etm_event_init(struct perf_event *event) { int ret =3D 0; =20 - if (event->attr.type !=3D etm_pmu.type) { - ret =3D -ENOENT; - goto out; - } - ret =3D etm_addr_filters_alloc(event); if (ret) goto out; diff --git a/drivers/hwtracing/ptt/hisi_ptt.c b/drivers/hwtracing/ptt/hisi_= ptt.c index 3090479a2979..470226defa14 100644 --- a/drivers/hwtracing/ptt/hisi_ptt.c +++ b/drivers/hwtracing/ptt/hisi_ptt.c @@ -998,14 +998,6 @@ static int hisi_ptt_pmu_event_init(struct perf_event *= event) int ret; u32 val; =20 - if (event->attr.type !=3D hisi_ptt->hisi_ptt_pmu.type) - return -ENOENT; - - if (event->cpu < 0) { - dev_dbg(event->pmu->dev, "Per-task mode not supported\n"); - return -EOPNOTSUPP; - } - if (event->attach_state & PERF_ATTACH_TASK) return -EOPNOTSUPP; =20 diff --git a/drivers/iommu/intel/perfmon.c b/drivers/iommu/intel/perfmon.c index c3a1ac14cb2b..2b9bb89e1fd3 100644 --- a/drivers/iommu/intel/perfmon.c +++ b/drivers/iommu/intel/perfmon.c @@ -284,16 +284,6 @@ static int iommu_pmu_event_init(struct perf_event *eve= nt) { struct hw_perf_event *hwc =3D &event->hw; =20 - if (event->attr.type !=3D event->pmu->type) - return -ENOENT; - - /* sampling not supported */ - if (event->attr.sample_period) - return -EINVAL; - - if (event->cpu < 0) - return -EINVAL; - if (iommu_pmu_validate_event(event)) return -EINVAL; =20 diff --git a/drivers/perf/alibaba_uncore_drw_pmu.c b/drivers/perf/alibaba_u= ncore_drw_pmu.c index 0081618741c3..2404333ff902 100644 --- a/drivers/perf/alibaba_uncore_drw_pmu.c +++ b/drivers/perf/alibaba_uncore_drw_pmu.c @@ -528,24 +528,7 @@ static int ali_drw_pmu_event_init(struct perf_event *e= vent) struct hw_perf_event *hwc =3D &event->hw; struct device *dev =3D drw_pmu->pmu.dev; =20 - if (event->attr.type !=3D event->pmu->type) - return -ENOENT; - - if (is_sampling_event(event)) { - dev_err(dev, "Sampling not supported!\n"); - return -EOPNOTSUPP; - } - - if (event->attach_state & PERF_ATTACH_TASK) { - dev_err(dev, "Per-task counter cannot allocate!\n"); - return -EOPNOTSUPP; - } - event->cpu =3D drw_pmu->cpu; - if (event->cpu < 0) { - dev_err(dev, "Per-task mode not supported!\n"); - return -EOPNOTSUPP; - } =20 if (in_hardware_group(event)) { dev_err(dev, "driveway only allow one event!\n"); diff --git a/drivers/perf/amlogic/meson_ddr_pmu_core.c b/drivers/perf/amlog= ic/meson_ddr_pmu_core.c index c1e755c356a3..8f46cf835fb5 100644 --- a/drivers/perf/amlogic/meson_ddr_pmu_core.c +++ b/drivers/perf/amlogic/meson_ddr_pmu_core.c @@ -121,15 +121,6 @@ static int meson_ddr_perf_event_init(struct perf_event= *event) u64 config1 =3D event->attr.config1; u64 config2 =3D event->attr.config2; =20 - if (event->attr.type !=3D event->pmu->type) - return -ENOENT; - - if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK) - return -EOPNOTSUPP; - - if (event->cpu < 0) - return -EOPNOTSUPP; - /* check if the number of parameters is too much */ if (event->attr.config !=3D ALL_CHAN_COUNTER_ID && hweight64(config1) + hweight64(config2) > MAX_AXI_PORTS_OF_CHANNEL) diff --git a/drivers/perf/arm-cci.c b/drivers/perf/arm-cci.c index 086d4363fcc8..84ba97389c65 100644 --- a/drivers/perf/arm-cci.c +++ b/drivers/perf/arm-cci.c @@ -1283,13 +1283,6 @@ static int cci_pmu_event_init(struct perf_event *eve= nt) atomic_t *active_events =3D &cci_pmu->active_events; int err =3D 0; =20 - if (event->attr.type !=3D event->pmu->type) - return -ENOENT; - - /* Shared by all CPUs, no meaningful state to sample */ - if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK) - return -EOPNOTSUPP; - /* * Following the example set by other "uncore" PMUs, we accept any CPU * and rewrite its affinity dynamically rather than having perf core @@ -1299,8 +1292,6 @@ static int cci_pmu_event_init(struct perf_event *even= t) * the event being installed into its context, so the PMU's CPU can't * change under our feet. */ - if (event->cpu < 0) - return -EINVAL; event->cpu =3D cci_pmu->cpu; =20 event->destroy =3D hw_perf_event_destroy; diff --git a/drivers/perf/arm-ccn.c b/drivers/perf/arm-ccn.c index 63549aad3b99..6ec4cb9417e7 100644 --- a/drivers/perf/arm-ccn.c +++ b/drivers/perf/arm-ccn.c @@ -704,30 +704,12 @@ static void arm_ccn_pmu_event_release(struct perf_eve= nt *event) static int arm_ccn_pmu_event_init(struct perf_event *event) { struct arm_ccn *ccn; - struct hw_perf_event *hw =3D &event->hw; u32 node_xp, type, event_id; int valid; int i; =20 - if (event->attr.type !=3D event->pmu->type) - return -ENOENT; - ccn =3D pmu_to_arm_ccn(event->pmu); =20 - if (hw->sample_period) { - dev_dbg(ccn->dev, "Sampling not supported!\n"); - return -EOPNOTSUPP; - } - - if (has_branch_stack(event)) { - dev_dbg(ccn->dev, "Can't exclude execution levels!\n"); - return -EINVAL; - } - - if (event->cpu < 0) { - dev_dbg(ccn->dev, "Can't provide per-task data!\n"); - return -EOPNOTSUPP; - } /* * Many perf core operations (eg. events rotation) operate on a * single CPU context. This is obvious for CPU PMUs, where one diff --git a/drivers/perf/arm-cmn.c b/drivers/perf/arm-cmn.c index f8c9be9fa6c0..0f65d28c1b7a 100644 --- a/drivers/perf/arm-cmn.c +++ b/drivers/perf/arm-cmn.c @@ -1765,16 +1765,6 @@ static int arm_cmn_event_init(struct perf_event *eve= nt) bool bynodeid; u16 nodeid, eventid; =20 - if (event->attr.type !=3D event->pmu->type) - return -ENOENT; - - if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK) - return -EINVAL; - - event->cpu =3D cmn->cpu; - if (event->cpu < 0) - return -EINVAL; - type =3D CMN_EVENT_TYPE(event); /* DTC events (i.e. cycles) already have everything they need */ if (type =3D=3D CMN_TYPE_DTC) diff --git a/drivers/perf/arm-ni.c b/drivers/perf/arm-ni.c index d6b683a0264e..c48c82097412 100644 --- a/drivers/perf/arm-ni.c +++ b/drivers/perf/arm-ni.c @@ -309,12 +309,6 @@ static int arm_ni_event_init(struct perf_event *event) { struct arm_ni_cd *cd =3D pmu_to_cd(event->pmu); =20 - if (event->attr.type !=3D event->pmu->type) - return -ENOENT; - - if (is_sampling_event(event)) - return -EINVAL; - event->cpu =3D cd_to_ni(cd)->cpu; if (NI_EVENT_TYPE(event) =3D=3D NI_PMU) return arm_ni_validate_group(event); diff --git a/drivers/perf/arm_cspmu/arm_cspmu.c b/drivers/perf/arm_cspmu/ar= m_cspmu.c index 761b438db231..47d207a97bfc 100644 --- a/drivers/perf/arm_cspmu/arm_cspmu.c +++ b/drivers/perf/arm_cspmu/arm_cspmu.c @@ -601,19 +601,6 @@ static int arm_cspmu_event_init(struct perf_event *eve= nt) =20 cspmu =3D to_arm_cspmu(event->pmu); =20 - if (event->attr.type !=3D event->pmu->type) - return -ENOENT; - - /* - * Following other "uncore" PMUs, we do not support sampling mode or - * attach to a task (per-process mode). - */ - if (event->cpu < 0 || event->attach_state & PERF_ATTACH_TASK) { - dev_dbg(cspmu->pmu.dev, - "Can't support per-task counters\n"); - return -EINVAL; - } - /* * Make sure the CPU assignment is on one of the CPUs associated with * this PMU. diff --git a/drivers/perf/arm_dmc620_pmu.c b/drivers/perf/arm_dmc620_pmu.c index 24308de80246..751a06ba5319 100644 --- a/drivers/perf/arm_dmc620_pmu.c +++ b/drivers/perf/arm_dmc620_pmu.c @@ -514,20 +514,6 @@ static int dmc620_pmu_event_init(struct perf_event *ev= ent) struct dmc620_pmu *dmc620_pmu =3D to_dmc620_pmu(event->pmu); struct hw_perf_event *hwc =3D &event->hw; =20 - if (event->attr.type !=3D event->pmu->type) - return -ENOENT; - - /* - * DMC 620 PMUs are shared across all cpus and cannot - * support task bound and sampling events. - */ - if (is_sampling_event(event) || - event->attach_state & PERF_ATTACH_TASK) { - dev_dbg(dmc620_pmu->pmu.dev, - "Can't support per-task counters\n"); - return -EOPNOTSUPP; - } - /* * Many perf core operations (eg. events rotation) operate on a * single CPU context. This is obvious for CPU PMUs, where one @@ -538,8 +524,6 @@ static int dmc620_pmu_event_init(struct perf_event *eve= nt) * processor. */ event->cpu =3D dmc620_pmu->irq->cpu; - if (event->cpu < 0) - return -EINVAL; =20 hwc->idx =3D -1; =20 diff --git a/drivers/perf/arm_dsu_pmu.c b/drivers/perf/arm_dsu_pmu.c index 7480fd6fe377..eacbe1864794 100644 --- a/drivers/perf/arm_dsu_pmu.c +++ b/drivers/perf/arm_dsu_pmu.c @@ -524,26 +524,6 @@ static int dsu_pmu_event_init(struct perf_event *event) { struct dsu_pmu *dsu_pmu =3D to_dsu_pmu(event->pmu); =20 - if (event->attr.type !=3D event->pmu->type) - return -ENOENT; - - /* We don't support sampling */ - if (is_sampling_event(event)) { - dev_dbg(dsu_pmu->pmu.dev, "Can't support sampling events\n"); - return -EOPNOTSUPP; - } - - /* We cannot support task bound events */ - if (event->cpu < 0 || event->attach_state & PERF_ATTACH_TASK) { - dev_dbg(dsu_pmu->pmu.dev, "Can't support per-task counters\n"); - return -EINVAL; - } - - if (has_branch_stack(event)) { - dev_dbg(dsu_pmu->pmu.dev, "Can't support filtering\n"); - return -EINVAL; - } - if (!cpumask_test_cpu(event->cpu, &dsu_pmu->associated_cpus)) { dev_dbg(dsu_pmu->pmu.dev, "Requested cpu is not associated with the DSU\n"); diff --git a/drivers/perf/arm_smmuv3_pmu.c b/drivers/perf/arm_smmuv3_pmu.c index 7cac380a3528..d534a4eb457a 100644 --- a/drivers/perf/arm_smmuv3_pmu.c +++ b/drivers/perf/arm_smmuv3_pmu.c @@ -398,19 +398,6 @@ static int smmu_pmu_event_init(struct perf_event *even= t) int group_num_events =3D 1; u16 event_id; =20 - if (event->attr.type !=3D event->pmu->type) - return -ENOENT; - - if (hwc->sample_period) { - dev_dbg(dev, "Sampling not supported\n"); - return -EOPNOTSUPP; - } - - if (event->cpu < 0) { - dev_dbg(dev, "Per-task mode not supported\n"); - return -EOPNOTSUPP; - } - /* Verify specified event is supported on this PMU */ event_id =3D get_event(event); if (event_id < SMMU_PMCG_ARCH_MAX_EVENTS && diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c index dbd52851f5c6..89001d2ceabf 100644 --- a/drivers/perf/arm_spe_pmu.c +++ b/drivers/perf/arm_spe_pmu.c @@ -718,10 +718,6 @@ static int arm_spe_pmu_event_init(struct perf_event *e= vent) struct perf_event_attr *attr =3D &event->attr; struct arm_spe_pmu *spe_pmu =3D to_spe_pmu(event->pmu); =20 - /* This is, of course, deeply driver-specific */ - if (attr->type !=3D event->pmu->type) - return -ENOENT; - if (event->cpu >=3D 0 && !cpumask_test_cpu(event->cpu, &spe_pmu->supported_cpus)) return -ENOENT; diff --git a/drivers/perf/cxl_pmu.c b/drivers/perf/cxl_pmu.c index d094030220bf..c4f8d5ae45a1 100644 --- a/drivers/perf/cxl_pmu.c +++ b/drivers/perf/cxl_pmu.c @@ -563,12 +563,6 @@ static int cxl_pmu_event_init(struct perf_event *event) struct cxl_pmu_info *info =3D pmu_to_cxl_pmu_info(event->pmu); int rc; =20 - /* Top level type sanity check - is this a Hardware Event being requested= */ - if (event->attr.type !=3D event->pmu->type) - return -ENOENT; - - if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK) - return -EOPNOTSUPP; /* TODO: Validation of any filter */ =20 /* diff --git a/drivers/perf/dwc_pcie_pmu.c b/drivers/perf/dwc_pcie_pmu.c index 78c522658d84..a0eb72c38fdb 100644 --- a/drivers/perf/dwc_pcie_pmu.c +++ b/drivers/perf/dwc_pcie_pmu.c @@ -355,17 +355,6 @@ static int dwc_pcie_pmu_event_init(struct perf_event *= event) enum dwc_pcie_event_type type =3D DWC_PCIE_EVENT_TYPE(event); u32 lane; =20 - if (event->attr.type !=3D event->pmu->type) - return -ENOENT; - - /* We don't support sampling */ - if (is_sampling_event(event)) - return -EINVAL; - - /* We cannot support task bound events */ - if (event->cpu < 0 || event->attach_state & PERF_ATTACH_TASK) - return -EINVAL; - /* Disallow groups since we can't start/stop/read multiple counters at on= ce */ if (in_hardware_group(event)) return -EINVAL; diff --git a/drivers/perf/fsl_imx8_ddr_perf.c b/drivers/perf/fsl_imx8_ddr_p= erf.c index 56fe281974d2..d63d5d4d9084 100644 --- a/drivers/perf/fsl_imx8_ddr_perf.c +++ b/drivers/perf/fsl_imx8_ddr_perf.c @@ -401,17 +401,6 @@ static int ddr_perf_event_init(struct perf_event *even= t) struct hw_perf_event *hwc =3D &event->hw; struct perf_event *sibling; =20 - if (event->attr.type !=3D event->pmu->type) - return -ENOENT; - - if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK) - return -EOPNOTSUPP; - - if (event->cpu < 0) { - dev_warn(pmu->dev, "Can't provide per-task data!\n"); - return -EOPNOTSUPP; - } - if (event !=3D event->group_leader && pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER) { if (!ddr_perf_filters_compatible(event, event->group_leader)) diff --git a/drivers/perf/fsl_imx9_ddr_perf.c b/drivers/perf/fsl_imx9_ddr_p= erf.c index 85874ec5ecd0..9e0b2a969481 100644 --- a/drivers/perf/fsl_imx9_ddr_perf.c +++ b/drivers/perf/fsl_imx9_ddr_perf.c @@ -553,17 +553,6 @@ static int ddr_perf_event_init(struct perf_event *even= t) struct ddr_pmu *pmu =3D to_ddr_pmu(event->pmu); struct hw_perf_event *hwc =3D &event->hw; =20 - if (event->attr.type !=3D event->pmu->type) - return -ENOENT; - - if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK) - return -EOPNOTSUPP; - - if (event->cpu < 0) { - dev_warn(pmu->dev, "Can't provide per-task data!\n"); - return -EOPNOTSUPP; - } - event->cpu =3D pmu->cpu; hwc->idx =3D -1; =20 diff --git a/drivers/perf/hisilicon/hisi_pcie_pmu.c b/drivers/perf/hisilico= n/hisi_pcie_pmu.c index 3b0b2f7197d0..b0b736af82e3 100644 --- a/drivers/perf/hisilicon/hisi_pcie_pmu.c +++ b/drivers/perf/hisilicon/hisi_pcie_pmu.c @@ -378,19 +378,11 @@ static int hisi_pcie_pmu_event_init(struct perf_event= *event) struct hisi_pcie_pmu *pcie_pmu =3D to_pcie_pmu(event->pmu); struct hw_perf_event *hwc =3D &event->hw; =20 - /* Check the type first before going on, otherwise it's not our event */ - if (event->attr.type !=3D event->pmu->type) - return -ENOENT; - if (EXT_COUNTER_IS_USED(hisi_pcie_get_event(event))) hwc->event_base =3D HISI_PCIE_EXT_CNT; else hwc->event_base =3D HISI_PCIE_CNT; =20 - /* Sampling is not supported. */ - if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK) - return -EOPNOTSUPP; - if (!hisi_pcie_pmu_valid_filter(event, pcie_pmu)) return -EINVAL; =20 diff --git a/drivers/perf/hisilicon/hisi_uncore_pmu.c b/drivers/perf/hisili= con/hisi_uncore_pmu.c index 3c531b36cf25..67d64d664b4f 100644 --- a/drivers/perf/hisilicon/hisi_uncore_pmu.c +++ b/drivers/perf/hisilicon/hisi_uncore_pmu.c @@ -199,24 +199,6 @@ int hisi_uncore_pmu_event_init(struct perf_event *even= t) struct hw_perf_event *hwc =3D &event->hw; struct hisi_pmu *hisi_pmu; =20 - if (event->attr.type !=3D event->pmu->type) - return -ENOENT; - - /* - * We do not support sampling as the counters are all - * shared by all CPU cores in a CPU die(SCCL). Also we - * do not support attach to a task(per-process mode) - */ - if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK) - return -EOPNOTSUPP; - - /* - * The uncore counters not specific to any CPU, so cannot - * support per-task - */ - if (event->cpu < 0) - return -EINVAL; - /* * Validate if the events in group does not exceed the * available counters in hardware. diff --git a/drivers/perf/hisilicon/hns3_pmu.c b/drivers/perf/hisilicon/hns= 3_pmu.c index 382e469257f9..f6996eafea5a 100644 --- a/drivers/perf/hisilicon/hns3_pmu.c +++ b/drivers/perf/hisilicon/hns3_pmu.c @@ -1233,13 +1233,6 @@ static int hns3_pmu_event_init(struct perf_event *ev= ent) int idx; int ret; =20 - if (event->attr.type !=3D event->pmu->type) - return -ENOENT; - - /* Sampling is not supported */ - if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK) - return -EOPNOTSUPP; - event->cpu =3D hns3_pmu->on_cpu; =20 idx =3D hns3_pmu_get_event_idx(hns3_pmu); diff --git a/drivers/perf/marvell_cn10k_ddr_pmu.c b/drivers/perf/marvell_cn= 10k_ddr_pmu.c index 54e3fd206d39..26ad83cdb735 100644 --- a/drivers/perf/marvell_cn10k_ddr_pmu.c +++ b/drivers/perf/marvell_cn10k_ddr_pmu.c @@ -474,19 +474,6 @@ static int cn10k_ddr_perf_event_init(struct perf_event= *event) struct cn10k_ddr_pmu *pmu =3D to_cn10k_ddr_pmu(event->pmu); struct hw_perf_event *hwc =3D &event->hw; =20 - if (event->attr.type !=3D event->pmu->type) - return -ENOENT; - - if (is_sampling_event(event)) { - dev_info(pmu->dev, "Sampling not supported!\n"); - return -EOPNOTSUPP; - } - - if (event->cpu < 0) { - dev_warn(pmu->dev, "Can't provide per-task data!\n"); - return -EOPNOTSUPP; - } - /* Set ownership of event to one CPU, same event can not be observed * on multiple cpus at same time. */ diff --git a/drivers/perf/marvell_cn10k_tad_pmu.c b/drivers/perf/marvell_cn= 10k_tad_pmu.c index a162e707a639..6ed30a649ed3 100644 --- a/drivers/perf/marvell_cn10k_tad_pmu.c +++ b/drivers/perf/marvell_cn10k_tad_pmu.c @@ -149,9 +149,6 @@ static int tad_pmu_event_init(struct perf_event *event) { struct tad_pmu *tad_pmu =3D to_tad_pmu(event->pmu); =20 - if (event->attr.type !=3D event->pmu->type) - return -ENOENT; - /* Disallow groups since we can't start/stop/read multiple counters at on= ce */ if (in_hardware_group(event)) return -EINVAL; diff --git a/drivers/perf/marvell_pem_pmu.c b/drivers/perf/marvell_pem_pmu.c index 53a35a5de7f8..5c7abae77c12 100644 --- a/drivers/perf/marvell_pem_pmu.c +++ b/drivers/perf/marvell_pem_pmu.c @@ -191,20 +191,9 @@ static int pem_perf_event_init(struct perf_event *even= t) struct pem_pmu *pmu =3D to_pem_pmu(event->pmu); struct hw_perf_event *hwc =3D &event->hw; =20 - if (event->attr.type !=3D event->pmu->type) - return -ENOENT; - if (event->attr.config >=3D PEM_EVENTIDS_MAX) return -EINVAL; =20 - if (is_sampling_event(event) || - event->attach_state & PERF_ATTACH_TASK) { - return -EOPNOTSUPP; - } - - if (event->cpu < 0) - return -EOPNOTSUPP; - /* Disallow groups since we can't start/stop/read multiple counters at on= ce */ if (in_hardware_group(event)) return -EINVAL; diff --git a/drivers/perf/qcom_l2_pmu.c b/drivers/perf/qcom_l2_pmu.c index 9c4e1d89718d..eba9a7e40293 100644 --- a/drivers/perf/qcom_l2_pmu.c +++ b/drivers/perf/qcom_l2_pmu.c @@ -442,23 +442,8 @@ static int l2_cache_event_init(struct perf_event *even= t) struct perf_event *sibling; struct l2cache_pmu *l2cache_pmu; =20 - if (event->attr.type !=3D event->pmu->type) - return -ENOENT; - l2cache_pmu =3D to_l2cache_pmu(event->pmu); =20 - if (hwc->sample_period) { - dev_dbg_ratelimited(&l2cache_pmu->pdev->dev, - "Sampling not supported\n"); - return -EOPNOTSUPP; - } - - if (event->cpu < 0) { - dev_dbg_ratelimited(&l2cache_pmu->pdev->dev, - "Per-task mode not supported\n"); - return -EOPNOTSUPP; - } - if (((L2_EVT_GROUP(event->attr.config) > L2_EVT_GROUP_MAX) || ((event->attr.config & ~L2_EVT_MASK) !=3D 0)) && (event->attr.config !=3D L2CYCLE_CTR_RAW_CODE)) { diff --git a/drivers/perf/qcom_l3_pmu.c b/drivers/perf/qcom_l3_pmu.c index f0cf6c33418d..af0ced386fb1 100644 --- a/drivers/perf/qcom_l3_pmu.c +++ b/drivers/perf/qcom_l3_pmu.c @@ -478,25 +478,6 @@ static int qcom_l3_cache__event_init(struct perf_event= *event) struct l3cache_pmu *l3pmu =3D to_l3cache_pmu(event->pmu); struct hw_perf_event *hwc =3D &event->hw; =20 - /* - * Is the event for this PMU? - */ - if (event->attr.type !=3D event->pmu->type) - return -ENOENT; - - /* - * Sampling not supported since these events are not core-attributable. - */ - if (hwc->sample_period) - return -EINVAL; - - /* - * Task mode not available, we run the counters as socket counters, - * not attributable to any CPU and therefore cannot attribute per-task. - */ - if (event->cpu < 0) - return -EINVAL; - /* Validate the group */ if (!qcom_l3_cache__validate_event_group(event)) return -EINVAL; diff --git a/drivers/perf/starfive_starlink_pmu.c b/drivers/perf/starfive_s= tarlink_pmu.c index e185f307e639..ee5216403417 100644 --- a/drivers/perf/starfive_starlink_pmu.c +++ b/drivers/perf/starfive_starlink_pmu.c @@ -366,20 +366,6 @@ static int starlink_pmu_event_init(struct perf_event *= event) struct starlink_pmu *starlink_pmu =3D to_starlink_pmu(event->pmu); struct hw_perf_event *hwc =3D &event->hw; =20 - /* - * Sampling is not supported, as counters are shared - * by all CPU. - */ - if (hwc->sample_period) - return -EOPNOTSUPP; - - /* - * Per-task and attach to a task are not supported, - * as uncore events are not specific to any CPU. - */ - if (event->cpu < 0 || event->attach_state & PERF_ATTACH_TASK) - return -EOPNOTSUPP; - if (!starlink_pmu_validate_event_group(event)) return -EINVAL; =20 diff --git a/drivers/perf/thunderx2_pmu.c b/drivers/perf/thunderx2_pmu.c index 472eb4494fd1..0ef85cb72289 100644 --- a/drivers/perf/thunderx2_pmu.c +++ b/drivers/perf/thunderx2_pmu.c @@ -553,21 +553,6 @@ static int tx2_uncore_event_init(struct perf_event *ev= ent) struct hw_perf_event *hwc =3D &event->hw; struct tx2_uncore_pmu *tx2_pmu; =20 - /* Test the event attr type check for PMU enumeration */ - if (event->attr.type !=3D event->pmu->type) - return -ENOENT; - - /* - * SOC PMU counters are shared across all cores. - * Therefore, it does not support per-process mode. - * Also, it does not support event sampling mode. - */ - if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK) - return -EINVAL; - - if (event->cpu < 0) - return -EINVAL; - tx2_pmu =3D pmu_to_tx2_pmu(event->pmu); if (tx2_pmu->cpu >=3D nr_cpu_ids) return -EINVAL; diff --git a/drivers/perf/xgene_pmu.c b/drivers/perf/xgene_pmu.c index 5e80ae0e692d..408e69533e7a 100644 --- a/drivers/perf/xgene_pmu.c +++ b/drivers/perf/xgene_pmu.c @@ -878,20 +878,6 @@ static int xgene_perf_event_init(struct perf_event *ev= ent) struct xgene_pmu_dev *pmu_dev =3D to_pmu_dev(event->pmu); struct hw_perf_event *hw =3D &event->hw; =20 - /* Test the event attr type check for PMU enumeration */ - if (event->attr.type !=3D event->pmu->type) - return -ENOENT; - - /* - * SOC PMU counters are shared across all cores. - * Therefore, it does not support per-process mode. - * Also, it does not support event sampling mode. - */ - if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK) - return -EINVAL; - - if (event->cpu < 0) - return -EINVAL; /* * Many perf core operations (eg. events rotation) operate on a * single CPU context. This is obvious for CPU PMUs, where one diff --git a/drivers/powercap/intel_rapl_common.c b/drivers/powercap/intel_= rapl_common.c index 38470351217b..eff369b02773 100644 --- a/drivers/powercap/intel_rapl_common.c +++ b/drivers/powercap/intel_rapl_common.c @@ -1791,17 +1791,10 @@ static int rapl_pmu_event_init(struct perf_event *e= vent) u64 cfg =3D event->attr.config & RAPL_EVENT_MASK; int domain, idx; =20 - /* Only look at RAPL events */ - if (event->attr.type !=3D event->pmu->type) - return -ENOENT; - /* Check for supported events only */ if (!cfg || cfg >=3D PERF_RAPL_MAX) return -EINVAL; =20 - if (event->cpu < 0) - return -EINVAL; - /* Find out which Package the event belongs to */ list_for_each_entry(pos, &rapl_packages, plist) { if (is_rp_pmu_cpu(pos, event->cpu)) { --=20 2.39.2.101.g768bb238c484.dirty