From nobody Sat Oct 4 22:33:08 2025 Received: from pegase2.c-s.fr (pegase2.c-s.fr [93.17.235.10]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D8B632ED86F; Tue, 12 Aug 2025 11:21:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=93.17.235.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754997664; cv=none; b=tTNmYrNLo/tyakzuCd+QeUW23v0OZ2+BF1kdVlAMd4h3MeShAFLuahwskqyk4H0tR5uFs0DR7D7eDEnZKP1Vpl9cYWiEoIMvB4j7mc+2KNeIjoyvcbJNTYuwmJar2FLT/awk1fuiLNbFX8lDSG6iIAvZ9y9QgyJaFrIttDYhE88= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754997664; c=relaxed/simple; bh=WPex1Yqsty/iZf3dA0/61+TQ4SmTdE50vpw/kqBQT0g=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qqSTlWJHz9pY00e2AaOjT0sTDWsJ5Ix4OHX7ZBd1f+097XDG0qeGi5wE+nbAaW0i5Qs0VaVKdW1XczkDQxS0c03t6JS5ZVKZowRjCTrC6V+OHAxTzm6uw4nSNZMIqYZrPTxqyb/pPdeMEEsPGtp/8zE3BhiwUeaGC6JdkzuRCjQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=csgroup.eu; spf=pass smtp.mailfrom=csgroup.eu; arc=none smtp.client-ip=93.17.235.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=csgroup.eu Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=csgroup.eu Received: from localhost (mailhub4.si.c-s.fr [172.26.127.67]) by localhost (Postfix) with ESMTP id 4c1TBN1Y3Gz9sSr; Tue, 12 Aug 2025 13:03:08 +0200 (CEST) X-Virus-Scanned: amavisd-new at c-s.fr Received: from pegase2.c-s.fr ([172.26.127.65]) by localhost (pegase2.c-s.fr [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id aqZGFjYI7JVc; Tue, 12 Aug 2025 13:03:08 +0200 (CEST) Received: from messagerie.si.c-s.fr (messagerie.si.c-s.fr [192.168.25.192]) by pegase2.c-s.fr (Postfix) with ESMTP id 4c1TBN0bxcz9sSj; Tue, 12 Aug 2025 13:03:08 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by messagerie.si.c-s.fr (Postfix) with ESMTP id F32678B765; Tue, 12 Aug 2025 13:03:07 +0200 (CEST) X-Virus-Scanned: amavisd-new at c-s.fr Received: from messagerie.si.c-s.fr ([127.0.0.1]) by localhost (messagerie.si.c-s.fr [127.0.0.1]) (amavisd-new, port 10023) with ESMTP id goOITLSSY6vA; Tue, 12 Aug 2025 13:03:07 +0200 (CEST) Received: from PO20335.idsi0.si.c-s.fr (unknown [192.168.235.99]) by messagerie.si.c-s.fr (Postfix) with ESMTP id 5D1B88B763; Tue, 12 Aug 2025 13:03:07 +0200 (CEST) From: Christophe Leroy To: Qiang Zhao , Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Christophe Leroy , linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 1/4] soc: fsl: qe: Add an interrupt controller for QUICC Engine Ports Date: Tue, 12 Aug 2025 13:02:51 +0200 Message-ID: <1dcc9528e97d228ea7889caa00cc254ef0375ed4.1754996033.git.christophe.leroy@csgroup.eu> X-Mailer: git-send-email 2.49.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1754996575; l=5167; i=christophe.leroy@csgroup.eu; s=20211009; h=from:subject:message-id; bh=WPex1Yqsty/iZf3dA0/61+TQ4SmTdE50vpw/kqBQT0g=; b=iuEPS/cUKH08Rr6/vdpWQIiuCh6T4gHqCrBGgyTNoCggCQ5IQOipYvvM6kxoRgpryGcWp+iGG bSNEG57GtPrCjg0JSMitvJRZ6t/FAF660q0V+hXERQCi0jLJn23HOsH X-Developer-Key: i=christophe.leroy@csgroup.eu; a=ed25519; pk=HIzTzUj91asvincQGOFx6+ZF5AoUuP9GdOtQChs7Mm0= Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The QUICC Engine provides interrupts for a few I/O ports. This is handled via a separate interrupt ID and managed via a triplet of dedicated registers hosted by the SoC. Implement an interrupt driver for it for that those IRQs can then be linked to the related GPIOs. The number of ports for which interrupts are supported depends on the microcontroller: - mpc8323 has 10 interrupts - mpc8360 has 28 interrupts - mpc8568 has 18 interrupts So add this information as data of the compatible. Signed-off-by: Christophe Leroy --- drivers/soc/fsl/qe/Makefile | 2 +- drivers/soc/fsl/qe/qe_ports_ic.c | 156 +++++++++++++++++++++++++++++++ 2 files changed, 157 insertions(+), 1 deletion(-) create mode 100644 drivers/soc/fsl/qe/qe_ports_ic.c diff --git a/drivers/soc/fsl/qe/Makefile b/drivers/soc/fsl/qe/Makefile index ec8506e131136..901a9c40d5eb7 100644 --- a/drivers/soc/fsl/qe/Makefile +++ b/drivers/soc/fsl/qe/Makefile @@ -11,4 +11,4 @@ obj-$(CONFIG_UCC_SLOW) +=3D ucc_slow.o obj-$(CONFIG_UCC_FAST) +=3D ucc_fast.o obj-$(CONFIG_QE_TDM) +=3D qe_tdm.o obj-$(CONFIG_QE_USB) +=3D usb.o -obj-$(CONFIG_QE_GPIO) +=3D gpio.o +obj-$(CONFIG_QE_GPIO) +=3D gpio.o qe_ports_ic.o diff --git a/drivers/soc/fsl/qe/qe_ports_ic.c b/drivers/soc/fsl/qe/qe_ports= _ic.c new file mode 100644 index 0000000000000..2ab82ac259564 --- /dev/null +++ b/drivers/soc/fsl/qe/qe_ports_ic.c @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * QUICC ENGINE I/O Ports Interrupt Controller + * + * Copyright (c) 2025 Christophe Leroy CS GROUP France (christophe.leroy@c= sgroup.eu) + */ + +#include +#include +#include + +/* QE IC registers offset */ +#define CEPIER 0x0c +#define CEPIMR 0x10 +#define CEPICR 0x14 + +struct qepic_data { + void __iomem *reg; + struct irq_domain *host; +}; + +static void qepic_mask(struct irq_data *d) +{ + struct qepic_data *data =3D irq_data_get_irq_chip_data(d); + + clrbits32(data->reg + CEPIMR, 1 << (31 - irqd_to_hwirq(d))); +} + +static void qepic_unmask(struct irq_data *d) +{ + struct qepic_data *data =3D irq_data_get_irq_chip_data(d); + + setbits32(data->reg + CEPIMR, 1 << (31 - irqd_to_hwirq(d))); +} + +static void qepic_end(struct irq_data *d) +{ + struct qepic_data *data =3D irq_data_get_irq_chip_data(d); + + out_be32(data->reg + CEPIER, 1 << (31 - irqd_to_hwirq(d))); +} + +static int qepic_set_type(struct irq_data *d, unsigned int flow_type) +{ + struct qepic_data *data =3D irq_data_get_irq_chip_data(d); + unsigned int vec =3D (unsigned int)irqd_to_hwirq(d); + + switch (flow_type & IRQ_TYPE_SENSE_MASK) { + case IRQ_TYPE_EDGE_FALLING: + setbits32(data->reg + CEPICR, 1 << (31 - vec)); + return 0; + case IRQ_TYPE_EDGE_BOTH: + case IRQ_TYPE_NONE: + clrbits32(data->reg + CEPICR, 1 << (31 - vec)); + return 0; + } + return -EINVAL; +} + +static struct irq_chip qepic =3D { + .name =3D "QEPIC", + .irq_mask =3D qepic_mask, + .irq_unmask =3D qepic_unmask, + .irq_eoi =3D qepic_end, + .irq_set_type =3D qepic_set_type, +}; + +static int qepic_get_irq(struct irq_desc *desc) +{ + struct qepic_data *data =3D irq_desc_get_handler_data(desc); + u32 event =3D in_be32(data->reg + CEPIER); + + if (!event) + return -1; + + return irq_find_mapping(data->host, 32 - ffs(event)); +} + +static void qepic_cascade(struct irq_desc *desc) +{ + generic_handle_irq(qepic_get_irq(desc)); +} + +static int qepic_host_map(struct irq_domain *h, unsigned int virq, irq_hw_= number_t hw) +{ + irq_set_chip_data(virq, h->host_data); + irq_set_chip_and_handler(virq, &qepic, handle_fasteoi_irq); + return 0; +} + +static const struct irq_domain_ops qepic_host_ops =3D { + .map =3D qepic_host_map, +}; + +static int qepic_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct qepic_data *data; + int irq; + int nb; + + nb =3D (int)of_device_get_match_data(dev); + if (nb < 1 || nb > 32) + return -EINVAL; + + data =3D devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->reg =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(data->reg)) + return PTR_ERR(data->reg); + + irq =3D platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + data->host =3D irq_domain_add_linear(dev->of_node, nb, &qepic_host_ops, d= ata); + if (!data->host) + return -ENODEV; + + irq_set_handler_data(irq, data); + irq_set_chained_handler(irq, qepic_cascade); + + return 0; +} + +static const struct of_device_id qepic_match[] =3D { + { + .compatible =3D "fsl,mpc8323-qe-ports-ic", + .data =3D (void *)10, + }, + { + .compatible =3D "fsl,mpc8360-qe-ports-ic", + .data =3D (void *)28, + }, + { + .compatible =3D "fsl,mpc8568-qe-ports-ic", + .data =3D (void *)18, + }, + {}, +}; + +static struct platform_driver qepic_driver =3D { + .driver =3D { + .name =3D "qe_ports_ic", + .of_match_table =3D qepic_match, + }, + .probe =3D qepic_probe, +}; + +static int __init qepic_init(void) +{ + return platform_driver_register(&qepic_driver); +} +arch_initcall(qepic_init); --=20 2.49.0 From nobody Sat Oct 4 22:33:08 2025 Received: from pegase2.c-s.fr (pegase2.c-s.fr [93.17.235.10]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 8CCF02ED85C; Tue, 12 Aug 2025 11:20:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=93.17.235.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754997660; cv=none; b=tNtGh5V8P/O86gyIwhibZo8Zt5dUHKQYmlD98IrfnVogHSGBtLd/jkqXLBY+8U39aliOD2YH5j+LJxvEWN6PLSALVJkD8M4aYOx5NFNvR6C5zK03AHdeNSiGNWKiooTClLiPkFrToUICMipN39UFrzCcxo7IawfaQaZ4PsBpWSU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754997660; c=relaxed/simple; bh=VYssVgP/HSCvUsH61iWhixO+M16MVUEty2f4L9mgniA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GTtEkX9ehRzRkf3kQgY3QNTyFqaShUa1xetf/rBCTcf1W3zEJfaqoBoa4/Adj04cYRp+APr5HVTd015eI4vanue0QCF/p2rDdZ0Ie8VNIkQSvkLHkRNYlswYk+vot1qUtMbhMxQxetoK9PluemmMy5CdQUTIbX/wDAcUlRkRVpg= ARC-Authentication-Results: i=1; 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Tue, 12 Aug 2025 13:03:08 +0200 (CEST) X-Virus-Scanned: amavisd-new at c-s.fr Received: from messagerie.si.c-s.fr ([127.0.0.1]) by localhost (messagerie.si.c-s.fr [127.0.0.1]) (amavisd-new, port 10023) with ESMTP id XDZeo0gya3AY; Tue, 12 Aug 2025 13:03:08 +0200 (CEST) Received: from PO20335.idsi0.si.c-s.fr (unknown [192.168.235.99]) by messagerie.si.c-s.fr (Postfix) with ESMTP id EAD738B764; Tue, 12 Aug 2025 13:03:07 +0200 (CEST) From: Christophe Leroy To: Qiang Zhao , Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Christophe Leroy , linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 2/4] soc: fsl: qe: Change GPIO driver to a proper platform driver Date: Tue, 12 Aug 2025 13:02:52 +0200 Message-ID: X-Mailer: git-send-email 2.49.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1754996575; l=3238; i=christophe.leroy@csgroup.eu; s=20211009; h=from:subject:message-id; bh=VYssVgP/HSCvUsH61iWhixO+M16MVUEty2f4L9mgniA=; b=iodPhBkh8iWD/od14mpEwzyP2AImC5CmU51Db62oh3CqMDvFaocRNpunshUxSvRzZ/wMVVWaw WMzyeRAJqalAHJY+M1Y8ugaWisKOtZ46bpCFGqhsP7ObMLulySbbKO+ X-Developer-Key: i=christophe.leroy@csgroup.eu; a=ed25519; pk=HIzTzUj91asvincQGOFx6+ZF5AoUuP9GdOtQChs7Mm0= Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In order to be able to add interrupts to the GPIOs, first change the QE GPIO driver to the proper platform driver in order to allow initialisation to be done in the right order, otherwise the GPIOs get added before the interrupts are registered. Signed-off-by: Christophe Leroy Reviewed-by: Bartosz Golaszewski --- drivers/soc/fsl/qe/gpio.c | 88 +++++++++++++++++++++++---------------- 1 file changed, 53 insertions(+), 35 deletions(-) diff --git a/drivers/soc/fsl/qe/gpio.c b/drivers/soc/fsl/qe/gpio.c index 8df1e8fa86a5f..b502377193192 100644 --- a/drivers/soc/fsl/qe/gpio.c +++ b/drivers/soc/fsl/qe/gpio.c @@ -19,6 +19,7 @@ #include #include #include +#include =20 #include =20 @@ -295,45 +296,62 @@ void qe_pin_set_gpio(struct qe_pin *qe_pin) } EXPORT_SYMBOL(qe_pin_set_gpio); =20 -static int __init qe_add_gpiochips(void) +static int qe_gpio_probe(struct platform_device *ofdev) { - struct device_node *np; - - for_each_compatible_node(np, NULL, "fsl,mpc8323-qe-pario-bank") { - int ret; - struct qe_gpio_chip *qe_gc; - struct of_mm_gpio_chip *mm_gc; - struct gpio_chip *gc; - - qe_gc =3D kzalloc(sizeof(*qe_gc), GFP_KERNEL); - if (!qe_gc) { - ret =3D -ENOMEM; - goto err; - } + struct device *dev =3D &ofdev->dev; + struct device_node *np =3D dev->of_node; + int ret; + struct qe_gpio_chip *qe_gc; + struct of_mm_gpio_chip *mm_gc; + struct gpio_chip *gc; + + qe_gc =3D kzalloc(sizeof(*qe_gc), GFP_KERNEL); + if (!qe_gc) { + ret =3D -ENOMEM; + goto err; + } =20 - spin_lock_init(&qe_gc->lock); + spin_lock_init(&qe_gc->lock); =20 - mm_gc =3D &qe_gc->mm_gc; - gc =3D &mm_gc->gc; + mm_gc =3D &qe_gc->mm_gc; + gc =3D &mm_gc->gc; =20 - mm_gc->save_regs =3D qe_gpio_save_regs; - gc->ngpio =3D QE_PIO_PINS; - gc->direction_input =3D qe_gpio_dir_in; - gc->direction_output =3D qe_gpio_dir_out; - gc->get =3D qe_gpio_get; - gc->set =3D qe_gpio_set; - gc->set_multiple =3D qe_gpio_set_multiple; + mm_gc->save_regs =3D qe_gpio_save_regs; + gc->ngpio =3D QE_PIO_PINS; + gc->direction_input =3D qe_gpio_dir_in; + gc->direction_output =3D qe_gpio_dir_out; + gc->get =3D qe_gpio_get; + gc->set =3D qe_gpio_set; + gc->set_multiple =3D qe_gpio_set_multiple; =20 - ret =3D of_mm_gpiochip_add_data(np, mm_gc, qe_gc); - if (ret) - goto err; - continue; + ret =3D of_mm_gpiochip_add_data(np, mm_gc, qe_gc); + if (!ret) + return 0; err: - pr_err("%pOF: registration failed with status %d\n", - np, ret); - kfree(qe_gc); - /* try others anyway */ - } - return 0; + dev_err(dev, "registration failed with status %d\n", ret); + kfree(qe_gc); + + return ret; +} + +static const struct of_device_id qe_gpio_match[] =3D { + { + .compatible =3D "fsl,mpc8323-qe-pario-bank", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, qe_gpio_match); + +static struct platform_driver qe_gpio_driver =3D { + .probe =3D qe_gpio_probe, + .driver =3D { + .name =3D "qe-gpio", + .of_match_table =3D qe_gpio_match, + }, +}; + +static int __init qe_gpio_init(void) +{ + return platform_driver_register(&qe_gpio_driver); } -arch_initcall(qe_add_gpiochips); +arch_initcall(qe_gpio_init); --=20 2.49.0 From nobody Sat Oct 4 22:33:08 2025 Received: from pegase2.c-s.fr (pegase2.c-s.fr [93.17.235.10]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 0C1312EB5D2; Tue, 12 Aug 2025 11:20:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Tue, 12 Aug 2025 13:03:08 +0200 (CEST) From: Christophe Leroy To: Qiang Zhao , Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Christophe Leroy , linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 3/4] soc: fsl: qe: Add support of IRQ in QE GPIO Date: Tue, 12 Aug 2025 13:02:53 +0200 Message-ID: <22b3847fd0011024c10aff48f1e5223894ce718a.1754996033.git.christophe.leroy@csgroup.eu> X-Mailer: git-send-email 2.49.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1754996575; l=2725; i=christophe.leroy@csgroup.eu; s=20211009; h=from:subject:message-id; bh=v14Dk1KvyA4jB0LrdnvGbfGjnbuOs9htFoqSNoWkYtI=; b=dXtCrFHN514T4E/+vNSzepJEqiPBNmxYhnTflHs68WWX2CBvxIoCBh8xJ/qz54T5GIKOuB9uB 8/NM/UEmSe3CNdXNEgNpmWyRAEbLLMxt2jbdc7GgWwSqpsaS8xWZXxl X-Developer-Key: i=christophe.leroy@csgroup.eu; a=ed25519; pk=HIzTzUj91asvincQGOFx6+ZF5AoUuP9GdOtQChs7Mm0= Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In the QE, a few GPIOs are IRQ capable. Similarly to commit 726bd223105c ("powerpc/8xx: Adding support of IRQ in MPC8xx GPIO"), add IRQ support to QE GPIO. Add property 'fsl,qe-gpio-irq-mask' similar to 'fsl,cpm1-gpio-irq-mask' that define which of the GPIOs have IRQs. Here is an exemple for port B of mpc8323 which has IRQs for GPIOs PB7, PB9, PB25 and PB27. qe_pio_b: gpio-controller@1418 { #gpio-cells =3D <2>; compatible =3D "fsl,mpc8323-qe-pario-bank"; reg =3D <0x1418 0x18>; interrupts =3D <4 5 6 7>; fsl,qe-gpio-irq-mask =3D <0x01400050>; interrupt-parent =3D <&qepic>; gpio-controller; }; Signed-off-by: Christophe Leroy --- drivers/soc/fsl/qe/gpio.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/soc/fsl/qe/gpio.c b/drivers/soc/fsl/qe/gpio.c index b502377193192..59145652ad850 100644 --- a/drivers/soc/fsl/qe/gpio.c +++ b/drivers/soc/fsl/qe/gpio.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -32,6 +33,8 @@ struct qe_gpio_chip { =20 /* saved_regs used to restore dedicated functions */ struct qe_pio_regs saved_regs; + + int irq[32]; }; =20 static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_gc) @@ -141,6 +144,13 @@ static int qe_gpio_dir_out(struct gpio_chip *gc, unsig= ned int gpio, int val) return 0; } =20 +static int qe_gpio_to_irq(struct gpio_chip *gc, unsigned int gpio) +{ + struct qe_gpio_chip *qe_gc =3D gpiochip_get_data(gc); + + return qe_gc->irq[gpio] ? : -ENXIO; +} + struct qe_pin { /* * The qe_gpio_chip name is unfortunate, we should change that to @@ -304,6 +314,7 @@ static int qe_gpio_probe(struct platform_device *ofdev) struct qe_gpio_chip *qe_gc; struct of_mm_gpio_chip *mm_gc; struct gpio_chip *gc; + u32 mask; =20 qe_gc =3D kzalloc(sizeof(*qe_gc), GFP_KERNEL); if (!qe_gc) { @@ -313,6 +324,14 @@ static int qe_gpio_probe(struct platform_device *ofdev) =20 spin_lock_init(&qe_gc->lock); =20 + if (!of_property_read_u32(np, "fsl,qe-gpio-irq-mask", &mask)) { + int i, j; + + for (i =3D 0, j =3D 0; i < 32; i++) + if (mask & (1 << (31 - i))) + qe_gc->irq[i] =3D irq_of_parse_and_map(np, j++); + } + mm_gc =3D &qe_gc->mm_gc; gc =3D &mm_gc->gc; =20 @@ -323,6 +342,7 @@ static int qe_gpio_probe(struct platform_device *ofdev) gc->get =3D qe_gpio_get; gc->set =3D qe_gpio_set; gc->set_multiple =3D qe_gpio_set_multiple; + gc->to_irq =3D qe_gpio_to_irq; =20 ret =3D of_mm_gpiochip_add_data(np, mm_gc, qe_gc); if (!ret) --=20 2.49.0 From nobody Sat Oct 4 22:33:08 2025 Received: from pegase2.c-s.fr (pegase2.c-s.fr [93.17.235.10]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 84CE42E6137; Tue, 12 Aug 2025 11:20:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=93.17.235.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754997646; cv=none; b=DVPJnOqIKBKmLtMrNL5BAvRnhkCbngm3ToJws/ogLSE7KB7qAMPd0Aani0ogcXVave8jBj03U59RrsTx9lwT45rrk7jU+dQitSxlygL45/Kdi+mjSgEm0iplZ+1e/D0vZ1m7TsmLfbdVsMzEWlsmJr17SeVTo7QdpwYh4yLMAK8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754997646; c=relaxed/simple; bh=sBDv7vR+It1XYOsUbKJGVxht0ECRwLjzMeT3ejRDm/U=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=n5fqdY8t9JbUhGPYKbbCELfibq/9MJZf1eDJHTw/QPSyoZJ3+uQb7cJfn3EnUjh7a0r+4UyyBUr8k2ZNAnyizxNrXQERwbjeLgFssIDvCObqdsc0ZxkTQqRunwf2ilytpbokD1Q2R03E+Ff80Pyhf9qMVtrPqi9hwSMWS69zLvg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=csgroup.eu; spf=pass smtp.mailfrom=csgroup.eu; arc=none smtp.client-ip=93.17.235.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=csgroup.eu Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=csgroup.eu Received: from localhost (mailhub4.si.c-s.fr [172.26.127.67]) by localhost (Postfix) with ESMTP id 4c1TBR4kXzz9sT7; Tue, 12 Aug 2025 13:03:11 +0200 (CEST) X-Virus-Scanned: amavisd-new at c-s.fr Received: from pegase2.c-s.fr ([172.26.127.65]) by localhost (pegase2.c-s.fr [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 3y8dTxRQA3KN; Tue, 12 Aug 2025 13:03:11 +0200 (CEST) Received: from messagerie.si.c-s.fr (messagerie.si.c-s.fr [192.168.25.192]) by pegase2.c-s.fr (Postfix) with ESMTP id 4c1TBP5hjWz9sSs; Tue, 12 Aug 2025 13:03:09 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by messagerie.si.c-s.fr (Postfix) with ESMTP id AE0E58B763; Tue, 12 Aug 2025 13:03:09 +0200 (CEST) X-Virus-Scanned: amavisd-new at c-s.fr Received: from messagerie.si.c-s.fr ([127.0.0.1]) by localhost (messagerie.si.c-s.fr [127.0.0.1]) (amavisd-new, port 10023) with ESMTP id Qz7WChCQ-Wh5; Tue, 12 Aug 2025 13:03:09 +0200 (CEST) Received: from PO20335.idsi0.si.c-s.fr (unknown [192.168.235.99]) by messagerie.si.c-s.fr (Postfix) with ESMTP id 20F128B764; Tue, 12 Aug 2025 13:03:09 +0200 (CEST) From: Christophe Leroy To: Qiang Zhao , Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Christophe Leroy , linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 4/4] dt-bindings: soc: fsl: qe: Add an interrupt controller for QUICC Engine Ports Date: Tue, 12 Aug 2025 13:02:54 +0200 Message-ID: <0b56ef403a7c8d0f8305e847d68959a1037d365e.1754996033.git.christophe.leroy@csgroup.eu> X-Mailer: git-send-email 2.49.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1754996575; l=2493; i=christophe.leroy@csgroup.eu; s=20211009; h=from:subject:message-id; bh=sBDv7vR+It1XYOsUbKJGVxht0ECRwLjzMeT3ejRDm/U=; b=BOrAHvPX1MdgLy+6wlTvGbgoypCVvvGj7lfPu6JAC3QbSLnZxuD3Vq6NaU3gedK/5SowU993K yN7/zKYS8O5AWY9thNswXKEYACGBAOQv5dd7OmZYqNex0uG2y6q4nwB X-Developer-Key: i=christophe.leroy@csgroup.eu; a=ed25519; pk=HIzTzUj91asvincQGOFx6+ZF5AoUuP9GdOtQChs7Mm0= Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The QUICC Engine provides interrupts for a few I/O ports. This is handled via a separate interrupt ID and managed via a triplet of dedicated registers hosted by the SoC. Implement an interrupt driver for it for that those IRQs can then be linked to the related GPIOs. Signed-off-by: Christophe Leroy --- .../soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml | 63 +++++++++++++++++++ 1 file changed, 63 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe= -ports-ic.yaml diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-= ic.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-ic.= yaml new file mode 100644 index 0000000000000..7c98706d03dd1 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + +title: Freescale QUICC Engine I/O Ports Interrupt Controller + +maintainers: + - name: Christophe Leroy + email: christophe.leroy@csgroup.eu + +description: | + Interrupt controller for the QUICC Engine I/O ports found on some + Freescale/NXP PowerQUICC and QorIQ SoCs. + +properties: + compatible: + enum: + - fsl,mpc8323-qe-ports-ic + - fsl,mpc8360-qe-ports-ic + - fsl,mpc8568-qe-ports-ic + + reg: + description: Base address and size of the QE I/O Ports Interrupt Contr= oller registers. + minItems: 1 + maxItems: 1 + + interrupt-controller: + type: boolean + description: Indicates this node is an interrupt controller. + + '#address-cells': + const: 0 + description: Must be 0. + + '#interrupt-cells': + const: 1 + description: Number of cells to encode an interrupt specifier. + + interrupts: + minItems: 1 + maxItems: 1 + description: Interrupt line to which the QE I/O Ports controller is co= nnected. + + interrupt-parent: + description: Phandle to the parent interrupt controller. + +required: + - compatible + - reg + - interrupt-controller + - '#address-cells' + - '#interrupt-cells' + - interrupts + - interrupt-parent + +examples: + - | + interrupt-controller@c00 { + interrupt-controller; + compatible =3D "fsl,mpc8323-qe-ports-ic"; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + reg =3D <0xc00 0x18>; + interrupts =3D <74 0x8>; + interrupt-parent =3D <&ipic>; --=20 2.49.0