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Mon, 11 Aug 2025 01:50:31 -0700 (PDT) Received: from mva-rohm ([2a10:a5c0:800d:dd00:8fdf:935a:2c85:d703]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-55b8898c158sm4214963e87.14.2025.08.11.01.50.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Aug 2025 01:50:30 -0700 (PDT) Date: Mon, 11 Aug 2025 11:50:27 +0300 From: Matti Vaittinen To: Matti Vaittinen , Matti Vaittinen Cc: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , David Lechner , Nuno =?iso-8859-1?Q?S=E1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matti Vaittinen , Liam Girdwood , Mark Brown , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 01/11] iio: adc: ad7476: Simplify chip type detection Message-ID: <9e179bb3ba52303448ae4a559c1f011acd3f2fa6.1754901948.git.mazziesaccount@gmail.com> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="y7WQOdzmi8PUw1JG" Content-Disposition: inline In-Reply-To: --y7WQOdzmi8PUw1JG Content-Disposition: inline Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The ad7476 driver uses a table of structures for defining the IC variant specific data. Table is indexed using enum values, which are picked by SPI ID. Having the table and an enum adds extra complexity and may encourage adding IC specific quircks in the code, instead of centralizing the IC differences in one place, the chip-info. Simplify this by dropping the table and using individual structures for the IC specific data, and storing the IC specific structure's address directly in the SPI ID data. Finally, switch to the spi_get_device_match_data() and add a check for the return value. Signed-off-by: Matti Vaittinen Reviewed-by: Nuno S=C3=A1 Reviewed-by: Andy Shevchenko --- Revision history: v1 =3D> - No changes This patch was originally sent as an RFC in 2 patch series: https://lore.kernel.org/all/cover.1754041258.git.mazziesaccount@gmail.com/ Changes from the RFC =3D> v1: - Use spi_get_device_match_data() - Slightly reword commit message --- drivers/iio/adc/ad7476.c | 296 +++++++++++++++++++-------------------- 1 file changed, 146 insertions(+), 150 deletions(-) diff --git a/drivers/iio/adc/ad7476.c b/drivers/iio/adc/ad7476.c index aea734aa06bd..9869526c1524 100644 --- a/drivers/iio/adc/ad7476.c +++ b/drivers/iio/adc/ad7476.c @@ -52,29 +52,6 @@ struct ad7476_state { unsigned char data[ALIGN(2, sizeof(s64)) + sizeof(s64)] __aligned(IIO_DMA= _MINALIGN); }; =20 -enum ad7476_supported_device_ids { - ID_AD7091, - ID_AD7091R, - ID_AD7273, - ID_AD7274, - ID_AD7276, - ID_AD7277, - ID_AD7278, - ID_AD7466, - ID_AD7467, - ID_AD7468, - ID_AD7475, - ID_AD7495, - ID_AD7940, - ID_ADC081S, - ID_ADC101S, - ID_ADC121S, - ID_ADS7866, - ID_ADS7867, - ID_ADS7868, - ID_LTC2314_14, -}; - static void ad7091_convst(struct ad7476_state *st) { if (!st->convst_gpio) @@ -190,102 +167,119 @@ static int ad7476_read_raw(struct iio_dev *indio_de= v, #define ADS786X_CHAN(bits) _AD7476_CHAN((bits), 12 - (bits), \ BIT(IIO_CHAN_INFO_RAW)) =20 -static const struct ad7476_chip_info ad7476_chip_info_tbl[] =3D { - [ID_AD7091] =3D { - .channel[0] =3D AD7091R_CHAN(12), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - .convst_channel[0] =3D AD7091R_CONVST_CHAN(12), - .convst_channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - .reset =3D ad7091_reset, - }, - [ID_AD7091R] =3D { - .channel[0] =3D AD7091R_CHAN(12), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - .convst_channel[0] =3D AD7091R_CONVST_CHAN(12), - .convst_channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - .int_vref_uv =3D 2500000, - .has_vref =3D true, - .reset =3D ad7091_reset, - }, - [ID_AD7273] =3D { - .channel[0] =3D AD7940_CHAN(10), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - .has_vref =3D true, - }, - [ID_AD7274] =3D { - .channel[0] =3D AD7940_CHAN(12), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - .has_vref =3D true, - }, - [ID_AD7276] =3D { - .channel[0] =3D AD7940_CHAN(12), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - }, - [ID_AD7277] =3D { - .channel[0] =3D AD7940_CHAN(10), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - }, - [ID_AD7278] =3D { - .channel[0] =3D AD7940_CHAN(8), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - }, - [ID_AD7466] =3D { - .channel[0] =3D AD7476_CHAN(12), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - }, - [ID_AD7467] =3D { - .channel[0] =3D AD7476_CHAN(10), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - }, - [ID_AD7468] =3D { - .channel[0] =3D AD7476_CHAN(8), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - }, - [ID_AD7475] =3D { - .channel[0] =3D AD7476_CHAN(12), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - .has_vref =3D true, - .has_vdrive =3D true, - }, - [ID_AD7495] =3D { - .channel[0] =3D AD7476_CHAN(12), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - .int_vref_uv =3D 2500000, - .has_vdrive =3D true, - }, - [ID_AD7940] =3D { - .channel[0] =3D AD7940_CHAN(14), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - }, - [ID_ADC081S] =3D { - .channel[0] =3D ADC081S_CHAN(8), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - }, - [ID_ADC101S] =3D { - .channel[0] =3D ADC081S_CHAN(10), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - }, - [ID_ADC121S] =3D { - .channel[0] =3D ADC081S_CHAN(12), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - }, - [ID_ADS7866] =3D { - .channel[0] =3D ADS786X_CHAN(12), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - }, - [ID_ADS7867] =3D { - .channel[0] =3D ADS786X_CHAN(10), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - }, - [ID_ADS7868] =3D { - .channel[0] =3D ADS786X_CHAN(8), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - }, - [ID_LTC2314_14] =3D { - .channel[0] =3D AD7940_CHAN(14), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - .has_vref =3D true, - }, +static const struct ad7476_chip_info ad7091_chip_info =3D { + .channel[0] =3D AD7091R_CHAN(12), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), + .convst_channel[0] =3D AD7091R_CONVST_CHAN(12), + .convst_channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), + .reset =3D ad7091_reset, +}; + +static const struct ad7476_chip_info ad7091r_chip_info =3D { + .channel[0] =3D AD7091R_CHAN(12), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), + .convst_channel[0] =3D AD7091R_CONVST_CHAN(12), + .convst_channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), + .int_vref_uv =3D 2500000, + .has_vref =3D true, + .reset =3D ad7091_reset, +}; + +static const struct ad7476_chip_info ad7273_chip_info =3D { + .channel[0] =3D AD7940_CHAN(10), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), + .has_vref =3D true, +}; + +static const struct ad7476_chip_info ad7274_chip_info =3D { + .channel[0] =3D AD7940_CHAN(12), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), + .has_vref =3D true, +}; + +static const struct ad7476_chip_info ad7276_chip_info =3D { + .channel[0] =3D AD7940_CHAN(12), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), +}; + +static const struct ad7476_chip_info ad7277_chip_info =3D { + .channel[0] =3D AD7940_CHAN(10), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), +}; + +static const struct ad7476_chip_info ad7278_chip_info =3D { + .channel[0] =3D AD7940_CHAN(8), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), +}; + +static const struct ad7476_chip_info ad7466_chip_info =3D { + .channel[0] =3D AD7476_CHAN(12), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), +}; + +static const struct ad7476_chip_info ad7467_chip_info =3D { + .channel[0] =3D AD7476_CHAN(10), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), +}; + +static const struct ad7476_chip_info ad7468_chip_info =3D { + .channel[0] =3D AD7476_CHAN(8), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), +}; + +static const struct ad7476_chip_info ad7475_chip_info =3D { + .channel[0] =3D AD7476_CHAN(12), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), + .has_vref =3D true, + .has_vdrive =3D true, +}; + +static const struct ad7476_chip_info ad7495_chip_info =3D { + .channel[0] =3D AD7476_CHAN(12), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), + .int_vref_uv =3D 2500000, + .has_vdrive =3D true, +}; + +static const struct ad7476_chip_info ad7940_chip_info =3D { + .channel[0] =3D AD7940_CHAN(14), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), +}; + +static const struct ad7476_chip_info adc081s_chip_info =3D { + .channel[0] =3D ADC081S_CHAN(8), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), +}; + +static const struct ad7476_chip_info adc101s_chip_info =3D { + .channel[0] =3D ADC081S_CHAN(10), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), +}; + +static const struct ad7476_chip_info adc121s_chip_info =3D { + .channel[0] =3D ADC081S_CHAN(12), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), +}; + +static const struct ad7476_chip_info ads7866_chip_info =3D { + .channel[0] =3D ADS786X_CHAN(12), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), +}; + +static const struct ad7476_chip_info ads7867_chip_info =3D { + .channel[0] =3D ADS786X_CHAN(10), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), +}; + +static const struct ad7476_chip_info ads7868_chip_info =3D { + .channel[0] =3D ADS786X_CHAN(8), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), +}; + +static const struct ad7476_chip_info ltc2314_14_chip_info =3D { + .channel[0] =3D AD7940_CHAN(14), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), + .has_vref =3D true, }; =20 static const struct iio_info ad7476_info =3D { @@ -311,8 +305,10 @@ static int ad7476_probe(struct spi_device *spi) return -ENOMEM; =20 st =3D iio_priv(indio_dev); - st->chip_info =3D - &ad7476_chip_info_tbl[spi_get_device_id(spi)->driver_data]; + + st->chip_info =3D spi_get_device_match_data(spi); + if (!st->chip_info) + return -ENODEV; =20 reg =3D devm_regulator_get(&spi->dev, "vcc"); if (IS_ERR(reg)) @@ -408,41 +404,41 @@ static int ad7476_probe(struct spi_device *spi) } =20 static const struct spi_device_id ad7476_id[] =3D { - { "ad7091", ID_AD7091 }, - { "ad7091r", ID_AD7091R }, - { "ad7273", ID_AD7273 }, - { "ad7274", ID_AD7274 }, - { "ad7276", ID_AD7276}, - { "ad7277", ID_AD7277 }, - { "ad7278", ID_AD7278 }, - { "ad7466", ID_AD7466 }, - { "ad7467", ID_AD7467 }, - { "ad7468", ID_AD7468 }, - { "ad7475", ID_AD7475 }, - { "ad7476", ID_AD7466 }, - { "ad7476a", ID_AD7466 }, - { "ad7477", ID_AD7467 }, - { "ad7477a", ID_AD7467 }, - { "ad7478", ID_AD7468 }, - { "ad7478a", ID_AD7468 }, - { "ad7495", ID_AD7495 }, - { "ad7910", ID_AD7467 }, - { "ad7920", ID_AD7466 }, - { "ad7940", ID_AD7940 }, - { "adc081s", ID_ADC081S }, - { "adc101s", ID_ADC101S }, - { "adc121s", ID_ADC121S }, - { "ads7866", ID_ADS7866 }, - { "ads7867", ID_ADS7867 }, - { "ads7868", ID_ADS7868 }, + { "ad7091", (kernel_ulong_t)&ad7091_chip_info }, + { "ad7091r", (kernel_ulong_t)&ad7091r_chip_info }, + { "ad7273", (kernel_ulong_t)&ad7273_chip_info }, + { "ad7274", (kernel_ulong_t)&ad7274_chip_info }, + { "ad7276", (kernel_ulong_t)&ad7276_chip_info }, + { "ad7277", (kernel_ulong_t)&ad7277_chip_info }, + { "ad7278", (kernel_ulong_t)&ad7278_chip_info }, + { "ad7466", (kernel_ulong_t)&ad7466_chip_info }, + { "ad7467", (kernel_ulong_t)&ad7467_chip_info }, + { "ad7468", (kernel_ulong_t)&ad7468_chip_info }, + { "ad7475", (kernel_ulong_t)&ad7475_chip_info }, + { "ad7476", (kernel_ulong_t)&ad7466_chip_info }, + { "ad7476a", (kernel_ulong_t)&ad7466_chip_info }, + { "ad7477", (kernel_ulong_t)&ad7467_chip_info }, + { "ad7477a", (kernel_ulong_t)&ad7467_chip_info }, + { "ad7478", (kernel_ulong_t)&ad7468_chip_info }, + { "ad7478a", (kernel_ulong_t)&ad7468_chip_info }, + { "ad7495", (kernel_ulong_t)&ad7495_chip_info }, + { "ad7910", (kernel_ulong_t)&ad7467_chip_info }, + { "ad7920", (kernel_ulong_t)&ad7466_chip_info }, + { "ad7940", (kernel_ulong_t)&ad7940_chip_info }, + { "adc081s", (kernel_ulong_t)&adc081s_chip_info }, + { "adc101s", (kernel_ulong_t)&adc101s_chip_info }, + { "adc121s", (kernel_ulong_t)&adc121s_chip_info }, + { "ads7866", (kernel_ulong_t)&ads7866_chip_info }, + { "ads7867", (kernel_ulong_t)&ads7867_chip_info }, + { "ads7868", (kernel_ulong_t)&ads7868_chip_info }, /* * The ROHM BU79100G is identical to the TI's ADS7866 from the software * point of view. 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Mon, 11 Aug 2025 01:50:45 -0700 (PDT) Received: from mva-rohm ([2a10:a5c0:800d:dd00:8fdf:935a:2c85:d703]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-3326ebb6581sm27011131fa.57.2025.08.11.01.50.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Aug 2025 01:50:44 -0700 (PDT) Date: Mon, 11 Aug 2025 11:50:41 +0300 From: Matti Vaittinen To: Matti Vaittinen , Matti Vaittinen Cc: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , David Lechner , Nuno =?iso-8859-1?Q?S=E1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matti Vaittinen , Liam Girdwood , Mark Brown , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 02/11] iio: adc: ad7476: Simplify scale handling Message-ID: <4a497cc5ac0f6506c1c94d10849e0ae1cacf1191.1754901948.git.mazziesaccount@gmail.com> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="BKTTlH+fa4DxGJK9" Content-Disposition: inline In-Reply-To: --BKTTlH+fa4DxGJK9 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The ad7476 driver supports variants with different amount of supply regulators. On some variants there is only VCC, which is used as a reference voltage. Others have separate VREF regulator, and some rely on internal VREF. Some have both internal VREF and option to connect external one. The ad7476 driver reads the regulator voltage only when the user asks to get the scale. This means the driver needs to do some dancing while picking the correct reference regulator (or internal reference), and store it for the later use. According to the discussion [1] variable voltage references are rare, making it hard to justify the added complexity for supporting those. Drop the support for the variable voltage references and simplify things by using the managed regulator get and enable interfaces. Link: https://lore.kernel.org/linux-iio/20250331122247.05c6b09d@jic23-huawe= i/ #1 Signed-off-by: Matti Vaittinen Reviewed-by: Nuno S=C3=A1 Reviewed-by: Andy Shevchenko --- Revision history: v2 =3D> : - No changes v1 =3D> v2: - use link-tag This patch was originally sent as an RFC in 2 patch series: https://lore.kernel.org/all/cover.1754041258.git.mazziesaccount@gmail.com/ Changes from the RFC: - Fix the faulty conversion from uV to mV as pointed out by David. --- drivers/iio/adc/ad7476.c | 84 ++++++++++------------------------------ 1 file changed, 21 insertions(+), 63 deletions(-) diff --git a/drivers/iio/adc/ad7476.c b/drivers/iio/adc/ad7476.c index 9869526c1524..f117aafd8fad 100644 --- a/drivers/iio/adc/ad7476.c +++ b/drivers/iio/adc/ad7476.c @@ -39,10 +39,10 @@ struct ad7476_chip_info { struct ad7476_state { struct spi_device *spi; const struct ad7476_chip_info *chip_info; - struct regulator *ref_reg; struct gpio_desc *convst_gpio; struct spi_transfer xfer; struct spi_message msg; + int scale_mv; /* * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. @@ -111,7 +111,6 @@ static int ad7476_read_raw(struct iio_dev *indio_dev, { int ret; struct ad7476_state *st =3D iio_priv(indio_dev); - int scale_uv; =20 switch (m) { case IIO_CHAN_INFO_RAW: @@ -126,14 +125,7 @@ static int ad7476_read_raw(struct iio_dev *indio_dev, GENMASK(st->chip_info->channel[0].scan_type.realbits - 1, 0); return IIO_VAL_INT; case IIO_CHAN_INFO_SCALE: - if (st->ref_reg) { - scale_uv =3D regulator_get_voltage(st->ref_reg); - if (scale_uv < 0) - return scale_uv; - } else { - scale_uv =3D st->chip_info->int_vref_uv; - } - *val =3D scale_uv / 1000; + *val =3D st->scale_mv; *val2 =3D chan->scan_type.realbits; return IIO_VAL_FRACTIONAL_LOG2; } @@ -286,18 +278,10 @@ static const struct iio_info ad7476_info =3D { .read_raw =3D &ad7476_read_raw, }; =20 -static void ad7476_reg_disable(void *data) -{ - struct regulator *reg =3D data; - - regulator_disable(reg); -} - static int ad7476_probe(struct spi_device *spi) { struct ad7476_state *st; struct iio_dev *indio_dev; - struct regulator *reg; int ret; =20 indio_dev =3D devm_iio_device_alloc(&spi->dev, sizeof(*st)); @@ -310,58 +294,32 @@ static int ad7476_probe(struct spi_device *spi) if (!st->chip_info) return -ENODEV; =20 - reg =3D devm_regulator_get(&spi->dev, "vcc"); - if (IS_ERR(reg)) - return PTR_ERR(reg); - - ret =3D regulator_enable(reg); - if (ret) - return ret; - - ret =3D devm_add_action_or_reset(&spi->dev, ad7476_reg_disable, reg); - if (ret) - return ret; - - /* Either vcc or vref (below) as appropriate */ - if (!st->chip_info->int_vref_uv) - st->ref_reg =3D reg; + /* Use VCC for reference voltage if vref / internal vref aren't used */ + if (!st->chip_info->int_vref_uv && !st->chip_info->has_vref) { + ret =3D devm_regulator_get_enable_read_voltage(&spi->dev, "vcc"); + if (ret < 0) + return ret; + st->scale_mv =3D ret / 1000; + } else { + ret =3D devm_regulator_get_enable(&spi->dev, "vcc"); + if (ret < 0) + return ret; + } =20 if (st->chip_info->has_vref) { - - /* If a device has an internal reference vref is optional */ - if (st->chip_info->int_vref_uv) { - reg =3D devm_regulator_get_optional(&spi->dev, "vref"); - if (IS_ERR(reg) && (PTR_ERR(reg) !=3D -ENODEV)) - return PTR_ERR(reg); - } else { - reg =3D devm_regulator_get(&spi->dev, "vref"); - if (IS_ERR(reg)) - return PTR_ERR(reg); - } - - if (!IS_ERR(reg)) { - ret =3D regulator_enable(reg); - if (ret) + ret =3D devm_regulator_get_enable_read_voltage(&spi->dev, "vref"); + if (ret < 0) { + /* Vref is optional if a device has an internal reference */ + if (!st->chip_info->int_vref_uv || ret !=3D -ENODEV) return ret; - - ret =3D devm_add_action_or_reset(&spi->dev, - ad7476_reg_disable, - reg); - if (ret) - return ret; - st->ref_reg =3D reg; } else { - /* - * Can only get here if device supports both internal - * and external reference, but the regulator connected - * to the external reference is not connected. - * Set the reference regulator pointer to NULL to - * indicate this. - */ - st->ref_reg =3D NULL; + st->scale_mv =3D ret / 1000; } } =20 + if (!st->scale_mv) + st->scale_mv =3D st->chip_info->int_vref_uv / 1000; + if (st->chip_info->has_vdrive) { ret =3D devm_regulator_get_enable(&spi->dev, "vdrive"); if (ret) --=20 2.50.1 --BKTTlH+fa4DxGJK9 Content-Type: application/pgp-signature; name=signature.asc -----BEGIN PGP SIGNATURE----- iQEzBAEBCgAdFiEEIx+f8wZb28fLKEhTeFA3/03aocUFAmiZruEACgkQeFA3/03a ocVTWQf/fRlCRPd2gphSq1P0fnTqUEAcvWenf7g9fP2mCOmdFCKFWG73KkpaHWZW 6JRCAx4euHHWphadV2ZJnRsMCFR2LnaqixMNVsI2zKxAV3J0xwnW/n0A5lvVjWcg 8ujtUQMcrF06tK7+8LF6TSmaSgDFlVezdr91SxxK7QmIsI5tXi8hbZkwRO7hlxB+ PxNWdX2ehLO6ENGKaWJGIhWYvv0Efj3OO46l1uEHBwbMDogrk7Vq3Bm9OlOQmrnR pfEgnwKk+etMflZ3/HfIR/9q0l5BihaELxxkOqgcGzj735k7xAqLHp/uPPrEakSX 6LHYCT1mJN3rZ2iI5iNjYXyVUnBicw== =CIfe -----END PGP SIGNATURE----- --BKTTlH+fa4DxGJK9-- From nobody Sun Dec 14 03:24:06 2025 Received: from mail-lj1-f169.google.com (mail-lj1-f169.google.com [209.85.208.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 785BD2DAFB0; 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Mon, 11 Aug 2025 01:50:59 -0700 (PDT) Received: from mva-rohm ([2a10:a5c0:800d:dd00:8fdf:935a:2c85:d703]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-33238911615sm39070741fa.72.2025.08.11.01.50.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Aug 2025 01:50:58 -0700 (PDT) Date: Mon, 11 Aug 2025 11:50:55 +0300 From: Matti Vaittinen To: Matti Vaittinen , Matti Vaittinen Cc: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , David Lechner , Nuno =?iso-8859-1?Q?S=E1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matti Vaittinen , Liam Girdwood , Mark Brown , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 03/11] iio: adc: ad7476: Use mV for internal reference Message-ID: <1c26529fcc039a3ce8b5a336948229ec727ee281.1754901948.git.mazziesaccount@gmail.com> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="/+QrcToVZaXPTnln" Content-Disposition: inline In-Reply-To: --/+QrcToVZaXPTnln Content-Disposition: inline Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The ad7476 supports some ICs with an internal reference voltage. For those ICs the reference voltage has been hard-coded as micro volts, but the value which is later used in code needs to be milli volts. This results the need to divide hard coded voltage by 1000 before using it. Simplify code by changing the hard-coded voltage to millivolts and by dropping the division. Signed-off-by: Matti Vaittinen Reviewed-by: Nuno S=C3=A1 Reviewed-by: Andy Shevchenko --- Revision history: v1 =3D> : - No changes --- drivers/iio/adc/ad7476.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/iio/adc/ad7476.c b/drivers/iio/adc/ad7476.c index f117aafd8fad..7b6d36999afc 100644 --- a/drivers/iio/adc/ad7476.c +++ b/drivers/iio/adc/ad7476.c @@ -27,7 +27,7 @@ struct ad7476_state; =20 struct ad7476_chip_info { - unsigned int int_vref_uv; + unsigned int int_vref_mv; struct iio_chan_spec channel[2]; /* channels used when convst gpio is defined */ struct iio_chan_spec convst_channel[2]; @@ -172,7 +172,7 @@ static const struct ad7476_chip_info ad7091r_chip_info = =3D { .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), .convst_channel[0] =3D AD7091R_CONVST_CHAN(12), .convst_channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - .int_vref_uv =3D 2500000, + .int_vref_mv =3D 2500, .has_vref =3D true, .reset =3D ad7091_reset, }; @@ -229,7 +229,7 @@ static const struct ad7476_chip_info ad7475_chip_info = =3D { static const struct ad7476_chip_info ad7495_chip_info =3D { .channel[0] =3D AD7476_CHAN(12), .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - .int_vref_uv =3D 2500000, + .int_vref_mv =3D 2500, .has_vdrive =3D true, }; =20 @@ -295,7 +295,7 @@ static int ad7476_probe(struct spi_device *spi) return -ENODEV; =20 /* Use VCC for reference voltage if vref / internal vref aren't used */ - if (!st->chip_info->int_vref_uv && !st->chip_info->has_vref) { + if (!st->chip_info->int_vref_mv && !st->chip_info->has_vref) { ret =3D devm_regulator_get_enable_read_voltage(&spi->dev, "vcc"); if (ret < 0) return ret; @@ -310,7 +310,7 @@ static int ad7476_probe(struct spi_device *spi) ret =3D devm_regulator_get_enable_read_voltage(&spi->dev, "vref"); if (ret < 0) { /* Vref is optional if a device has an internal reference */ - if (!st->chip_info->int_vref_uv || ret !=3D -ENODEV) + if (!st->chip_info->int_vref_mv || ret !=3D -ENODEV) return ret; } else { st->scale_mv =3D ret / 1000; @@ -318,7 +318,7 @@ static int ad7476_probe(struct spi_device *spi) } =20 if (!st->scale_mv) - st->scale_mv =3D st->chip_info->int_vref_uv / 1000; + st->scale_mv =3D st->chip_info->int_vref_mv; =20 if (st->chip_info->has_vdrive) { ret =3D devm_regulator_get_enable(&spi->dev, "vdrive"); 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Mon, 11 Aug 2025 01:51:10 -0700 (PDT) Received: from mva-rohm ([2a10:a5c0:800d:dd00:8fdf:935a:2c85:d703]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-332385b247csm43054671fa.39.2025.08.11.01.51.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Aug 2025 01:51:10 -0700 (PDT) Date: Mon, 11 Aug 2025 11:51:06 +0300 From: Matti Vaittinen To: Matti Vaittinen , Matti Vaittinen Cc: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , David Lechner , Nuno =?iso-8859-1?Q?S=E1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matti Vaittinen , Liam Girdwood , Mark Brown , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 04/11] iio: adc: ad7476: Use correct channel for bit info Message-ID: <70619e39023bc497ef68cc1eff11943ab68cbdf8.1754901948.git.mazziesaccount@gmail.com> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="XZARgE2KwM5nkx4m" Content-Disposition: inline In-Reply-To: --XZARgE2KwM5nkx4m Content-Disposition: inline Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The ad7476 supports ADCs which use separate GPIO for starting the conversion. For such devices, the driver uses different channel information if the GPIO is found. The bit information is still always used from the original (non 'convstart') channels. This has not been causing problems because the bit information for the 'convstart' -channel and the 'normal' -channel is identical. It, however, will cause issues if an IC has different characteristics for an 'convstart' -channel and regular channel. Furthermore, this will cause problems if a device always requires the convstart GPIO and thus only defines the convstart channel. Signed-off-by: Matti Vaittinen Reviewed-by: Nuno S=C3=A1 Reviewed-by: Andy Shevchenko --- Revision history: v1 =3D> : - No changes --- drivers/iio/adc/ad7476.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/iio/adc/ad7476.c b/drivers/iio/adc/ad7476.c index 7b6d36999afc..fc701267358e 100644 --- a/drivers/iio/adc/ad7476.c +++ b/drivers/iio/adc/ad7476.c @@ -121,8 +121,8 @@ static int ad7476_read_raw(struct iio_dev *indio_dev, =20 if (ret < 0) return ret; - *val =3D (ret >> st->chip_info->channel[0].scan_type.shift) & - GENMASK(st->chip_info->channel[0].scan_type.realbits - 1, 0); + *val =3D (ret >> chan->scan_type.shift) & + GENMASK(chan->scan_type.realbits - 1, 0); return IIO_VAL_INT; case IIO_CHAN_INFO_SCALE: *val =3D st->scale_mv; @@ -345,7 +345,7 @@ static int ad7476_probe(struct spi_device *spi) /* Setup default message */ =20 st->xfer.rx_buf =3D &st->data; - st->xfer.len =3D st->chip_info->channel[0].scan_type.storagebits / 8; + st->xfer.len =3D indio_dev->channels[0].scan_type.storagebits / 8; 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Mon, 11 Aug 2025 01:51:21 -0700 (PDT) Received: from mva-rohm ([2a10:a5c0:800d:dd00:8fdf:935a:2c85:d703]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-55b88caf6dcsm4230172e87.159.2025.08.11.01.51.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Aug 2025 01:51:21 -0700 (PDT) Date: Mon, 11 Aug 2025 11:51:17 +0300 From: Matti Vaittinen To: Matti Vaittinen , Matti Vaittinen Cc: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , David Lechner , Nuno =?iso-8859-1?Q?S=E1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matti Vaittinen , Liam Girdwood , Mark Brown , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 05/11] iio: adc: ad7476: use *_cansleep GPIO APIs Message-ID: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="Akev5Rr95kwSAiEp" Content-Disposition: inline In-Reply-To: --Akev5Rr95kwSAiEp Content-Disposition: inline Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The ad7476 driver supports ADCs which require a GPIO pin to be used to start conversion. The GPIO line status seems to be always toggled from a process context, either from the user-initiated "raw-read conversion", or from a threaded IRQ handler. Furthermore, these ICs are connected via SPI bus, which is usually implemented in a way that the access to the device can sleep. The GPIO here is toggled from the same context which is reading the results over SPI. Thus it seems very likely these GPIOs are toggled from a context which can sleep. Swap the gpiod_set_value() to gpiod_set_value_cansleep() accordinlgy. Suggested-by: Nuno S=C3=A1 Signed-off-by: Matti Vaittinen Reviewed-by: Nuno S=C3=A1 Reviewed-by: Andy Shevchenko --- Revision history: v3 =3D> : - No changes v2 =3D> v3: - New patch --- drivers/iio/adc/ad7476.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/iio/adc/ad7476.c b/drivers/iio/adc/ad7476.c index fc701267358e..1445f0f599d9 100644 --- a/drivers/iio/adc/ad7476.c +++ b/drivers/iio/adc/ad7476.c @@ -57,9 +57,9 @@ static void ad7091_convst(struct ad7476_state *st) if (!st->convst_gpio) return; =20 - gpiod_set_value(st->convst_gpio, 0); + gpiod_set_value_cansleep(st->convst_gpio, 0); udelay(1); /* CONVST pulse width: 10 ns min */ - gpiod_set_value(st->convst_gpio, 1); + gpiod_set_value_cansleep(st->convst_gpio, 1); udelay(1); /* Conversion time: 650 ns max */ } =20 --=20 2.50.1 --Akev5Rr95kwSAiEp Content-Type: application/pgp-signature; name=signature.asc -----BEGIN PGP SIGNATURE----- iQEzBAEBCgAdFiEEIx+f8wZb28fLKEhTeFA3/03aocUFAmiZrwUACgkQeFA3/03a ocUnXAf/RDW+pnIiD2FSS2EPB5fx9n6LRgIg/WSFrxtg3yZcT+nCyRPSBjbZ5fwL HFUWsHOAV4bkrm888rs0/3gBwlhTjAcx9CS0+6hRckbgtvG/i7Z4EsA05K7Kr4Uc yDc3Eo7ax4qF2rvBiidmS8gK+DjQ6MiG5iqAH8pdzUOkrkydzpiCaLlfxwzjHgXv 6AyOxNfzwgxiwpNayAGVjqSKvX8u3ZNCC+P/HQpWwWGGqoLh7FkQnotHJibvUkGP ThdfsaXwGD1r8F877lh2GlI4obWHk2Vyj5pbRrNeVBZs4shbd+MOvdmG+/w8XcI/ 5u4p/XAdcTrlTgH9CY3XVKsqm3tNdA== =vEfI -----END PGP SIGNATURE----- --Akev5Rr95kwSAiEp-- From nobody Sun Dec 14 03:24:06 2025 Received: from mail-lf1-f47.google.com (mail-lf1-f47.google.com [209.85.167.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E5ACC2DCBF2; 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Mon, 11 Aug 2025 01:51:32 -0700 (PDT) Received: from mva-rohm ([2a10:a5c0:800d:dd00:8fdf:935a:2c85:d703]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-55b887f72f4sm4237349e87.0.2025.08.11.01.51.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Aug 2025 01:51:31 -0700 (PDT) Date: Mon, 11 Aug 2025 11:51:28 +0300 From: Matti Vaittinen To: Matti Vaittinen , Matti Vaittinen Cc: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , David Lechner , Nuno =?iso-8859-1?Q?S=E1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matti Vaittinen , Liam Girdwood , Mark Brown , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 06/11] iio: adc: ad7476: Drop convstart chan_spec Message-ID: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="qUzuhLq20cKqadNw" Content-Disposition: inline In-Reply-To: --qUzuhLq20cKqadNw Content-Disposition: inline Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The ad7476 driver defines separate chan_spec structures for operation with and without convstart GPIO. At quick glance this may seem as if the driver did provide more than 1 data-channel to users - one for the regular data, other for the data obtained with the convstart GPIO. The only difference between the 'convstart' and 'non convstart' -channels is presence / absence of the BIT(IIO_CHAN_INFO_RAW) in channel's flags. We can drop the convstart channel spec, and related convstart macro, by allocating a mutable per driver instance channel spec and adding the flag in probe if needed. This will simplify the driver with the cost of added memory consumption. Assuming there aren't systems with very many ADCs and very few resources, this tradeoff seems worth making. Simplify the driver by dropping the 'convstart' channel spec and allocating the channel spec for each driver instance. Signed-off-by: Matti Vaittinen Reviewed-by: Nuno S=C3=A1 Reviewed-by: Andy Shevchenko --- Revision history: v3 =3D> : - No changes v2 =3D> v3: - Use __set_bit() instead of |=3D - Swicth BUILD_BUG_ON to static_assert - Clarify a comment - Improve commit message v1 =3D> v2: - New patch --- drivers/iio/adc/ad7476.c | 31 +++++++++++++++++++------------ 1 file changed, 19 insertions(+), 12 deletions(-) diff --git a/drivers/iio/adc/ad7476.c b/drivers/iio/adc/ad7476.c index 1445f0f599d9..ad9e629f0cbd 100644 --- a/drivers/iio/adc/ad7476.c +++ b/drivers/iio/adc/ad7476.c @@ -6,6 +6,7 @@ * Copyright 2010 Analog Devices Inc. */ =20 +#include #include #include #include @@ -29,8 +30,6 @@ struct ad7476_state; struct ad7476_chip_info { unsigned int int_vref_mv; struct iio_chan_spec channel[2]; - /* channels used when convst gpio is defined */ - struct iio_chan_spec convst_channel[2]; void (*reset)(struct ad7476_state *); bool has_vref; bool has_vdrive; @@ -42,6 +41,7 @@ struct ad7476_state { struct gpio_desc *convst_gpio; struct spi_transfer xfer; struct spi_message msg; + struct iio_chan_spec channel[2]; int scale_mv; /* * DMA (thus cache coherency maintenance) may require the @@ -154,24 +154,18 @@ static int ad7476_read_raw(struct iio_dev *indio_dev, #define AD7940_CHAN(bits) _AD7476_CHAN((bits), 15 - (bits), \ BIT(IIO_CHAN_INFO_RAW)) #define AD7091R_CHAN(bits) _AD7476_CHAN((bits), 16 - (bits), 0) -#define AD7091R_CONVST_CHAN(bits) _AD7476_CHAN((bits), 16 - (bits), \ - BIT(IIO_CHAN_INFO_RAW)) #define ADS786X_CHAN(bits) _AD7476_CHAN((bits), 12 - (bits), \ BIT(IIO_CHAN_INFO_RAW)) =20 static const struct ad7476_chip_info ad7091_chip_info =3D { .channel[0] =3D AD7091R_CHAN(12), .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - .convst_channel[0] =3D AD7091R_CONVST_CHAN(12), - .convst_channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), .reset =3D ad7091_reset, }; =20 static const struct ad7476_chip_info ad7091r_chip_info =3D { .channel[0] =3D AD7091R_CHAN(12), .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - .convst_channel[0] =3D AD7091R_CONVST_CHAN(12), - .convst_channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), .int_vref_mv =3D 2500, .has_vref =3D true, .reset =3D ad7091_reset, @@ -282,6 +276,7 @@ static int ad7476_probe(struct spi_device *spi) { struct ad7476_state *st; struct iio_dev *indio_dev; + unsigned int i; int ret; =20 indio_dev =3D devm_iio_device_alloc(&spi->dev, sizeof(*st)); @@ -332,16 +327,28 @@ static int ad7476_probe(struct spi_device *spi) if (IS_ERR(st->convst_gpio)) return PTR_ERR(st->convst_gpio); =20 + /* + * This will never happen. Unless someone changes the channel specs + * in this driver. And if someone does, without changing the loop + * below, then we'd better immediately produce a big fat error, before + * the change proceeds from that developer's table. + */ + static_assert(ARRAY_SIZE(st->channel) =3D=3D ARRAY_SIZE(st->chip_info->ch= annel)); + for (i =3D 0; i < ARRAY_SIZE(st->channel); i++) { + st->channel[i] =3D st->chip_info->channel[i]; + if (st->convst_gpio) + __set_bit(IIO_CHAN_INFO_RAW, + &st->channel[i].info_mask_separate); + } + st->spi =3D spi; =20 indio_dev->name =3D spi_get_device_id(spi)->name; indio_dev->modes =3D INDIO_DIRECT_MODE; - indio_dev->channels =3D st->chip_info->channel; - indio_dev->num_channels =3D 2; + indio_dev->channels =3D st->channel; + indio_dev->num_channels =3D ARRAY_SIZE(st->channel); indio_dev->info =3D &ad7476_info; =20 - if (st->convst_gpio) - indio_dev->channels =3D st->chip_info->convst_channel; /* Setup default message */ =20 st->xfer.rx_buf =3D &st->data; --=20 2.50.1 --qUzuhLq20cKqadNw Content-Type: application/pgp-signature; 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Mon, 11 Aug 2025 01:51:43 -0700 (PDT) Received: from mva-rohm ([2a10:a5c0:800d:dd00:8fdf:935a:2c85:d703]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-55b889ad021sm4233661e87.74.2025.08.11.01.51.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Aug 2025 01:51:42 -0700 (PDT) Date: Mon, 11 Aug 2025 11:51:39 +0300 From: Matti Vaittinen To: Matti Vaittinen , Matti Vaittinen Cc: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , David Lechner , Nuno =?iso-8859-1?Q?S=E1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matti Vaittinen , Liam Girdwood , Mark Brown , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 07/11] iio: adc: ad7476: Conditionally call convstart Message-ID: <9760cde888fac7335c17d7ab63d5fb2e7c59ac51.1754901948.git.mazziesaccount@gmail.com> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="sZzpSYC3Ny0Q1aET" Content-Disposition: inline In-Reply-To: --sZzpSYC3Ny0Q1aET Content-Disposition: inline Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The ad7476 supports two IC variants which may have a 'convstart' -GPIO for starting the conversion. Currently the driver calls a function which tries to access the GPIO for all of the IC variants, whether they support 'convstart' or not. This is not an error because this function returns early if GPIO information is not populated. We can do a tad better by calling this function only for the ICs which have the 'convstart' by providing a function pointer to the convstart function from the chip_info structure, and calling this function only for the ICs which have the function pointer set. This does also allow to support ICs which require different convstart handling than the currently supported ICs. Call convstart function only on the ICs which can support it and allow IC-specific convstart functions for the ICs which require different handling. Signed-off-by: Matti Vaittinen Reviewed-by: Nuno S=C3=A1 Reviewed-by: Andy Shevchenko --- Revision history: v3 =3D> : - No changes v2 =3D> v3: - Use indirect call to convstart (via function pointer) also from the ad7476_scan_direct(). - Adapt to the change which returned the chip_info pointer back to the driver's state structure. v1 =3D> v2: - Adapt to the change which removed the chip_info pointer from the driver's state structure. The follow-up patch adding support for the ROHM BD79105 will bring different 'convstart' functions in use. The IC specific pointer will also prepare the way for this. --- drivers/iio/adc/ad7476.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/iio/adc/ad7476.c b/drivers/iio/adc/ad7476.c index ad9e629f0cbd..6cb2cbeafbd3 100644 --- a/drivers/iio/adc/ad7476.c +++ b/drivers/iio/adc/ad7476.c @@ -31,6 +31,7 @@ struct ad7476_chip_info { unsigned int int_vref_mv; struct iio_chan_spec channel[2]; void (*reset)(struct ad7476_state *); + void (*conversion_pre_op)(struct ad7476_state *st); bool has_vref; bool has_vdrive; }; @@ -70,7 +71,8 @@ static irqreturn_t ad7476_trigger_handler(int irq, void = *p) struct ad7476_state *st =3D iio_priv(indio_dev); int b_sent; =20 - ad7091_convst(st); + if (st->chip_info->conversion_pre_op) + st->chip_info->conversion_pre_op(st); =20 b_sent =3D spi_sync(st->spi, &st->msg); if (b_sent < 0) @@ -94,7 +96,8 @@ static int ad7476_scan_direct(struct ad7476_state *st) { int ret; =20 - ad7091_convst(st); + if (st->chip_info->conversion_pre_op) + st->chip_info->conversion_pre_op(st); =20 ret =3D spi_sync(st->spi, &st->msg); if (ret) @@ -160,12 +163,14 @@ static int ad7476_read_raw(struct iio_dev *indio_dev, static const struct ad7476_chip_info ad7091_chip_info =3D { .channel[0] =3D AD7091R_CHAN(12), .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), + .conversion_pre_op =3D ad7091_convst, .reset =3D ad7091_reset, }; =20 static const struct ad7476_chip_info ad7091r_chip_info =3D { .channel[0] =3D AD7091R_CHAN(12), .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), + .conversion_pre_op =3D ad7091_convst, .int_vref_mv =3D 2500, .has_vref =3D true, .reset =3D ad7091_reset, --=20 2.50.1 --sZzpSYC3Ny0Q1aET Content-Type: application/pgp-signature; name=signature.asc -----BEGIN PGP SIGNATURE----- iQEzBAEBCgAdFiEEIx+f8wZb28fLKEhTeFA3/03aocUFAmiZrxsACgkQeFA3/03a ocUvSQf+IvW6HdeYk/he3GicwRposZgQSmMXpvu6Brmdy3Qm/VejXDK16dyC6knO ttxjiGZ82/HrcoqPFcCLguxS1Pkn+TpYB7kwWVsT5ffpbUNoeRB6jlIorChLRa1U b4dcz+FsIYi4vkBX+r3r3zS61exjYE69zopnw2JOunfwIuuh5KgmZVdBDiJh5xga w+STlIl13X2rBkKhVrf+lNQ/Nsr+ifR0Vzipk1zN+UXa5XRYMQsyYoX17/pc4fJL EzD+9DI8m2aN2gx/YIk9zsZaNM2ual5QwtTw08cRVAe8gpzkk4Axh/wieKS+pei/ /1fNry1f38o1KzN/iCDJugJdgk4wGg== =yApc -----END PGP SIGNATURE----- --sZzpSYC3Ny0Q1aET-- From nobody Sun Dec 14 03:24:06 2025 Received: from mail-lf1-f45.google.com (mail-lf1-f45.google.com [209.85.167.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CEEA72DC353; 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Mon, 11 Aug 2025 01:51:54 -0700 (PDT) Received: from mva-rohm ([2a10:a5c0:800d:dd00:8fdf:935a:2c85:d703]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-55ccc0617f7sm921690e87.166.2025.08.11.01.51.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Aug 2025 01:51:53 -0700 (PDT) Date: Mon, 11 Aug 2025 11:51:50 +0300 From: Matti Vaittinen To: Matti Vaittinen , Matti Vaittinen Cc: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , David Lechner , Nuno =?iso-8859-1?Q?S=E1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matti Vaittinen , Liam Girdwood , Mark Brown , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 08/11] dt-bindings: iio: adc: ad7476: Drop redundant prop: true Message-ID: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="kiPr8Lj+77WZ/2pb" Content-Disposition: inline In-Reply-To: --kiPr8Lj+77WZ/2pb Content-Disposition: inline Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The ad7476 supports a few variants with different power-supplies and control GPIOs. The binding first unconditionally introduces all the properties, and later sets them 'true' or 'false' based on the combatible. The 'true' seems to be implied by the initial property introduction so the 'true' -branches in later conditional handling (based on the compatible) can be omitted. Drop the redundant true -branches. Signed-off-by: Matti Vaittinen Reviewed-by: Krzysztof Kozlowski --- Revision history: v3 =3D> v4: - New patch --- .../bindings/iio/adc/adi,ad7476.yaml | 54 +++++++++---------- 1 file changed, 24 insertions(+), 30 deletions(-) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7476.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad7476.yaml index d0cb32f136e5..db2a9662bd94 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7476.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7476.yaml @@ -106,19 +106,17 @@ allOf: - vcc-supply # Devices with a vref - if: - properties: - compatible: - contains: - enum: - - adi,ad7091r - - adi,ad7273 - - adi,ad7274 - - adi,ad7475 - - lltc,ltc2314-14 + not: + properties: + compatible: + contains: + enum: + - adi,ad7091r + - adi,ad7273 + - adi,ad7274 + - adi,ad7475 + - lltc,ltc2314-14 then: - properties: - vref-supply: true - else: properties: vref-supply: false # Devices with a vref where it is not optional @@ -135,29 +133,25 @@ allOf: required: - vref-supply - if: - properties: - compatible: - contains: - enum: - - adi,ad7475 - - adi,ad7495 + not: + properties: + compatible: + contains: + enum: + - adi,ad7475 + - adi,ad7495 then: - properties: - vdrive-supply: true - else: properties: vdrive-supply: false - if: - properties: - compatible: - contains: - enum: - - adi,ad7091 - - adi,ad7091r + not: + properties: + compatible: + contains: + enum: + - adi,ad7091 + - adi,ad7091r then: - properties: - adi,conversion-start-gpios: true - else: properties: adi,conversion-start-gpios: false =20 --=20 2.50.1 --kiPr8Lj+77WZ/2pb Content-Type: application/pgp-signature; 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Mon, 11 Aug 2025 01:52:09 -0700 (PDT) Received: from mva-rohm ([2a10:a5c0:800d:dd00:8fdf:935a:2c85:d703]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-55cca00f74esm1006099e87.65.2025.08.11.01.52.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Aug 2025 01:52:08 -0700 (PDT) Date: Mon, 11 Aug 2025 11:52:04 +0300 From: Matti Vaittinen To: Matti Vaittinen , Matti Vaittinen Cc: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , David Lechner , Nuno =?iso-8859-1?Q?S=E1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matti Vaittinen , Liam Girdwood , Mark Brown , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 09/11] dt-bindings: iio: adc: ad7476: Add ROHM bd79105 Message-ID: <3f70f68665225be3091f8a0412e74037b6a2a88e.1754901948.git.mazziesaccount@gmail.com> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="4smEFqmVtnc1ZMXb" Content-Disposition: inline In-Reply-To: --4smEFqmVtnc1ZMXb Content-Disposition: inline Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The ROHM BD79105 is a simple, 16-bit, 1-channel ADC with a 'CONVSTART' pin used to start the ADC conversion. Other than the 'CONVSTART', there are 3 supply pins (one used as a reference), analog inputs, ground and communication pins. It's worth noting that the pin somewhat confusingly labeled as 'DIN', is a pin which should be used as a chip-select. The IC does not have any writable registers. The device is designed so that the output pin can, in addition to outputting the data, be used as a 'data-ready'-IRQ. There are cases where the IRQ can't be used (because it is delivered via SPI data-line). Hence, some systems may use a GPIO for polling the data readiness. Add a compatible for the bd79105 and add the data-ready GPIO to the binding. Signed-off-by: Matti Vaittinen Reviewed-by: Krzysztof Kozlowski --- Revision history: v3 =3D> v4: - Drop the redundant 'true' branches v2 =3D> v3: - No changes v1 =3D> v2: - BD79105 can provide data-ready IRQ (or GPIO) via DOUT-pin. --- .../bindings/iio/adc/adi,ad7476.yaml | 52 +++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7476.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad7476.yaml index db2a9662bd94..55880191c511 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7476.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7476.yaml @@ -41,6 +41,7 @@ properties: - adi,ad7910 - adi,ad7920 - adi,ad7940 + - rohm,bd79105 - ti,adc081s - ti,adc101s - ti,adc121s @@ -55,6 +56,11 @@ properties: reg: maxItems: 1 =20 + interrupts: + description: + The data-ready interrupt. Provided via DOUT pin. + maxItems: 1 + vcc-supply: description: Main powersupply voltage for the chips, sometimes referred to as VDD= on @@ -75,6 +81,10 @@ properties: description: A GPIO used to trigger the start of a conversion maxItems: 1 =20 + rdy-gpios: + description: A GPIO for detecting the data-ready. + maxItems: 1 + required: - compatible - reg @@ -82,6 +92,20 @@ required: allOf: - $ref: /schemas/spi/spi-peripheral-props.yaml# =20 +# Devices with an IRQ + - if: + properties: + compatible: + contains: + enum: + - rohm,bd79105 + then: + properties: + interrupts: true + else: + properties: + interrupts: false + # Devices where reference is vcc - if: properties: @@ -116,6 +140,7 @@ allOf: - adi,ad7274 - adi,ad7475 - lltc,ltc2314-14 + - rohm,bd79105 then: properties: vref-supply: false @@ -129,6 +154,7 @@ allOf: - adi,ad7274 - adi,ad7475 - lltc,ltc2314-14 + - rohm,bd79105 then: required: - vref-supply @@ -140,9 +166,23 @@ allOf: enum: - adi,ad7475 - adi,ad7495 + - rohm,bd79105 then: properties: vdrive-supply: false + + # Devices which support polling the data-ready via GPIO + - if: + not: + properties: + compatible: + contains: + enum: + - rohm,bd79105 + then: + properties: + rdy-gpios: false + - if: not: properties: @@ -151,10 +191,22 @@ allOf: enum: - adi,ad7091 - adi,ad7091r + - rohm,bd79105 then: properties: adi,conversion-start-gpios: false =20 + # Devices with a convstart GPIO where it is not optional + - if: + properties: + compatible: + contains: + enum: + - rohm,bd79105 + then: + required: + - adi,conversion-start-gpios + unevaluatedProperties: false =20 examples: --=20 2.50.1 --4smEFqmVtnc1ZMXb Content-Type: application/pgp-signature; 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Mon, 11 Aug 2025 01:52:27 -0700 (PDT) Received: from mva-rohm ([2a10:a5c0:800d:dd00:8fdf:935a:2c85:d703]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-332624953b1sm33197611fa.80.2025.08.11.01.52.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Aug 2025 01:52:26 -0700 (PDT) Date: Mon, 11 Aug 2025 11:52:22 +0300 From: Matti Vaittinen To: Matti Vaittinen , Matti Vaittinen Cc: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , David Lechner , Nuno =?iso-8859-1?Q?S=E1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matti Vaittinen , Liam Girdwood , Mark Brown , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 10/11] iio: adc: ad7476: Support ROHM BD79105 Message-ID: <6ee06d551256db9213ccbe72f44cfe9452717716.1754901948.git.mazziesaccount@gmail.com> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="uNvoIjZaMUqxG5XO" Content-Disposition: inline In-Reply-To: --uNvoIjZaMUqxG5XO Content-Disposition: inline Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The ROHM BD79105 is a simple 16-bit ADC accessible via SPI*. The BD79105 has a CONVSTART pin, which must be set high to start the ADC conversion. Unlike with the ad7091 and ad7091r which also have a CONVSTART pin, the BD79105 requires that the pin must remain high also for the duration of the SPI access. (*) Couple of words about the SPI. The BD79105 has pins named as CONVSTART, SCLK, DIN and DOUT. For the curious reader, DIN is not SPI ISO. DIN is a signal which can be used as a chip-select. When DIN is pulled low, the ADC will output the completed measurement via DOUT as SCLK is clocked. According to the data-sheet, the DIN can also be used for daisy-chaining multiple ADCs. Furthermore, DOUT can be used also for a 'data-ready' -IRQ. These modes aren't supported by this driver. Support reading ADC scale and data from the BD79105 using SPI, when DIN is used as a chip-select. Signed-off-by: Matti Vaittinen Reviewed-by: Nuno S=C3=A1 Reviewed-by: Andy Shevchenko --- Revision history: v3 =3D> : - No changes v2 =3D> v3: - Check for missing convstart GPIO at probe. - Use indirect call to convstart (via function pointer) also from the ad7476_scan_direct(). v1 =3D> v2: - Fix the conversion delay for the BD79105 - Drop unnecessary GPIO check from the convstart disable - Drop unintended whitespace change - Fix spelling --- drivers/iio/adc/ad7476.c | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/drivers/iio/adc/ad7476.c b/drivers/iio/adc/ad7476.c index 6cb2cbeafbd3..1bec6657394c 100644 --- a/drivers/iio/adc/ad7476.c +++ b/drivers/iio/adc/ad7476.c @@ -32,8 +32,10 @@ struct ad7476_chip_info { struct iio_chan_spec channel[2]; void (*reset)(struct ad7476_state *); void (*conversion_pre_op)(struct ad7476_state *st); + void (*conversion_post_op)(struct ad7476_state *st); bool has_vref; bool has_vdrive; + bool convstart_required; }; =20 struct ad7476_state { @@ -64,6 +66,18 @@ static void ad7091_convst(struct ad7476_state *st) udelay(1); /* Conversion time: 650 ns max */ } =20 +static void bd79105_convst_disable(struct ad7476_state *st) +{ + gpiod_set_value_cansleep(st->convst_gpio, 0); +} + +static void bd79105_convst_enable(struct ad7476_state *st) +{ + gpiod_set_value_cansleep(st->convst_gpio, 1); + /* Worst case, 2790 ns required for conversion */ + ndelay(2790); +} + static irqreturn_t ad7476_trigger_handler(int irq, void *p) { struct iio_poll_func *pf =3D p; @@ -81,6 +95,8 @@ static irqreturn_t ad7476_trigger_handler(int irq, void = *p) iio_push_to_buffers_with_ts(indio_dev, st->data, sizeof(st->data), iio_get_time_ns(indio_dev)); done: + if (st->chip_info->conversion_post_op) + st->chip_info->conversion_post_op(st); iio_trigger_notify_done(indio_dev->trig); =20 return IRQ_HANDLED; @@ -103,6 +119,9 @@ static int ad7476_scan_direct(struct ad7476_state *st) if (ret) return ret; =20 + if (st->chip_info->conversion_post_op) + st->chip_info->conversion_post_op(st); + return be16_to_cpup((__be16 *)st->data); } =20 @@ -273,6 +292,22 @@ static const struct ad7476_chip_info ltc2314_14_chip_i= nfo =3D { .has_vref =3D true, }; =20 +static const struct ad7476_chip_info bd79105_chip_info =3D { + .channel[0] =3D AD7091R_CHAN(16), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), + /* + * The BD79105 starts ADC data conversion when the CONVSTART line is + * set HIGH. The CONVSTART must be kept HIGH until the data has been + * read from the ADC. + */ + .conversion_pre_op =3D bd79105_convst_enable, + .conversion_post_op =3D bd79105_convst_disable, + /* BD79105 won't do conversion without convstart */ + .convstart_required =3D true, + .has_vref =3D true, + .has_vdrive =3D true, +}; + static const struct iio_info ad7476_info =3D { .read_raw =3D &ad7476_read_raw, }; @@ -332,6 +367,9 @@ static int ad7476_probe(struct spi_device *spi) if (IS_ERR(st->convst_gpio)) return PTR_ERR(st->convst_gpio); =20 + if (st->chip_info->convstart_required && !st->convst_gpio) + return dev_err_probe(&spi->dev, -EINVAL, "No convstart GPIO\n"); + /* * This will never happen. Unless someone changes the channel specs * in this driver. And if someone does, without changing the loop @@ -401,6 +439,7 @@ static const struct spi_device_id ad7476_id[] =3D { { "ads7866", (kernel_ulong_t)&ads7866_chip_info }, { "ads7867", (kernel_ulong_t)&ads7867_chip_info }, { "ads7868", (kernel_ulong_t)&ads7868_chip_info }, + { "bd79105", (kernel_ulong_t)&bd79105_chip_info }, /* * The ROHM BU79100G is identical to the TI's ADS7866 from the software * point of view. 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Mon, 11 Aug 2025 01:52:39 -0700 (PDT) Received: from mva-rohm ([2a10:a5c0:800d:dd00:8fdf:935a:2c85:d703]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-333a7a116b2sm13423971fa.82.2025.08.11.01.52.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Aug 2025 01:52:38 -0700 (PDT) Date: Mon, 11 Aug 2025 11:52:34 +0300 From: Matti Vaittinen To: Matti Vaittinen , Matti Vaittinen Cc: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , David Lechner , Nuno =?iso-8859-1?Q?S=E1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matti Vaittinen , Liam Girdwood , Mark Brown , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 11/11] MAINTAINERS: A driver for simple 1-channel SPI ADCs Message-ID: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="5P4693bN41puOZdB" Content-Disposition: inline In-Reply-To: --5P4693bN41puOZdB Content-Disposition: inline Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add undersigned as a maintainer for the ad7476.c which supports a few simple 1-channel ADC connected to SPI. Signed-off-by: Matti Vaittinen --- Revision history: v1 =3D> : - No changes. I'll try to keep this on eye. I only have access to the ROHM BD79105 and BU79100g. I would welcome anyone with access to other supported ADCs (and time, energy and the knowledge) to join me. :) --- MAINTAINERS | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index f8c8f682edf6..36fa6333f7b5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -455,6 +455,11 @@ F: Documentation/devicetree/bindings/iio/adc/adi,ad738= 0.yaml F: Documentation/iio/ad7380.rst F: drivers/iio/adc/ad7380.c =20 +AD7476 ADC DRIVER FOR VARIOUS SIMPLE 1-CHANNEL SPI ADCs +M: Matti Vaittinen +S: Maintained +F: drivers/iio/adc/ad7476.c + AD7877 TOUCHSCREEN DRIVER M: Michael Hennerich S: Supported --=20 2.50.1 --5P4693bN41puOZdB Content-Type: application/pgp-signature; name=signature.asc -----BEGIN PGP SIGNATURE----- iQEzBAEBCgAdFiEEIx+f8wZb28fLKEhTeFA3/03aocUFAmiZr1IACgkQeFA3/03a ocX0IQgAhEfQ8vViRdvmtNKTjHF31C9nQlS8FaI+fCGeOvSoArhGDS2KYJACHpjH Y64+HyOZTTvSzNSeediyHRklde3vmKD0ckJ4139xQl+dN1lfifNJHpy9csFbuxR+ Z/8YsVoHUgdTS+kh3+Ea/RuP/G8w12fNBHpW4I01E8BQFsajlRo4znAqs2F6Tt4P HhPJIEDlHauSnfivpqqNfXrZAfa6LHNbP3XBLzT+V60eyKFxsKUZWd5GbMcdEGmz Lm/3mjDtxpNh+rBctX2ptPBcFCWu/aUuZqmv8UnZdoJNCbVk3s+y0X4l+mLi4sVf VZ2ksuCyhyPmrKOBjxDB6ljxKvlfcg== =fTm1 -----END PGP SIGNATURE----- --5P4693bN41puOZdB--