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The AAF provides additional sign= al + rejection within the frequency range of fs =C2=B1 f3dB, where fs is = the sampling + frequency, and f3dB is the -3dB cutoff frequency. The specific value= s of + fs and f3dB, as well as the rejection intensity, depend on the digit= al + filter configuration. + + This parameter is required for the ADAQ7767-1 and ADAQ7769-1 devices. + The gain is determined by the selected input pin: + * For the ADAQ7767-1: The input selection of IN1=C2=B1, IN2=C2=B1 or= IN3=C2=B1. + * For the ADAQ7769-1: The connections of OUT_PGA to IN1_AAF+, IN2_AA= F+, + or IN3_AAF+. + $ref: /schemas/types.yaml#/definitions/uint16 + enum: [143, 364, 1000] + adi,sync-in-gpios: maxItems: 1 description: @@ -147,6 +172,21 @@ patternProperties: allOf: - $ref: /schemas/spi/spi-peripheral-props.yaml# =20 + # AAF Gain property only applies to ADAQ7767-1 and ADAQ7769-1 devices + - if: + properties: + compatible: + contains: + enum: + - adi,adaq7767-1 + - adi,adaq7769-1 + then: + required: + - adi,aaf-gain + else: + properties: + adi,aaf-gain: false + unevaluatedProperties: false =20 examples: --=20 2.34.1 From nobody Sat Oct 4 20:52:50 2025 Received: from mx0b-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E67D8271444; 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Tue, 12 Aug 2025 22:49:00 -0400 From: Jonathan Santos To: , , CC: Jonathan Santos , , , , , , , , , Subject: [PATCH 2/4] iio: adc: ad7768-1: introduce chip info for future multidevice support Date: Tue, 12 Aug 2025 23:48:57 -0300 Message-ID: <22ea35425827176a842ea0e523040acd20e27bcc.1754617360.git.Jonathan.Santos@analog.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODExMDA5NyBTYWx0ZWRfX66EDTM2s7FdN Q2IO2Ob2llKYbRmq520BJ4955YjWDQMjDP3oyq0Zfuz9vkthAozjuqNyEPlg5NyFghjj3iiFRKt qaT7uJf+0CNGVNUtBkS7QbJQO0MhlfO2y0fMZJl3v4Db3kDCLNux2XKz+bVo9OI2izBo+DrLPvo A8XFZquuQaYyiR5t4fh4khub6j3Vc62ZHxSyxvSpdl9+luaBJa/y/shgFJFkVxhlHu/NPVNX00K QT/6YUAZBY99+7Wp/pOJkZnK1zVCDIIVMUQESBR/UA9JuDnE9RqcGu9AeoykX174EBJ7WS9VWf9 o9reUmbhjuf48ZxBbCwKCzuZCAfI1KBZjWPWXJTk3ewlcK7hhzjlwf8wZF2/rOay8WiUDwNbwi/ v+wlTAvP X-Proofpoint-ORIG-GUID: Aouw8WZfeAiW5wTkKvrVBJa5pJjVMDor X-Authority-Analysis: v=2.4 cv=IMMCChvG c=1 sm=1 tr=0 ts=689bfd26 cx=c_pps a=PpDZqlmH/M8setHirZLBMw==:117 a=PpDZqlmH/M8setHirZLBMw==:17 a=2OwXVqhp2XgA:10 a=gAnH3GRIAAAA:8 a=PeubA13TOwIOKtPvs58A:9 X-Proofpoint-GUID: Aouw8WZfeAiW5wTkKvrVBJa5pJjVMDor X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-12_08,2025-08-11_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 adultscore=0 priorityscore=1501 bulkscore=0 spamscore=0 impostorscore=0 phishscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508110097 Content-Type: text/plain; charset="utf-8" Add Chip info struct in SPI device to store channel information for each supported part. Signed-off-by: Jonathan Santos Reviewed-by: Nuno S=C3=A1 --- drivers/iio/adc/ad7768-1.c | 76 ++++++++++++++++++++++++++------------ 1 file changed, 53 insertions(+), 23 deletions(-) diff --git a/drivers/iio/adc/ad7768-1.c b/drivers/iio/adc/ad7768-1.c index a2e061f0cb08..36ba208fc119 100644 --- a/drivers/iio/adc/ad7768-1.c +++ b/drivers/iio/adc/ad7768-1.c @@ -106,6 +106,7 @@ #define AD7768_GPIO_READ_MSK GENMASK(3, 0) =20 #define AD7768_VCM_OFF 0x07 +#define AD7768_CHAN_INFO_NONE 0 =20 #define AD7768_TRIGGER_SOURCE_SYNC_IDX 0 =20 @@ -213,6 +214,13 @@ static const struct iio_scan_type ad7768_scan_type[] = =3D { }, }; =20 +struct ad7768_chip_info { + const char *name; + const struct iio_chan_spec *channel_spec; + const unsigned long *available_masks; + int num_channels; +}; + struct ad7768_state { struct spi_device *spi; struct regmap *regmap; @@ -234,6 +242,7 @@ struct ad7768_state { struct gpio_desc *gpio_reset; const char *labels[AD7768_MAX_CHANNELS]; struct gpio_chip gpiochip; + const struct ad7768_chip_info *chip; bool en_spi_sync; /* * DMA (thus cache coherency maintenance) may require the @@ -750,24 +759,27 @@ static const struct iio_chan_spec_ext_info ad7768_ext= _info[] =3D { { } }; =20 +#define AD7768_CHAN(_idx, _msk_avail) { \ + .type =3D IIO_VOLTAGE,\ + .info_mask_separate_available =3D _msk_avail,\ + .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW),\ + .info_mask_shared_by_type =3D BIT(IIO_CHAN_INFO_SCALE) | \ + BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \ + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO),\ + .info_mask_shared_by_type_available =3D BIT(IIO_CHAN_INFO_OVERSAMPLING_RA= TIO),\ + .info_mask_shared_by_all =3D BIT(IIO_CHAN_INFO_SAMP_FREQ), \ + .info_mask_shared_by_all_available =3D BIT(IIO_CHAN_INFO_SAMP_FREQ),\ + .ext_info =3D ad7768_ext_info,\ + .indexed =3D 1,\ + .channel =3D _idx,\ + .scan_index =3D _idx,\ + .has_ext_scan_type =3D 1,\ + .ext_scan_type =3D ad7768_scan_type,\ + .num_ext_scan_type =3D ARRAY_SIZE(ad7768_scan_type),\ +} + static const struct iio_chan_spec ad7768_channels[] =3D { - { - .type =3D IIO_VOLTAGE, - .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW), - .info_mask_shared_by_type =3D BIT(IIO_CHAN_INFO_SCALE) | - BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | - BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), - .info_mask_shared_by_type_available =3D BIT(IIO_CHAN_INFO_OVERSAMPLING_R= ATIO), - .info_mask_shared_by_all =3D BIT(IIO_CHAN_INFO_SAMP_FREQ), - .info_mask_shared_by_all_available =3D BIT(IIO_CHAN_INFO_SAMP_FREQ), - .ext_info =3D ad7768_ext_info, - .indexed =3D 1, - .channel =3D 0, - .scan_index =3D 0, - .has_ext_scan_type =3D 1, - .ext_scan_type =3D ad7768_scan_type, - .num_ext_scan_type =3D ARRAY_SIZE(ad7768_scan_type), - }, + AD7768_CHAN(0, AD7768_CHAN_INFO_NONE), }; =20 static int ad7768_read_raw(struct iio_dev *indio_dev, @@ -1334,6 +1346,18 @@ static int ad7768_register_regulators(struct device = *dev, struct ad7768_state *s return 0; } =20 +static const unsigned long ad7768_channel_masks[] =3D { + BIT(0), + 0, +}; + +static const struct ad7768_chip_info ad7768_chip_info =3D { + .name =3D "ad7768-1", + .channel_spec =3D ad7768_channels, + .num_channels =3D ARRAY_SIZE(ad7768_channels), + .available_masks =3D ad7768_channel_masks, +}; + static int ad7768_probe(struct spi_device *spi) { struct ad7768_state *st; @@ -1392,9 +1416,15 @@ static int ad7768_probe(struct spi_device *spi) =20 st->mclk_freq =3D clk_get_rate(st->mclk); =20 - indio_dev->channels =3D ad7768_channels; - indio_dev->num_channels =3D ARRAY_SIZE(ad7768_channels); - indio_dev->name =3D spi_get_device_id(spi)->name; + st->chip =3D spi_get_device_match_data(spi); + if (!st->chip) + return dev_err_probe(&spi->dev, -ENODEV, + "Could not find chip info data\n"); + + indio_dev->channels =3D st->chip->channel_spec; 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Tue, 12 Aug 2025 22:49:09 -0400 From: Jonathan Santos To: , , CC: Jonathan Santos , , , , , , , , , Subject: [PATCH 3/4] iio: adc: ad7768-1: use devm_regulator_get_enable_read_voltage Date: Tue, 12 Aug 2025 23:49:07 -0300 Message-ID: <3b9f5a9f188af8b1df947806e1049269f3a0dfa3.1754617360.git.Jonathan.Santos@analog.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Authority-Analysis: v=2.4 cv=EOsG00ZC c=1 sm=1 tr=0 ts=689bfd31 cx=c_pps a=PpDZqlmH/M8setHirZLBMw==:117 a=PpDZqlmH/M8setHirZLBMw==:17 a=2OwXVqhp2XgA:10 a=gAnH3GRIAAAA:8 a=A5znH7WzVNNAUNHUab8A:9 X-Proofpoint-GUID: CG5zqnSGEsysSXuNHmm7UWk0CJLTwZEV X-Proofpoint-ORIG-GUID: CG5zqnSGEsysSXuNHmm7UWk0CJLTwZEV X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODEyMDE2NCBTYWx0ZWRfX0zIaeMGQqVdl 5sRIwAcpLuVqELZTWv+p3QU8zZFF34rjUXdcxdllGlr99nlPiaRyoXjT7eUHMFpcSPHr0j3XRN+ Oz3JW19ZKib+/7+mFE5PnOEjRVcghhspyWyoFmn7B43z9ZxPF3Hu/08Ws7OIg31ju2bu0QiTaah MX6seHOCuFIUGyetumayvmS5lV6acazhWypU+ZCgxkKKtMn+sFqfLclLNS2wvdLScKDQ5sv1Q6o 7ozIkf4AosybFZayOvdrOvkdFqQluuQeaxX0n9QMqy7DOqRjCZ7W1ccQFLMvei0+wqhow8W4Gmg Go1eQ+JHNX97F7R/k4Y97nYPC0Tur50sBudM5HyLfmehgIsVmC+wpRFVVzC5sXSmhbfOnWzCzMA FXnQTWrO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-12_08,2025-08-11_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 phishscore=0 spamscore=0 suspectscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508120164 Content-Type: text/plain; charset="utf-8" Use devm_regulator_get_enable_read_voltage function as a standard and concise way of reading the voltage from the regulator and keep the regulator enabled. Replace the regulator descriptor with the direct voltage value in the device struct. Signed-off-by: Jonathan Santos Reviewed-by: Marcelo Schmitt Reviewed-by: Nuno S=C3=A1 --- drivers/iio/adc/ad7768-1.c | 29 +++++++---------------------- 1 file changed, 7 insertions(+), 22 deletions(-) diff --git a/drivers/iio/adc/ad7768-1.c b/drivers/iio/adc/ad7768-1.c index 36ba208fc119..d0b9764a8f92 100644 --- a/drivers/iio/adc/ad7768-1.c +++ b/drivers/iio/adc/ad7768-1.c @@ -225,7 +225,7 @@ struct ad7768_state { struct spi_device *spi; struct regmap *regmap; struct regmap *regmap24; - struct regulator *vref; + int vref_uv; struct regulator_dev *vcm_rdev; unsigned int vcm_output_sel; struct clk *mclk; @@ -809,7 +809,7 @@ static int ad7768_read_raw(struct iio_dev *indio_dev, return IIO_VAL_INT; =20 case IIO_CHAN_INFO_SCALE: - scale_uv =3D regulator_get_voltage(st->vref); + scale_uv =3D st->vref_uv; if (scale_uv < 0) return scale_uv; =20 @@ -1146,13 +1146,6 @@ static const struct iio_trigger_ops ad7768_trigger_o= ps =3D { .validate_device =3D iio_trigger_validate_own_device, }; =20 -static void ad7768_regulator_disable(void *data) -{ - struct ad7768_state *st =3D data; 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charset="utf-8" Add support for ADAQ7767/68/69-1 series, which includes PGIA and Anti-aliasing filter (AAF) gains. The PGA gain is configured in run-time through the scale attribute, if supported by the device. The scale options are updated according to the output data width. The AAF gain is configured in the devicetree and it should correspond to the AAF channel selected in hardware. Signed-off-by: Jonathan Santos Reviewed-by: Nuno S=C3=A1 --- drivers/iio/adc/ad7768-1.c | 286 ++++++++++++++++++++++++++++++++++++- 1 file changed, 279 insertions(+), 7 deletions(-) diff --git a/drivers/iio/adc/ad7768-1.c b/drivers/iio/adc/ad7768-1.c index d0b9764a8f92..4397d044f5de 100644 --- a/drivers/iio/adc/ad7768-1.c +++ b/drivers/iio/adc/ad7768-1.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -98,16 +99,22 @@ /* AD7768_REG_GPIO_CONTROL */ #define AD7768_GPIO_UNIVERSAL_EN BIT(7) #define AD7768_GPIO_CONTROL_MSK GENMASK(3, 0) +#define AD7768_GPIO_PGIA_EN (AD7768_GPIO_UNIVERSAL_EN | GENMASK(2, 0)) =20 /* AD7768_REG_GPIO_WRITE */ #define AD7768_GPIO_WRITE_MSK GENMASK(3, 0) +#define AD7768_GPIO_WRITE(x) FIELD_PREP(AD7768_GPIO_WRITE_MSK, x) =20 /* AD7768_REG_GPIO_READ */ #define AD7768_GPIO_READ_MSK GENMASK(3, 0) +#define AD7768_GPIO_READ(x) FIELD_PREP(AD7768_GPIO_READ_MSK, x) =20 #define AD7768_VCM_OFF 0x07 #define AD7768_CHAN_INFO_NONE 0 =20 +#define ADAQ776X_GAIN_MAX_NANO (128 * NANO) +#define ADAQ776X_MAX_GAIN_MODES 8 + #define AD7768_TRIGGER_SOURCE_SYNC_IDX 0 =20 #define AD7768_MAX_CHANNELS 1 @@ -154,6 +161,52 @@ enum ad7768_scan_type { AD7768_SCAN_TYPE_HIGH_SPEED, }; =20 +enum { + AD7768_PGA_GAIN_0, + AD7768_PGA_GAIN_1, + AD7768_PGA_GAIN_2, + AD7768_PGA_GAIN_3, + AD7768_PGA_GAIN_4, + AD7768_PGA_GAIN_5, + AD7768_PGA_GAIN_6, + AD7768_PGA_GAIN_7, + AD7768_MAX_PGA_GAIN, +}; + +enum { + AD7768_AAF_IN1, + AD7768_AAF_IN2, + AD7768_AAF_IN3, +}; + +/* PGA and AAF gains in V/V */ +static const int adaq7768_gains[7] =3D { + [AD7768_PGA_GAIN_0] =3D 325, /* 0.325 */ + [AD7768_PGA_GAIN_1] =3D 650, /* 0.650 */ + [AD7768_PGA_GAIN_2] =3D 1300, /* 1.300 */ + [AD7768_PGA_GAIN_3] =3D 2600, /* 2.600 */ + [AD7768_PGA_GAIN_4] =3D 5200, /* 5.200 */ + [AD7768_PGA_GAIN_5] =3D 10400, /* 10.400 */ + [AD7768_PGA_GAIN_6] =3D 20800 /* 20.800 */ +}; + +static const int adaq7769_gains[8] =3D { + [AD7768_PGA_GAIN_0] =3D 1000, /* 1.000 */ + [AD7768_PGA_GAIN_1] =3D 2000, /* 2.000 */ + [AD7768_PGA_GAIN_2] =3D 4000, /* 4.000 */ + [AD7768_PGA_GAIN_3] =3D 8000, /* 8.000 */ + [AD7768_PGA_GAIN_4] =3D 16000, /* 16.000 */ + [AD7768_PGA_GAIN_5] =3D 32000, /* 32.000 */ + [AD7768_PGA_GAIN_6] =3D 64000, /* 64.000 */ + [AD7768_PGA_GAIN_7] =3D 128000 /* 128.000 */ +}; + +static const int ad7768_aaf_gains[3] =3D { + [AD7768_AAF_IN1] =3D 1000, /* 1.000 */ + [AD7768_AAF_IN2] =3D 364, /* 0.364 */ + [AD7768_AAF_IN3] =3D 143 /* 0.143 */ +}; + /* -3dB cutoff frequency multipliers (relative to ODR) for each filter typ= e. */ static const int ad7768_filter_3db_odr_multiplier[] =3D { [AD7768_FILTER_SINC5] =3D 204, /* 0.204 */ @@ -216,6 +269,12 @@ static const struct iio_scan_type ad7768_scan_type[] = =3D { =20 struct ad7768_chip_info { const char *name; + bool has_variable_aaf; + bool has_pga; + int num_pga_modes; + int default_pga_mode; + int pgia_mode2pin_offset; + const int *pga_gains; const struct iio_chan_spec *channel_spec; const unsigned long *available_masks; int num_channels; @@ -236,6 +295,9 @@ struct ad7768_state { unsigned int samp_freq; unsigned int samp_freq_avail[ARRAY_SIZE(ad7768_mclk_div_rates)]; unsigned int samp_freq_avail_len; + int pga_gain_mode; + int aaf_gain; + int scale_tbl[ADAQ776X_MAX_GAIN_MODES][2]; struct completion completion; struct iio_trigger *trig; struct gpio_desc *gpio_sync_in; @@ -466,6 +528,43 @@ static int ad7768_reg_access(struct iio_dev *indio_dev, return ret; } =20 +static void ad7768_fill_scale_tbl(struct iio_dev *dev) +{ + struct ad7768_state *st =3D iio_priv(dev); + const struct iio_scan_type *scan_type; + int val, val2, tmp0, tmp1, i; + unsigned long denominator, numerator; + u64 tmp2; + + scan_type =3D iio_get_current_scan_type(dev, &dev->channels[0]); + if (scan_type->sign =3D=3D 's') + val2 =3D scan_type->realbits - 1; + else + val2 =3D scan_type->realbits; + + for (i =3D 0; i < st->chip->num_pga_modes; i++) { + /* Convert gain to a fraction format */ + numerator =3D st->chip->pga_gains[i]; + denominator =3D MILLI; + if (st->chip->has_variable_aaf) { + numerator *=3D ad7768_aaf_gains[st->aaf_gain]; + denominator *=3D MILLI; + } + + rational_best_approximation(numerator, denominator, __INT_MAX__, __INT_M= AX__, + &numerator, &denominator); + + val =3D st->vref_uv / 1000; + /* Multiply by MILLI here to avoid losing precision */ + val =3D mult_frac(val, denominator * MILLI, numerator); + /* Would multiply by NANO here but we already multiplied by MILLI */ + tmp2 =3D shift_right((u64)val * MICRO, val2); + tmp0 =3D (int)div_s64_rem(tmp2, NANO, &tmp1); + st->scale_tbl[i][0] =3D tmp0; /* Integer part */ + st->scale_tbl[i][1] =3D abs(tmp1); /* Fractional part */ + } +} + static int ad7768_set_sinc3_dec_rate(struct ad7768_state *st, unsigned int dec_rate) { @@ -567,12 +666,68 @@ static int ad7768_configure_dig_fil(struct iio_dev *d= ev, st->oversampling_ratio =3D ad7768_dec_rate_values[dec_rate_idx]; } =20 + /* Update scale table: scale values vary according to the precision */ + ad7768_fill_scale_tbl(dev); + ad7768_fill_samp_freq_tbl(st); =20 /* A sync-in pulse is required after every configuration change */ return ad7768_send_sync_pulse(st); } =20 +static int ad7768_calc_pga_gain(struct ad7768_state *st, int gain_int, + int gain_fract, int precision) +{ + u64 gain_nano, tmp; + int gain_idx; + + precision--; + gain_nano =3D gain_int * NANO + gain_fract; + if (gain_nano < 0 || gain_nano > ADAQ776X_GAIN_MAX_NANO) + return -EINVAL; + + tmp =3D DIV_ROUND_CLOSEST_ULL(gain_nano << precision, NANO); + gain_nano =3D DIV_ROUND_CLOSEST_ULL(st->vref_uv, tmp); + if (st->chip->has_variable_aaf) + /* remove the AAF gain from the overall gain */ + gain_nano =3D DIV_ROUND_CLOSEST_ULL(gain_nano * MILLI, + ad7768_aaf_gains[st->aaf_gain]); + tmp =3D st->chip->num_pga_modes; + gain_idx =3D find_closest(gain_nano, st->chip->pga_gains, tmp); + + return gain_idx; +} + +static int ad7768_set_pga_gain(struct ad7768_state *st, + int gain_mode) +{ + int pgia_pins_value =3D abs(gain_mode - st->chip->pgia_mode2pin_offset); + int check_val; + int ret; + + /* Check GPIO control register */ + ret =3D regmap_read(st->regmap, AD7768_REG_GPIO_CONTROL, &check_val); + if (ret < 0) + return ret; + + if ((check_val & AD7768_GPIO_PGIA_EN) !=3D AD7768_GPIO_PGIA_EN) { + /* Enable PGIA GPIOs and set them as output */ + ret =3D regmap_write(st->regmap, AD7768_REG_GPIO_CONTROL, AD7768_GPIO_PG= IA_EN); + if (ret < 0) + return ret; + } + + /* Write the respective gain values to GPIOs 0, 1, 2 */ + ret =3D regmap_write(st->regmap, AD7768_REG_GPIO_WRITE, + AD7768_GPIO_WRITE(pgia_pins_value)); + if (ret < 0) + return ret; + + st->pga_gain_mode =3D gain_mode; + + return 0; +} + static int ad7768_gpio_direction_input(struct gpio_chip *chip, unsigned in= t offset) { struct iio_dev *indio_dev =3D gpiochip_get_data(chip); @@ -782,13 +937,17 @@ static const struct iio_chan_spec ad7768_channels[] = =3D { AD7768_CHAN(0, AD7768_CHAN_INFO_NONE), }; =20 +static const struct iio_chan_spec adaq776x_channels[] =3D { + AD7768_CHAN(0, BIT(IIO_CHAN_INFO_SCALE)), +}; + static int ad7768_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long info) { struct ad7768_state *st =3D iio_priv(indio_dev); const struct iio_scan_type *scan_type; - int scale_uv, ret, temp; + int ret, temp; =20 scan_type =3D iio_get_current_scan_type(indio_dev, chan); if (IS_ERR(scan_type)) @@ -809,12 +968,19 @@ static int ad7768_read_raw(struct iio_dev *indio_dev, return IIO_VAL_INT; =20 case IIO_CHAN_INFO_SCALE: - scale_uv =3D st->vref_uv; - if (scale_uv < 0) - return scale_uv; - - *val =3D (scale_uv * 2) / 1000; - *val2 =3D scan_type->realbits; + if (st->chip->has_pga) { + *val =3D st->scale_tbl[st->pga_gain_mode][0]; + *val2 =3D st->scale_tbl[st->pga_gain_mode][1]; + return IIO_VAL_INT_PLUS_NANO; + } + *val =3D st->vref_uv / 1000; + if (st->chip->has_variable_aaf) + *val =3D (*val * MILLI) / ad7768_aaf_gains[st->aaf_gain]; + /* + * ADC output code is two's complement so only (realbits - 1) + * bits express voltage magnitude. + */ + *val2 =3D scan_type->realbits - 1; =20 return IIO_VAL_FRACTIONAL_LOG2; =20 @@ -869,18 +1035,42 @@ static int ad7768_read_avail(struct iio_dev *indio_d= ev, *length =3D st->samp_freq_avail_len; *type =3D IIO_VAL_INT; return IIO_AVAIL_LIST; + case IIO_CHAN_INFO_SCALE: + *vals =3D (int *)st->scale_tbl; + *length =3D st->chip->num_pga_modes * 2; + *type =3D IIO_VAL_INT_PLUS_NANO; + return IIO_AVAIL_LIST; default: return -EINVAL; } } =20 +static int ad7768_write_raw_get_fmt(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, long mask) +{ + switch (mask) { + case IIO_CHAN_INFO_SCALE: + return IIO_VAL_INT_PLUS_NANO; + default: + return IIO_VAL_INT_PLUS_MICRO; + } + + return -EINVAL; +} + static int __ad7768_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int val, int val2, long info) { struct ad7768_state *st =3D iio_priv(indio_dev); + const struct iio_scan_type *scan_type; + int gain_mode; int ret; =20 + scan_type =3D iio_get_current_scan_type(indio_dev, chan); + if (IS_ERR(scan_type)) + return PTR_ERR(scan_type); + switch (info) { case IIO_CHAN_INFO_SAMP_FREQ: return ad7768_set_freq(st, val); @@ -892,6 +1082,13 @@ static int __ad7768_write_raw(struct iio_dev *indio_d= ev, =20 /* Update sampling frequency */ return ad7768_set_freq(st, st->samp_freq); + case IIO_CHAN_INFO_SCALE: + if (!st->chip->has_pga) + return -EOPNOTSUPP; + + gain_mode =3D ad7768_calc_pga_gain(st, val, val2, + scan_type->realbits); + return ad7768_set_pga_gain(st, gain_mode); default: return -EINVAL; } @@ -933,6 +1130,7 @@ static const struct iio_info ad7768_info =3D { .read_raw =3D &ad7768_read_raw, .read_avail =3D &ad7768_read_avail, .write_raw =3D &ad7768_write_raw, + .write_raw_get_fmt =3D &ad7768_write_raw_get_fmt, .read_label =3D ad7768_read_label, .get_current_scan_type =3D &ad7768_get_current_scan_type, .debugfs_reg_access =3D &ad7768_reg_access, @@ -1351,10 +1549,46 @@ static const struct ad7768_chip_info ad7768_chip_in= fo =3D { .available_masks =3D ad7768_channel_masks, }; =20 +static const struct ad7768_chip_info adaq7767_chip_info =3D { + .name =3D "adaq7767-1", + .channel_spec =3D ad7768_channels, + .num_channels =3D ARRAY_SIZE(ad7768_channels), + .available_masks =3D ad7768_channel_masks, + .has_pga =3D false, + .has_variable_aaf =3D true +}; + +static const struct ad7768_chip_info adaq7768_chip_info =3D { + .name =3D "adaq7768-1", + .channel_spec =3D adaq776x_channels, + .num_channels =3D ARRAY_SIZE(adaq776x_channels), + .available_masks =3D ad7768_channel_masks, + .pga_gains =3D adaq7768_gains, + .default_pga_mode =3D AD7768_PGA_GAIN_2, + .num_pga_modes =3D ARRAY_SIZE(adaq7768_gains), + .pgia_mode2pin_offset =3D 6, + .has_pga =3D true, + .has_variable_aaf =3D false +}; + +static const struct ad7768_chip_info adaq7769_chip_info =3D { + .name =3D "adaq7769-1", + .channel_spec =3D adaq776x_channels, + .num_channels =3D ARRAY_SIZE(adaq776x_channels), + .available_masks =3D ad7768_channel_masks, + .pga_gains =3D adaq7769_gains, + .default_pga_mode =3D AD7768_PGA_GAIN_0, + .num_pga_modes =3D ARRAY_SIZE(adaq7769_gains), + .pgia_mode2pin_offset =3D 0, + .has_pga =3D true, + .has_variable_aaf =3D true +}; + static int ad7768_probe(struct spi_device *spi) { struct ad7768_state *st; struct iio_dev *indio_dev; + u32 val; int ret; =20 indio_dev =3D devm_iio_device_alloc(&spi->dev, sizeof(*st)); @@ -1418,6 +1652,35 @@ static int ad7768_probe(struct spi_device *spi) if (ret) return ret; =20 + st->aaf_gain =3D AD7768_AAF_IN1; + ret =3D device_property_read_u32(&spi->dev, "adi,aaf-gain", &val); + if (ret) { + /* AAF gain required, but not specified */ + if (st->chip->has_variable_aaf) + return dev_err_probe(&spi->dev, -EINVAL, "AAF gain not specified\n"); + + } else if (!st->chip->has_variable_aaf) { + /* AAF gain provided, but not supported */ + return dev_err_probe(&spi->dev, -EINVAL, "AAF gain not supported for %s\= n", + st->chip->name); + } else { + /* Device supports variable AAF gain, validate and set the gain */ + switch (val) { + case 1000: + st->aaf_gain =3D AD7768_AAF_IN1; + break; + case 364: + st->aaf_gain =3D AD7768_AAF_IN2; + break; + case 143: + st->aaf_gain =3D AD7768_AAF_IN3; + break; + default: + return dev_err_probe(&spi->dev, -EINVAL, + "Invalid firmware provided gain\n"); + } + } + ret =3D ad7768_setup(indio_dev); if (ret < 0) { dev_err(&spi->dev, "AD7768 setup failed\n"); @@ -1426,6 +1689,9 @@ static int ad7768_probe(struct spi_device *spi) =20 init_completion(&st->completion); =20 + if (st->chip->has_pga) + ad7768_set_pga_gain(st, st->chip->default_pga_mode); + ret =3D ad7768_set_channel_label(indio_dev, st->chip->num_channels); if (ret) return ret; @@ -1446,12 +1712,18 @@ static int ad7768_probe(struct spi_device *spi) =20 static const struct spi_device_id ad7768_id_table[] =3D { { "ad7768-1", (kernel_ulong_t)&ad7768_chip_info }, + { "adaq7767-1", (kernel_ulong_t)&adaq7767_chip_info }, + { "adaq7768-1", (kernel_ulong_t)&adaq7768_chip_info }, + { "adaq7769-1", (kernel_ulong_t)&adaq7769_chip_info }, { } }; MODULE_DEVICE_TABLE(spi, ad7768_id_table); =20 static const struct of_device_id ad7768_of_match[] =3D { { .compatible =3D "adi,ad7768-1", .data =3D &ad7768_chip_info }, + { .compatible =3D "adi,adaq7767-1", .data =3D &adaq7767_chip_info }, + { .compatible =3D "adi,adaq7768-1", .data =3D &adaq7768_chip_info }, + { .compatible =3D "adi,adaq7769-1", .data =3D &adaq7769_chip_info }, { } }; MODULE_DEVICE_TABLE(of, ad7768_of_match); --=20 2.34.1