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Wed, 06 Aug 2025 00:02:58 -0700 (PDT) Received: from mva-rohm ([2a10:a5c0:800d:dd00:8fdf:935a:2c85:d703]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-55b8899ebf9sm2196573e87.43.2025.08.06.00.02.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Aug 2025 00:02:57 -0700 (PDT) Date: Wed, 6 Aug 2025 10:02:53 +0300 From: Matti Vaittinen To: Matti Vaittinen , Matti Vaittinen Cc: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , David Lechner , Nuno =?iso-8859-1?Q?S=E1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matti Vaittinen , Liam Girdwood , Mark Brown , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/8] iio: adc: ad7476: Simplify chip type detection Message-ID: <4e9aaa826d152e80ff317413f961818ef0afe8da.1754463393.git.mazziesaccount@gmail.com> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="r2W1TOD/KtAd1uwi" Content-Disposition: inline In-Reply-To: --r2W1TOD/KtAd1uwi Content-Disposition: inline Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The ad7476 driver uses a table of structures for defining the IC variant specific data. Table is indexed using enum values, which are picked by SPI ID. Having the table and an enum adds extra complexity and may encourage adding IC specific quircks in the code, instead of centralizing the IC differences in one place, the chip-info. Simplify this by dropping the table and using individual structures for the IC specific data, and storing the IC specific structure's address directly in the SPI ID data. Finally, switch to the spi_get_device_match_data() and add a check for the return value. Signed-off-by: Matti Vaittinen Reviewed-by: Nuno S=C3=A1 --- Revision history: This patch was originally sent as an RFC in 2 patch series: https://lore.kernel.org/all/cover.1754041258.git.mazziesaccount@gmail.com/ Changes from the RFC: - Use spi_get_device_match_data() - Slightly reword commit message --- drivers/iio/adc/ad7476.c | 296 +++++++++++++++++++-------------------- 1 file changed, 146 insertions(+), 150 deletions(-) diff --git a/drivers/iio/adc/ad7476.c b/drivers/iio/adc/ad7476.c index aea734aa06bd..9869526c1524 100644 --- a/drivers/iio/adc/ad7476.c +++ b/drivers/iio/adc/ad7476.c @@ -52,29 +52,6 @@ struct ad7476_state { unsigned char data[ALIGN(2, sizeof(s64)) + sizeof(s64)] __aligned(IIO_DMA= _MINALIGN); }; =20 -enum ad7476_supported_device_ids { - ID_AD7091, - ID_AD7091R, - ID_AD7273, - ID_AD7274, - ID_AD7276, - ID_AD7277, - ID_AD7278, - ID_AD7466, - ID_AD7467, - ID_AD7468, - ID_AD7475, - ID_AD7495, - ID_AD7940, - ID_ADC081S, - ID_ADC101S, - ID_ADC121S, - ID_ADS7866, - ID_ADS7867, - ID_ADS7868, - ID_LTC2314_14, -}; - static void ad7091_convst(struct ad7476_state *st) { if (!st->convst_gpio) @@ -190,102 +167,119 @@ static int ad7476_read_raw(struct iio_dev *indio_de= v, #define ADS786X_CHAN(bits) _AD7476_CHAN((bits), 12 - (bits), \ BIT(IIO_CHAN_INFO_RAW)) =20 -static const struct ad7476_chip_info ad7476_chip_info_tbl[] =3D { - [ID_AD7091] =3D { - .channel[0] =3D AD7091R_CHAN(12), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - .convst_channel[0] =3D AD7091R_CONVST_CHAN(12), - .convst_channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - .reset =3D ad7091_reset, - }, - [ID_AD7091R] =3D { - .channel[0] =3D AD7091R_CHAN(12), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - .convst_channel[0] =3D AD7091R_CONVST_CHAN(12), - .convst_channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - .int_vref_uv =3D 2500000, - .has_vref =3D true, - .reset =3D ad7091_reset, - }, - [ID_AD7273] =3D { - .channel[0] =3D AD7940_CHAN(10), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - .has_vref =3D true, - }, - [ID_AD7274] =3D { - .channel[0] =3D AD7940_CHAN(12), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - .has_vref =3D true, - }, - [ID_AD7276] =3D { - .channel[0] =3D AD7940_CHAN(12), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - }, - [ID_AD7277] =3D { - .channel[0] =3D AD7940_CHAN(10), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - }, - [ID_AD7278] =3D { - .channel[0] =3D AD7940_CHAN(8), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - }, - [ID_AD7466] =3D { - .channel[0] =3D AD7476_CHAN(12), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - }, - [ID_AD7467] =3D { - .channel[0] =3D AD7476_CHAN(10), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - }, - [ID_AD7468] =3D { - .channel[0] =3D AD7476_CHAN(8), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - }, - [ID_AD7475] =3D { - .channel[0] =3D AD7476_CHAN(12), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - .has_vref =3D true, - .has_vdrive =3D true, - }, - [ID_AD7495] =3D { - .channel[0] =3D AD7476_CHAN(12), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - .int_vref_uv =3D 2500000, - .has_vdrive =3D true, - }, - [ID_AD7940] =3D { - .channel[0] =3D AD7940_CHAN(14), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - }, - [ID_ADC081S] =3D { - .channel[0] =3D ADC081S_CHAN(8), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - }, - [ID_ADC101S] =3D { - .channel[0] =3D ADC081S_CHAN(10), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - }, - [ID_ADC121S] =3D { - .channel[0] =3D ADC081S_CHAN(12), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - }, - [ID_ADS7866] =3D { - .channel[0] =3D ADS786X_CHAN(12), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - }, - [ID_ADS7867] =3D { - .channel[0] =3D ADS786X_CHAN(10), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - }, - [ID_ADS7868] =3D { - .channel[0] =3D ADS786X_CHAN(8), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - }, - [ID_LTC2314_14] =3D { - .channel[0] =3D AD7940_CHAN(14), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - .has_vref =3D true, - }, +static const struct ad7476_chip_info ad7091_chip_info =3D { + .channel[0] =3D AD7091R_CHAN(12), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), + .convst_channel[0] =3D AD7091R_CONVST_CHAN(12), + .convst_channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), + .reset =3D ad7091_reset, +}; + +static const struct ad7476_chip_info ad7091r_chip_info =3D { + .channel[0] =3D AD7091R_CHAN(12), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), + .convst_channel[0] =3D AD7091R_CONVST_CHAN(12), + .convst_channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), + .int_vref_uv =3D 2500000, + .has_vref =3D true, + .reset =3D ad7091_reset, +}; + +static const struct ad7476_chip_info ad7273_chip_info =3D { + .channel[0] =3D AD7940_CHAN(10), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), + .has_vref =3D true, +}; + +static const struct ad7476_chip_info ad7274_chip_info =3D { + .channel[0] =3D AD7940_CHAN(12), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), + .has_vref =3D true, +}; + +static const struct ad7476_chip_info ad7276_chip_info =3D { + .channel[0] =3D AD7940_CHAN(12), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), +}; + +static const struct ad7476_chip_info ad7277_chip_info =3D { + .channel[0] =3D AD7940_CHAN(10), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), +}; + +static const struct ad7476_chip_info ad7278_chip_info =3D { + .channel[0] =3D AD7940_CHAN(8), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), +}; + +static const struct ad7476_chip_info ad7466_chip_info =3D { + .channel[0] =3D AD7476_CHAN(12), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), +}; + +static const struct ad7476_chip_info ad7467_chip_info =3D { + .channel[0] =3D AD7476_CHAN(10), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), +}; + +static const struct ad7476_chip_info ad7468_chip_info =3D { + .channel[0] =3D AD7476_CHAN(8), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), +}; + +static const struct ad7476_chip_info ad7475_chip_info =3D { + .channel[0] =3D AD7476_CHAN(12), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), + .has_vref =3D true, + .has_vdrive =3D true, +}; + +static const struct ad7476_chip_info ad7495_chip_info =3D { + .channel[0] =3D AD7476_CHAN(12), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), + .int_vref_uv =3D 2500000, + .has_vdrive =3D true, +}; + +static const struct ad7476_chip_info ad7940_chip_info =3D { + .channel[0] =3D AD7940_CHAN(14), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), +}; + +static const struct ad7476_chip_info adc081s_chip_info =3D { + .channel[0] =3D ADC081S_CHAN(8), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), +}; + +static const struct ad7476_chip_info adc101s_chip_info =3D { + .channel[0] =3D ADC081S_CHAN(10), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), +}; + +static const struct ad7476_chip_info adc121s_chip_info =3D { + .channel[0] =3D ADC081S_CHAN(12), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), +}; + +static const struct ad7476_chip_info ads7866_chip_info =3D { + .channel[0] =3D ADS786X_CHAN(12), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), +}; + +static const struct ad7476_chip_info ads7867_chip_info =3D { + .channel[0] =3D ADS786X_CHAN(10), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), +}; + +static const struct ad7476_chip_info ads7868_chip_info =3D { + .channel[0] =3D ADS786X_CHAN(8), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), +}; + +static const struct ad7476_chip_info ltc2314_14_chip_info =3D { + .channel[0] =3D AD7940_CHAN(14), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), + .has_vref =3D true, }; =20 static const struct iio_info ad7476_info =3D { @@ -311,8 +305,10 @@ static int ad7476_probe(struct spi_device *spi) return -ENOMEM; =20 st =3D iio_priv(indio_dev); - st->chip_info =3D - &ad7476_chip_info_tbl[spi_get_device_id(spi)->driver_data]; + + st->chip_info =3D spi_get_device_match_data(spi); + if (!st->chip_info) + return -ENODEV; =20 reg =3D devm_regulator_get(&spi->dev, "vcc"); if (IS_ERR(reg)) @@ -408,41 +404,41 @@ static int ad7476_probe(struct spi_device *spi) } =20 static const struct spi_device_id ad7476_id[] =3D { - { "ad7091", ID_AD7091 }, - { "ad7091r", ID_AD7091R }, - { "ad7273", ID_AD7273 }, - { "ad7274", ID_AD7274 }, - { "ad7276", ID_AD7276}, - { "ad7277", ID_AD7277 }, - { "ad7278", ID_AD7278 }, - { "ad7466", ID_AD7466 }, - { "ad7467", ID_AD7467 }, - { "ad7468", ID_AD7468 }, - { "ad7475", ID_AD7475 }, - { "ad7476", ID_AD7466 }, - { "ad7476a", ID_AD7466 }, - { "ad7477", ID_AD7467 }, - { "ad7477a", ID_AD7467 }, - { "ad7478", ID_AD7468 }, - { "ad7478a", ID_AD7468 }, - { "ad7495", ID_AD7495 }, - { "ad7910", ID_AD7467 }, - { "ad7920", ID_AD7466 }, - { "ad7940", ID_AD7940 }, - { "adc081s", ID_ADC081S }, - { "adc101s", ID_ADC101S }, - { "adc121s", ID_ADC121S }, - { "ads7866", ID_ADS7866 }, - { "ads7867", ID_ADS7867 }, - { "ads7868", ID_ADS7868 }, + { "ad7091", (kernel_ulong_t)&ad7091_chip_info }, + { "ad7091r", (kernel_ulong_t)&ad7091r_chip_info }, + { "ad7273", (kernel_ulong_t)&ad7273_chip_info }, + { "ad7274", (kernel_ulong_t)&ad7274_chip_info }, + { "ad7276", (kernel_ulong_t)&ad7276_chip_info }, + { "ad7277", (kernel_ulong_t)&ad7277_chip_info }, + { "ad7278", (kernel_ulong_t)&ad7278_chip_info }, + { "ad7466", (kernel_ulong_t)&ad7466_chip_info }, + { "ad7467", (kernel_ulong_t)&ad7467_chip_info }, + { "ad7468", (kernel_ulong_t)&ad7468_chip_info }, + { "ad7475", (kernel_ulong_t)&ad7475_chip_info }, + { "ad7476", (kernel_ulong_t)&ad7466_chip_info }, + { "ad7476a", (kernel_ulong_t)&ad7466_chip_info }, + { "ad7477", (kernel_ulong_t)&ad7467_chip_info }, + { "ad7477a", (kernel_ulong_t)&ad7467_chip_info }, + { "ad7478", (kernel_ulong_t)&ad7468_chip_info }, + { "ad7478a", (kernel_ulong_t)&ad7468_chip_info }, + { "ad7495", (kernel_ulong_t)&ad7495_chip_info }, + { "ad7910", (kernel_ulong_t)&ad7467_chip_info }, + { "ad7920", (kernel_ulong_t)&ad7466_chip_info }, + { "ad7940", (kernel_ulong_t)&ad7940_chip_info }, + { "adc081s", (kernel_ulong_t)&adc081s_chip_info }, + { "adc101s", (kernel_ulong_t)&adc101s_chip_info }, + { "adc121s", (kernel_ulong_t)&adc121s_chip_info }, + { "ads7866", (kernel_ulong_t)&ads7866_chip_info }, + { "ads7867", (kernel_ulong_t)&ads7867_chip_info }, + { "ads7868", (kernel_ulong_t)&ads7868_chip_info }, /* * The ROHM BU79100G is identical to the TI's ADS7866 from the software * point of view. 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Wed, 06 Aug 2025 00:03:13 -0700 (PDT) Received: from mva-rohm ([2a10:a5c0:800d:dd00:8fdf:935a:2c85:d703]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-55b88cb7e15sm2198377e87.176.2025.08.06.00.03.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Aug 2025 00:03:12 -0700 (PDT) Date: Wed, 6 Aug 2025 10:03:07 +0300 From: Matti Vaittinen To: Matti Vaittinen , Matti Vaittinen Cc: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , David Lechner , Nuno =?iso-8859-1?Q?S=E1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matti Vaittinen , Liam Girdwood , Mark Brown , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/8] iio: adc: ad7476: Simplify scale handling Message-ID: <645ac6fb917e12db6cdc0fc343487531f61c176a.1754463393.git.mazziesaccount@gmail.com> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="tSziX7xv44S3yHgS" Content-Disposition: inline In-Reply-To: --tSziX7xv44S3yHgS Content-Disposition: inline Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The ad7476 driver supports variants with different amount of supply regulators. On some variants there is only VCC, which is used as a reference voltage. Others have separate VREF regulator, and some rely on internal VREF. Some have both internal VREF and option to connect external one. The ad7476 driver reads the regulator voltage only when the user asks to get the scale. This means the driver needs to do some dancing while picking the correct reference regulator (or internal reference), and store it for the later use. According to the discussion: https://lore.kernel.org/linux-iio/20250331122247.05c6b09d@jic23-huawei/ variable voltage references are rare, making it hard to justify the added complexity for supporting those. Drop the support for the variable voltage references and simplify things by using the managed regulator get and enable interfaces. Signed-off-by: Matti Vaittinen Reviewed-by: Nuno S=C3=A1 --- Revision history: This patch was originally sent as an RFC in 2 patch series: https://lore.kernel.org/all/cover.1754041258.git.mazziesaccount@gmail.com/ Changes from the RFC: - Fix the faulty conversion from uV to mV as pointed out by David. --- drivers/iio/adc/ad7476.c | 84 ++++++++++------------------------------ 1 file changed, 21 insertions(+), 63 deletions(-) diff --git a/drivers/iio/adc/ad7476.c b/drivers/iio/adc/ad7476.c index 9869526c1524..f117aafd8fad 100644 --- a/drivers/iio/adc/ad7476.c +++ b/drivers/iio/adc/ad7476.c @@ -39,10 +39,10 @@ struct ad7476_chip_info { struct ad7476_state { struct spi_device *spi; const struct ad7476_chip_info *chip_info; - struct regulator *ref_reg; struct gpio_desc *convst_gpio; struct spi_transfer xfer; struct spi_message msg; + int scale_mv; /* * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. @@ -111,7 +111,6 @@ static int ad7476_read_raw(struct iio_dev *indio_dev, { int ret; struct ad7476_state *st =3D iio_priv(indio_dev); - int scale_uv; =20 switch (m) { case IIO_CHAN_INFO_RAW: @@ -126,14 +125,7 @@ static int ad7476_read_raw(struct iio_dev *indio_dev, GENMASK(st->chip_info->channel[0].scan_type.realbits - 1, 0); return IIO_VAL_INT; case IIO_CHAN_INFO_SCALE: - if (st->ref_reg) { - scale_uv =3D regulator_get_voltage(st->ref_reg); - if (scale_uv < 0) - return scale_uv; - } else { - scale_uv =3D st->chip_info->int_vref_uv; - } - *val =3D scale_uv / 1000; + *val =3D st->scale_mv; *val2 =3D chan->scan_type.realbits; return IIO_VAL_FRACTIONAL_LOG2; } @@ -286,18 +278,10 @@ static const struct iio_info ad7476_info =3D { .read_raw =3D &ad7476_read_raw, }; =20 -static void ad7476_reg_disable(void *data) -{ - struct regulator *reg =3D data; - - regulator_disable(reg); -} - static int ad7476_probe(struct spi_device *spi) { struct ad7476_state *st; struct iio_dev *indio_dev; - struct regulator *reg; int ret; =20 indio_dev =3D devm_iio_device_alloc(&spi->dev, sizeof(*st)); @@ -310,58 +294,32 @@ static int ad7476_probe(struct spi_device *spi) if (!st->chip_info) return -ENODEV; =20 - reg =3D devm_regulator_get(&spi->dev, "vcc"); - if (IS_ERR(reg)) - return PTR_ERR(reg); - - ret =3D regulator_enable(reg); - if (ret) - return ret; - - ret =3D devm_add_action_or_reset(&spi->dev, ad7476_reg_disable, reg); - if (ret) - return ret; - - /* Either vcc or vref (below) as appropriate */ - if (!st->chip_info->int_vref_uv) - st->ref_reg =3D reg; + /* Use VCC for reference voltage if vref / internal vref aren't used */ + if (!st->chip_info->int_vref_uv && !st->chip_info->has_vref) { + ret =3D devm_regulator_get_enable_read_voltage(&spi->dev, "vcc"); + if (ret < 0) + return ret; + st->scale_mv =3D ret / 1000; + } else { + ret =3D devm_regulator_get_enable(&spi->dev, "vcc"); + if (ret < 0) + return ret; + } =20 if (st->chip_info->has_vref) { - - /* If a device has an internal reference vref is optional */ - if (st->chip_info->int_vref_uv) { - reg =3D devm_regulator_get_optional(&spi->dev, "vref"); - if (IS_ERR(reg) && (PTR_ERR(reg) !=3D -ENODEV)) - return PTR_ERR(reg); - } else { - reg =3D devm_regulator_get(&spi->dev, "vref"); - if (IS_ERR(reg)) - return PTR_ERR(reg); - } - - if (!IS_ERR(reg)) { - ret =3D regulator_enable(reg); - if (ret) + ret =3D devm_regulator_get_enable_read_voltage(&spi->dev, "vref"); + if (ret < 0) { + /* Vref is optional if a device has an internal reference */ + if (!st->chip_info->int_vref_uv || ret !=3D -ENODEV) return ret; - - ret =3D devm_add_action_or_reset(&spi->dev, - ad7476_reg_disable, - reg); - if (ret) - return ret; - st->ref_reg =3D reg; } else { - /* - * Can only get here if device supports both internal - * and external reference, but the regulator connected - * to the external reference is not connected. - * Set the reference regulator pointer to NULL to - * indicate this. - */ - st->ref_reg =3D NULL; + st->scale_mv =3D ret / 1000; } } =20 + if (!st->scale_mv) + st->scale_mv =3D st->chip_info->int_vref_uv / 1000; + if (st->chip_info->has_vdrive) { ret =3D devm_regulator_get_enable(&spi->dev, "vdrive"); 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Wed, 06 Aug 2025 00:03:31 -0700 (PDT) Received: from mva-rohm ([2a10:a5c0:800d:dd00:8fdf:935a:2c85:d703]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-55c9c847db8sm262502e87.84.2025.08.06.00.03.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Aug 2025 00:03:30 -0700 (PDT) Date: Wed, 6 Aug 2025 10:03:26 +0300 From: Matti Vaittinen To: Matti Vaittinen , Matti Vaittinen Cc: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , David Lechner , Nuno =?iso-8859-1?Q?S=E1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matti Vaittinen , Liam Girdwood , Mark Brown , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/8] iio: adc: ad7476: Use mV for internal reference Message-ID: <8d2e75bfbf518848d496915e9713541fb7c9bb3a.1754463393.git.mazziesaccount@gmail.com> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="itIkFx5ypfyPt7Gy" Content-Disposition: inline In-Reply-To: --itIkFx5ypfyPt7Gy Content-Disposition: inline Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The ad7476 supports some ICs with an internal reference voltage. For those ICs the reference voltage has been hard-coded as micro volts, but the value which is later used in code needs to be milli volts. This results the need to divide hard coded voltage by 1000 before using it. Simplify code by changing the hard-coded voltage to millivolts and by dropping the division. Signed-off-by: Matti Vaittinen --- drivers/iio/adc/ad7476.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/iio/adc/ad7476.c b/drivers/iio/adc/ad7476.c index f117aafd8fad..7b6d36999afc 100644 --- a/drivers/iio/adc/ad7476.c +++ b/drivers/iio/adc/ad7476.c @@ -27,7 +27,7 @@ struct ad7476_state; =20 struct ad7476_chip_info { - unsigned int int_vref_uv; + unsigned int int_vref_mv; struct iio_chan_spec channel[2]; /* channels used when convst gpio is defined */ struct iio_chan_spec convst_channel[2]; @@ -172,7 +172,7 @@ static const struct ad7476_chip_info ad7091r_chip_info = =3D { .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), .convst_channel[0] =3D AD7091R_CONVST_CHAN(12), .convst_channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - .int_vref_uv =3D 2500000, + .int_vref_mv =3D 2500, .has_vref =3D true, .reset =3D ad7091_reset, }; @@ -229,7 +229,7 @@ static const struct ad7476_chip_info ad7475_chip_info = =3D { static const struct ad7476_chip_info ad7495_chip_info =3D { .channel[0] =3D AD7476_CHAN(12), .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - .int_vref_uv =3D 2500000, + .int_vref_mv =3D 2500, .has_vdrive =3D true, }; =20 @@ -295,7 +295,7 @@ static int ad7476_probe(struct spi_device *spi) return -ENODEV; =20 /* Use VCC for reference voltage if vref / internal vref aren't used */ - if (!st->chip_info->int_vref_uv && !st->chip_info->has_vref) { + if (!st->chip_info->int_vref_mv && !st->chip_info->has_vref) { ret =3D devm_regulator_get_enable_read_voltage(&spi->dev, "vcc"); if (ret < 0) return ret; @@ -310,7 +310,7 @@ static int ad7476_probe(struct spi_device *spi) ret =3D devm_regulator_get_enable_read_voltage(&spi->dev, "vref"); if (ret < 0) { /* Vref is optional if a device has an internal reference */ - if (!st->chip_info->int_vref_uv || ret !=3D -ENODEV) + if (!st->chip_info->int_vref_mv || ret !=3D -ENODEV) return ret; } else { st->scale_mv =3D ret / 1000; @@ -318,7 +318,7 @@ static int ad7476_probe(struct spi_device *spi) } =20 if (!st->scale_mv) - st->scale_mv =3D st->chip_info->int_vref_uv / 1000; + st->scale_mv =3D st->chip_info->int_vref_mv; =20 if (st->chip_info->has_vdrive) { ret =3D devm_regulator_get_enable(&spi->dev, "vdrive"); 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Wed, 06 Aug 2025 00:03:47 -0700 (PDT) Received: from mva-rohm ([2a10:a5c0:800d:dd00:8fdf:935a:2c85:d703]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-55b8898bc7fsm2185475e87.33.2025.08.06.00.03.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Aug 2025 00:03:46 -0700 (PDT) Date: Wed, 6 Aug 2025 10:03:43 +0300 From: Matti Vaittinen To: Matti Vaittinen , Matti Vaittinen Cc: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , David Lechner , Nuno =?iso-8859-1?Q?S=E1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matti Vaittinen , Liam Girdwood , Mark Brown , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/8] iio: adc: ad7476: Use correct channel for bit info Message-ID: <7c353ad496e0056e9fb3869bf07e7fd66d816018.1754463393.git.mazziesaccount@gmail.com> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="NI9ctx46G+gVAh0K" Content-Disposition: inline In-Reply-To: --NI9ctx46G+gVAh0K Content-Disposition: inline Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The ad7476 supports ADCs which use separate GPIO for starting the conversion. For such devices, the driver uses different channel information if the GPIO is found. The bit information is still always used from the original (non 'convstart') channels. This has not been causing problems because the bit information for the 'convstart' -channel and the 'normal' -channel is identical. It, however, will cause issues if an IC has different characteristics for an 'convstart' -channel and regular channel. Furthermore, this will cause problems if a device always requires the convstart GPIO and thus only defines the convstart channel. Signed-off-by: Matti Vaittinen --- It appears that the _only_ difference between the 'convstart' -channel and the 'normal' channel is a lack of the 'raw-read' support. I might prefer seeing the _same_ channel information being used for 'convstart' and 'normal' channels, just setting the IIO_CHAN_INFO_RAW -bit when the CONVSTART GPIO is found. This would allow getting rid of the 'convstart' -channel spec altogeher. Having only one channel info spec would also help the code-reader to understand that the driver really provides only one data channel to the users. Currently a quick reader may assume the driver for some reason provides both the 'convstart' and the 'normal' channels. Adding the IIO_CHAN_INFO_RAW when CONVSTART GPIO is obtained would however require the channel information structs to be mutable - which may be seen as a "no, no" by some. Hence this minimally intrusive patch. --- drivers/iio/adc/ad7476.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/iio/adc/ad7476.c b/drivers/iio/adc/ad7476.c index 7b6d36999afc..fc701267358e 100644 --- a/drivers/iio/adc/ad7476.c +++ b/drivers/iio/adc/ad7476.c @@ -121,8 +121,8 @@ static int ad7476_read_raw(struct iio_dev *indio_dev, =20 if (ret < 0) return ret; - *val =3D (ret >> st->chip_info->channel[0].scan_type.shift) & - GENMASK(st->chip_info->channel[0].scan_type.realbits - 1, 0); + *val =3D (ret >> chan->scan_type.shift) & + GENMASK(chan->scan_type.realbits - 1, 0); return IIO_VAL_INT; case IIO_CHAN_INFO_SCALE: *val =3D st->scale_mv; @@ -345,7 +345,7 @@ static int ad7476_probe(struct spi_device *spi) /* Setup default message */ =20 st->xfer.rx_buf =3D &st->data; - st->xfer.len =3D st->chip_info->channel[0].scan_type.storagebits / 8; + st->xfer.len =3D indio_dev->channels[0].scan_type.storagebits / 8; =20 spi_message_init(&st->msg); spi_message_add_tail(&st->xfer, &st->msg); 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Wed, 06 Aug 2025 00:04:04 -0700 (PDT) Received: from mva-rohm ([2a10:a5c0:800d:dd00:8fdf:935a:2c85:d703]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-55b88c98c35sm2249459e87.97.2025.08.06.00.04.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Aug 2025 00:04:03 -0700 (PDT) Date: Wed, 6 Aug 2025 10:04:00 +0300 From: Matti Vaittinen To: Matti Vaittinen , Matti Vaittinen Cc: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , David Lechner , Nuno =?iso-8859-1?Q?S=E1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matti Vaittinen , Liam Girdwood , Mark Brown , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/8] iio: adc: ad7476: Conditionally call convstart Message-ID: <2030974bcd7a6fd0a904ae8dc9e9872086c59886.1754463393.git.mazziesaccount@gmail.com> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="MCDLFsQ7gMQ0bgWA" Content-Disposition: inline In-Reply-To: --MCDLFsQ7gMQ0bgWA Content-Disposition: inline Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The ad7476 supports two IC variants which may have a 'convstart' -GPIO for starting the conversion. Currently the driver calls a function which tries to access the GPIO for all of the IC variants, whether they support 'convstart' or not. This is not an error because this function returns early if GPIO information is not populated. We can do a tad better by calling this function only for the ICs which have the 'convstart' by providing a function pointer to the convstart function from the chip_info structure, and calling this function only for the ICs which have the function pointer set. This does also allow to support ICs which require different convstart handling than the currently supported ICs. Call convstart function only on the ICs which can support it and allow IC-specific convstart functions for the ICs which require different handling. Signed-off-by: Matti Vaittinen --- The follow-up patch adding support for the ROHM BD79105 will bring different 'convstart' functions in use. The IC specific pointer will also prepare the way for this. --- drivers/iio/adc/ad7476.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/iio/adc/ad7476.c b/drivers/iio/adc/ad7476.c index fc701267358e..1f736be09663 100644 --- a/drivers/iio/adc/ad7476.c +++ b/drivers/iio/adc/ad7476.c @@ -32,6 +32,7 @@ struct ad7476_chip_info { /* channels used when convst gpio is defined */ struct iio_chan_spec convst_channel[2]; void (*reset)(struct ad7476_state *); + void (*conversion_pre_op)(struct ad7476_state *st); bool has_vref; bool has_vdrive; }; @@ -70,7 +71,8 @@ static irqreturn_t ad7476_trigger_handler(int irq, void = *p) struct ad7476_state *st =3D iio_priv(indio_dev); int b_sent; =20 - ad7091_convst(st); + if (st->chip_info->conversion_pre_op) + st->chip_info->conversion_pre_op(st); =20 b_sent =3D spi_sync(st->spi, &st->msg); if (b_sent < 0) @@ -164,6 +166,7 @@ static const struct ad7476_chip_info ad7091_chip_info = =3D { .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), .convst_channel[0] =3D AD7091R_CONVST_CHAN(12), .convst_channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), + .conversion_pre_op =3D ad7091_convst, .reset =3D ad7091_reset, }; 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Wed, 06 Aug 2025 00:04:32 -0700 (PDT) Received: from mva-rohm ([2a10:a5c0:800d:dd00:8fdf:935a:2c85:d703]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-55b889a1942sm2194053e87.53.2025.08.06.00.04.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Aug 2025 00:04:31 -0700 (PDT) Date: Wed, 6 Aug 2025 10:04:28 +0300 From: Matti Vaittinen To: Matti Vaittinen , Matti Vaittinen Cc: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , David Lechner , Nuno =?iso-8859-1?Q?S=E1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matti Vaittinen , Liam Girdwood , Mark Brown , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 6/8] dt-bindings: iio: adc: ad7476: Add ROHM bd79105 Message-ID: <3066337cb183afa5f53a4e6cf94ce15a36d14ec8.1754463393.git.mazziesaccount@gmail.com> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="ZCvq7TjMx19kadkQ" Content-Disposition: inline In-Reply-To: --ZCvq7TjMx19kadkQ Content-Disposition: inline Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The ROHM BD79105 is a simple, 16-bit, 1-channel ADC with a 'CONVSTART' pin used to start the ADC conversion. Other than the 'CONVSTART', there are 3 supply pins (one used as a reference), analog inputs, ground and communication pins. It's worth noting that the pin somewhat confusingly labeled as 'DIN', is a pin which should be used as a chip-select. The IC does not have any writable registers. The device is designed so that the output pin can, in addition to outputting the data, be used as a 'data-ready'-IRQ. This, however, would require the IRQ to be masked from host side for the duration of the data reads - and it wouldn't also work when the SPI is shared. (As access to the other SPI devices would cause data line changes to be detected as IRQs - and the BD79105 provides no means to detect if it has generated an IRQ). Hence the device-tree does not contain any IRQ properties. Add a compatible for the bd79105. Signed-off-by: Matti Vaittinen --- .../devicetree/bindings/iio/adc/adi,ad7476.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7476.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad7476.yaml index d0cb32f136e5..16d3866dd633 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7476.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7476.yaml @@ -41,6 +41,7 @@ properties: - adi,ad7910 - adi,ad7920 - adi,ad7940 + - rohm,bd79105 - ti,adc081s - ti,adc101s - ti,adc121s @@ -115,6 +116,7 @@ allOf: - adi,ad7274 - adi,ad7475 - lltc,ltc2314-14 + - rohm,bd79105 then: properties: vref-supply: true @@ -131,6 +133,7 @@ allOf: - adi,ad7274 - adi,ad7475 - lltc,ltc2314-14 + - rohm,bd79105 then: required: - vref-supply @@ -141,6 +144,7 @@ allOf: enum: - adi,ad7475 - adi,ad7495 + - rohm,bd79105 then: properties: vdrive-supply: true @@ -154,6 +158,7 @@ allOf: enum: - adi,ad7091 - adi,ad7091r + - rohm,bd79105 then: properties: adi,conversion-start-gpios: true @@ -161,6 +166,17 @@ allOf: properties: adi,conversion-start-gpios: false =20 + # Devices with a convstart GPIO where it is not optional + - if: + properties: + compatible: + contains: + enum: + - rohm,bd79105 + then: + required: + - adi,conversion-start-gpios + unevaluatedProperties: false =20 examples: --=20 2.50.1 --ZCvq7TjMx19kadkQ Content-Type: application/pgp-signature; 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Wed, 06 Aug 2025 00:04:47 -0700 (PDT) Received: from mva-rohm ([2a10:a5c0:800d:dd00:8fdf:935a:2c85:d703]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-55ca388556asm263590e87.95.2025.08.06.00.04.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Aug 2025 00:04:46 -0700 (PDT) Date: Wed, 6 Aug 2025 10:04:43 +0300 From: Matti Vaittinen To: Matti Vaittinen , Matti Vaittinen Cc: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , David Lechner , Nuno =?iso-8859-1?Q?S=E1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matti Vaittinen , Liam Girdwood , Mark Brown , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 7/8] iio: adc: ad7476: Support ROHM BD79105 Message-ID: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="aUGwjoVvL5m2/5qa" Content-Disposition: inline In-Reply-To: --aUGwjoVvL5m2/5qa Content-Disposition: inline Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The ROHM BD79105 is a simple 16-bit ADC accessible via SPI*. The BD79105 has a CONVSTART pin, which must be set high to start the ADC conversion. Unlike with the ad7091 and ad7091r which also have a CONVSTART pin, the BD79105 requires that the pin must remain high also for the duration of the SPI access. (*) Couple of words about the SPI. The BD79105 has pins named as CONVSTART, SCLK, DIN and DOUT. For the curious reader, DIN is not SPI ISO. DIN is a signal which can be used as a chip-select. When DIN is pulled low, the ADC will output the completed measurement via DOUT as SCLK is clocked. According to the data-sheet, the DIN can also be used for daisy-chaining multiple ADCs. Also, DOUT can be used also for a 'data-ready' -IRQ. These modes aren't supported by this driver. Support reading ADC scale and data from the BD79105 using SPI, when DIN is used as a chip-select. Signed-off-by: Matti Vaittinen --- drivers/iio/adc/ad7476.c | 36 +++++++++++++++++++++++++++++++++++- 1 file changed, 35 insertions(+), 1 deletion(-) diff --git a/drivers/iio/adc/ad7476.c b/drivers/iio/adc/ad7476.c index 1f736be09663..fc98aadc4077 100644 --- a/drivers/iio/adc/ad7476.c +++ b/drivers/iio/adc/ad7476.c @@ -33,6 +33,7 @@ struct ad7476_chip_info { struct iio_chan_spec convst_channel[2]; void (*reset)(struct ad7476_state *); void (*conversion_pre_op)(struct ad7476_state *st); + void (*conversion_post_op)(struct ad7476_state *st); bool has_vref; bool has_vdrive; }; @@ -64,6 +65,23 @@ static void ad7091_convst(struct ad7476_state *st) udelay(1); /* Conversion time: 650 ns max */ } =20 +static void bd79105_convst_disable(struct ad7476_state *st) +{ + if (!st->convst_gpio) + return; + + gpiod_set_value(st->convst_gpio, 0); +} + +static void bd79105_convst_enable(struct ad7476_state *st) +{ + if (!st->convst_gpio) + return; + + gpiod_set_value(st->convst_gpio, 1); + udelay(1); /* 10ns required for conversion */ +} + static irqreturn_t ad7476_trigger_handler(int irq, void *p) { struct iio_poll_func *pf =3D p; @@ -81,6 +99,8 @@ static irqreturn_t ad7476_trigger_handler(int irq, void = *p) iio_push_to_buffers_with_ts(indio_dev, st->data, sizeof(st->data), iio_get_time_ns(indio_dev)); done: + if (st->chip_info->conversion_post_op) + st->chip_info->conversion_post_op(st); iio_trigger_notify_done(indio_dev->trig); =20 return IRQ_HANDLED; @@ -278,6 +298,20 @@ static const struct ad7476_chip_info ltc2314_14_chip_i= nfo =3D { .has_vref =3D true, }; =20 +static const struct ad7476_chip_info bd79105_chip_info =3D { + .convst_channel[0] =3D AD7091R_CONVST_CHAN(16), + .convst_channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), + /* + * The BD79105 starts ADC data conversion when thw CONVSTART is set + * HIGH. The CONVSTART must be kept HIGH until the data has been + * read from the ADC. + */ + .conversion_pre_op =3D bd79105_convst_enable, + .conversion_post_op =3D bd79105_convst_disable, + .has_vref =3D true, + .has_vdrive =3D true, +}; + static const struct iio_info ad7476_info =3D { .read_raw =3D &ad7476_read_raw, }; @@ -347,7 +381,6 @@ static int ad7476_probe(struct spi_device *spi) if (st->convst_gpio) indio_dev->channels =3D st->chip_info->convst_channel; /* Setup default message */ - st->xfer.rx_buf =3D &st->data; st->xfer.len =3D indio_dev->channels[0].scan_type.storagebits / 8; =20 @@ -393,6 +426,7 @@ static const struct spi_device_id ad7476_id[] =3D { { "ads7866", (kernel_ulong_t)&ads7866_chip_info }, { "ads7867", (kernel_ulong_t)&ads7867_chip_info }, { "ads7868", (kernel_ulong_t)&ads7868_chip_info }, + { "bd79105", (kernel_ulong_t)&bd79105_chip_info }, /* * The ROHM BU79100G is identical to the TI's ADS7866 from the software * point of view. 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Wed, 06 Aug 2025 00:05:03 -0700 (PDT) Received: from mva-rohm ([2a10:a5c0:800d:dd00:8fdf:935a:2c85:d703]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-332382a9054sm21907041fa.28.2025.08.06.00.05.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Aug 2025 00:05:02 -0700 (PDT) Date: Wed, 6 Aug 2025 10:04:59 +0300 From: Matti Vaittinen To: Matti Vaittinen , Matti Vaittinen Cc: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , David Lechner , Nuno =?iso-8859-1?Q?S=E1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matti Vaittinen , Liam Girdwood , Mark Brown , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 8/8] MAINTAINERS: A driver for simple 1-channel SPI ADCs Message-ID: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="FRYUNwuGdlf6494p" Content-Disposition: inline In-Reply-To: --FRYUNwuGdlf6494p Content-Disposition: inline Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add undersigned as a maintainer for the ad7476.c which supports a few simple 1-channel ADC connected to SPI. Signed-off-by: Matti Vaittinen --- I'll try to keep this on eye. I only have access to the ROHM BD79105 and BU79100g. I would welcome anyone with access to other supported ADCs (and time, energy and the knowledge) to join me. :) --- MAINTAINERS | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index f8c8f682edf6..36fa6333f7b5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -455,6 +455,11 @@ F: Documentation/devicetree/bindings/iio/adc/adi,ad738= 0.yaml F: Documentation/iio/ad7380.rst F: drivers/iio/adc/ad7380.c =20 +AD7476 ADC DRIVER FOR VARIOUS SIMPLE 1-CHANNEL SPI ADCs +M: Matti Vaittinen +S: Maintained +F: drivers/iio/adc/ad7476.c + AD7877 TOUCHSCREEN DRIVER M: Michael Hennerich S: Supported --=20 2.50.1 --FRYUNwuGdlf6494p Content-Type: application/pgp-signature; name=signature.asc -----BEGIN PGP SIGNATURE----- iQEzBAEBCgAdFiEEIx+f8wZb28fLKEhTeFA3/03aocUFAmiS/psACgkQeFA3/03a ocVNowgA0TdC3tO5f+X4k2YSfdqbaPiI5OAVA6kHDbpleeBppf0yWagjXh2ecY/X B4d4W4/SrjOnfjlMdN9x+q5zacokUTDzc41f0mMwdwblLH84lsjfXto3YAMXVL1/ KdBgZ3tvLgKAa75NcQeNj9HL8CrUJtaiR9JhtzOuHT1AmTLsjy24OMs5pDL2zH2a UNE7NZ/9zvEtsHTfFXCLwE5Y3gc3geakWhNgL+bp2gExaYok1YH54fogKE9CW7kL /t5st4NmjsyOCyuGy8hsNUmhNkzJiGtNXg2B6A99r/FnjLFk79y+b6KI4QNatnmV cHahdtZd+ZLjWX2YI0PmrBzOANcs5Q== =1cUJ -----END PGP SIGNATURE----- --FRYUNwuGdlf6494p--