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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Aug 2025 23:30:55.1766 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 624aacae-ea59-4337-42b9-08ddd4781fe0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003F66.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN7PPF08EEA05B5 Content-Type: text/plain; charset="utf-8" Smart Data Cache Injection (SDCI) is a mechanism that enables direct insertion of data from I/O devices into the L3 cache. By directly caching data from I/O devices rather than first storing the I/O data in DRAM, SDCI reduces demands on DRAM bandwidth and reduces latency to the processor consuming the I/O data. The SDCIAE (SDCI Allocation Enforcement) PQE feature allows system software to control the portion of the L3 cache used for SDCI. When enabled, SDCIAE forces all SDCI lines to be placed into the L3 cache partitions identified by the highest-supported L3_MASK_n register, where n is the maximum supported CLOSID. Add CPUID feature bit that can be used to configure SDCIAE. The feature details are documented in APM listed below [1]. [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming Publication # 24593 Revision 3.41 section 19.4.7 L3 Smart Data Cache Injection Allocation Enforcement (SDCIAE) Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537 Signed-off-by: Babu Moger Acked-by: Borislav Petkov (AMD) Reviewed-by: Reinette Chatre --- v8: Added Acked-by, Reviewed-by tags. v7: No changes. Fixed few conflicts in arch/x86/include/asm/cpufeatures.h arch/x86/kernel/cpu/scattered.c v6: Resolved conflicts in cpufeatures.h. v5: No changes. v4: Resolved a minor conflict in cpufeatures.h. v3: No changes. v2: Added dependancy on X86_FEATURE_CAT_L3 Removed the "" in CPU feature definition. Minor text changes. --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/cpuid-deps.c | 1 + arch/x86/kernel/cpu/scattered.c | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index 602957dd2609..db020bd60edc 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -494,6 +494,7 @@ #define X86_FEATURE_TSA_SQ_NO (21*32+11) /* AMD CPU not vulnerable to TSA= -SQ */ #define X86_FEATURE_TSA_L1_NO (21*32+12) /* AMD CPU not vulnerable to TSA= -L1 */ #define X86_FEATURE_CLEAR_CPU_BUF_VM (21*32+13) /* Clear CPU buffers using= VERW before VMRUN */ +#define X86_FEATURE_SDCIAE (21*32+14) /* L3 Smart Data Cache Injection Al= location Enforcement */ =20 /* * BUG word(s) diff --git a/arch/x86/kernel/cpu/cpuid-deps.c b/arch/x86/kernel/cpu/cpuid-d= eps.c index 46efcbd6afa4..87e78586395b 100644 --- a/arch/x86/kernel/cpu/cpuid-deps.c +++ b/arch/x86/kernel/cpu/cpuid-deps.c @@ -72,6 +72,7 @@ static const struct cpuid_dep cpuid_deps[] =3D { { X86_FEATURE_CQM_MBM_LOCAL, X86_FEATURE_CQM_LLC }, { X86_FEATURE_BMEC, X86_FEATURE_CQM_MBM_TOTAL }, { X86_FEATURE_BMEC, X86_FEATURE_CQM_MBM_LOCAL }, + { X86_FEATURE_SDCIAE, X86_FEATURE_CAT_L3 }, { X86_FEATURE_AVX512_BF16, X86_FEATURE_AVX512VL }, { X86_FEATURE_AVX512_FP16, X86_FEATURE_AVX512BW }, { X86_FEATURE_ENQCMD, X86_FEATURE_XSAVES }, diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattere= d.c index b4a1f6732a3a..b22bfe81d262 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -50,6 +50,7 @@ static const struct cpuid_bit cpuid_bits[] =3D { { X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 }, { X86_FEATURE_SMBA, CPUID_EBX, 2, 0x80000020, 0 }, { X86_FEATURE_BMEC, CPUID_EBX, 3, 0x80000020, 0 }, + { X86_FEATURE_SDCIAE, CPUID_EBX, 6, 0x80000020, 0 }, { X86_FEATURE_TSA_SQ_NO, CPUID_ECX, 1, 0x80000021, 0 }, { X86_FEATURE_TSA_L1_NO, CPUID_ECX, 2, 0x80000021, 0 }, { X86_FEATURE_AMD_WORKLOAD_CLASS, CPUID_EAX, 22, 0x80000021, 0 }, --=20 2.34.1 From nobody Sun Oct 5 09:05:14 2025 Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2073.outbound.protection.outlook.com [40.107.237.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5E0F1244677; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Aug 2025 23:31:04.5190 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a67b312c-0a14-4c37-8393-08ddd4782571 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003F66.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8355 Content-Type: text/plain; charset="utf-8" Add the command line options to enable or disable the new resctrl feature L3 Smart Data Cache Injection Allocation Enforcement (SDCIAE). Signed-off-by: Babu Moger --- v8: Updated Documentation/filesystems/resctrl.rst. v7: No changes. v6: No changes. v5: No changes. v4: No changes. v3: No changes. v2: No changes. --- .../admin-guide/kernel-parameters.txt | 2 +- Documentation/filesystems/resctrl.rst | 21 ++++++++++--------- arch/x86/kernel/cpu/resctrl/core.c | 2 ++ 3 files changed, 14 insertions(+), 11 deletions(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentatio= n/admin-guide/kernel-parameters.txt index 0d2ea9a60145..0170c0af03cc 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -6089,7 +6089,7 @@ rdt=3D [HW,X86,RDT] Turn on/off individual RDT features. List is: cmt, mbmtotal, mbmlocal, l3cat, l3cdp, l2cat, l2cdp, - mba, smba, bmec. + mba, smba, bmec, sdciae. E.g. to turn on cmt and turn off mba use: rdt=3Dcmt,!mba =20 diff --git a/Documentation/filesystems/resctrl.rst b/Documentation/filesyst= ems/resctrl.rst index c7949dd44f2f..f08699030312 100644 --- a/Documentation/filesystems/resctrl.rst +++ b/Documentation/filesystems/resctrl.rst @@ -17,16 +17,17 @@ AMD refers to this feature as AMD Platform Quality of S= ervice(AMD QoS). This feature is enabled by the CONFIG_X86_CPU_RESCTRL and the x86 /proc/cp= uinfo flag bits: =20 -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D -RDT (Resource Director Technology) Allocation "rdt_a" -CAT (Cache Allocation Technology) "cat_l3", "cat_l2" -CDP (Code and Data Prioritization) "cdp_l3", "cdp_l2" -CQM (Cache QoS Monitoring) "cqm_llc", "cqm_occup_llc" -MBM (Memory Bandwidth Monitoring) "cqm_mbm_total", "cqm_mbm_local" -MBA (Memory Bandwidth Allocation) "mba" -SMBA (Slow Memory Bandwidth Allocation) "" -BMEC (Bandwidth Monitoring Event Configuration) "" -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +RDT (Resource Director Technology) Allocation "rdt_a" +CAT (Cache Allocation Technology) "cat_l3", "cat_l2" +CDP (Code and Data Prioritization) "cdp_l3", "cdp_l2" +CQM (Cache QoS Monitoring) "cqm_llc", "cqm_occup_llc" +MBM (Memory Bandwidth Monitoring) "cqm_mbm_total", "cqm_mbm_local" +MBA (Memory Bandwidth Allocation) "mba" +SMBA (Slow Memory Bandwidth Allocation) "" +BMEC (Bandwidth Monitoring Event Configuration) "" +SDCIAE (Smart Data Cache Injection Allocation Enforcement) "" +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 Historically, new features were made visible by default in /proc/cpuinfo. = This resulted in the feature flags becoming hard to parse by humans. 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Aug 2025 23:31:17.5850 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 864ec592-3ee0-456b-5966-08ddd4782d3b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003F63.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS2PR12MB9616 Content-Type: text/plain; charset="utf-8" Smart Data Cache Injection (SDCI) is a mechanism that enables direct insertion of data from I/O devices into the L3 cache. It can reduce the demands on DRAM bandwidth and reduces latency to the processor consuming the I/O data. Introduce cache resource property "io_alloc_capable" that an architecture can set if a portion of the cache can be allocated for I/O traffic. Set this property on x86 systems that support SDCIAE (L3 Smart Data Cache Injection Allocation Enforcement). This property is set only for the L3 cache resource on systems that support SDCIAE. Signed-off-by: Babu Moger Reviewed-by: Reinette Chatre --- v8: Added Reviewed-by tag. v7: Few text updates in changelog and resctrl.h. v6: No changes. v5: No changes. v4: Updated the commit message and code comment based on feedback. v3: Rewrote commit log. Changed the text to bit generic than the AMD specif= ic. Renamed the rdt_get_sdciae_alloc_cfg() to rdt_set_io_alloc_capable(). Removed leftover comment from v2. v2: Changed sdciae_capable to io_alloc_capable to make it generic feature. Also moved the io_alloc_capable in struct resctrl_cache. --- arch/x86/kernel/cpu/resctrl/core.c | 7 +++++++ include/linux/resctrl.h | 3 +++ 2 files changed, 10 insertions(+) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index f6d84882cc4e..1d1002526745 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -274,6 +274,11 @@ static void rdt_get_cdp_config(int level) rdt_resources_all[level].r_resctrl.cdp_capable =3D true; } =20 +static void rdt_set_io_alloc_capable(struct rdt_resource *r) +{ + r->cache.io_alloc_capable =3D true; +} + static void rdt_get_cdp_l3_config(void) { rdt_get_cdp_config(RDT_RESOURCE_L3); @@ -842,6 +847,8 @@ static __init bool get_rdt_alloc_resources(void) rdt_get_cache_alloc_cfg(1, r); if (rdt_cpu_has(X86_FEATURE_CDP_L3)) rdt_get_cdp_l3_config(); + if (rdt_cpu_has(X86_FEATURE_SDCIAE)) + rdt_set_io_alloc_capable(r); ret =3D true; } if (rdt_cpu_has(X86_FEATURE_CAT_L2)) { diff --git a/include/linux/resctrl.h b/include/linux/resctrl.h index 6fb4894b8cfd..010f238843b2 100644 --- a/include/linux/resctrl.h +++ b/include/linux/resctrl.h @@ -191,6 +191,8 @@ struct rdt_mon_domain { * @arch_has_sparse_bitmasks: True if a bitmask like f00f is valid. * @arch_has_per_cpu_cfg: True if QOS_CFG register for this cache * level has CPU scope. + * @io_alloc_capable: True if portion of the cache can be configured + * for I/O traffic. */ struct resctrl_cache { unsigned int cbm_len; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Aug 2025 23:31:31.5027 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cdecda39-9c37-45d2-dc28-08ddd4783586 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003F64.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7263 Content-Type: text/plain; charset="utf-8" "io_alloc" enables direct insertion of data from I/O devices into the cache. On AMD systems, "io_alloc" feature is backed by L3 Smart Data Cache Injection Allocation Enforcement (SDCIAE). Change SDCIAE state by setting (to enable) or clearing (to disable) bit 1 of MSR L3_QOS_EXT_CFG on all logical processors within the cache domain. Introduce architecture-specific call to enable and disable the feature. The SDCIAE feature details are available in APM listed below [1]. [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming Publication # 24593 Revision 3.41 section 19.4.7 L3 Smart Data Cache Injection Allocation Enforcement (SDCIAE) Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537 Signed-off-by: Babu Moger --- v8: Moved resctrl_arch_io_alloc_enable() and its dependancies to arch/x86/kernel/cpu/resctrl/ctrlmondata.c file. v7: Removed the inline for resctrl_arch_get_io_alloc_enabled(). Update code comment in resctrl.h. Changed the subject to x86,fs/resctrl. v6: Added lockdep_assert_cpus_held() in _resctrl_sdciae_enable() to protect r->ctrl_domains. Added more comments in include/linux/resctrl.h. v5: Resolved conflicts due to recent resctrl FS/ARCH code restructure. The files monitor.c/rdtgroup.c have been split between FS and ARCH dire= ctories. Moved prototypes of resctrl_arch_io_alloc_enable() and resctrl_arch_get_io_alloc_enabled() to include/linux/resctrl.h. v4: Updated the commit log to address the feedback. v3: Passed the struct rdt_resource to resctrl_arch_get_io_alloc_enabled() i= nstead of resource id. Renamed the _resctrl_io_alloc_enable() to _resctrl_sdciae_enable() as i= t is arch specific. Changed the return to void in _resctrl_sdciae_enable() instead of int. Added more context in commit log and fixed few typos. v2: Renamed the functions to simplify the code. Renamed sdciae_capable to io_alloc_capable. Changed the name of few arch functions similar to ABMC series. resctrl_arch_get_io_alloc_enabled() resctrl_arch_io_alloc_enable() --- arch/x86/include/asm/msr-index.h | 1 + arch/x86/kernel/cpu/resctrl/ctrlmondata.c | 40 +++++++++++++++++++++++ arch/x86/kernel/cpu/resctrl/internal.h | 5 +++ include/linux/resctrl.h | 21 ++++++++++++ 4 files changed, 67 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-in= dex.h index 7490bb5c0776..c998cf0e1375 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -1222,6 +1222,7 @@ /* - AMD: */ #define MSR_IA32_MBA_BW_BASE 0xc0000200 #define MSR_IA32_SMBA_BW_BASE 0xc0000280 +#define MSR_IA32_L3_QOS_EXT_CFG 0xc00003ff #define MSR_IA32_EVT_CFG_BASE 0xc0000400 =20 /* AMD-V MSRs */ diff --git a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c b/arch/x86/kernel/cp= u/resctrl/ctrlmondata.c index 1189c0df4ad7..85b6bd6bfb81 100644 --- a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c +++ b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c @@ -91,3 +91,43 @@ u32 resctrl_arch_get_config(struct rdt_resource *r, stru= ct rdt_ctrl_domain *d, =20 return hw_dom->ctrl_val[idx]; } + +bool resctrl_arch_get_io_alloc_enabled(struct rdt_resource *r) +{ + return resctrl_to_arch_res(r)->sdciae_enabled; +} + +static void resctrl_sdciae_set_one_amd(void *arg) +{ + bool *enable =3D arg; + + if (*enable) + msr_set_bit(MSR_IA32_L3_QOS_EXT_CFG, SDCIAE_ENABLE_BIT); + else + msr_clear_bit(MSR_IA32_L3_QOS_EXT_CFG, SDCIAE_ENABLE_BIT); +} + +static void _resctrl_sdciae_enable(struct rdt_resource *r, bool enable) +{ + struct rdt_ctrl_domain *d; + + /* Walking r->ctrl_domains, ensure it can't race with cpuhp */ + lockdep_assert_cpus_held(); + + /* Update L3_QOS_EXT_CFG MSR on all the CPUs in all domains */ + list_for_each_entry(d, &r->ctrl_domains, hdr.list) + on_each_cpu_mask(&d->hdr.cpu_mask, resctrl_sdciae_set_one_amd, &enable, = 1); +} + +int resctrl_arch_io_alloc_enable(struct rdt_resource *r, bool enable) +{ + struct rdt_hw_resource *hw_res =3D resctrl_to_arch_res(r); + + if (hw_res->r_resctrl.cache.io_alloc_capable && + hw_res->sdciae_enabled !=3D enable) { + _resctrl_sdciae_enable(r, enable); + hw_res->sdciae_enabled =3D enable; + } + + return 0; +} diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index 5e3c41b36437..70f5317f1ce4 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -37,6 +37,9 @@ struct arch_mbm_state { u64 prev_msr; }; =20 +/* Setting bit 1 in L3_QOS_EXT_CFG enables the SDCIAE feature. */ +#define SDCIAE_ENABLE_BIT 1 + /** * struct rdt_hw_ctrl_domain - Arch private attributes of a set of CPUs th= at share * a resource for a control function @@ -102,6 +105,7 @@ struct msr_param { * @mon_scale: cqm counter * mon_scale =3D occupancy in bytes * @mbm_width: Monitor width, to detect and correct for overflow. * @cdp_enabled: CDP state of this resource + * @sdciae_enabled: SDCIAE feature (backing "io_alloc") is enabled. * * Members of this structure are either private to the architecture * e.g. mbm_width, or accessed via helpers that provide abstraction. e.g. @@ -115,6 +119,7 @@ struct rdt_hw_resource { unsigned int mon_scale; unsigned int mbm_width; bool cdp_enabled; + bool sdciae_enabled; }; =20 static inline struct rdt_hw_resource *resctrl_to_arch_res(struct rdt_resou= rce *r) diff --git a/include/linux/resctrl.h b/include/linux/resctrl.h index 010f238843b2..d98933ce77af 100644 --- a/include/linux/resctrl.h +++ b/include/linux/resctrl.h @@ -531,6 +531,27 @@ void resctrl_arch_reset_rmid_all(struct rdt_resource *= r, struct rdt_mon_domain * */ void resctrl_arch_reset_all_ctrls(struct rdt_resource *r); =20 +/** + * resctrl_arch_io_alloc_enable() - Enable/disable io_alloc feature. + * @r: The resctrl resource. + * @enable: Enable (true) or disable (false) io_alloc on resource @r. + * + * This can be called from any CPU. + * + * Return: + * 0 on success, <0 on error. + */ +int resctrl_arch_io_alloc_enable(struct rdt_resource *r, bool enable); + +/** + * resctrl_arch_get_io_alloc_enabled() - Get io_alloc feature state. + * @r: The resctrl resource. + * + * Return: + * true if io_alloc is enabled or false if disabled. + */ +bool resctrl_arch_get_io_alloc_enabled(struct rdt_resource *r); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Aug 2025 23:31:40.2517 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c24bf093-c7fd-4f43-db7b-08ddd4783abd X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003F63.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9456 Content-Type: text/plain; charset="utf-8" "io_alloc" feature in resctrl allows direct insertion of data from I/O devices into the cache. Introduce the 'io_alloc' resctrl file to indicate the support for the feature. Signed-off-by: Babu Moger --- v8: Updated Documentation/filesystems/resctrl.rst. Moved resctrl_io_alloc_show() to fs/resctrl/ctrlmondata.c. Added prototype for rdt_kn_parent_priv() in fs/resctrl/internal.h so, it can be uses in other fs/resctrl/ files. Added comment for io_alloc_init(). v7: Updated the changelog. Updated user doc for io_alloc in resctrl.rst. Added mutex rdtgroup_mutex in resctrl_io_alloc_show(); v6: Added "io_alloc_cbm" details in user doc resctrl.rst. Resource name is not printed in CBM now. Corrected the texts about it in resctrl.rst. v5: Resolved conflicts due to recent resctrl FS/ARCH code restructure. Updated show_doms() to print the resource if only it is valid. Pass NUL= L while printing io_alloc CBM. Changed the code to access the CBMs via either L3CODE or L3DATA resourc= es. v4: Updated the change log. Added rdtgroup_mutex before rdt_last_cmd_puts(). Returned -ENODEV when resource type is CDP_DATA. Kept the resource name while printing the CBM (L3:0=3Dfff) that way I dont have to change show_doms() just for this feature and it is consistant across all the schemata display. v3: Minor changes due to changes in resctrl_arch_get_io_alloc_enabled() and resctrl_io_alloc_closid_get(). Added the check to verify CDP resource type. Updated the commit log. v2: Fixed to display only on L3 resources. Added the locks while processing. Rename the displat to io_alloc_cbm (from sdciae_cmd). --- Documentation/filesystems/resctrl.rst | 29 +++++++++++++++++++++++++++ fs/resctrl/ctrlmondata.c | 21 +++++++++++++++++++ fs/resctrl/internal.h | 5 +++++ fs/resctrl/rdtgroup.c | 24 +++++++++++++++++++++- 4 files changed, 78 insertions(+), 1 deletion(-) diff --git a/Documentation/filesystems/resctrl.rst b/Documentation/filesyst= ems/resctrl.rst index f08699030312..fff7e04d1e2a 100644 --- a/Documentation/filesystems/resctrl.rst +++ b/Documentation/filesystems/resctrl.rst @@ -136,6 +136,35 @@ related to allocation: "1": Non-contiguous 1s value in CBM is supported. =20 +"io_alloc": + "io_alloc" enables system software to configure the portion of + the cache allocated for I/O traffic. File may only exist if the + system supports this feature on some of its cache resources. + + "disabled": + Portions of cache used for allocation of I/O traffic + cannot be configured. + "enabled": + Portions of cache used for allocation of I/O traffic + can be configured using "io_alloc_cbm". + "not supported": + Support not available for this resource. + + The underlying implementation may reduce resources available to + general (CPU) cache allocation. See architecture specific notes + below. Depending on usage requirements the feature can be enabled + or disabled. + + On AMD systems, the io_alloc feature is supported by the L3 Smart + Data Cache Injection Allocation Enforcement (SDCIAE). The CLOSID for + io_alloc is the highest CLOSID supported by the resource. When + io_alloc is enabled, the highest CLOSID is dedicated to io_alloc and + no longer available for general (CPU) cache allocation. When CDP is + enabled, io_alloc routes I/O traffic using the highest CLOSID allocated + for the instruction cache (L3CODE), making this CLOSID no longer + available for general (CPU) cache allocation for both the L3CODE and + L3DATA resources. + Memory bandwidth(MB) subdirectory contains the following files with respect to allocation: =20 diff --git a/fs/resctrl/ctrlmondata.c b/fs/resctrl/ctrlmondata.c index d98e0d2de09f..d495a5d5c9d5 100644 --- a/fs/resctrl/ctrlmondata.c +++ b/fs/resctrl/ctrlmondata.c @@ -664,3 +664,24 @@ int rdtgroup_mondata_show(struct seq_file *m, void *ar= g) rdtgroup_kn_unlock(of->kn); return ret; } + +int resctrl_io_alloc_show(struct kernfs_open_file *of, struct seq_file *se= q, void *v) +{ + struct resctrl_schema *s =3D rdt_kn_parent_priv(of->kn); + struct rdt_resource *r =3D s->res; + + mutex_lock(&rdtgroup_mutex); + + if (r->cache.io_alloc_capable) { + if (resctrl_arch_get_io_alloc_enabled(r)) + seq_puts(seq, "enabled\n"); + else + seq_puts(seq, "disabled\n"); + } else { + seq_puts(seq, "not supported\n"); + } + + mutex_unlock(&rdtgroup_mutex); + + return 0; +} diff --git a/fs/resctrl/internal.h b/fs/resctrl/internal.h index 0a1eedba2b03..1a4543c2b988 100644 --- a/fs/resctrl/internal.h +++ b/fs/resctrl/internal.h @@ -375,6 +375,11 @@ bool closid_allocated(unsigned int closid); =20 int resctrl_find_cleanest_closid(void); =20 +int resctrl_io_alloc_show(struct kernfs_open_file *of, struct seq_file *se= q, + void *v); + +void *rdt_kn_parent_priv(struct kernfs_node *kn); + #ifdef CONFIG_RESCTRL_FS_PSEUDO_LOCK int rdtgroup_locksetup_enter(struct rdtgroup *rdtgrp); =20 diff --git a/fs/resctrl/rdtgroup.c b/fs/resctrl/rdtgroup.c index 77d08229d855..acc9edc1a268 100644 --- a/fs/resctrl/rdtgroup.c +++ b/fs/resctrl/rdtgroup.c @@ -981,7 +981,7 @@ static int rdt_last_cmd_status_show(struct kernfs_open_= file *of, return 0; } =20 -static void *rdt_kn_parent_priv(struct kernfs_node *kn) +void *rdt_kn_parent_priv(struct kernfs_node *kn) { /* * The parent pointer is only valid within RCU section since it can be @@ -1893,6 +1893,12 @@ static struct rftype res_common_files[] =3D { .kf_ops =3D &rdtgroup_kf_single_ops, .seq_show =3D rdt_thread_throttle_mode_show, }, + { + .name =3D "io_alloc", + .mode =3D 0444, + .kf_ops =3D &rdtgroup_kf_single_ops, + .seq_show =3D resctrl_io_alloc_show, + }, { .name =3D "max_threshold_occupancy", .mode =3D 0644, @@ -2062,6 +2068,20 @@ static void thread_throttle_mode_init(void) RFTYPE_CTRL_INFO | RFTYPE_RES_MB); } =20 +/* + * The resctrl file "io_alloc" is added using L3 resource. However, it res= ults + * in this file being visible for *all* cache resources (eg. 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Tue, 5 Aug 2025 23:31:49 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SA2PEPF00003F66.mail.protection.outlook.com (10.167.248.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.9009.8 via Frontend Transport; Tue, 5 Aug 2025 23:31:49 +0000 Received: from bmoger-ubuntu.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 5 Aug 2025 18:31:46 -0500 From: Babu Moger To: , , , , , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v8 06/10] fs/resctrl: Add user interface to enable/disable io_alloc feature Date: Tue, 5 Aug 2025 18:30:26 -0500 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003F66:EE_|SA5PPFCB4F033D6:EE_ X-MS-Office365-Filtering-Correlation-Id: 1f92cb40-f780-4022-af93-08ddd4784009 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|36860700013|1800799024|7416014|13003099007; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Aug 2025 23:31:49.1370 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1f92cb40-f780-4022-af93-08ddd4784009 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003F66.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA5PPFCB4F033D6 Content-Type: text/plain; charset="utf-8" "io_alloc" feature in resctrl enables direct insertion of data from I/O devices into the cache. On AMD systems, when io_alloc is enabled, the highest CLOSID is reserved exclusively for I/O allocation traffic and is no longer available for general CPU cache allocation. Users are encouraged to enable it only when running workloads that can benefit from this functionality. Since CLOSIDs are managed by resctrl fs, it is least invasive to make the "io_alloc is supported by maximum supported CLOSID" part of the initial resctrl fs support for io_alloc. Take care not to expose this use of CLOSID for io_alloc to user space so that this is not required from other architectures that may support io_alloc differently in the future. Introduce user interface to enable/disable io_alloc feature. Signed-off-by: Babu Moger --- v8: Updated the changelog. Renamed resctrl_io_alloc_init_cat() to resctrl_io_alloc_init_cbm(). Moved resctrl_io_alloc_write() and all its dependancies to fs/resctrl/c= trlmondata.c. Added prototypes for all the functions in fs/resctrl/internal.h. v7: Separated resctrl_io_alloc_show and bit_usage changes in two separate patches. Added resctrl_io_alloc_closid_supported() to verify io_alloc CLOSID. Initialized the schema for both CDP_DATA and CDP_CODE when CDP is enabl= ed. v6: Changed the subject to fs/resctrl: v5: Resolved conflicts due to recent resctrl FS/ARCH code restructure. Used rdt_kn_name to get the rdtgroup name instead of accesssing it dire= ctly while printing group name used by the io_alloc_closid. Updated bit_usage to reflect the io_alloc CBM as discussed in the threa= d: https://lore.kernel.org/lkml/3ca0a5dc-ad9c-4767-9011-b79d986e1e8d@intel= .com/ Modified rdt_bit_usage_show() to read io_alloc_cbm in hw_shareable, ens= uring that bit_usage accurately represents the CBMs. Updated the code to modify io_alloc either with L3CODE or L3DATA. https://lore.kernel.org/lkml/c00c00ea-a9ac-4c56-961c-dc5bf633476b@intel= .com/ v4: Updated the change log. Updated the user doc. The "io_alloc" interface will report "enabled/disabled/not supported". Updated resctrl_io_alloc_closid_get() to verify the max closid availabi= lity. Updated the documentation for "shareable_bits" and "bit_usage". Introduced io_alloc_init() to initialize fflags. Printed the group name when io_alloc enablement fails. NOTE: io_alloc is about specific CLOS. rdt_bit_usage_show() is not desi= gned handle bit_usage for specific CLOS. Its about overall system. So, we ca= nnot really tell the user which CLOS is shared across both hardware and soft= ware. We need to discuss this. v3: Rewrote the change to make it generic. Rewrote the documentation in resctrl.rst to be generic and added AMD feature details in the end. Added the check to verify if MAX CLOSID availability on the system. Added CDP check to make sure io_alloc is configured in CDP_CODE. Added resctrl_io_alloc_closid_free() to free the io_alloc CLOSID. Added errors in few cases when CLOSID allocation fails. Fixes splat reported when info/L3/bit_usage is accesed when io_alloc is enabled. https://lore.kernel.org/lkml/SJ1PR11MB60837B532254E7B23BC27E84FC052@SJ1= PR11MB6083.namprd11.prod.outlook.com/ v2: Renamed the feature to "io_alloc". Added generic texts for the feature in commit log and resctrl.rst doc. Added resctrl_io_alloc_init_cat() to initialize io_alloc to default values when enabled. Fixed io_alloc show functinality to display only on L3 resource. --- Documentation/filesystems/resctrl.rst | 8 ++ fs/resctrl/ctrlmondata.c | 137 ++++++++++++++++++++++++++ fs/resctrl/internal.h | 11 +++ fs/resctrl/rdtgroup.c | 24 ++++- 4 files changed, 177 insertions(+), 3 deletions(-) diff --git a/Documentation/filesystems/resctrl.rst b/Documentation/filesyst= ems/resctrl.rst index fff7e04d1e2a..bd0a633afbb9 100644 --- a/Documentation/filesystems/resctrl.rst +++ b/Documentation/filesystems/resctrl.rst @@ -150,6 +150,14 @@ related to allocation: "not supported": Support not available for this resource. =20 + The feature can be modified by writing to the interface, for example: + + To enable: + # echo 1 > /sys/fs/resctrl/info/L3/io_alloc + + To disable: + # echo 0 > /sys/fs/resctrl/info/L3/io_alloc + The underlying implementation may reduce resources available to general (CPU) cache allocation. See architecture specific notes below. Depending on usage requirements the feature can be enabled diff --git a/fs/resctrl/ctrlmondata.c b/fs/resctrl/ctrlmondata.c index d495a5d5c9d5..bf982eab7b18 100644 --- a/fs/resctrl/ctrlmondata.c +++ b/fs/resctrl/ctrlmondata.c @@ -685,3 +685,140 @@ int resctrl_io_alloc_show(struct kernfs_open_file *of= , struct seq_file *seq, voi =20 return 0; } + +/* + * resctrl_io_alloc_closid_supported() - io_alloc feature utilizes the + * highest CLOSID value to direct I/O traffic. Ensure that io_alloc_closid + * is in the supported range. + */ +static bool resctrl_io_alloc_closid_supported(u32 io_alloc_closid) +{ + return io_alloc_closid < closids_supported(); +} + +static struct resctrl_schema *resctrl_get_schema(enum resctrl_conf_type ty= pe) +{ + struct resctrl_schema *schema; + + list_for_each_entry(schema, &resctrl_schema_all, list) { + if (schema->conf_type =3D=3D type) + return schema; + } + + return NULL; +} + +/* + * Initialize io_alloc CLOSID cache resource CBM with all usable (shared + * and unused) cache portions. + */ +static int resctrl_io_alloc_init_cbm(struct resctrl_schema *s, u32 closid) +{ + struct rdt_resource *r =3D s->res; + enum resctrl_conf_type peer_type; + struct resctrl_schema *peer_s; + int ret; + + rdt_staged_configs_clear(); + + ret =3D rdtgroup_init_cat(s, closid); + if (ret < 0) + goto out; + + /* Initialize schema for both CDP_DATA and CDP_CODE when CDP is enabled */ + if (resctrl_arch_get_cdp_enabled(r->rid)) { + peer_type =3D resctrl_peer_type(s->conf_type); + peer_s =3D resctrl_get_schema(peer_type); + if (peer_s) { + ret =3D rdtgroup_init_cat(peer_s, closid); + if (ret < 0) + goto out; + } + } + + ret =3D resctrl_arch_update_domains(r, closid); + +out: + rdt_staged_configs_clear(); + return ret; +} + +/* + * resctrl_io_alloc_closid() - io_alloc feature routes I/O traffic using + * the highest available CLOSID. Retrieve the maximum CLOSID supported by = the + * resource. Note that if Code Data Prioritization (CDP) is enabled, the n= umber + * of available CLOSIDs is reduced by half. + */ +static u32 resctrl_io_alloc_closid(struct rdt_resource *r) +{ + if (resctrl_arch_get_cdp_enabled(r->rid)) + return resctrl_arch_get_num_closid(r) / 2 - 1; + else + return resctrl_arch_get_num_closid(r) - 1; +} + +ssize_t resctrl_io_alloc_write(struct kernfs_open_file *of, char *buf, + size_t nbytes, loff_t off) +{ + struct resctrl_schema *s =3D rdt_kn_parent_priv(of->kn); + struct rdt_resource *r =3D s->res; + char const *grp_name; + u32 io_alloc_closid; + bool enable; + int ret; + + ret =3D kstrtobool(buf, &enable); + if (ret) + return ret; + + cpus_read_lock(); + mutex_lock(&rdtgroup_mutex); + + rdt_last_cmd_clear(); + + if (!r->cache.io_alloc_capable) { + rdt_last_cmd_printf("io_alloc is not supported on %s\n", s->name); + ret =3D -ENODEV; + goto out_unlock; + } + + io_alloc_closid =3D resctrl_io_alloc_closid(r); + if (!resctrl_io_alloc_closid_supported(io_alloc_closid)) { + rdt_last_cmd_printf("io_alloc CLOSID (ctrl_hw_id) %d is not available\n", + io_alloc_closid); + ret =3D -EINVAL; + goto out_unlock; + } + + /* If the feature is already up to date, no action is needed. */ + if (resctrl_arch_get_io_alloc_enabled(r) =3D=3D enable) + goto out_unlock; + + if (enable) { + if (!closid_alloc_fixed(io_alloc_closid)) { + grp_name =3D rdtgroup_name_by_closid(io_alloc_closid); + WARN_ON_ONCE(!grp_name); + rdt_last_cmd_printf("CLOSID (ctrl_hw_id) %d for io_alloc is used by %s = group\n", + io_alloc_closid, grp_name ? grp_name : "another"); + ret =3D -ENOSPC; + goto out_unlock; + } + + ret =3D resctrl_io_alloc_init_cbm(s, io_alloc_closid); + if (ret) { + rdt_last_cmd_puts("Failed to initialize io_alloc allocations\n"); + closid_free(io_alloc_closid); + goto out_unlock; + } + } else { + closid_free(io_alloc_closid); + } + + ret =3D resctrl_arch_io_alloc_enable(r, enable); + +out_unlock: + mutex_unlock(&rdtgroup_mutex); + cpus_read_unlock(); + + return ret ?: nbytes; +} diff --git a/fs/resctrl/internal.h b/fs/resctrl/internal.h index 1a4543c2b988..335def7af1f6 100644 --- a/fs/resctrl/internal.h +++ b/fs/resctrl/internal.h @@ -373,6 +373,8 @@ void rdt_staged_configs_clear(void); =20 bool closid_allocated(unsigned int closid); =20 +bool closid_alloc_fixed(u32 closid); + int resctrl_find_cleanest_closid(void); =20 int resctrl_io_alloc_show(struct kernfs_open_file *of, struct seq_file *se= q, @@ -380,6 +382,15 @@ int resctrl_io_alloc_show(struct kernfs_open_file *of,= struct seq_file *seq, =20 void *rdt_kn_parent_priv(struct kernfs_node *kn); =20 +int rdtgroup_init_cat(struct resctrl_schema *s, u32 closid); + +enum resctrl_conf_type resctrl_peer_type(enum resctrl_conf_type my_type); + +ssize_t resctrl_io_alloc_write(struct kernfs_open_file *of, char *buf, + size_t nbytes, loff_t off); + +const char *rdtgroup_name_by_closid(int closid); + #ifdef CONFIG_RESCTRL_FS_PSEUDO_LOCK int rdtgroup_locksetup_enter(struct rdtgroup *rdtgrp); =20 diff --git a/fs/resctrl/rdtgroup.c b/fs/resctrl/rdtgroup.c index acc9edc1a268..380ebc86c748 100644 --- a/fs/resctrl/rdtgroup.c +++ b/fs/resctrl/rdtgroup.c @@ -232,6 +232,11 @@ bool closid_allocated(unsigned int closid) return !test_bit(closid, closid_free_map); } =20 +bool closid_alloc_fixed(u32 closid) +{ + return __test_and_clear_bit(closid, closid_free_map); +} + /** * rdtgroup_mode_by_closid - Return mode of resource group with closid * @closid: closid if the resource group @@ -1250,7 +1255,7 @@ static int rdtgroup_mode_show(struct kernfs_open_file= *of, return 0; } =20 -static enum resctrl_conf_type resctrl_peer_type(enum resctrl_conf_type my_= type) +enum resctrl_conf_type resctrl_peer_type(enum resctrl_conf_type my_type) { switch (my_type) { case CDP_CODE: @@ -1803,6 +1808,18 @@ static ssize_t mbm_local_bytes_config_write(struct k= ernfs_open_file *of, return ret ?: nbytes; } =20 +const char *rdtgroup_name_by_closid(int closid) +{ + struct rdtgroup *rdtgrp; + + list_for_each_entry(rdtgrp, &rdt_all_groups, rdtgroup_list) { + if (rdtgrp->closid =3D=3D closid) + return rdt_kn_name(rdtgrp->kn); + } + + return NULL; +} + /* rdtgroup information files for one cache resource. */ static struct rftype res_common_files[] =3D { { @@ -1895,9 +1912,10 @@ static struct rftype res_common_files[] =3D { }, { .name =3D "io_alloc", - .mode =3D 0444, + .mode =3D 0644, .kf_ops =3D &rdtgroup_kf_single_ops, .seq_show =3D resctrl_io_alloc_show, + .write =3D resctrl_io_alloc_write, }, { .name =3D "max_threshold_occupancy", @@ -3365,7 +3383,7 @@ static int __init_one_rdt_domain(struct rdt_ctrl_doma= in *d, struct resctrl_schem * If there are no more shareable bits available on any domain then * the entire allocation will fail. */ -static int rdtgroup_init_cat(struct resctrl_schema *s, u32 closid) +int rdtgroup_init_cat(struct resctrl_schema *s, u32 closid) { struct rdt_ctrl_domain *d; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Aug 2025 23:31:58.7042 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 54b04f52-f049-4a82-c301-08ddd47845be X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003F66.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5727 Content-Type: text/plain; charset="utf-8" The io_alloc feature in resctrl enables system software to configure the portion of the cache allocated for I/O traffic. Add "io_alloc_cbm" resctrl file to display CBMs (Capacity Bit Mask) of io_alloc feature. The CBM interface file io_alloc_cbm resides in the info directory (e.g., /sys/fs/resctrl/info/L3/). Displaying the resource name is not necessary. Pass the resource name to show_doms() and print it only if the name is valid. For io_alloc, pass NULL to suppress printing the resource name. When CDP is enabled, io_alloc routes traffic using the highest CLOSID associated with the L3CODE resource. To ensure consistent cache allocation behavior, the L3CODE and L3DATA resources must remain synchronized. rdtgroup_init_cat() function takes both L3CODE and L3DATA into account when initializing CBMs for new groups. The io_alloc feature adheres to this same principle, meaning that the Cache Bit Masks (CBMs) accessed through either L3CODE or L3DATA will reflect identical values. Signed-off-by: Babu Moger --- v8: Updated the changelog. Moved resctrl_io_alloc_cbm_show() to fs/resctrl/ctrlmondata.c. show_doms is remains static with this change. v7: Updated changelog. Updated use doc (resctrl.rst). Removed if (io_alloc_closid < 0) check. Not required anymore. v6: Added "io_alloc_cbm" details in user doc resctrl.rst. Resource name is not printed in CBM now. Corrected the texts about it in resctrl.rst. v5: Resolved conflicts due to recent resctrl FS/ARCH code restructure. Updated show_doms() to print the resource if only it is valid. Pass NUL= L while printing io_alloc CBM. Changed the code to access the CBMs via either L3CODE or L3DATA resourc= es. v4: Updated the change log. Added rdtgroup_mutex before rdt_last_cmd_puts(). Returned -ENODEV when resource type is CDP_DATA. Kept the resource name while printing the CBM (L3:0=3Dfff) that way I dont have to change show_doms() just for this feature and it is consistant across all the schemata display. v3: Minor changes due to changes in resctrl_arch_get_io_alloc_enabled() and resctrl_io_alloc_closid_get(). Added the check to verify CDP resource type. Updated the commit log. v2: Fixed to display only on L3 resources. Added the locks while processing. Rename the displat to io_alloc_cbm (from sdciae_cmd). --- Documentation/filesystems/resctrl.rst | 19 +++++++++++++ fs/resctrl/ctrlmondata.c | 39 ++++++++++++++++++++++++--- fs/resctrl/internal.h | 3 +++ fs/resctrl/rdtgroup.c | 11 +++++++- 4 files changed, 68 insertions(+), 4 deletions(-) diff --git a/Documentation/filesystems/resctrl.rst b/Documentation/filesyst= ems/resctrl.rst index bd0a633afbb9..3002f7fdb2fe 100644 --- a/Documentation/filesystems/resctrl.rst +++ b/Documentation/filesystems/resctrl.rst @@ -173,6 +173,25 @@ related to allocation: available for general (CPU) cache allocation for both the L3CODE and L3DATA resources. =20 +"io_alloc_cbm": + CBMs(Capacity Bit Masks) that describe the portions of cache instances + to which I/O traffic from supported I/O devices are routed when "io_allo= c" + is enabled. + + CBMs are displayed in the following format: + + =3D;=3D;... + + Example:: + + # cat /sys/fs/resctrl/info/L3/io_alloc_cbm + 0=3Dffff;1=3Dffff + + When CDP is enabled "io_alloc_cbm" associated with the DATA and CODE + resources may reflect the same values. For example, values read from and + written to /sys/fs/resctrl/info/L3DATA/io_alloc_cbm may be reflected by + /sys/fs/resctrl/info/L3CODE/io_alloc_cbm and vice versa. + Memory bandwidth(MB) subdirectory contains the following files with respect to allocation: =20 diff --git a/fs/resctrl/ctrlmondata.c b/fs/resctrl/ctrlmondata.c index bf982eab7b18..edb9dd131eed 100644 --- a/fs/resctrl/ctrlmondata.c +++ b/fs/resctrl/ctrlmondata.c @@ -381,7 +381,8 @@ ssize_t rdtgroup_schemata_write(struct kernfs_open_file= *of, return ret ?: nbytes; } =20 -static void show_doms(struct seq_file *s, struct resctrl_schema *schema, i= nt closid) +static void show_doms(struct seq_file *s, struct resctrl_schema *schema, + char *resource_name, int closid) { struct rdt_resource *r =3D schema->res; struct rdt_ctrl_domain *dom; @@ -391,7 +392,8 @@ static void show_doms(struct seq_file *s, struct resctr= l_schema *schema, int clo /* Walking r->domains, ensure it can't race with cpuhp */ lockdep_assert_cpus_held(); =20 - seq_printf(s, "%*s:", max_name_width, schema->name); + if (resource_name) + seq_printf(s, "%*s:", max_name_width, resource_name); list_for_each_entry(dom, &r->ctrl_domains, hdr.list) { if (sep) seq_puts(s, ";"); @@ -437,7 +439,7 @@ int rdtgroup_schemata_show(struct kernfs_open_file *of, closid =3D rdtgrp->closid; list_for_each_entry(schema, &resctrl_schema_all, list) { if (closid < schema->num_closid) - show_doms(s, schema, closid); + show_doms(s, schema, schema->name, closid); } } } else { @@ -822,3 +824,34 @@ ssize_t resctrl_io_alloc_write(struct kernfs_open_file= *of, char *buf, =20 return ret ?: nbytes; } + +int resctrl_io_alloc_cbm_show(struct kernfs_open_file *of, struct seq_file= *seq, void *v) +{ + struct resctrl_schema *s =3D rdt_kn_parent_priv(of->kn); + struct rdt_resource *r =3D s->res; + int ret =3D 0; + + cpus_read_lock(); + mutex_lock(&rdtgroup_mutex); + + rdt_last_cmd_clear(); + + if (!r->cache.io_alloc_capable) { + rdt_last_cmd_printf("io_alloc is not supported on %s\n", s->name); + ret =3D -ENODEV; + goto out_unlock; + } + + if (!resctrl_arch_get_io_alloc_enabled(r)) { + rdt_last_cmd_printf("io_alloc is not enabled on %s\n", s->name); + ret =3D -EINVAL; + goto out_unlock; + } + + show_doms(seq, s, NULL, resctrl_io_alloc_closid(r)); + +out_unlock: + mutex_unlock(&rdtgroup_mutex); + cpus_read_unlock(); + return ret; +} diff --git a/fs/resctrl/internal.h b/fs/resctrl/internal.h index 335def7af1f6..49934cd3dc40 100644 --- a/fs/resctrl/internal.h +++ b/fs/resctrl/internal.h @@ -389,6 +389,9 @@ enum resctrl_conf_type resctrl_peer_type(enum resctrl_c= onf_type my_type); ssize_t resctrl_io_alloc_write(struct kernfs_open_file *of, char *buf, size_t nbytes, loff_t off); =20 +int resctrl_io_alloc_cbm_show(struct kernfs_open_file *of, struct seq_file= *seq, + void *v); + const char *rdtgroup_name_by_closid(int closid); =20 #ifdef CONFIG_RESCTRL_FS_PSEUDO_LOCK diff --git a/fs/resctrl/rdtgroup.c b/fs/resctrl/rdtgroup.c index 380ebc86c748..6af8ff6c8385 100644 --- a/fs/resctrl/rdtgroup.c +++ b/fs/resctrl/rdtgroup.c @@ -1917,6 +1917,12 @@ static struct rftype res_common_files[] =3D { .seq_show =3D resctrl_io_alloc_show, .write =3D resctrl_io_alloc_write, }, + { + .name =3D "io_alloc_cbm", + .mode =3D 0444, + .kf_ops =3D &rdtgroup_kf_single_ops, + .seq_show =3D resctrl_io_alloc_cbm_show, + }, { .name =3D "max_threshold_occupancy", .mode =3D 0644, @@ -2095,9 +2101,12 @@ static void io_alloc_init(void) { struct rdt_resource *r =3D resctrl_arch_get_resource(RDT_RESOURCE_L3); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Aug 2025 23:32:10.0738 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a8dca1b7-5fe1-41ae-a4f6-08ddd4784c85 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003F67.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4373 Content-Type: text/plain; charset="utf-8" parse_cbm() and parse_bw() require mode and CLOSID to validate the Capacity Bit Mask (CBM). It is passed via struct rdtgroup in struct rdt_parse_data. The io_alloc feature also uses CBMs to indicate which portions of cache are allocated for I/O traffic. The CBMs are provided by user space and need to be validated the same as CBMs provided for general (CPU) cache allocation. parse_cbm() cannot be used as-is since io_alloc does not have rdtgroup context. Pass the mode and CLOSID directly to parse_cbm() via struct rdt_parse_data instead of through the rdtgroup struct to facilitate calling parse_cbm() to verify the CBM of the io_alloc feature. Signed-off-by: Babu Moger --- v8: Rephrase of changelog. v7: Rephrase of changelog. v6: Changed the subject line to fs/resctrl. v5: Resolved conflicts due to recent resctrl FS/ARCH code restructure. v4: New patch to call parse_cbm() directly to avoid code duplication. --- fs/resctrl/ctrlmondata.c | 25 ++++++++++++++----------- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/fs/resctrl/ctrlmondata.c b/fs/resctrl/ctrlmondata.c index edb9dd131eed..641094aac322 100644 --- a/fs/resctrl/ctrlmondata.c +++ b/fs/resctrl/ctrlmondata.c @@ -24,7 +24,8 @@ #include "internal.h" =20 struct rdt_parse_data { - struct rdtgroup *rdtgrp; + u32 closid; + enum rdtgrp_mode mode; char *buf; }; =20 @@ -77,8 +78,8 @@ static int parse_bw(struct rdt_parse_data *data, struct r= esctrl_schema *s, struct rdt_ctrl_domain *d) { struct resctrl_staged_config *cfg; - u32 closid =3D data->rdtgrp->closid; struct rdt_resource *r =3D s->res; + u32 closid =3D data->closid; u32 bw_val; =20 cfg =3D &d->staged_config[s->conf_type]; @@ -156,9 +157,10 @@ static bool cbm_validate(char *buf, u32 *data, struct = rdt_resource *r) static int parse_cbm(struct rdt_parse_data *data, struct resctrl_schema *s, struct rdt_ctrl_domain *d) { - struct rdtgroup *rdtgrp =3D data->rdtgrp; + enum rdtgrp_mode mode =3D data->mode; struct resctrl_staged_config *cfg; struct rdt_resource *r =3D s->res; + u32 closid =3D data->closid; u32 cbm_val; =20 cfg =3D &d->staged_config[s->conf_type]; @@ -171,7 +173,7 @@ static int parse_cbm(struct rdt_parse_data *data, struc= t resctrl_schema *s, * Cannot set up more than one pseudo-locked region in a cache * hierarchy. */ - if (rdtgrp->mode =3D=3D RDT_MODE_PSEUDO_LOCKSETUP && + if (mode =3D=3D RDT_MODE_PSEUDO_LOCKSETUP && rdtgroup_pseudo_locked_in_hierarchy(d)) { rdt_last_cmd_puts("Pseudo-locked region in hierarchy\n"); return -EINVAL; @@ -180,8 +182,8 @@ static int parse_cbm(struct rdt_parse_data *data, struc= t resctrl_schema *s, if (!cbm_validate(data->buf, &cbm_val, r)) return -EINVAL; =20 - if ((rdtgrp->mode =3D=3D RDT_MODE_EXCLUSIVE || - rdtgrp->mode =3D=3D RDT_MODE_SHAREABLE) && + if ((mode =3D=3D RDT_MODE_EXCLUSIVE || + mode =3D=3D RDT_MODE_SHAREABLE) && rdtgroup_cbm_overlaps_pseudo_locked(d, cbm_val)) { rdt_last_cmd_puts("CBM overlaps with pseudo-locked region\n"); return -EINVAL; @@ -191,14 +193,14 @@ static int parse_cbm(struct rdt_parse_data *data, str= uct resctrl_schema *s, * The CBM may not overlap with the CBM of another closid if * either is exclusive. */ - if (rdtgroup_cbm_overlaps(s, d, cbm_val, rdtgrp->closid, true)) { + if (rdtgroup_cbm_overlaps(s, d, cbm_val, closid, true)) { rdt_last_cmd_puts("Overlaps with exclusive group\n"); return -EINVAL; } =20 - if (rdtgroup_cbm_overlaps(s, d, cbm_val, rdtgrp->closid, false)) { - if (rdtgrp->mode =3D=3D RDT_MODE_EXCLUSIVE || - rdtgrp->mode =3D=3D RDT_MODE_PSEUDO_LOCKSETUP) { + if (rdtgroup_cbm_overlaps(s, d, cbm_val, closid, false)) { + if (mode =3D=3D RDT_MODE_EXCLUSIVE || + mode =3D=3D RDT_MODE_PSEUDO_LOCKSETUP) { rdt_last_cmd_puts("Overlaps with other group\n"); return -EINVAL; } @@ -262,7 +264,8 @@ static int parse_line(char *line, struct resctrl_schema= *s, list_for_each_entry(d, &r->ctrl_domains, hdr.list) { if (d->hdr.id =3D=3D dom_id) { data.buf =3D dom; - data.rdtgrp =3D rdtgrp; + data.closid =3D rdtgrp->closid; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Aug 2025 23:32:21.0320 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 34e8fe9c-de45-43eb-c967-08ddd478530d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003F67.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4206 Content-Type: text/plain; charset="utf-8" "io_alloc" feature enables direct insertion of data from I/O devices into the cache. By directly caching data from I/O devices rather than first storing the I/O data in DRAM, it reduces the demands on DRAM bandwidth and reduces latency to the processor consuming the I/O data. When CDP is enabled, io_alloc routes traffic using the highest CLOSID associated with the L3CODE resource. To ensure consistent cache allocation behavior, the L3CODE and L3DATA resources must remain synchronized. rdtgroup_init_cat() function takes both L3CODE and L3DATA into account when initializing CBMs for new groups. The io_alloc feature must maintain the same behavior, ensuring that the Cache Bit Masks (CBMs) for both L3CODE and L3DATA are updated together. Enable users to modify io_alloc CBMs (Capacity Bit Masks) via the io_alloc_cbm resctrl file when io_alloc is enabled. Signed-off-by: Babu Moger --- v8: Updated changelog. Moved resctrl_io_alloc_parse_line() and resctrl_io_alloc_cbm_write() to fs/resctrl/ctrlmondata.c. Added resctrl_arch_get_cdp_enabled() check inside resctrl_io_alloc_pars= e_line(). Made parse_cbm() static again as everything moved to ctrlmondata.c. v7: Updated changelog. Updated CBMs for both CDP_DATA and CDP_CODE when CDP is enabled. v6: Updated the user doc restctr.doc for minor texts. Changed the subject to fs/resctrl. v5: Changes due to FS/ARCH code restructure. The files monitor.c/rdtgroup.c have been split between FS and ARCH directories. Changed the code to access the CBMs via either L3CODE or L3DATA resourc= es. v4: Removed resctrl_io_alloc_parse_cbm and called parse_cbm() directly. v3: Minor changes due to changes in resctrl_arch_get_io_alloc_enabled() and resctrl_io_alloc_closid_get(). Taken care of handling the CBM update when CDP is enabled. Updated the commit log to make it generic. v2: Added more generic text in documentation. --- Documentation/filesystems/resctrl.rst | 8 +++ fs/resctrl/ctrlmondata.c | 97 +++++++++++++++++++++++++++ fs/resctrl/internal.h | 3 + fs/resctrl/rdtgroup.c | 3 +- 4 files changed, 110 insertions(+), 1 deletion(-) diff --git a/Documentation/filesystems/resctrl.rst b/Documentation/filesyst= ems/resctrl.rst index 3002f7fdb2fe..d955e8525af0 100644 --- a/Documentation/filesystems/resctrl.rst +++ b/Documentation/filesystems/resctrl.rst @@ -187,6 +187,14 @@ related to allocation: # cat /sys/fs/resctrl/info/L3/io_alloc_cbm 0=3Dffff;1=3Dffff =20 + CBMs can be configured by writing to the interface. + + Example:: + + # echo 1=3DFF > /sys/fs/resctrl/info/L3/io_alloc_cbm + # cat /sys/fs/resctrl/info/L3/io_alloc_cbm + 0=3Dffff;1=3D00ff + When CDP is enabled "io_alloc_cbm" associated with the DATA and CODE resources may reflect the same values. For example, values read from and written to /sys/fs/resctrl/info/L3DATA/io_alloc_cbm may be reflected by diff --git a/fs/resctrl/ctrlmondata.c b/fs/resctrl/ctrlmondata.c index 641094aac322..1f69117f96f8 100644 --- a/fs/resctrl/ctrlmondata.c +++ b/fs/resctrl/ctrlmondata.c @@ -858,3 +858,100 @@ int resctrl_io_alloc_cbm_show(struct kernfs_open_file= *of, struct seq_file *seq, cpus_read_unlock(); return ret; } + +static int resctrl_io_alloc_parse_line(char *line, struct rdt_resource *r, + struct resctrl_schema *s, u32 closid) +{ + enum resctrl_conf_type peer_type; + struct resctrl_schema *peer_s; + struct rdt_parse_data data; + struct rdt_ctrl_domain *d; + char *dom =3D NULL, *id; + unsigned long dom_id; + +next: + if (!line || line[0] =3D=3D '\0') + return 0; + + dom =3D strsep(&line, ";"); + id =3D strsep(&dom, "=3D"); + if (!dom || kstrtoul(id, 10, &dom_id)) { + rdt_last_cmd_puts("Missing '=3D' or non-numeric domain\n"); + return -EINVAL; + } + + dom =3D strim(dom); + list_for_each_entry(d, &r->ctrl_domains, hdr.list) { + if (d->hdr.id =3D=3D dom_id) { + data.buf =3D dom; + data.mode =3D RDT_MODE_SHAREABLE; + data.closid =3D closid; + if (parse_cbm(&data, s, d)) + return -EINVAL; + /* + * When CDP is enabled, update the schema for both CDP_DATA + * and CDP_CODE. + */ + if (resctrl_arch_get_cdp_enabled(r->rid)) { + peer_type =3D resctrl_peer_type(s->conf_type); + peer_s =3D resctrl_get_schema(peer_type); + if (parse_cbm(&data, peer_s, d)) + return -EINVAL; + } + goto next; + } + } + + return -EINVAL; +} + +ssize_t resctrl_io_alloc_cbm_write(struct kernfs_open_file *of, char *buf, + size_t nbytes, loff_t off) +{ + struct resctrl_schema *s =3D rdt_kn_parent_priv(of->kn); + struct rdt_resource *r =3D s->res; + u32 io_alloc_closid; + int ret =3D 0; + + /* Valid input requires a trailing newline */ + if (nbytes =3D=3D 0 || buf[nbytes - 1] !=3D '\n') + return -EINVAL; + + buf[nbytes - 1] =3D '\0'; + + cpus_read_lock(); + mutex_lock(&rdtgroup_mutex); + + rdt_last_cmd_clear(); + + if (!r->cache.io_alloc_capable) { + rdt_last_cmd_printf("io_alloc is not supported on %s\n", s->name); + ret =3D -ENODEV; + goto out_unlock; + } + + rdt_last_cmd_clear(); + rdt_staged_configs_clear(); + + if (!resctrl_arch_get_io_alloc_enabled(r)) { + rdt_last_cmd_printf("io_alloc is not enabled on %s\n", s->name); + ret =3D -ENODEV; + goto out_unlock; + } + + io_alloc_closid =3D resctrl_io_alloc_closid(r); + + ret =3D resctrl_io_alloc_parse_line(buf, r, s, io_alloc_closid); + + if (ret) + goto out_unlock; + + ret =3D resctrl_arch_update_domains(r, io_alloc_closid); + +out_unlock: + rdt_staged_configs_clear(); + mutex_unlock(&rdtgroup_mutex); + cpus_read_unlock(); + + return ret ?: nbytes; +} diff --git a/fs/resctrl/internal.h b/fs/resctrl/internal.h index 49934cd3dc40..5467c3ad1b6d 100644 --- a/fs/resctrl/internal.h +++ b/fs/resctrl/internal.h @@ -392,6 +392,9 @@ ssize_t resctrl_io_alloc_write(struct kernfs_open_file = *of, char *buf, int resctrl_io_alloc_cbm_show(struct kernfs_open_file *of, struct seq_file= *seq, void *v); =20 +ssize_t resctrl_io_alloc_cbm_write(struct kernfs_open_file *of, char *buf, + size_t nbytes, loff_t off); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Aug 2025 23:32:45.4839 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c76d6c86-93bc-4838-b152-08ddd47861a0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003F64.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6411 Content-Type: text/plain; charset="utf-8" When the io_alloc feature is enabled, a portion of the cache can be configured for shared use between hardware and software. Update the bit_usage representation to reflect the io_alloc configuration. Signed-off-by: Babu Moger --- v8: Moved the patch to last after all the concepts are initialized. Updated user doc resctrl.rst. Simplified the CDT check in rdt_bit_usage_show() as CDP_DATA and CDP_C= ODE are in sync with io_alloc enabled. v7: New patch split from earlier patch #5. Added resctrl_io_alloc_closid() to return max COSID. --- Documentation/filesystems/resctrl.rst | 19 +++++++++++++------ fs/resctrl/ctrlmondata.c | 2 +- fs/resctrl/internal.h | 2 ++ fs/resctrl/rdtgroup.c | 18 ++++++++++++++++-- 4 files changed, 32 insertions(+), 9 deletions(-) diff --git a/Documentation/filesystems/resctrl.rst b/Documentation/filesyst= ems/resctrl.rst index d955e8525af0..1e46231b929c 100644 --- a/Documentation/filesystems/resctrl.rst +++ b/Documentation/filesystems/resctrl.rst @@ -90,12 +90,19 @@ related to allocation: must be set when writing a mask. =20 "shareable_bits": - Bitmask of shareable resource with other executing - entities (e.g. I/O). User can use this when - setting up exclusive cache partitions. Note that - some platforms support devices that have their - own settings for cache use which can over-ride - these bits. + Bitmask of shareable resource with other executing entities + (e.g. I/O). Applies to all instances of this resource. User + can use this when setting up exclusive cache partitions. + Note that some platforms support devices that have their + own settings for cache use which can over-ride these bits. + + When "io_alloc" is enabled, a portion of each cache instance can + be configured for shared use between hardware and software. + "bit_usage" should be used to see which portions of each cache + instance is configured for hardware use via "io_alloc" feature + because every cache instance can have its "io_alloc" bitmask + configured independently via io_alloc_cbm. + "bit_usage": Annotated capacity bitmasks showing how all instances of the resource are used. The legend is: diff --git a/fs/resctrl/ctrlmondata.c b/fs/resctrl/ctrlmondata.c index 1f69117f96f8..cfa766319189 100644 --- a/fs/resctrl/ctrlmondata.c +++ b/fs/resctrl/ctrlmondata.c @@ -754,7 +754,7 @@ static int resctrl_io_alloc_init_cbm(struct resctrl_sch= ema *s, u32 closid) * resource. Note that if Code Data Prioritization (CDP) is enabled, the n= umber * of available CLOSIDs is reduced by half. */ -static u32 resctrl_io_alloc_closid(struct rdt_resource *r) +u32 resctrl_io_alloc_closid(struct rdt_resource *r) { if (resctrl_arch_get_cdp_enabled(r->rid)) return resctrl_arch_get_num_closid(r) / 2 - 1; diff --git a/fs/resctrl/internal.h b/fs/resctrl/internal.h index 5467c3ad1b6d..98b87725508b 100644 --- a/fs/resctrl/internal.h +++ b/fs/resctrl/internal.h @@ -395,6 +395,8 @@ int resctrl_io_alloc_cbm_show(struct kernfs_open_file *= of, struct seq_file *seq, ssize_t resctrl_io_alloc_cbm_write(struct kernfs_open_file *of, char *buf, size_t nbytes, loff_t off); =20 +u32 resctrl_io_alloc_closid(struct rdt_resource *r); + const char *rdtgroup_name_by_closid(int closid); =20 #ifdef CONFIG_RESCTRL_FS_PSEUDO_LOCK diff --git a/fs/resctrl/rdtgroup.c b/fs/resctrl/rdtgroup.c index a3ab2851c6da..b85c2622c94b 100644 --- a/fs/resctrl/rdtgroup.c +++ b/fs/resctrl/rdtgroup.c @@ -1068,15 +1068,17 @@ static int rdt_bit_usage_show(struct kernfs_open_fi= le *of, =20 cpus_read_lock(); mutex_lock(&rdtgroup_mutex); - hw_shareable =3D r->cache.shareable_bits; list_for_each_entry(dom, &r->ctrl_domains, hdr.list) { if (sep) seq_putc(seq, ';'); + hw_shareable =3D r->cache.shareable_bits; sw_shareable =3D 0; exclusive =3D 0; seq_printf(seq, "%d=3D", dom->hdr.id); for (i =3D 0; i < closids_supported(); i++) { - if (!closid_allocated(i)) + if (!closid_allocated(i) || + (resctrl_arch_get_io_alloc_enabled(r) && + i =3D=3D resctrl_io_alloc_closid(r))) continue; ctrl_val =3D resctrl_arch_get_config(r, dom, i, s->conf_type); @@ -1104,6 +1106,18 @@ static int rdt_bit_usage_show(struct kernfs_open_fil= e *of, break; } } + + /* + * When the "io_alloc" feature is enabled, a portion of the + * cache is configured for shared use between hardware and software. + */ + if (resctrl_arch_get_io_alloc_enabled(r)) { + ctrl_val =3D resctrl_arch_get_config(r, dom, + resctrl_io_alloc_closid(r), + s->conf_type); + hw_shareable |=3D ctrl_val; + } + for (i =3D r->cache.cbm_len - 1; i >=3D 0; i--) { pseudo_locked =3D dom->plr ? dom->plr->cbm : 0; hwb =3D test_bit(i, &hw_shareable); --=20 2.34.1