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Fri, 01 Aug 2025 03:07:18 -0700 (PDT) Received: from mva-rohm ([2a10:a5c0:800d:dd00:8fdf:935a:2c85:d703]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-55b8898bcd5sm543013e87.31.2025.08.01.03.07.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Aug 2025 03:07:17 -0700 (PDT) Date: Fri, 1 Aug 2025 13:07:13 +0300 From: Matti Vaittinen To: Matti Vaittinen , Matti Vaittinen Cc: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , David Lechner , Nuno =?iso-8859-1?Q?S=E1?= , Andy Shevchenko , Liam Girdwood , Mark Brown , linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH 1/2] iio: adc: ad7476: Simplify chip type detection Message-ID: <0ed3a1e9346d84d20838e89a531e8d99f95bcb97.1754041258.git.mazziesaccount@gmail.com> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="dkf8v2MGdo4/7nKW" Content-Disposition: inline In-Reply-To: --dkf8v2MGdo4/7nKW Content-Disposition: inline Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The ad7476 driver uses a table of structures for defining the IC variant specific data. Table is indexed using enum values, which are picked by SPI ID. Having the table and an enum adds extra complexity. It is potentially unsafe if someone alters the enumeration values, or size of the IC data table. Simplify this by dropping the table and using individual structures for the IC specific data, and storing the IC specific structure's address directly in the SPI ID data. Signed-off-by: Matti Vaittinen Reviewed-by: Nuno S=C3=A1 --- 100% Untested. No functional changes intended --- drivers/iio/adc/ad7476.c | 292 +++++++++++++++++++-------------------- 1 file changed, 143 insertions(+), 149 deletions(-) diff --git a/drivers/iio/adc/ad7476.c b/drivers/iio/adc/ad7476.c index aea734aa06bd..bdfffc4f5724 100644 --- a/drivers/iio/adc/ad7476.c +++ b/drivers/iio/adc/ad7476.c @@ -52,29 +52,6 @@ struct ad7476_state { unsigned char data[ALIGN(2, sizeof(s64)) + sizeof(s64)] __aligned(IIO_DMA= _MINALIGN); }; =20 -enum ad7476_supported_device_ids { - ID_AD7091, - ID_AD7091R, - ID_AD7273, - ID_AD7274, - ID_AD7276, - ID_AD7277, - ID_AD7278, - ID_AD7466, - ID_AD7467, - ID_AD7468, - ID_AD7475, - ID_AD7495, - ID_AD7940, - ID_ADC081S, - ID_ADC101S, - ID_ADC121S, - ID_ADS7866, - ID_ADS7867, - ID_ADS7868, - ID_LTC2314_14, -}; - static void ad7091_convst(struct ad7476_state *st) { if (!st->convst_gpio) @@ -190,102 +167,119 @@ static int ad7476_read_raw(struct iio_dev *indio_de= v, #define ADS786X_CHAN(bits) _AD7476_CHAN((bits), 12 - (bits), \ BIT(IIO_CHAN_INFO_RAW)) =20 -static const struct ad7476_chip_info ad7476_chip_info_tbl[] =3D { - [ID_AD7091] =3D { - .channel[0] =3D AD7091R_CHAN(12), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - .convst_channel[0] =3D AD7091R_CONVST_CHAN(12), - .convst_channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - .reset =3D ad7091_reset, - }, - [ID_AD7091R] =3D { - .channel[0] =3D AD7091R_CHAN(12), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - .convst_channel[0] =3D AD7091R_CONVST_CHAN(12), - .convst_channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - .int_vref_uv =3D 2500000, - .has_vref =3D true, - .reset =3D ad7091_reset, - }, - [ID_AD7273] =3D { - .channel[0] =3D AD7940_CHAN(10), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - .has_vref =3D true, - }, - [ID_AD7274] =3D { - .channel[0] =3D AD7940_CHAN(12), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - .has_vref =3D true, - }, - [ID_AD7276] =3D { - .channel[0] =3D AD7940_CHAN(12), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - }, - [ID_AD7277] =3D { - .channel[0] =3D AD7940_CHAN(10), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - }, - [ID_AD7278] =3D { - .channel[0] =3D AD7940_CHAN(8), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - }, - [ID_AD7466] =3D { - .channel[0] =3D AD7476_CHAN(12), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - }, - [ID_AD7467] =3D { - .channel[0] =3D AD7476_CHAN(10), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - }, - [ID_AD7468] =3D { - .channel[0] =3D AD7476_CHAN(8), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - }, - [ID_AD7475] =3D { - .channel[0] =3D AD7476_CHAN(12), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - .has_vref =3D true, - .has_vdrive =3D true, - }, - [ID_AD7495] =3D { - .channel[0] =3D AD7476_CHAN(12), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - .int_vref_uv =3D 2500000, - .has_vdrive =3D true, - }, - [ID_AD7940] =3D { - .channel[0] =3D AD7940_CHAN(14), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - }, - [ID_ADC081S] =3D { - .channel[0] =3D ADC081S_CHAN(8), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - }, - [ID_ADC101S] =3D { - .channel[0] =3D ADC081S_CHAN(10), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - }, - [ID_ADC121S] =3D { - .channel[0] =3D ADC081S_CHAN(12), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - }, - [ID_ADS7866] =3D { - .channel[0] =3D ADS786X_CHAN(12), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - }, - [ID_ADS7867] =3D { - .channel[0] =3D ADS786X_CHAN(10), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - }, - [ID_ADS7868] =3D { - .channel[0] =3D ADS786X_CHAN(8), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - }, - [ID_LTC2314_14] =3D { - .channel[0] =3D AD7940_CHAN(14), - .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), - .has_vref =3D true, - }, +static const struct ad7476_chip_info ad7091_chip_info =3D { + .channel[0] =3D AD7091R_CHAN(12), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), + .convst_channel[0] =3D AD7091R_CONVST_CHAN(12), + .convst_channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), + .reset =3D ad7091_reset, +}; + +static const struct ad7476_chip_info ad7091r_chip_info =3D { + .channel[0] =3D AD7091R_CHAN(12), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), + .convst_channel[0] =3D AD7091R_CONVST_CHAN(12), + .convst_channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), + .int_vref_uv =3D 2500000, + .has_vref =3D true, + .reset =3D ad7091_reset, +}; + +static const struct ad7476_chip_info ad7273_chip_info =3D { + .channel[0] =3D AD7940_CHAN(10), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), + .has_vref =3D true, +}; + +static const struct ad7476_chip_info ad7274_chip_info =3D { + .channel[0] =3D AD7940_CHAN(12), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), + .has_vref =3D true, +}; + +static const struct ad7476_chip_info ad7276_chip_info =3D { + .channel[0] =3D AD7940_CHAN(12), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), +}; + +static const struct ad7476_chip_info ad7277_chip_info =3D { + .channel[0] =3D AD7940_CHAN(10), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), +}; + +static const struct ad7476_chip_info ad7278_chip_info =3D { + .channel[0] =3D AD7940_CHAN(8), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), +}; + +static const struct ad7476_chip_info ad7466_chip_info =3D { + .channel[0] =3D AD7476_CHAN(12), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), +}; + +static const struct ad7476_chip_info ad7467_chip_info =3D { + .channel[0] =3D AD7476_CHAN(10), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), +}; + +static const struct ad7476_chip_info ad7468_chip_info =3D { + .channel[0] =3D AD7476_CHAN(8), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), +}; + +static const struct ad7476_chip_info ad7475_chip_info =3D { + .channel[0] =3D AD7476_CHAN(12), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), + .has_vref =3D true, + .has_vdrive =3D true, +}; + +static const struct ad7476_chip_info ad7495_chip_info =3D { + .channel[0] =3D AD7476_CHAN(12), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), + .int_vref_uv =3D 2500000, + .has_vdrive =3D true, +}; + +static const struct ad7476_chip_info ad7940_chip_info =3D { + .channel[0] =3D AD7940_CHAN(14), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), +}; + +static const struct ad7476_chip_info adc081s_chip_info =3D { + .channel[0] =3D ADC081S_CHAN(8), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), +}; + +static const struct ad7476_chip_info adc101s_chip_info =3D { + .channel[0] =3D ADC081S_CHAN(10), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), +}; + +static const struct ad7476_chip_info adc121s_chip_info =3D { + .channel[0] =3D ADC081S_CHAN(12), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), +}; + +static const struct ad7476_chip_info ads7866_chip_info =3D { + .channel[0] =3D ADS786X_CHAN(12), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), +}; + +static const struct ad7476_chip_info ads7867_chip_info =3D { + .channel[0] =3D ADS786X_CHAN(10), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), +}; + +static const struct ad7476_chip_info ads7868_chip_info =3D { + .channel[0] =3D ADS786X_CHAN(8), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), +}; + +static const struct ad7476_chip_info ltc2314_14_chip_info =3D { + .channel[0] =3D AD7940_CHAN(14), + .channel[1] =3D IIO_CHAN_SOFT_TIMESTAMP(1), + .has_vref =3D true, }; =20 static const struct iio_info ad7476_info =3D { @@ -312,7 +306,7 @@ static int ad7476_probe(struct spi_device *spi) =20 st =3D iio_priv(indio_dev); st->chip_info =3D - &ad7476_chip_info_tbl[spi_get_device_id(spi)->driver_data]; + (struct ad7476_chip_info *)spi_get_device_id(spi)->driver_data; =20 reg =3D devm_regulator_get(&spi->dev, "vcc"); if (IS_ERR(reg)) @@ -408,41 +402,41 @@ static int ad7476_probe(struct spi_device *spi) } =20 static const struct spi_device_id ad7476_id[] =3D { - { "ad7091", ID_AD7091 }, - { "ad7091r", ID_AD7091R }, - { "ad7273", ID_AD7273 }, - { "ad7274", ID_AD7274 }, - { "ad7276", ID_AD7276}, - { "ad7277", ID_AD7277 }, - { "ad7278", ID_AD7278 }, - { "ad7466", ID_AD7466 }, - { "ad7467", ID_AD7467 }, - { "ad7468", ID_AD7468 }, - { "ad7475", ID_AD7475 }, - { "ad7476", ID_AD7466 }, - { "ad7476a", ID_AD7466 }, - { "ad7477", ID_AD7467 }, - { "ad7477a", ID_AD7467 }, - { "ad7478", ID_AD7468 }, - { "ad7478a", ID_AD7468 }, - { "ad7495", ID_AD7495 }, - { "ad7910", ID_AD7467 }, - { "ad7920", ID_AD7466 }, - { "ad7940", ID_AD7940 }, - { "adc081s", ID_ADC081S }, - { "adc101s", ID_ADC101S }, - { "adc121s", ID_ADC121S }, - { "ads7866", ID_ADS7866 }, - { "ads7867", ID_ADS7867 }, - { "ads7868", ID_ADS7868 }, + { "ad7091", (kernel_ulong_t)&ad7091_chip_info }, + { "ad7091r", (kernel_ulong_t)&ad7091r_chip_info }, + { "ad7273", (kernel_ulong_t)&ad7273_chip_info }, + { "ad7274", (kernel_ulong_t)&ad7274_chip_info }, + { "ad7276", (kernel_ulong_t)&ad7276_chip_info }, + { "ad7277", (kernel_ulong_t)&ad7277_chip_info }, + { "ad7278", (kernel_ulong_t)&ad7278_chip_info }, + { "ad7466", (kernel_ulong_t)&ad7466_chip_info }, + { "ad7467", (kernel_ulong_t)&ad7467_chip_info }, + { "ad7468", (kernel_ulong_t)&ad7468_chip_info }, + { "ad7475", (kernel_ulong_t)&ad7475_chip_info }, + { "ad7476", (kernel_ulong_t)&ad7466_chip_info }, + { "ad7476a", (kernel_ulong_t)&ad7466_chip_info }, + { "ad7477", (kernel_ulong_t)&ad7467_chip_info }, + { "ad7477a", (kernel_ulong_t)&ad7467_chip_info }, + { "ad7478", (kernel_ulong_t)&ad7468_chip_info }, + { "ad7478a", (kernel_ulong_t)&ad7468_chip_info }, + { "ad7495", (kernel_ulong_t)&ad7495_chip_info }, + { "ad7910", (kernel_ulong_t)&ad7467_chip_info }, + { "ad7920", (kernel_ulong_t)&ad7466_chip_info }, + { "ad7940", (kernel_ulong_t)&ad7940_chip_info }, + { "adc081s", (kernel_ulong_t)&adc081s_chip_info }, + { "adc101s", (kernel_ulong_t)&adc101s_chip_info }, + { "adc121s", (kernel_ulong_t)&adc121s_chip_info }, + { "ads7866", (kernel_ulong_t)&ads7866_chip_info }, + { "ads7867", (kernel_ulong_t)&ads7867_chip_info }, + { "ads7868", (kernel_ulong_t)&ads7868_chip_info }, /* * The ROHM BU79100G is identical to the TI's ADS7866 from the software * point of view. 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Fri, 01 Aug 2025 03:07:43 -0700 (PDT) Received: from mva-rohm ([2a10:a5c0:800d:dd00:8fdf:935a:2c85:d703]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-55b88ca3214sm538712e87.126.2025.08.01.03.07.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Aug 2025 03:07:42 -0700 (PDT) Date: Fri, 1 Aug 2025 13:07:39 +0300 From: Matti Vaittinen To: Matti Vaittinen , Matti Vaittinen Cc: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , David Lechner , Nuno =?iso-8859-1?Q?S=E1?= , Andy Shevchenko , Liam Girdwood , Mark Brown , linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH 2/2] iio: adc: ad7476: Simplify scale handling Message-ID: <1ce13bf8f5cfc5076e45f12c5e9499113f86df16.1754041258.git.mazziesaccount@gmail.com> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="QxQjTTFP1NoL/Kg6" Content-Disposition: inline In-Reply-To: --QxQjTTFP1NoL/Kg6 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The ad7476 driver supports variants with different amount of supply regulators. On some variants there is only VCC, which is used as a reference voltage. Others have separate VREF regulator, and some rely on internal VREF. Some have both internal VREF and option to connect external one. The ad7476 driver reads the regulator voltage only when the user asks to get the scale. This means the driver needs to do some dancing while picking the correct reference regulator (or internal reference), and store it for the later use. According to the discussion: https://lore.kernel.org/linux-iio/20250331122247.05c6b09d@jic23-huawei/ variable voltage references are rare, making it hard to justify the added complexity for supporting those. Drop the support for the variable voltage references and simplify things by using the managed regulator get and enable interfaces. Signed-off-by: Matti Vaittinen Reviewed-by: Nuno S=C3=A1 --- NOTE: This is 100% untested as I lack of the hardware. I have tried to maintain the existing logic, but there is always some room for an error. All testing and logic reviewing is greatly appreciated. --- drivers/iio/adc/ad7476.c | 84 ++++++++++------------------------------ 1 file changed, 21 insertions(+), 63 deletions(-) diff --git a/drivers/iio/adc/ad7476.c b/drivers/iio/adc/ad7476.c index bdfffc4f5724..7b1d6a0fd941 100644 --- a/drivers/iio/adc/ad7476.c +++ b/drivers/iio/adc/ad7476.c @@ -39,10 +39,10 @@ struct ad7476_chip_info { struct ad7476_state { struct spi_device *spi; const struct ad7476_chip_info *chip_info; - struct regulator *ref_reg; struct gpio_desc *convst_gpio; struct spi_transfer xfer; struct spi_message msg; + int scale_mv; /* * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. @@ -111,7 +111,6 @@ static int ad7476_read_raw(struct iio_dev *indio_dev, { int ret; struct ad7476_state *st =3D iio_priv(indio_dev); - int scale_uv; =20 switch (m) { case IIO_CHAN_INFO_RAW: @@ -126,14 +125,7 @@ static int ad7476_read_raw(struct iio_dev *indio_dev, GENMASK(st->chip_info->channel[0].scan_type.realbits - 1, 0); return IIO_VAL_INT; case IIO_CHAN_INFO_SCALE: - if (st->ref_reg) { - scale_uv =3D regulator_get_voltage(st->ref_reg); - if (scale_uv < 0) - return scale_uv; - } else { - scale_uv =3D st->chip_info->int_vref_uv; - } - *val =3D scale_uv / 1000; + *val =3D st->scale_mv; *val2 =3D chan->scan_type.realbits; return IIO_VAL_FRACTIONAL_LOG2; } @@ -286,18 +278,10 @@ static const struct iio_info ad7476_info =3D { .read_raw =3D &ad7476_read_raw, }; =20 -static void ad7476_reg_disable(void *data) -{ - struct regulator *reg =3D data; - - regulator_disable(reg); -} - static int ad7476_probe(struct spi_device *spi) { struct ad7476_state *st; struct iio_dev *indio_dev; - struct regulator *reg; int ret; =20 indio_dev =3D devm_iio_device_alloc(&spi->dev, sizeof(*st)); @@ -308,58 +292,32 @@ static int ad7476_probe(struct spi_device *spi) st->chip_info =3D (struct ad7476_chip_info *)spi_get_device_id(spi)->driver_data; =20 - reg =3D devm_regulator_get(&spi->dev, "vcc"); - if (IS_ERR(reg)) - return PTR_ERR(reg); - - ret =3D regulator_enable(reg); - if (ret) - return ret; - - ret =3D devm_add_action_or_reset(&spi->dev, ad7476_reg_disable, reg); - if (ret) - return ret; - - /* Either vcc or vref (below) as appropriate */ - if (!st->chip_info->int_vref_uv) - st->ref_reg =3D reg; + /* Use VCC for reference voltage if vref / internal vref aren't used */ + if (!st->chip_info->int_vref_uv && !st->chip_info->has_vref) { + ret =3D devm_regulator_get_enable_read_voltage(&spi->dev, "vcc"); + if (ret < 0) + return ret; + st->scale_mv =3D ret / 1000; + } else { + ret =3D devm_regulator_get_enable(&spi->dev, "vcc"); + if (ret < 0) + return ret; + } =20 if (st->chip_info->has_vref) { - - /* If a device has an internal reference vref is optional */ - if (st->chip_info->int_vref_uv) { - reg =3D devm_regulator_get_optional(&spi->dev, "vref"); - if (IS_ERR(reg) && (PTR_ERR(reg) !=3D -ENODEV)) - return PTR_ERR(reg); - } else { - reg =3D devm_regulator_get(&spi->dev, "vref"); - if (IS_ERR(reg)) - return PTR_ERR(reg); - } - - if (!IS_ERR(reg)) { - ret =3D regulator_enable(reg); - if (ret) + ret =3D devm_regulator_get_enable_read_voltage(&spi->dev, "vref"); + if (ret < 0) { + /* Vref is optional if a device has an internal reference */ + if (!st->chip_info->int_vref_uv || ret !=3D -ENODEV) return ret; - - ret =3D devm_add_action_or_reset(&spi->dev, - ad7476_reg_disable, - reg); - if (ret) - return ret; - st->ref_reg =3D reg; } else { - /* - * Can only get here if device supports both internal - * and external reference, but the regulator connected - * to the external reference is not connected. - * Set the reference regulator pointer to NULL to - * indicate this. - */ - st->ref_reg =3D NULL; + st->scale_mv =3D ret / 1000; } } =20 + if (!st->scale_mv) + st->scale_mv =3D st->chip_info->int_vref_uv / 100; + if (st->chip_info->has_vdrive) { ret =3D devm_regulator_get_enable(&spi->dev, "vdrive"); if (ret) --=20 2.50.1 --QxQjTTFP1NoL/Kg6 Content-Type: application/pgp-signature; name=signature.asc -----BEGIN PGP SIGNATURE----- iQEzBAEBCgAdFiEEIx+f8wZb28fLKEhTeFA3/03aocUFAmiMkesACgkQeFA3/03a ocX//gf/TAURqv8cvjFpzH7Hf9NyMobNOLx6oj4zfAQ3PUCQYKHRsj1s5kQMnlky MKae4smTlhnI9c6T18SA8lTULbXQUcTdvGvOl13ppcXnrhY2N1qYigUHcuXXIy4L t2+nj0NIh2/6m7bL7NtVMFd+XWfHFiXvc74kMyy+9eNnROh1t/LLJlDCPS4eL1sa IyMFl8bk+ynCfVVmWbQDTApBBr2AQYFFrC1W82aw1yWvFO5MJfrzFMpFWTfnkEYM qm+TDb1S4L6IS7cYSZ/eTBhCCd5aEyqhzAKZqOKLZuQwvcKdQ050Wx3/STQrnC8s u19IHuFQX5q8MHmugW293cFnBeDUBQ== =yQsV -----END PGP SIGNATURE----- --QxQjTTFP1NoL/Kg6--