From nobody Mon Oct 6 17:02:11 2025 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2052.outbound.protection.outlook.com [40.107.243.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EEFD72D77F0; Fri, 18 Jul 2025 11:24:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.243.52 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752837871; cv=fail; b=oTrMc/skPd5Eze374+eb8AXOByq7TZ/w+ijKCsws7Eo9Fh+M3NwitT2sb7nfK1GhI3w2LffEFOmHve3sGK/wveeIEyZonWrODPBZXxThzHD3/eeQxe1DGFrxDlfR966/iCAd7rnjxqTINPpuezrnB+Evsv5bOGxhVJIFZCZqxmU= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752837871; c=relaxed/simple; bh=tcqZav8s2lrCjMN5groouZ/gXf15w9BB89+28GGlRj8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=TOTqSnGBCqYYG80mJa9Z36J/Xnnx0SiMVlYyKqgJr+2IUrxB5qNv6k0r2d59/ki5l782l0iNj9fHInBPHW9hjlKZBdWWtNf9pjB5uGi9YxmUsd8qoSgWrBOHPRPLaE+JeQzDEb/mRxxrLAYKwX7ZWWNSekAtY4DrhBG3cQqj4X4= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com; spf=fail smtp.mailfrom=amd.com; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b=wusU9Oe2; arc=fail smtp.client-ip=40.107.243.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=amd.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="wusU9Oe2" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=R+JMqgXn5dllUlmwvbfQ5nzvAqDHC/fRYEPos9TyTen6X07eIAjZGn4M2kDeP0UGFqXwxkyimv7iqorzbSp+PG/JRLxqIe2qpVbVKf45GMAQN0/NNdAOtUVPuRhfpmBPcL3zIj2AAYYMO5fzAFReKDorMROrJHlYpEKOkTUXujmrzIBwZyG7m1ATUhr7Yjn8J9FlkAyjwSw5kzfjDUoRfwi6GkJ5cVQNcbuJRg905TRnVqLQIpHE/nK/22s5ZBL6Rz5/Yrqmq6h4yO23p7kpdkOUqX4YRzNKrnjCDbo5OhnGY21JZOECW1ABjQnXrl+H9/0HHZ3HOEhvTo6kNYPEqg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=XOgCMEoCJzELv83glUnmlOCcrr6VlVVYipxh4L0NKE4=; b=x25/W6mWabjfE0aqfUUZ+ctRllIiw/djD0SNyGtRY/uM84jXM01nxs6TZYVnJK1OEmeR5W02GqywBQdp7CYEI+PvAgnfggD0XgUlNjgrFjxT2n7NeXsft1gB3KzWOXCkTpYsKGAd+g9cwzuvz33mfbZfFC+oujdCeG6Rd4YrEK2sspt4o3SfmamkmP/h6E6JZpy7l4nNYh5n3njethm4t0INnLUocPZJ2ufJMRMbIFpXg/jQn2+WKc3DuTJoDbKlWcFteLJ4DM4FILpezXczZ1nAaZurATeI/E9N/3rJcey/OkX1pRHT2pGtFyw2JRaiAnvIamdlhgjSR4Ke16L87g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=XOgCMEoCJzELv83glUnmlOCcrr6VlVVYipxh4L0NKE4=; b=wusU9Oe2eeTlYZ68D3NyYcaphcCjBkHFTEDugyqmZAMj2bp+uRCInidzgtUXDFw/6pZ35VMQ1PPsg1/5h3doSmUU18pxZGzoSk7ZWK4hO/YXA3XO+sOfS0MXP5XeKuHx3QWLGzIZwVHSLM/q9LcTwcJyGDiKBgr6qXYkk33tjoc= Received: from SA9PR13CA0034.namprd13.prod.outlook.com (2603:10b6:806:22::9) by DM6PR12MB4058.namprd12.prod.outlook.com (2603:10b6:5:21d::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8922.39; Fri, 18 Jul 2025 11:24:26 +0000 Received: from SN1PEPF0002636D.namprd02.prod.outlook.com (2603:10b6:806:22:cafe::84) by SA9PR13CA0034.outlook.office365.com (2603:10b6:806:22::9) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8943.17 via Frontend Transport; Fri, 18 Jul 2025 11:24:26 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C Received: from SATLEXMB03.amd.com (165.204.84.17) by SN1PEPF0002636D.mail.protection.outlook.com (10.167.241.138) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8943.21 via Frontend Transport; Fri, 18 Jul 2025 11:24:26 +0000 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 18 Jul 2025 06:24:19 -0500 Received: from localhost (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39 via Frontend Transport; Fri, 18 Jul 2025 06:24:19 -0500 From: Michal Simek To: , , , CC: Conor Dooley , Krzysztof Kozlowski , Rob Herring , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "moderated list:ARM/ZYNQ ARCHITECTURE" Subject: [PATCH 1/3] dt-bindings: soc: xilinx: Add support for K24, KR260 and KD240 CCs Date: Fri, 18 Jul 2025 13:24:06 +0200 Message-ID: <8ff66d0dc4e0de6f239c25d43a2a96b4224305e8.1752837842.git.michal.simek@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3826; i=michal.simek@amd.com; h=from:subject:message-id; bh=tcqZav8s2lrCjMN5groouZ/gXf15w9BB89+28GGlRj8=; b=owGbwMvMwCG2mv3fB7+vgl8ZT6slMWRU6V2/faF92453E3fVvH0jvM5wse0065NllrKfOxI+L pzu2aG1rqOUhUGMg0FWTJFlOpOOw5pv15aKLY/Mh5nDygQyhIGLUwAmojydkWG69xWnZxcr7hxY si8vsnyWwXkfzqeO0VK6dzs1drzbFpPC8M+i4bDo//IjV9/Msf/a1XgtTV/nYIGJkquQ+OHjukJ zs7gB X-Developer-Key: i=michal.simek@amd.com; a=openpgp; fpr=67350C9BF5CCEE9B5364356A377C7F21FE3D1F91 Content-Transfer-Encoding: quoted-printable Received-SPF: None (SATLEXMB03.amd.com: michal.simek@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002636D:EE_|DM6PR12MB4058:EE_ X-MS-Office365-Filtering-Correlation-Id: 98471440-b93d-4968-8cb3-08ddc5eda794 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?pdAbRluWvi42m+pCQytH5bEkS9NGNiIvnajnn4ioNd/8g8qFtKb2g6xwo1wq?= =?us-ascii?Q?vt0aR+ayByp6g9DFeSNl6St6KH7PpuKzIAaiNYfghm/p1ehhjvJS1O76PyN8?= =?us-ascii?Q?Xq8tnH3U0TJWYEY5I+jWpBMTagG/WNTVKa8EM7kI26OUfF5DR9qbTWxOrdht?= =?us-ascii?Q?YakiLwDncKKTnIFXQMd6JJaM4fs4BFXwYGQdcfpvwuuj2kY7k+XRda2AXWLN?= =?us-ascii?Q?XnlJmUpDcSwlsiVBQzm0v9vaCgHP9xM4yVdMkyWMkf6uINDYUBVdlsSB8G6g?= =?us-ascii?Q?AT0v5l3+HL9KlYCUt0ofn8BKPMUSMpQnwvZi0KQdjp+uL7LcEY+BzbQflstS?= =?us-ascii?Q?mTifdZeYWiflcWxhrLzg7QBAfVd2eogqOXqgxkX48VqxnfSP6SqjvrKxdjNy?= =?us-ascii?Q?pWsiI55bL8ycFdP7NRHhtfx/e0wWlTFvGS3DSQd805QYZlqpphGKf1258keg?= =?us-ascii?Q?VebwIuWxRNjbAtbP3rFQfD5oewREycdw4wBXkDEY29oNr7Zh+H5+HNasfF8K?= =?us-ascii?Q?ZOcd53437c6KtddDxwLQqKfXmSwG44HVnJw4RJEq7Kra5eQW4QvIsAl89yY6?= =?us-ascii?Q?N8FTlFgnLfGGtAPOvGZNP38R08bql/mHb2FvRfUkQsvG4gclbntDAZkaBVEY?= =?us-ascii?Q?nxZfqYzRd/AS7JMxQ1ULOyZFeoAeGbIybANbFRBNbaTM94FGVu7mGbB4mOzo?= =?us-ascii?Q?6S7GDVNi6/YPYLhlPskAKQTKx1/KAnt9WYlD95mU+LDDqhyEtkm07VisBJXE?= =?us-ascii?Q?suI5lYgUzC8/QHV+68cPGDcdKzBouJkJA4c2o9NSAicj8IggL6EVsAC4FENd?= =?us-ascii?Q?aWFIWkSqLppkY4hNpbNQ6Rnxizx75CAbzCl+Ei7kJqDMscPwy0zxiw63vGh1?= =?us-ascii?Q?ZXKOy7y60D8F6ZkBXsu/ON3n0JUoeleqzGOtC/8LeOK88NeL489d+x13YF/W?= =?us-ascii?Q?pJNNQHxnKXw8at7i5Lc/UkWJKEFfISeUyV8G6cdduqs9AXILGe2IBUxQn9yM?= =?us-ascii?Q?qf6K5YgwuBMUBsxZ1hwwvQINYmWZ+as67jrzuNaG0T3oWTsK1vtwmhyz3lK+?= =?us-ascii?Q?azWm3ovvDBwoeZ0cHHbJ3t74fTSopBw+g+gYuE73oWLGm/68kIpzGoqjTgt7?= =?us-ascii?Q?O+q7kFTyRrWsfgsMsBoGCLVfCkyg6Qjt4jsVBrX+M5QIzJssJpKVRr2CmF9J?= =?us-ascii?Q?6ip15HzjaghDEbL2Mr7jgEiQ2KUukTYptsXNZaZOSQXVkTe45anRcpc6c0dn?= =?us-ascii?Q?hcBrv3183iIuKzZIlwDfEqGbOORVGwNlDgblM4up+6cKsMmnIk82iYptGSr8?= =?us-ascii?Q?JbfZBw38RZJm2ZDTyJu27CaMPp0ccYgJBUrQLE2fY4ONoj5qz2CrKkel04UH?= =?us-ascii?Q?2ylurdCEuBJvk0quxL3R4UcAUfTXij8aeySFcrZSqvPawgvlWP3lVbD+4EJy?= =?us-ascii?Q?voMjnQsr+Ep53C8vUZX8CrfwTIpB77duAwX1EoR4dMmqZ6CLt7J3LPpsslL3?= =?us-ascii?Q?FBA0SlzNWcDb2Ow+CpGHB8sG/7IMtTnSj4Aw?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(82310400026)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jul 2025 11:24:26.5282 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 98471440-b93d-4968-8cb3-08ddc5eda794 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002636D.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4058 Content-Type: text/plain; charset="utf-8" The commit 7a4c31ee877a ("arm64: zynqmp: Add support for Xilinx Kria SOM board") has added support for k26 and kv260 and the commit dbcd27526e6a ("dt-bindings: soc: xilinx: Add support for KV260 CC") has added support for KV260 and this is follow up patch for adding description for k24 SOM, KR260 (robotics platform) and KD240 (driver platform). The bootflow is the same that's why for more information please take a look at above commits. The KD240 kit is based on smaller k24 SOM with only 2GB of memory. Signed-off-by: Michal Simek Reviewed-by: Rob Herring (Arm) --- .../bindings/soc/xilinx/xilinx.yaml | 81 +++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml b/Doc= umentation/devicetree/bindings/soc/xilinx/xilinx.yaml index fb5c39c79d28..c9f99e0df2b3 100644 --- a/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml +++ b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml @@ -116,6 +116,36 @@ properties: - const: xlnx,zynqmp-zcu111 - const: xlnx,zynqmp =20 + - description: Xilinx Kria SOMs K24 + minItems: 3 + items: + enum: + - xlnx,zynqmp-sm-k24-rev1 + - xlnx,zynqmp-sm-k24-revB + - xlnx,zynqmp-sm-k24-revA + - xlnx,zynqmp-sm-k24 + - xlnx,zynqmp + allOf: + - contains: + const: xlnx,zynqmp + - contains: + const: xlnx,zynqmp-sm-k24 + + - description: Xilinx Kria SOMs K24 (starter) + minItems: 3 + items: + enum: + - xlnx,zynqmp-smk-k24-rev1 + - xlnx,zynqmp-smk-k24-revB + - xlnx,zynqmp-smk-k24-revA + - xlnx,zynqmp-smk-k24 + - xlnx,zynqmp + allOf: + - contains: + const: xlnx,zynqmp + - contains: + const: xlnx,zynqmp-smk-k24 + - description: Xilinx Kria SOMs minItems: 3 items: @@ -148,6 +178,57 @@ properties: - contains: const: xlnx,zynqmp-smk-k26 =20 + - description: Xilinx Kria SOM KD240 revA/B/1 + minItems: 3 + items: + enum: + - xlnx,zynqmp-sk-kd240-rev1 + - xlnx,zynqmp-sk-kd240-revB + - xlnx,zynqmp-sk-kd240-revA + - xlnx,zynqmp-sk-kd240 + - xlnx,zynqmp + allOf: + - contains: + const: xlnx,zynqmp-sk-kd240-revA + - contains: + const: xlnx,zynqmp-sk-kd240 + - contains: + const: xlnx,zynqmp + + - description: Xilinx Kria SOM KR260 revA/Y/Z + minItems: 3 + items: + enum: + - xlnx,zynqmp-sk-kr260-revA + - xlnx,zynqmp-sk-kr260-revY + - xlnx,zynqmp-sk-kr260-revZ + - xlnx,zynqmp-sk-kr260 + - xlnx,zynqmp + allOf: + - contains: + const: xlnx,zynqmp-sk-kr260-revA + - contains: + const: xlnx,zynqmp-sk-kr260 + - contains: + const: xlnx,zynqmp + + - description: Xilinx Kria SOM KR260 rev2/1/B + minItems: 3 + items: + enum: + - xlnx,zynqmp-sk-kr260-rev2 + - xlnx,zynqmp-sk-kr260-rev1 + - xlnx,zynqmp-sk-kr260-revB + - xlnx,zynqmp-sk-kr260 + - xlnx,zynqmp + allOf: + - contains: + const: xlnx,zynqmp-sk-kr260-revB + - contains: + const: xlnx,zynqmp-sk-kr260 + - contains: + const: xlnx,zynqmp + - description: Xilinx Kria SOM KV260 revA/Y/Z minItems: 3 items: --=20 2.43.0 From nobody Mon Oct 6 17:02:11 2025 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2082.outbound.protection.outlook.com [40.107.220.82]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A44352D8DA0; Fri, 18 Jul 2025 11:24:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.220.82 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752837875; cv=fail; b=FqxoTFSYtS5lLbcVRFOqCulhr9HAjm4uY26zgACsFC/6RvDy27UJWJYGgtFEpm0hwHD0JQz/adGxx5XiIhzkg5ntz6AIVjYdzxL0ld8VNJh1Pr4GnWteJ1BBKQbUXKC17aEleHLsX7r0bkb+vjBA2NODAVJKNqEpoe6LQ+TjcHU= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752837875; c=relaxed/simple; bh=AsdZuJVYhvvcz7Vn8iBGJJqMVW4b+Unr5J5Uht6sC8c=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=KkC35xxyanRf8o/uJt6CQOmCAn48SwOQLbO81mtQwKLmq97BSpk4g1YDDOXvee6h95iIuJvgV7Ir7VbmfZXruC43+QwW04Z8G0MLo0iihaYCytOyh2dG1K5Ez2/IVPpTzmjNUF0LgJwIfTa2ls79fn6cANfqICjDcyzwcCxDKNQ= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com; spf=fail smtp.mailfrom=amd.com; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b=fwlHTVVs; arc=fail smtp.client-ip=40.107.220.82 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=amd.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="fwlHTVVs" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=hlb8B0u1RJGBMIx80adKIclqI0ed5kI4nwzJHpDUGTulhfGA6qIfavI2+WiLPDygWuPQsWU3t42RkUXvh/s7jnAnWPMbV26lNSi+HmygEbimBErPyLwtNUN+wUi6glo+FY8oF4Rz9nldygjL3g7M3F+sl9PSvsr+a/OfAFwWikmFwelGcVMR70jyzaQs0INDh3DwXDb0egd5CoFuKWaF2dY2e8DNXRoGOIz80j4mjgxtB4iK5ZOF2mnsk9VGc/IZfVi2alwtApe+nYrw1lCDhE3vMk4q22sPG+T2airo2bevy3LIsk7XMhXILsa9/3LpAwkwH5aPTicKgxvGABlnPA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=SDMfDh+do25HPOXP2/p2fqJNvLHU5GUi3cdw2CGutZ8=; b=u7ximrD+RTDBZgHueMKQVXXmBiRfFW+JCVx6gfoPo0kyX2hlUdEf7M9KhJzrxC9Rv+8YpISItf4uJDKsi3bAI0eXZJzyT5hj4dznJ6uummtsz8ryat24HeK0zNyGB+Z94Dgpwt4+DstSje8+ufPNWdEB6kOLujV5smhjCG+ApO0smBfVNqEqj1eShPavlviyO0cm/kYQpznkI85VK0hYAEMPZImBKFy+y3/eleTiL/RW7mUfSXKnRIG/EN4DxmjTQdv1tZaN8R8+0nmpCLqEJMlEFvIwHAsgS3IaXqqbLwerpUIflXuBmOwjHM64MbZgevKwBtVEXJHgM57zd+Mx2Q== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=SDMfDh+do25HPOXP2/p2fqJNvLHU5GUi3cdw2CGutZ8=; b=fwlHTVVshXLUJNV7wGYym9KwWlobGVBlU/o3Qu9qCmo2feB3sRCHpqwgIq4RvScNZWomaLCNw+iz/RpRkA0YDo7XgURt/AQHSCmqJMMOVkWEOnBRT6UJZtLc+6c14qDlSOJ8S4qpufXHL8YZif4oYOnkMELYKrRdDEKcKe1I/Og= Received: from SN7P220CA0021.NAMP220.PROD.OUTLOOK.COM (2603:10b6:806:123::26) by MN0PR12MB6246.namprd12.prod.outlook.com (2603:10b6:208:3c2::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8943.28; Fri, 18 Jul 2025 11:24:29 +0000 Received: from SN1PEPF0002636B.namprd02.prod.outlook.com (2603:10b6:806:123:cafe::f7) by SN7P220CA0021.outlook.office365.com (2603:10b6:806:123::26) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8943.20 via Frontend Transport; Fri, 18 Jul 2025 11:24:29 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C Received: from SATLEXMB03.amd.com (165.204.84.17) by SN1PEPF0002636B.mail.protection.outlook.com (10.167.241.136) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8943.21 via Frontend Transport; Fri, 18 Jul 2025 11:24:29 +0000 Received: from SATLEXMB05.amd.com (10.181.40.146) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 18 Jul 2025 06:24:24 -0500 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB05.amd.com (10.181.40.146) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 18 Jul 2025 06:24:22 -0500 Received: from localhost (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39 via Frontend Transport; Fri, 18 Jul 2025 06:24:22 -0500 From: Michal Simek To: , , , CC: Conor Dooley , Krzysztof Kozlowski , Rob Herring , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "moderated list:ARM/ZYNQ ARCHITECTURE" Subject: [PATCH 2/3] arm64: zynqmp: Add support for kr260 board Date: Fri, 18 Jul 2025 13:24:07 +0200 Message-ID: <650ff5407528b8a90867ff1ac072b4112c91c866.1752837842.git.michal.simek@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=22626; i=michal.simek@amd.com; h=from:subject:message-id; bh=AsdZuJVYhvvcz7Vn8iBGJJqMVW4b+Unr5J5Uht6sC8c=; b=owGbwMvMwCG2mv3fB7+vgl8ZT6slMWRU6d1Im1/9ZNWd+vTISPb2R9VhSZtKC1y4t2bkXTpzW MyyLMS/o5SFQYyDQVZMkWU6k47Dmm/Xlootj8yHmcPKBDKEgYtTACbCEMbwP7nG0evvw+k3Xdkc rjT8jG/sP73DZXoh4/pppySk6w3V5zP8T1t0ydrJccZ/nw2rzy1IO7bq9vqq0Pec9xYZOBb0Xqp U4gEA X-Developer-Key: i=michal.simek@amd.com; a=openpgp; fpr=67350C9BF5CCEE9B5364356A377C7F21FE3D1F91 Content-Transfer-Encoding: quoted-printable Received-SPF: None (SATLEXMB05.amd.com: michal.simek@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002636B:EE_|MN0PR12MB6246:EE_ X-MS-Office365-Filtering-Correlation-Id: 3b6e34f4-66c9-4c69-4a8f-08ddc5eda930 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?6Z+hbFtH74TTXFYCXQF/tI7cLnacXY4628EelzV4pOV1AsNbhdGNbk/d6EMT?= =?us-ascii?Q?ZdTkcR/pRf1MiJ82+tFUHcF0xNXcPNw+M7XdsK6WD4hh7gq5gxpwdZLSQbqT?= =?us-ascii?Q?pzqVX58AWe6AOYy/qc4Y0vtyUef6cwSsWGSCm/wOeffAuBJMU2Gsnme7OBUF?= =?us-ascii?Q?GF/eC6FVgfKiMeT1SEG50FLxwxDbBT4C3QvBp1OTLK2M75UL8Y2nW/K1ZY6y?= =?us-ascii?Q?e5t+g4VxzVZyRdPTvC7vErU0eatm6O8LPAuXsoRK4VkSrRaVmikJY9wHtrpo?= =?us-ascii?Q?T9cVK5udnHrQahCAe9J4i5e2tOyiGxMYvmf79DUmkpyvAVZoQomaXzel3yHW?= =?us-ascii?Q?xThh3BUOB4i7caXBN96rFBDcoUVM/Qu5QRgN506ZroOIIlq90PfcNwyMPJcY?= =?us-ascii?Q?+CYqyk7vGkPRkZf3thJl5muMiQoOEE/91X7EceDu1XieRL4ou3wbaFxvSGLa?= =?us-ascii?Q?UObQhxSZcP6OhwMOjCfJBno6FH6+QcyPguXNhtRC77KDLjrI0aTu8lOLNLLu?= =?us-ascii?Q?WOr3i3+dwNXVLT6oR9T02CNNrdzpEeOsxq5vBD1hdEbGQDSIFq1cu1NWnRgt?= =?us-ascii?Q?Q9leZES3ei+N1MAC7aJ/AxoCyOw/Gn60/DvtoMoegsWa8VTj/+uy/Y2deUz/?= =?us-ascii?Q?Bn6iIR2SjoZ8b4cr9mLytI1kH5tlU1zKXkTWhvnKpJ0L2YxHknl/TRQFSGoq?= =?us-ascii?Q?if9Ss5O7At0gZtxuLokGOMZMAWevGONBXH/c0m5f4KdG6WPiWCHMNbno3Jup?= =?us-ascii?Q?3sQJM2iJb/uJ+XY+mzBRvyuvD3jaKFkUWXrcgTxhpjrwvIyRanekZqCnBO2V?= =?us-ascii?Q?r7VmTEfb2kJwDmynCwDJ5YNkYf6UkfLi8MgsqtB/XDZk4xgL/FNnvt+/lghx?= =?us-ascii?Q?Z1fyAhC7XQBqrHzZ8DGkdC7qY10t73+jDoHH+S6bnpT5dZG5uZfQYKfh3QhC?= =?us-ascii?Q?E1yJ63VkNLE07Exi+FvgYJR0d/vMySLBhPrNBoeuYVOO2UpLBur0LMBVvYYc?= =?us-ascii?Q?iMPbTzJt7a8nDZxs74WRTKgrSdAB4kEaDaxJsQiiZUQPlZqm6PtESlKJPYoI?= =?us-ascii?Q?My/isdV9b2UbsgRatdfxzWyQm2N+tD7bCkrLWsOhDN12DJyaoEYjsQDE5+Yc?= =?us-ascii?Q?8etw3yBd1MIpU6CegFgP3PB8YvyGvVQL9eEqTzM64nlhtbNuNmy9tuu/oNWk?= =?us-ascii?Q?DDexs+dAThryRC9VHZsxJpHP+uCQpsjYdz0sA7ueTEiLhfBULvZlzMIrXvEo?= =?us-ascii?Q?ayLTvh1Nr95Qx3xqH4WieeN6HEIrt267Gi1e5pU0ABONKSboROjr0c1Y/kzl?= =?us-ascii?Q?zET+XXxCSTp/MSf4j3IvukGbDx0YtfEGhSeGbEbAn45kmiBTNm/5FxnrjT+P?= =?us-ascii?Q?2gImW1WmDvG8IqxBXRdxYz6Xgz46lqs/O+SFGKr8RaJinOMF6AX95Tj1Pxbm?= =?us-ascii?Q?mts22x9Dz0vydo2YCb207d8aXS9lzEMrDzFpAyV1Oc5Wq+lvWVE18ko7xwQ9?= =?us-ascii?Q?KnTYY2fVCbgk+rtImloq03d9hYdLeuypS0W0wANJFcRhyU161UMqH65hag?= =?us-ascii?Q?=3D=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jul 2025 11:24:29.2267 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3b6e34f4-66c9-4c69-4a8f-08ddc5eda930 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002636B.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6246 Content-Type: text/plain; charset="utf-8" The kit based on K26 SOM is built for robotics and industrial application. Signed-off-by: Michal Simek --- https://www.amd.com/en/products/system-on-modules/kria/k26/kr260-robotics-s= tarter-kit.html --- arch/arm64/boot/dts/xilinx/Makefile | 9 + .../boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso | 438 +++++++++++++++++ .../boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso | 451 ++++++++++++++++++ 3 files changed, 898 insertions(+) create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xili= nx/Makefile index 7f5a8801cad1..5e84e3c725e2 100644 --- a/arch/arm64/boot/dts/xilinx/Makefile +++ b/arch/arm64/boot/dts/xilinx/Makefile @@ -30,4 +30,13 @@ dtb-$(CONFIG_ARCH_ZYNQMP) +=3D zynqmp-smk-k26-revA-sck-k= v-g-revA.dtb zynqmp-smk-k26-revA-sck-kv-g-revB-dtbs :=3D zynqmp-smk-k26-revA.dtb zynqmp= -sck-kv-g-revB.dtbo dtb-$(CONFIG_ARCH_ZYNQMP) +=3D zynqmp-smk-k26-revA-sck-kv-g-revB.dtb =20 +zynqmp-sm-k26-revA-sck-kr-g-revA-dtbs :=3D zynqmp-sm-k26-revA.dtb zynqmp-s= ck-kr-g-revA.dtbo +dtb-$(CONFIG_ARCH_ZYNQMP) +=3D zynqmp-sm-k26-revA-sck-kr-g-revA.dtb +zynqmp-sm-k26-revA-sck-kr-g-revB-dtbs :=3D zynqmp-sm-k26-revA.dtb zynqmp-s= ck-kr-g-revB.dtbo +dtb-$(CONFIG_ARCH_ZYNQMP) +=3D zynqmp-sm-k26-revA-sck-kr-g-revB.dtb +zynqmp-smk-k26-revA-sck-kr-g-revA-dtbs :=3D zynqmp-smk-k26-revA.dtb zynqmp= -sck-kr-g-revA.dtbo +dtb-$(CONFIG_ARCH_ZYNQMP) +=3D zynqmp-smk-k26-revA-sck-kr-g-revA.dtb +zynqmp-smk-k26-revA-sck-kr-g-revB-dtbs :=3D zynqmp-smk-k26-revA.dtb zynqmp= -sck-kr-g-revB.dtbo +dtb-$(CONFIG_ARCH_ZYNQMP) +=3D zynqmp-smk-k26-revA-sck-kr-g-revB.dtb + dtb-$(CONFIG_ARCH_ZYNQMP) +=3D versal-net-vn-x-b2197-01-revA.dtb diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso b/arch/ar= m64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso new file mode 100644 index 000000000000..fbacfa984d76 --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso @@ -0,0 +1,438 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for KR260 revA Carrier Card + * + * (C) Copyright 2021, Xilinx, Inc. + * + * Michal Simek + */ + +#include +#include +#include +#include + +/dts-v1/; +/plugin/; + +&{/} { + compatible =3D "xlnx,zynqmp-sk-kr260-revA", + "xlnx,zynqmp-sk-kr260", "xlnx,zynqmp"; + model =3D "ZynqMP KR260 revA"; + + aliases { + ethernet0 =3D "/axi/ethernet@ff0b0000"; /* &gem0 */ + ethernet1 =3D "/axi/ethernet@ff0c0000"; /* &gem1 */ + }; + + ina260-u14 { + compatible =3D "iio-hwmon"; + io-channels =3D <&u14 0>, <&u14 1>, <&u14 2>; + }; + + clk_27: clock0 { /* u86 - DP */ + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <27000000>; + }; + + clk_125: si5332-0 { /* u17 - GEM0/1 */ + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <125000000>; + }; + + clk_74: si5332-5 { /* u17 - SLVC-EC */ + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <74250000>; + }; + + clk_26: si5332-2 { /* u17 - USB */ + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <26000000>; + }; + + clk_156: si5332-3 { /* u17 - SFP+ */ + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <156250000>; + }; + + clk_25_0: si5332-1 { /* u17 - GEM2 */ + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <25000000>; + }; + + clk_25_1: si5332-4 { /* u17 - GEM3 */ + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <25000000>; + }; +}; + +&i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */ + #address-cells =3D <1>; + #size-cells =3D <0>; + pinctrl-names =3D "default", "gpio"; + pinctrl-0 =3D <&pinctrl_i2c1_default>; + pinctrl-1 =3D <&pinctrl_i2c1_gpio>; + scl-gpios =3D <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios =3D <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + u14: ina260@40 { /* u14 */ + compatible =3D "ti,ina260"; + #io-channel-cells =3D <1>; + label =3D "ina260-u14"; + reg =3D <0x40>; + }; + + slg7xl45106: gpio@11 { /* u19 - reset logic */ + compatible =3D "dlg,slg7xl45106"; + reg =3D <0x11>; + label =3D "resetchip"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D "USB0_PHY_RESET_B", "USB1_PHY_RESET_B", + "SD_RESET_B", "USB0_HUB_RESET_B", + "USB1_HUB_RESET_B", "PS_GEM0_RESET_B", + "PS_GEM1_RESET_B", ""; + }; + + i2c-mux@74 { /* u18 */ + compatible =3D "nxp,pca9546"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x74>; + usbhub_i2c0: i2c@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + hub_1: usb-hub@2d { + compatible =3D "microchip,usb5744"; + reg =3D <0x2d>; + }; + }; + usbhub_i2c1: i2c@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + hub_2: usb-hub@2d { + compatible =3D "microchip,usb5744"; + reg =3D <0x2d>; + }; + }; + /* Bus 2/3 are not connected */ + }; + + /* si5332@6a - u17 - clock-generator */ +}; + +/* GEM SGMII/DP and USB 3.0 */ +&psgtr { + status =3D "okay"; + /* gem0/1, dp, usb */ + clocks =3D <&clk_125>, <&clk_27>, <&clk_26>; + clock-names =3D "ref0", "ref1", "ref2"; +}; + +&zynqmp_dpsub { + status =3D "okay"; + phy-names =3D "dp-phy0"; + phys =3D <&psgtr 1 PHY_TYPE_DP 0 1>; + assigned-clock-rates =3D <27000000>, <25000000>, <300000000>; +}; + +&zynqmp_dpdma { + status =3D "okay"; + assigned-clock-rates =3D <600000000>; +}; + +&usb0 { /* mio52 - mio63 */ + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_usb0_default>; + phy-names =3D "usb3-phy"; + phys =3D <&psgtr 2 PHY_TYPE_USB3 0 2>; + reset-gpios =3D <&slg7xl45106 0 GPIO_ACTIVE_LOW>; + assigned-clock-rates =3D <250000000>, <20000000>; +}; + +&dwc3_0 { + status =3D "okay"; + dr_mode =3D "host"; + snps,usb3_lpm_capable; + maximum-speed =3D "super-speed"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + /* 2.0 hub on port 1 */ + hub_2_0: hub@1 { + compatible =3D "usb424,2744"; + reg =3D <1>; + peer-hub =3D <&hub_3_0>; + i2c-bus =3D <&hub_1>; + reset-gpios =3D <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + }; + + /* 3.0 hub on port 2 */ + hub_3_0: hub@2 { + compatible =3D "usb424,5744"; + reg =3D <2>; + peer-hub =3D <&hub_2_0>; + i2c-bus =3D <&hub_1>; + reset-gpios =3D <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + }; +}; + +&usb1 { /* mio64 - mio75 */ + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_usb1_default>; + phy-names =3D "usb3-phy"; + phys =3D <&psgtr 3 PHY_TYPE_USB3 1 2>; + reset-gpios =3D <&slg7xl45106 1 GPIO_ACTIVE_LOW>; + assigned-clock-rates =3D <250000000>, <20000000>; +}; + +&dwc3_1 { + status =3D "okay"; + dr_mode =3D "host"; + snps,usb3_lpm_capable; + maximum-speed =3D "super-speed"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + /* 2.0 hub on port 1 */ + hub1_2_0: hub@1 { + compatible =3D "usb424,2744"; + reg =3D <1>; + peer-hub =3D <&hub1_3_0>; + i2c-bus =3D <&hub_2>; + reset-gpios =3D <&slg7xl45106 4 GPIO_ACTIVE_LOW>; + }; + + /* 3.0 hub on port 2 */ + hub1_3_0: hub@2 { + compatible =3D "usb424,5744"; + reg =3D <2>; + peer-hub =3D <&hub1_2_0>; + i2c-bus =3D <&hub_2>; + reset-gpios =3D <&slg7xl45106 4 GPIO_ACTIVE_LOW>; + }; +}; + +&gem0 { /* mdio mio50/51 */ + status =3D "okay"; + phys =3D <&psgtr 0 PHY_TYPE_SGMII 0 0>; + phy-handle =3D <&phy0>; + phy-mode =3D "sgmii"; + assigned-clock-rates =3D <250000000>; +}; + +&gem1 { /* mdio mio50/51, gem mio38 - mio49 */ + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_gem1_default>; + phy-handle =3D <&phy1>; + phy-mode =3D "rgmii-id"; + assigned-clock-rates =3D <250000000>; + + mdio: mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + phy0: ethernet-phy@4 { /* u81 */ + #phy-cells =3D <1>; + compatible =3D "ethernet-phy-id2000.a231"; + reg =3D <4>; + ti,rx-internal-delay =3D ; + ti,tx-internal-delay =3D ; + ti,fifo-depth =3D ; + ti,dp83867-rxctrl-strap-quirk; + reset-assert-us =3D <300>; + reset-deassert-us =3D <280>; + reset-gpios =3D <&slg7xl45106 5 GPIO_ACTIVE_LOW>; + }; + phy1: ethernet-phy@8 { /* u36 */ + #phy-cells =3D <1>; + compatible =3D "ethernet-phy-id2000.a231"; + reg =3D <8>; + ti,rx-internal-delay =3D ; + ti,tx-internal-delay =3D ; + ti,fifo-depth =3D ; + ti,dp83867-rxctrl-strap-quirk; + reset-assert-us =3D <100>; + reset-deassert-us =3D <280>; + reset-gpios =3D <&slg7xl45106 6 GPIO_ACTIVE_LOW>; + }; + }; +}; + +/* gem2/gem3 via PL with phys u79@2 and u80@3 */ + +&pinctrl0 { + status =3D "okay"; + + pinctrl_uart1_default: uart1-default { + conf { + groups =3D "uart1_9_grp"; + slew-rate =3D ; + power-source =3D ; + drive-strength =3D <12>; + }; + + conf-rx { + pins =3D "MIO37"; + bias-high-impedance; + }; + + conf-tx { + pins =3D "MIO36"; + bias-disable; + output-enable; + }; + + mux { + groups =3D "uart1_9_grp"; + function =3D "uart1"; + }; + }; + + pinctrl_i2c1_default: i2c1-default { + conf { + groups =3D "i2c1_6_grp"; + bias-pull-up; + slew-rate =3D ; + power-source =3D ; + }; + + mux { + groups =3D "i2c1_6_grp"; + function =3D "i2c1"; + }; + }; + + pinctrl_i2c1_gpio: i2c1-gpio-grp { + conf { + groups =3D "gpio0_24_grp", "gpio0_25_grp"; + slew-rate =3D ; + power-source =3D ; + }; + + mux { + groups =3D "gpio0_24_grp", "gpio0_25_grp"; + function =3D "gpio0"; + }; + }; + + pinctrl_gem1_default: gem1-default { + conf { + groups =3D "ethernet1_0_grp"; + slew-rate =3D ; + power-source =3D ; + }; + + conf-rx { + pins =3D "MIO44", "MIO46", "MIO48"; + bias-high-impedance; + low-power-disable; + }; + + conf-bootstrap { + pins =3D "MIO45", "MIO47", "MIO49"; + bias-disable; + output-enable; + low-power-disable; + }; + + conf-tx { + pins =3D "MIO38", "MIO39", "MIO40", + "MIO41", "MIO42", "MIO43"; + bias-disable; + output-enable; + low-power-enable; + }; + + conf-mdio { + groups =3D "mdio1_0_grp"; + slew-rate =3D ; + power-source =3D ; + bias-disable; + output-enable; + }; + + mux-mdio { + function =3D "mdio1"; + groups =3D "mdio1_0_grp"; + }; + + mux { + function =3D "ethernet1"; + groups =3D "ethernet1_0_grp"; + }; + }; + + pinctrl_usb0_default: usb0-default { + conf { + groups =3D "usb0_0_grp"; + power-source =3D ; + }; + + conf-rx { + pins =3D "MIO52", "MIO53", "MIO55"; + bias-high-impedance; + drive-strength =3D <12>; + slew-rate =3D ; + }; + + conf-tx { + pins =3D "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", + "MIO60", "MIO61", "MIO62", "MIO63"; + bias-disable; + output-enable; + drive-strength =3D <4>; + slew-rate =3D ; + }; + + mux { + groups =3D "usb0_0_grp"; + function =3D "usb0"; + }; + }; + + pinctrl_usb1_default: usb1-default { + conf { + groups =3D "usb1_0_grp"; + power-source =3D ; + }; + + conf-rx { + pins =3D "MIO64", "MIO65", "MIO67"; + bias-high-impedance; + drive-strength =3D <12>; + slew-rate =3D ; + }; + + conf-tx { + pins =3D "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", + "MIO72", "MIO73", "MIO74", "MIO75"; + bias-disable; + output-enable; + drive-strength =3D <4>; + slew-rate =3D ; + }; + + mux { + groups =3D "usb1_0_grp"; + function =3D "usb1"; + }; + }; +}; + +&uart1 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart1_default>; +}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso b/arch/ar= m64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso new file mode 100644 index 000000000000..b7cda216b179 --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso @@ -0,0 +1,451 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for KR260 revB Carrier Card (A03 revision) + * + * (C) Copyright 2021 - 2022, Xilinx, Inc. + * + * Michal Simek + */ + +#include +#include +#include +#include + +/dts-v1/; +/plugin/; + +&{/} { + compatible =3D "xlnx,zynqmp-sk-kr260-revB", + "xlnx,zynqmp-sk-kr260", "xlnx,zynqmp"; + model =3D "ZynqMP KR260 revB"; + + ina260-u14 { + compatible =3D "iio-hwmon"; + io-channels =3D <&u14 0>, <&u14 1>, <&u14 2>; + }; + + clk_125: clock0 { /* u87 - GEM0/1 */ + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <125000000>; + }; + + clk_27: clock1 { /* u86 - DP */ + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <27000000>; + }; + + clk_26: clock2 { /* u89 - USB */ + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <26000000>; + }; + + clk_156: clock3 { /* u90 - SFP+ */ + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <156250000>; + }; + + clk_25_0: clock4 { /* u92/u91 - GEM2 */ + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <25000000>; + }; + + clk_25_1: clock5 { /* u92/u91 - GEM3 */ + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <25000000>; + }; + + clk_74: clock6 { /* u88 - SLVC-EC */ + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <74250000>; + }; + + dpcon { + compatible =3D "dp-connector"; + label =3D "P11"; + type =3D "full-size"; + + port { + dpcon_in: endpoint { + remote-endpoint =3D <&dpsub_dp_out>; + }; + }; + }; +}; + +&i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */ + #address-cells =3D <1>; + #size-cells =3D <0>; + pinctrl-names =3D "default", "gpio"; + pinctrl-0 =3D <&pinctrl_i2c1_default>; + pinctrl-1 =3D <&pinctrl_i2c1_gpio>; + scl-gpios =3D <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios =3D <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + u14: ina260@40 { /* u14 */ + compatible =3D "ti,ina260"; + #io-channel-cells =3D <1>; + label =3D "ina260-u14"; + reg =3D <0x40>; + }; + + slg7xl45106: gpio@11 { /* u19 - reset logic */ + compatible =3D "dlg,slg7xl45106"; + reg =3D <0x11>; + label =3D "resetchip"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D "USB0_PHY_RESET_B", "USB1_PHY_RESET_B", + "SD_RESET_B", "USB0_HUB_RESET_B", + "USB1_HUB_RESET_B", "PS_GEM0_RESET_B", + "PS_GEM1_RESET_B", ""; + }; + + i2c-mux@74 { /* u18 */ + compatible =3D "nxp,pca9546"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x74>; + usbhub_i2c0: i2c@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + hub_1: usb-hub@2d { + compatible =3D "microchip,usb5744"; + reg =3D <0x2d>; + }; + }; + usbhub_i2c1: i2c@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + hub_2: usb-hub@2d { + compatible =3D "microchip,usb5744"; + reg =3D <0x2d>; + }; + }; + /* Bus 2/3 are not connected */ + }; + + /* si5332@6a - u17 - clock-generator */ +}; + +/* GEM SGMII/DP and USB 3.0 */ +&psgtr { + status =3D "okay"; + /* gem0/1, dp, usb */ + clocks =3D <&clk_125>, <&clk_27>, <&clk_26>; + clock-names =3D "ref0", "ref1", "ref2"; +}; + +&zynqmp_dpsub { + status =3D "okay"; + phy-names =3D "dp-phy0"; + phys =3D <&psgtr 1 PHY_TYPE_DP 0 1>; + assigned-clock-rates =3D <27000000>, <25000000>, <300000000>; +}; + +&out_dp { + dpsub_dp_out: endpoint { + remote-endpoint =3D <&dpcon_in>; + }; +}; + +&zynqmp_dpdma { + status =3D "okay"; + assigned-clock-rates =3D <600000000>; +}; + +&usb0 { /* mio52 - mio63 */ + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_usb0_default>; + phy-names =3D "usb3-phy"; + phys =3D <&psgtr 2 PHY_TYPE_USB3 0 2>; + reset-gpios =3D <&slg7xl45106 0 GPIO_ACTIVE_LOW>; + assigned-clock-rates =3D <250000000>, <20000000>; +}; + +&dwc3_0 { + status =3D "okay"; + dr_mode =3D "host"; + snps,usb3_lpm_capable; + maximum-speed =3D "super-speed"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + /* 2.0 hub on port 1 */ + hub_2_0: hub@1 { + compatible =3D "usb424,2744"; + reg =3D <1>; + peer-hub =3D <&hub_3_0>; + i2c-bus =3D <&hub_1>; + reset-gpios =3D <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + }; + + /* 3.0 hub on port 2 */ + hub_3_0: hub@2 { + compatible =3D "usb424,5744"; + reg =3D <2>; + peer-hub =3D <&hub_2_0>; + i2c-bus =3D <&hub_1>; + reset-gpios =3D <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + }; +}; + +&usb1 { /* mio64 - mio75 */ + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_usb1_default>; + phy-names =3D "usb3-phy"; + phys =3D <&psgtr 3 PHY_TYPE_USB3 1 2>; + reset-gpios =3D <&slg7xl45106 1 GPIO_ACTIVE_LOW>; + assigned-clock-rates =3D <250000000>, <20000000>; +}; + +&dwc3_1 { + status =3D "okay"; + dr_mode =3D "host"; + snps,usb3_lpm_capable; + maximum-speed =3D "super-speed"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + /* 2.0 hub on port 1 */ + hub1_2_0: hub@1 { + compatible =3D "usb424,2744"; + reg =3D <1>; + peer-hub =3D <&hub1_3_0>; + i2c-bus =3D <&hub_2>; + reset-gpios =3D <&slg7xl45106 4 GPIO_ACTIVE_LOW>; + }; + + /* 3.0 hub on port 2 */ + hub1_3_0: hub@2 { + compatible =3D "usb424,5744"; + reg =3D <2>; + peer-hub =3D <&hub1_2_0>; + i2c-bus =3D <&hub_2>; + reset-gpios =3D <&slg7xl45106 4 GPIO_ACTIVE_LOW>; + }; +}; + +&gem0 { /* mdio mio50/51 */ + status =3D "okay"; + phys =3D <&psgtr 0 PHY_TYPE_SGMII 0 0>; + phy-handle =3D <&phy0>; + phy-mode =3D "sgmii"; + assigned-clock-rates =3D <250000000>; +}; + +&gem1 { /* mdio mio50/51, gem mio38 - mio49 */ + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_gem1_default>; + phy-handle =3D <&phy1>; + phy-mode =3D "rgmii-id"; + assigned-clock-rates =3D <250000000>; + + mdio: mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + phy0: ethernet-phy@4 { /* u81 */ + #phy-cells =3D <1>; + compatible =3D "ethernet-phy-id2000.a231"; + reg =3D <4>; + ti,rx-internal-delay =3D ; + ti,tx-internal-delay =3D ; + ti,fifo-depth =3D ; + ti,dp83867-rxctrl-strap-quirk; + reset-assert-us =3D <300>; + reset-deassert-us =3D <280>; + reset-gpios =3D <&slg7xl45106 5 GPIO_ACTIVE_LOW>; + }; + phy1: ethernet-phy@8 { /* u36 */ + #phy-cells =3D <1>; + compatible =3D "ethernet-phy-id2000.a231"; + reg =3D <8>; + ti,rx-internal-delay =3D ; + ti,tx-internal-delay =3D ; + ti,fifo-depth =3D ; + ti,dp83867-rxctrl-strap-quirk; + reset-assert-us =3D <100>; + reset-deassert-us =3D <280>; + reset-gpios =3D <&slg7xl45106 6 GPIO_ACTIVE_LOW>; + }; + }; +}; + +/* gem2/gem3 via PL with phys u79@2 and u80@3 */ + +&pinctrl0 { + status =3D "okay"; + + pinctrl_uart1_default: uart1-default { + conf { + groups =3D "uart1_9_grp"; + slew-rate =3D ; + power-source =3D ; + drive-strength =3D <12>; + }; + + conf-rx { + pins =3D "MIO37"; + bias-high-impedance; + }; + + conf-tx { + pins =3D "MIO36"; + bias-disable; + output-enable; + }; + + mux { + groups =3D "uart1_9_grp"; + function =3D "uart1"; + }; + }; + + pinctrl_i2c1_default: i2c1-default { + conf { + groups =3D "i2c1_6_grp"; + bias-pull-up; + slew-rate =3D ; + power-source =3D ; + }; + + mux { + groups =3D "i2c1_6_grp"; + function =3D "i2c1"; + }; + }; + + pinctrl_i2c1_gpio: i2c1-gpio-grp { + conf { + groups =3D "gpio0_24_grp", "gpio0_25_grp"; + slew-rate =3D ; + power-source =3D ; + }; + + mux { + groups =3D "gpio0_24_grp", "gpio0_25_grp"; + function =3D "gpio0"; + }; + }; + + pinctrl_gem1_default: gem1-default { + conf { + groups =3D "ethernet1_0_grp"; + slew-rate =3D ; + power-source =3D ; + }; + + conf-rx { + pins =3D "MIO44", "MIO46", "MIO48"; + bias-high-impedance; + low-power-disable; + }; + + conf-bootstrap { + pins =3D "MIO45", "MIO47", "MIO49"; + bias-disable; + output-enable; + low-power-disable; + }; + + conf-tx { + pins =3D "MIO38", "MIO39", "MIO40", + "MIO41", "MIO42", "MIO43"; + bias-disable; + output-enable; + low-power-enable; + }; + + conf-mdio { + groups =3D "mdio1_0_grp"; + slew-rate =3D ; + power-source =3D ; + bias-disable; + output-enable; + }; + + mux-mdio { + function =3D "mdio1"; + groups =3D "mdio1_0_grp"; + }; + + mux { + function =3D "ethernet1"; + groups =3D "ethernet1_0_grp"; + }; + }; + + pinctrl_usb0_default: usb0-default { + conf { + groups =3D "usb0_0_grp"; + power-source =3D ; + }; + + conf-rx { + pins =3D "MIO52", "MIO53", "MIO55"; + bias-high-impedance; + drive-strength =3D <12>; + slew-rate =3D ; + }; + + conf-tx { + pins =3D "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", + "MIO60", "MIO61", "MIO62", "MIO63"; + bias-disable; + output-enable; + drive-strength =3D <4>; + slew-rate =3D ; + }; + + mux { + groups =3D "usb0_0_grp"; + function =3D "usb0"; + }; + }; + + pinctrl_usb1_default: usb1-default { + conf { + groups =3D "usb1_0_grp"; + power-source =3D ; + }; + + conf-rx { + pins =3D "MIO64", "MIO65", "MIO67"; + bias-high-impedance; + drive-strength =3D <12>; + slew-rate =3D ; + }; + + conf-tx { + pins =3D "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", + "MIO72", "MIO73", "MIO74", "MIO75"; + bias-disable; + output-enable; + drive-strength =3D <4>; + slew-rate =3D ; + }; + + mux { + groups =3D "usb1_0_grp"; + function =3D "usb1"; + }; + }; +}; + +&uart1 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart1_default>; +}; --=20 2.43.0 From nobody Mon Oct 6 17:02:11 2025 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2077.outbound.protection.outlook.com [40.107.220.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0FC532D8DA1; Fri, 18 Jul 2025 11:24:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.220.77 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752837875; cv=fail; b=QyRYEcHlsuXsUhe5ViMn9JnSid6bK8KBfuh5ef0WqlY2h5uY/lq1NejBZAauyP5JAGO2var520dSJOmEJYKw66b6mcPkcdTjOGVW3Gi3avJ7AOhkSe7UKtN9ZMu8BIiCkqVcSms97ATQHHLAv6/94w98NTlfAX2BWrmQ60jIZt4= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752837875; c=relaxed/simple; bh=jIUZUlHT7s5cIOBFbdeB/PWThVqOU+TSdbF2sxzfa3U=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=iVAhlugM78IxyvKvZuu4hF8yYvVwZK7IfKFJ2UrFn1bUAE0DX6/HLrSh7MoS+JQL+MS4ah16cGwBpRhiB68Bl2pKxYwQgvo18blpL5jAUfvBW1PxOBXlb9I7K3FI00nEHFkf4VuO2mNcWzleHBdd3n/4VTkD8XYATwmIERkDmwo= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com; spf=fail smtp.mailfrom=amd.com; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b=sbYYfUac; arc=fail smtp.client-ip=40.107.220.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=amd.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="sbYYfUac" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=xQeIiiQCqP4CBTzBePNVvCXV1vuG3/RqvZYAAWQa1gnO3h4s78N81Z2WfwmzSO0QhaaWPRvf0cEsSO2XMlvZzTkWnT/r2wGuT02o5897honRlTnjCKBPVSM4+rU+c24a6LNmnbt+SG7dkvSbNlwYdEfdb3emPLiaHIzLhSIbGvaDnwgRtFZ7ix5ueg4E4kkaU1sxTIToYfVTm9RKYgbGkq72OvpHnVLuOxbKEY2xU5bkcp4YsNdE/pYBeaVd8OtspytYTDctl+hnPhzuqXOEgjUp5FeWIVHsJYz/MjRWpZ9J5tdnjruE0s+Sb8dChb1HCg536kpd9Xid20Ev2MuoWQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=3+J7i+QNvf36wOIqSZ6unwmt5DktLmKFsOj0EAaS4kY=; b=DGUBLZIu/Od9EbWuCKqLr4v1bdemIctOGfuQGICTp+h7sg2IT5gTsZ66n3XPJtp4+Vq5KvJxu9xUm9O3wiXdsazVygD6d8a4/1f6qQvQxsoF7b4H4kpBFYQbVcim4+Emi3qWTfmacNqPYS2+R4Hue4UFwy4RYs336C/zWOdOHxbEKBAyrG4zTV7skQG7l81HtbOj/yawCSlN8dSD8wGeIZkWsXFufhiq24PJMaG0OunqH6knBLHwe809EZ76CELT1UtNhTsJ3bKu2F8PuDZx/dsvazdZ8gR4XlCDeOxR6n+JVeFv6y/llP1G11ErsO854YGnSs+UdaYjV6YPKalCBg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=3+J7i+QNvf36wOIqSZ6unwmt5DktLmKFsOj0EAaS4kY=; b=sbYYfUacJvu8E0Yy0wH/m80sE9n1G+GbQK6v69Vu5JzwS10W7mVgraBy2b+us1CMjHkmiz5dVnfpkm/L+0gyHfNxZ6KVX3hda3O4ISBUMmYcidIZ7gvFpaYykmbYi7gcfioIwGa9lFj/578peXuetr0wrbwsADMGWGn45UHjqg4= Received: from CH0P223CA0010.NAMP223.PROD.OUTLOOK.COM (2603:10b6:610:116::20) by DS0PR12MB9728.namprd12.prod.outlook.com (2603:10b6:8:226::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8901.21; Fri, 18 Jul 2025 11:24:31 +0000 Received: from DS3PEPF000099DB.namprd04.prod.outlook.com (2603:10b6:610:116:cafe::74) by CH0P223CA0010.outlook.office365.com (2603:10b6:610:116::20) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8943.23 via Frontend Transport; Fri, 18 Jul 2025 11:24:31 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DS3PEPF000099DB.mail.protection.outlook.com (10.167.17.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8943.21 via Frontend Transport; Fri, 18 Jul 2025 11:24:31 +0000 Received: from SATLEXMB06.amd.com (10.181.40.147) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 18 Jul 2025 06:24:28 -0500 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB06.amd.com (10.181.40.147) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 18 Jul 2025 06:24:26 -0500 Received: from localhost (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39 via Frontend Transport; Fri, 18 Jul 2025 06:24:25 -0500 From: Michal Simek To: , , , CC: Conor Dooley , Krzysztof Kozlowski , Rob Herring , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "moderated list:ARM/ZYNQ ARCHITECTURE" Subject: [PATCH 3/3] arm64: zynqmp: Add support for kd240 board Date: Fri, 18 Jul 2025 13:24:08 +0200 Message-ID: <05ff505c6b6517e3aba983a21454c568c5e86389.1752837842.git.michal.simek@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=12562; i=michal.simek@amd.com; h=from:subject:message-id; bh=jIUZUlHT7s5cIOBFbdeB/PWThVqOU+TSdbF2sxzfa3U=; b=owGbwMvMwCG2mv3fB7+vgl8ZT6slMWRU6d34cfLQJy7NnlsBwmkM69aa9Qewv5HtkJo1KSzl+ vHIpfkrOkpZGMQ4GGTFFFmmM+k4rPl2banY8sh8mDmsTCBDGLg4BWAiInwM/+wPNMZPs9nCnLPe cXLvMpV7CUpTnHcrrOwKsl2pafpOQZXhn0150tk7m9e3NXvckpwTWd0585+O8IIWo2gzrR1fe2X 52QE= X-Developer-Key: i=michal.simek@amd.com; a=openpgp; fpr=67350C9BF5CCEE9B5364356A377C7F21FE3D1F91 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099DB:EE_|DS0PR12MB9728:EE_ X-MS-Office365-Filtering-Correlation-Id: afdf6543-2e21-4047-0bb2-08ddc5edaaaf X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?KH2ywSR/kKCe+ArMZFC4ePaWlfhZOr3ZiXkATloEGhBia6DqgzCu6IV3qll+?= =?us-ascii?Q?qnphArPgKbP/KkEviOeCgGo+McMRG+C/CUSAvVu7rLEjS8svJtYpRWhKpzGr?= =?us-ascii?Q?sceDsQkARj+aSjOE0TNH2cOBjn0qZ1utuxYvMXDBd6sH99be4LIV9BwHa9B/?= =?us-ascii?Q?FnxUr85e9HbE0UbItUiP+gfs6QVnTveenkFvPPiIVB2mF+HbhCKMIynQ4s1A?= =?us-ascii?Q?dQlcIAz0yONJ7oloeX+/wwKUpDbdENARqR7OWAheTNzdPCq+PojYv3bxuWn1?= =?us-ascii?Q?n/9RmHE6qS8KsqQTycLFjQA3Hzscf1kmI8Y7uUxtiyMWOfSYJTsp3623S42i?= =?us-ascii?Q?yF6IX8JzoioaRzOF2Y+/q1lJjo0yWoiG+xyFaq4z/GP466ta0TmI4MT7WPKV?= =?us-ascii?Q?Gz6uwZoCz72titSheA8ZMb6gwjMCUpomdjMblkvsmo6mkyls4zo+Q4XMCRha?= =?us-ascii?Q?94WbJ14KXIkOyLwhyQd9CakLA8OlkpravEmILiL+q1qfrWLKwaHsxmOJeL+Q?= =?us-ascii?Q?mpnnTwZ5Z32tdI17W8fMM8QvNdtfq/YMfmdpYeyn1S9INUKx2CKezE10fudW?= =?us-ascii?Q?NTocOeURhKNAjcP4GlnHvgBgjiBAjCB6svTfpKPGafywFftIfKAneaC6pDPF?= =?us-ascii?Q?CSsGmD3JmUpeISgTGVbJvhrmRASXgCC/0ZjI5fol2IwM+1CA2frsuc0/Ur3z?= =?us-ascii?Q?bM5O4H37Xz8XpCr2iXLEIe99FHaNTtKC5Fu9niivDxCS2TMLksdMob/PmOTP?= =?us-ascii?Q?mQb9u9RFFliO1QCEiJxCtLkiPll21un2/M0tO6IU260IMJoWVqMjQHH+87Ep?= =?us-ascii?Q?93HHiVy32qUfehYGSIxMv6s0BFRjeKYFIvRuyDzM+3U3u/5e+oMSd3SW/Jf5?= =?us-ascii?Q?iokPEss8SIM7ZeypEaWkRhhNQNUcXQBm/EfdkTVffVDyx4gV8/1mirutDPol?= =?us-ascii?Q?UKvFndcQTfGTCROxbqQlPrjAmra+Wb2Fi7NyBBGWvRC94AHBXTu1F9Z2qRxZ?= =?us-ascii?Q?5sXR9958AOvn9LBcZqR/r6JB8xrgR1J9p5QOoKAyGaKiw57axo06Ld2z/eD6?= =?us-ascii?Q?M3RhRAGCbtZ7Ptt6VVCPjfYxio6/gNia1PHjCaI4YDK0DenAHCoB1SSP3edC?= =?us-ascii?Q?Bg8RBkiDVTXiKRVmxAS3qEDOedr+GwhupJ66+iNmS84pH+1VYnt6O/Ni7ZC7?= =?us-ascii?Q?B4es2DfzFWCrVWTaQNv/E5OJt+SuE0jIdoy94tF5SM3Fz6led/Ra5C9iReB/?= =?us-ascii?Q?gYHm+UUWttwm4xK3G7PtGHSMSLuz/MdeLVW2/o2hIOmoUzeBpDKK6nv9Y0Ju?= =?us-ascii?Q?CnxZgkR/AuPBSWNzWPa89h0FFV0VplywzVsuLbu2hUdnYzqUGmdOOPPuUDf1?= =?us-ascii?Q?cUo5CYxx8GLpCvlajs7CYrkhrc0CfIvjfx4erX0R5NDXvvali9EyrDI7sqqm?= =?us-ascii?Q?atHerijF6Xavsv1eL3gQ4iw1ZBl3jRKA885oarOMPGm/LjuqE/07jrxOi2HY?= =?us-ascii?Q?cRGksBVVkgcFsrrThy4TZ52CozfwpgWulXsgSKlnsnayC2tTtZZ6Ja6cKQ?= =?us-ascii?Q?=3D=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jul 2025 11:24:31.7216 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: afdf6543-2e21-4047-0bb2-08ddc5edaaaf X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099DB.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB9728 Content-Type: text/plain; charset="utf-8" The kit is using k24 SOM by default and it is used for motor control and DSP applications. K24 SOM is also possible to used with kv260 and kr260 CC which are also wired in Makefile. Signed-off-by: Michal Simek --- https://www.amd.com/en/products/system-on-modules/kria/k24/k24i-industrial.= html https://www.amd.com/en/products/system-on-modules/kria/k24/kd240-drives-sta= rter-kit.html --- arch/arm64/boot/dts/xilinx/Makefile | 15 + .../boot/dts/xilinx/zynqmp-sck-kd-g-revA.dtso | 390 ++++++++++++++++++ .../boot/dts/xilinx/zynqmp-sm-k24-revA.dts | 23 ++ .../boot/dts/xilinx/zynqmp-smk-k24-revA.dts | 21 + 4 files changed, 449 insertions(+) create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-sck-kd-g-revA.dtso create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-sm-k24-revA.dts create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-smk-k24-revA.dts diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xili= nx/Makefile index 5e84e3c725e2..70fac0b276df 100644 --- a/arch/arm64/boot/dts/xilinx/Makefile +++ b/arch/arm64/boot/dts/xilinx/Makefile @@ -39,4 +39,19 @@ dtb-$(CONFIG_ARCH_ZYNQMP) +=3D zynqmp-smk-k26-revA-sck-k= r-g-revA.dtb zynqmp-smk-k26-revA-sck-kr-g-revB-dtbs :=3D zynqmp-smk-k26-revA.dtb zynqmp= -sck-kr-g-revB.dtbo dtb-$(CONFIG_ARCH_ZYNQMP) +=3D zynqmp-smk-k26-revA-sck-kr-g-revB.dtb =20 +zynqmp-sm-k24-revA-sck-kd-g-revA-dtbs :=3D zynqmp-sm-k24-revA.dtb zynqmp-s= ck-kd-g-revA.dtbo +dtb-$(CONFIG_ARCH_ZYNQMP) +=3D zynqmp-sm-k24-revA-sck-kd-g-revA.dtb +zynqmp-smk-k24-revA-sck-kd-g-revA-dtbs :=3D zynqmp-smk-k24-revA.dtb zynqmp= -sck-kd-g-revA.dtbo +dtb-$(CONFIG_ARCH_ZYNQMP) +=3D zynqmp-smk-k24-revA-sck-kd-g-revA.dtb + +zynqmp-sm-k24-revA-sck-kv-g-revB-dtbs :=3D zynqmp-sm-k24-revA.dtb zynqmp-s= ck-kv-g-revB.dtbo +dtb-$(CONFIG_ARCH_ZYNQMP) +=3D zynqmp-sm-k24-revA-sck-kv-g-revB.dtb +zynqmp-smk-k24-revA-sck-kv-g-revB-dtbs :=3D zynqmp-smk-k24-revA.dtb zynqmp= -sck-kv-g-revB.dtbo +dtb-$(CONFIG_ARCH_ZYNQMP) +=3D zynqmp-smk-k24-revA-sck-kv-g-revB.dtb + +zynqmp-sm-k24-revA-sck-kr-g-revB-dtbs :=3D zynqmp-sm-k24-revA.dtb zynqmp-s= ck-kr-g-revB.dtbo +dtb-$(CONFIG_ARCH_ZYNQMP) +=3D zynqmp-sm-k24-revA-sck-kr-g-revB.dtb +zynqmp-smk-k24-revA-sck-kr-g-revB-dtbs :=3D zynqmp-smk-k24-revA.dtb zynqmp= -sck-kr-g-revB.dtbo +dtb-$(CONFIG_ARCH_ZYNQMP) +=3D zynqmp-smk-k24-revA-sck-kr-g-revB.dtb + dtb-$(CONFIG_ARCH_ZYNQMP) +=3D versal-net-vn-x-b2197-01-revA.dtb diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kd-g-revA.dtso b/arch/ar= m64/boot/dts/xilinx/zynqmp-sck-kd-g-revA.dtso new file mode 100644 index 000000000000..02be5e1e8686 --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kd-g-revA.dtso @@ -0,0 +1,390 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for KD240 revA Carrier Card + * + * Copyright (C) 2021 - 2022, Xilinx, Inc. + * Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc. + * + * Michal Simek + */ + +#include +#include +#include + +/dts-v1/; +/plugin/; + +&{/} { + compatible =3D "xlnx,zynqmp-sk-kd240-rev1", + "xlnx,zynqmp-sk-kd240-revB", + "xlnx,zynqmp-sk-kd240-revA", + "xlnx,zynqmp-sk-kd240", "xlnx,zynqmp"; + model =3D "ZynqMP KD240 revA/B/1"; + + aliases { + ethernet0 =3D "/axi/ethernet@ff0c0000"; /* &gem1 */ + }; + + ina260-u3 { + compatible =3D "iio-hwmon"; + io-channels =3D <&u3 0>, <&u3 1>, <&u3 2>; + }; + + clk_26: clock2 { /* u17 - USB */ + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <26000000>; + }; + + clk_25_0: clock4 { /* u92/u91 - GEM2 */ + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <25000000>; + }; + + clk_25_1: clock5 { /* u92/u91 - GEM3 */ + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <25000000>; + }; +}; + +&can0 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_can0_default>; +}; + +&i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */ + #address-cells =3D <1>; + #size-cells =3D <0>; + pinctrl-names =3D "default", "gpio"; + pinctrl-0 =3D <&pinctrl_i2c1_default>; + pinctrl-1 =3D <&pinctrl_i2c1_gpio>; + scl-gpios =3D <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios =3D <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + u3: ina260@40 { /* u3 */ + compatible =3D "ti,ina260"; + #io-channel-cells =3D <1>; + label =3D "ina260-u14"; + reg =3D <0x40>; + }; + + slg7xl45106: gpio@11 { /* u13 - reset logic */ + compatible =3D "dlg,slg7xl45106"; + reg =3D <0x11>; + label =3D "resetchip"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D "USB0_PHY_RESET_B", "", + "SD_RESET_B", "USB0_HUB_RESET_B", + "", "PS_GEM0_RESET_B", + "", ""; + }; + + hub: usb-hub@2d { /* u36 */ + compatible =3D "microchip,usb5744"; + reg =3D <0x2d>; + }; +}; + +/* USB 3.0 */ +&psgtr { + status =3D "okay"; + /* usb */ + clocks =3D <&clk_26>; + clock-names =3D "ref2"; +}; + +&usb0 { /* mio52 - mio63 */ + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_usb0_default>; + phy-names =3D "usb3-phy"; + phys =3D <&psgtr 2 PHY_TYPE_USB3 0 2>; + reset-gpios =3D <&slg7xl45106 0 GPIO_ACTIVE_LOW>; + assigned-clock-rates =3D <250000000>, <20000000>; +}; + +&dwc3_0 { + status =3D "okay"; + dr_mode =3D "host"; + snps,usb3_lpm_capable; + maximum-speed =3D "super-speed"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + /* 2.0 hub on port 1 */ + hub_2_0: hub@1 { + compatible =3D "usb424,2744"; + reg =3D <1>; + peer-hub =3D <&hub_3_0>; + i2c-bus =3D <&hub>; + reset-gpios =3D <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + }; + + /* 3.0 hub on port 2 */ + hub_3_0: hub@2 { + compatible =3D "usb424,5744"; + reg =3D <2>; + peer-hub =3D <&hub_2_0>; + i2c-bus =3D <&hub>; + reset-gpios =3D <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + }; +}; + +&gem1 { /* mdio mio50/51 */ + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_gem1_default>; + assigned-clock-rates =3D <250000000>; + + phy-handle =3D <&phy0>; + phy-mode =3D "rgmii-id"; + mdio: mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + phy0: ethernet-phy@8 { /* Adin u31 */ + #phy-cells =3D <1>; + compatible =3D "ethernet-phy-id0283.bc30"; + reg =3D <8>; + adi,rx-internal-delay-ps =3D <2000>; + adi,tx-internal-delay-ps =3D <2000>; + adi,fifo-depth-bits =3D <8>; + reset-assert-us =3D <10>; + reset-deassert-us =3D <5000>; + reset-gpios =3D <&gpio 77 GPIO_ACTIVE_LOW>; + }; + }; +}; + +/* 2 more ethernet phys u32@2 and u34@3 */ + +&pinctrl0 { /* required by spec */ + status =3D "okay"; + + pinctrl_can0_default: can0-default { + mux { + function =3D "can0"; + groups =3D "can0_16_grp"; + }; + + conf { + groups =3D "can0_16_grp"; + slew-rate =3D ; + power-source =3D ; + }; + + conf-rx { + pins =3D "MIO66"; + bias-pull-up; + }; + + conf-tx { + pins =3D "MIO67"; + bias-pull-up; + drive-strength =3D <4>; + }; + }; + + pinctrl_uart0_default: uart0-default { + conf { + groups =3D "uart0_17_grp"; + slew-rate =3D ; + power-source =3D ; + drive-strength =3D <12>; + }; + + conf-rx { + pins =3D "MIO70"; + bias-high-impedance; + }; + + conf-tx { + pins =3D "MIO71"; + bias-disable; + }; + + mux { + groups =3D "uart0_17_grp"; + function =3D "uart0"; + }; + }; + + pinctrl_uart1_default: uart1-default { + conf { + groups =3D "uart1_9_grp"; + slew-rate =3D ; + power-source =3D ; + drive-strength =3D <12>; + }; + + conf-rx { + pins =3D "MIO37"; + bias-high-impedance; + }; + + conf-tx { + pins =3D "MIO36"; + bias-disable; + output-enable; + }; + + mux { + groups =3D "uart1_9_grp"; + function =3D "uart1"; + }; + }; + + pinctrl_i2c1_default: i2c1-default { + conf { + groups =3D "i2c1_6_grp"; + bias-pull-up; + slew-rate =3D ; + power-source =3D ; + }; + + mux { + groups =3D "i2c1_6_grp"; + function =3D "i2c1"; + }; + }; + + pinctrl_i2c1_gpio: i2c1-gpio-grp { + conf { + groups =3D "gpio0_24_grp", "gpio0_25_grp"; + slew-rate =3D ; + power-source =3D ; + }; + + mux { + groups =3D "gpio0_24_grp", "gpio0_25_grp"; + function =3D "gpio0"; + }; + }; + + pinctrl_gem1_default: gem1-default { + conf { + groups =3D "ethernet1_0_grp"; + slew-rate =3D ; + power-source =3D ; + }; + + conf-rx { + pins =3D "MIO45", "MIO46", "MIO47", "MIO48"; + bias-disable; + low-power-disable; + }; + + conf-bootstrap { + pins =3D "MIO44", "MIO49"; + bias-disable; + output-enable; + low-power-disable; + }; + + conf-tx { + pins =3D "MIO38", "MIO39", "MIO40", + "MIO41", "MIO42", "MIO43"; + bias-disable; + output-enable; + low-power-enable; + }; + + conf-mdio { + groups =3D "mdio1_0_grp"; + slew-rate =3D ; + power-source =3D ; + bias-disable; + output-enable; + }; + + mux-mdio { + function =3D "mdio1"; + groups =3D "mdio1_0_grp"; + }; + + mux { + function =3D "ethernet1"; + groups =3D "ethernet1_0_grp"; + }; + }; + + pinctrl_usb0_default: usb0-default { + conf { + groups =3D "usb0_0_grp"; + power-source =3D ; + }; + + conf-rx { + pins =3D "MIO52", "MIO53", "MIO55"; + bias-high-impedance; + drive-strength =3D <12>; + slew-rate =3D ; + }; + + conf-tx { + pins =3D "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", + "MIO60", "MIO61", "MIO62", "MIO63"; + bias-disable; + output-enable; + drive-strength =3D <4>; + slew-rate =3D ; + }; + + mux { + groups =3D "usb0_0_grp"; + function =3D "usb0"; + }; + }; + + pinctrl_usb1_default: usb1-default { + conf { + groups =3D "usb1_0_grp"; + power-source =3D ; + }; + + conf-rx { + pins =3D "MIO64", "MIO65", "MIO67"; + bias-high-impedance; + drive-strength =3D <12>; + slew-rate =3D ; + }; + + conf-tx { + pins =3D "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", + "MIO72", "MIO73", "MIO74", "MIO75"; + bias-disable; + output-enable; + drive-strength =3D <4>; + slew-rate =3D ; + }; + + mux { + groups =3D "usb1_0_grp"; + function =3D "usb1"; + }; + }; +}; + +&uart0 { + status =3D "okay"; + rts-gpios =3D <&gpio 72 GPIO_ACTIVE_HIGH>; + linux,rs485-enabled-at-boot-time; + rs485-rts-delay =3D <10 10>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart0_default>; + assigned-clock-rates =3D <100000000>; +}; + +&uart1 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart1_default>; +}; + +&zynqmp_dpsub { + status =3D "disabled"; +}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k24-revA.dts b/arch/arm64= /boot/dts/xilinx/zynqmp-sm-k24-revA.dts new file mode 100644 index 000000000000..653bd9362264 --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k24-revA.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP SM-K24 RevA + * + * (C) Copyright 2020 - 2021, Xilinx, Inc. + * (C) Copyright 2022, Advanced Micro Devices, Inc. + * + * Michal Simek + */ + +#include "zynqmp-sm-k26-revA.dts" + +/ { + model =3D "ZynqMP SM-K24 RevA/B/1"; + compatible =3D "xlnx,zynqmp-sm-k24-rev1", "xlnx,zynqmp-sm-k24-revB", + "xlnx,zynqmp-sm-k24-revA", "xlnx,zynqmp-sm-k24", + "xlnx,zynqmp"; + + memory@0 { + device_type =3D "memory"; /* 2GB */ + reg =3D <0 0 0 0x80000000>; + }; +}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-smk-k24-revA.dts b/arch/arm6= 4/boot/dts/xilinx/zynqmp-smk-k24-revA.dts new file mode 100644 index 000000000000..7308983b15a0 --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/zynqmp-smk-k24-revA.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP SMK-K24 RevA + * + * (C) Copyright 2020 - 2021, Xilinx, Inc. + * (C) Copyright 2022, Advanced Micro Devices, Inc. + * + * Michal Simek + */ + +#include "zynqmp-sm-k24-revA.dts" + +/ { + model =3D "ZynqMP SMK-K24 RevA"; + compatible =3D "xlnx,zynqmp-smk-k24-revA", "xlnx,zynqmp-smk-k24", + "xlnx,zynqmp"; +}; + +&sdhci0 { + status =3D "disabled"; +}; --=20 2.43.0