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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SJ1PEPF00001CE4.mail.protection.outlook.com (10.167.242.20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8922.22 via Frontend Transport; Tue, 15 Jul 2025 19:27:02 +0000 Received: from ethanolx7e2ehost.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 15 Jul 2025 14:26:59 -0500 From: Ashish Kalra To: , , , , , CC: , , , , , , , , , , , Subject: [PATCH v3 1/4] iommu/amd: Add support to remap/unmap IOMMU buffers for kdump Date: Tue, 15 Jul 2025 19:26:50 +0000 Message-ID: <7c7e241f960759934aced9a04d7620d204ad5d68.1752605725.git.ashish.kalra@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Jul 2025 19:27:02.6021 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ab85c45d-5a09-4968-f89a-08ddc3d5938c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE4.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6113 From: Ashish Kalra After a panic if SNP is enabled in the previous kernel then the kdump kernel boots with IOMMU SNP enforcement still enabled. IOMMU completion wait buffers (CWBs), command buffers and event buffer registers remain locked and exclusive to the previous kernel. Attempts to allocate and use new buffers in the kdump kernel fail, as hardware ignores writes to the locked MMIO registers as per AMD IOMMU spec Section 2.12.2.1. This results in repeated "Completion-Wait loop timed out" errors and a second kernel panic: "Kernel panic - not syncing: timer doesn't work through Interrupt-remapped IO-APIC" The following MMIO registers are locked and ignore writes after failed SNP shutdown: Command Buffer Base Address Register Event Log Base Address Register Completion Store Base Register/Exclusion Base Register Completion Store Limit Register/Exclusion Limit Register As a result, the kdump kernel cannot initialize the IOMMU or enable IRQ remapping, which is required for proper operation. Reuse the pages of the previous kernel for completion wait buffers, command buffers, event buffers and memremap them during kdump boot and essentially work with an already enabled IOMMU configuration and re-using the previous kernel=E2=80=99s data structures. Reusing of command buffers and event buffers is now done for kdump boot irrespective of SNP being enabled during kdump. Re-use of completion wait buffers is only done when SNP is enabled as the exclusion base register is used for the completion wait buffer (CWB) address only when SNP is enabled. Signed-off-by: Ashish Kalra --- drivers/iommu/amd/amd_iommu_types.h | 5 + drivers/iommu/amd/init.c | 163 ++++++++++++++++++++++++++-- drivers/iommu/amd/iommu.c | 2 +- 3 files changed, 157 insertions(+), 13 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_io= mmu_types.h index 9b64cd706c96..082eb1270818 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -791,6 +791,11 @@ struct amd_iommu { u32 flags; volatile u64 *cmd_sem; atomic64_t cmd_sem_val; + /* + * Track physical address to directly use it in build_completion_wait() + * and avoid adding any special checks and handling for kdump. + */ + u64 cmd_sem_paddr; =20 #ifdef CONFIG_AMD_IOMMU_DEBUGFS /* DebugFS Info */ diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index cadb2c735ffc..32295f26be1b 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -710,6 +710,23 @@ static void __init free_alias_table(struct amd_iommu_p= ci_seg *pci_seg) pci_seg->alias_table =3D NULL; } =20 +static inline void *iommu_memremap(unsigned long paddr, size_t size) +{ + phys_addr_t phys; + + if (!paddr) + return NULL; + + /* + * Obtain true physical address in kdump kernel when SME is enabled. + * Currently, IOMMU driver does not support booting into an unencrypted + * kdump kernel. + */ + phys =3D __sme_clr(paddr); + + return ioremap_encrypted(phys, size); +} + /* * Allocates the command buffer. This buffer is per AMD IOMMU. We can * write commands to that buffer later and the IOMMU will execute them @@ -942,8 +959,105 @@ static int iommu_init_ga_log(struct amd_iommu *iommu) static int __init alloc_cwwb_sem(struct amd_iommu *iommu) { iommu->cmd_sem =3D iommu_alloc_4k_pages(iommu, GFP_KERNEL, 1); + if (!iommu->cmd_sem) + return -ENOMEM; + iommu->cmd_sem_paddr =3D iommu_virt_to_phys((void *)iommu->cmd_sem); + return 0; +} + +static int __init remap_event_buffer(struct amd_iommu *iommu) +{ + u64 paddr; + + pr_info_once("Re-using event buffer from the previous kernel\n"); + /* + * Read-back the event log base address register and apply + * PM_ADDR_MASK to obtain the event log base address. + */ + paddr =3D readq(iommu->mmio_base + MMIO_EVT_BUF_OFFSET) & PM_ADDR_MASK; + iommu->evt_buf =3D iommu_memremap(paddr, EVT_BUFFER_SIZE); + + return iommu->evt_buf ? 0 : -ENOMEM; +} + +static int __init remap_command_buffer(struct amd_iommu *iommu) +{ + u64 paddr; + + pr_info_once("Re-using command buffer from the previous kernel\n"); + /* + * Read-back the command buffer base address register and apply + * PM_ADDR_MASK to obtain the command buffer base address. + */ + paddr =3D readq(iommu->mmio_base + MMIO_CMD_BUF_OFFSET) & PM_ADDR_MASK; + iommu->cmd_buf =3D iommu_memremap(paddr, CMD_BUFFER_SIZE); + + return iommu->cmd_buf ? 0 : -ENOMEM; +} + +static int __init remap_cwwb_sem(struct amd_iommu *iommu) +{ + u64 paddr; + + if (check_feature(FEATURE_SNP)) { + /* + * When SNP is enabled, the exclusion base register is used for the + * completion wait buffer (CWB) address. Read and re-use it. + */ + pr_info_once("Re-using CWB buffers from the previous kernel\n"); + /* + * Read-back the exclusion base register and apply PM_ADDR_MASK + * to obtain the exclusion range base address. + */ + paddr =3D readq(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET) & PM_ADDR_MASK; + iommu->cmd_sem =3D iommu_memremap(paddr, PAGE_SIZE); + if (!iommu->cmd_sem) + return -ENOMEM; + iommu->cmd_sem_paddr =3D paddr; + } else { + return alloc_cwwb_sem(iommu); + } + + return 0; +} + +static int __init alloc_iommu_buffers(struct amd_iommu *iommu) +{ + int ret; + + /* + * IOMMU Completion Store Base MMIO, Command Buffer Base Address MMIO + * registers are locked if SNP is enabled during kdump, reuse/remap + * the previous kernel's allocated completion wait and command buffers + * for kdump boot. + */ + if (is_kdump_kernel()) { + ret =3D remap_cwwb_sem(iommu); + if (ret) + return ret; + + ret =3D remap_command_buffer(iommu); + if (ret) + return ret; + + ret =3D remap_event_buffer(iommu); + if (ret) + return ret; + } else { + ret =3D alloc_cwwb_sem(iommu); + if (ret) + return ret; + + ret =3D alloc_command_buffer(iommu); + if (ret) + return ret; =20 - return iommu->cmd_sem ? 0 : -ENOMEM; + ret =3D alloc_event_buffer(iommu); + if (ret) + return ret; + } + + return 0; } =20 static void __init free_cwwb_sem(struct amd_iommu *iommu) @@ -951,6 +1065,38 @@ static void __init free_cwwb_sem(struct amd_iommu *io= mmu) if (iommu->cmd_sem) iommu_free_pages((void *)iommu->cmd_sem); } +static void __init unmap_cwwb_sem(struct amd_iommu *iommu) +{ + if (iommu->cmd_sem) { + if (check_feature(FEATURE_SNP)) + memunmap((void *)iommu->cmd_sem); + else + iommu_free_pages((void *)iommu->cmd_sem); + } +} + +static void __init unmap_command_buffer(struct amd_iommu *iommu) +{ + memunmap((void *)iommu->cmd_buf); +} + +static void __init unmap_event_buffer(struct amd_iommu *iommu) +{ + memunmap(iommu->evt_buf); +} + +static void __init free_iommu_buffers(struct amd_iommu *iommu) +{ + if (is_kdump_kernel()) { + unmap_cwwb_sem(iommu); + unmap_command_buffer(iommu); + unmap_event_buffer(iommu); + } else { + free_cwwb_sem(iommu); + free_command_buffer(iommu); + free_event_buffer(iommu); + } +} =20 static void iommu_enable_xt(struct amd_iommu *iommu) { @@ -1655,9 +1801,7 @@ static void __init free_sysfs(struct amd_iommu *iommu) static void __init free_iommu_one(struct amd_iommu *iommu) { free_sysfs(iommu); - free_cwwb_sem(iommu); - free_command_buffer(iommu); - free_event_buffer(iommu); + free_iommu_buffers(iommu); amd_iommu_free_ppr_log(iommu); free_ga_log(iommu); iommu_unmap_mmio_space(iommu); @@ -1821,14 +1965,9 @@ static int __init init_iommu_one_late(struct amd_iom= mu *iommu) { int ret; =20 - if (alloc_cwwb_sem(iommu)) - return -ENOMEM; - - if (alloc_command_buffer(iommu)) - return -ENOMEM; - - if (alloc_event_buffer(iommu)) - return -ENOMEM; + ret =3D alloc_iommu_buffers(iommu); + if (ret) + return ret; =20 iommu->int_enabled =3D false; =20 diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 7dc6d2dd8dd1..8e1b475e39c7 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -1201,7 +1201,7 @@ static void build_completion_wait(struct iommu_cmd *c= md, struct amd_iommu *iommu, u64 data) { - u64 paddr =3D iommu_virt_to_phys((void *)iommu->cmd_sem); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Jul 2025 19:27:20.8882 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f503860a-3b6b-4b16-d88a-08ddc3d59e8e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CEB.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8459 Content-Type: text/plain; charset="utf-8" From: Ashish Kalra After a panic if SNP is enabled in the previous kernel then the kdump kernel boots with IOMMU SNP enforcement still enabled. IOMMU device table register is locked and exclusive to the previous kernel. Attempts to copy old device table from the previous kernel fails in kdump kernel as hardware ignores writes to the locked device table base address register as per AMD IOMMU spec Section 2.12.2.1. This results in repeated "Completion-Wait loop timed out" errors and a second kernel panic: "Kernel panic - not syncing: timer doesn't work through Interrupt-remapped IO-APIC". Reuse device table instead of copying device table in case of kdump boot and remove all copying device table code. Signed-off-by: Ashish Kalra --- drivers/iommu/amd/init.c | 97 ++++++++++++---------------------------- 1 file changed, 28 insertions(+), 69 deletions(-) diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index 32295f26be1b..18bd869a82d9 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -406,6 +406,9 @@ static void iommu_set_device_table(struct amd_iommu *io= mmu) =20 BUG_ON(iommu->mmio_base =3D=3D NULL); =20 + if (is_kdump_kernel()) + return; + entry =3D iommu_virt_to_phys(dev_table); entry |=3D (dev_table_size >> 12) - 1; memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET, @@ -646,7 +649,10 @@ static inline int __init alloc_dev_table(struct amd_io= mmu_pci_seg *pci_seg) =20 static inline void free_dev_table(struct amd_iommu_pci_seg *pci_seg) { - iommu_free_pages(pci_seg->dev_table); + if (is_kdump_kernel()) + memunmap((void *)pci_seg->dev_table); + else + iommu_free_pages(pci_seg->dev_table); pci_seg->dev_table =3D NULL; } =20 @@ -1128,15 +1134,12 @@ static void set_dte_bit(struct dev_table_entry *dte= , u8 bit) dte->data[i] |=3D (1UL << _bit); } =20 -static bool __copy_device_table(struct amd_iommu *iommu) +static bool __reuse_device_table(struct amd_iommu *iommu) { - u64 int_ctl, int_tab_len, entry =3D 0; struct amd_iommu_pci_seg *pci_seg =3D iommu->pci_seg; - struct dev_table_entry *old_devtb =3D NULL; - u32 lo, hi, devid, old_devtb_size; + u32 lo, hi, old_devtb_size; phys_addr_t old_devtb_phys; - u16 dom_id, dte_v, irq_v; - u64 tmp; + u64 entry; =20 /* Each IOMMU use separate device table with the same size */ lo =3D readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET); @@ -1161,66 +1164,22 @@ static bool __copy_device_table(struct amd_iommu *i= ommu) pr_err("The address of old device table is above 4G, not trustworthy!\n"= ); return false; } - old_devtb =3D (cc_platform_has(CC_ATTR_HOST_MEM_ENCRYPT) && is_kdump_kern= el()) - ? (__force void *)ioremap_encrypted(old_devtb_phys, - pci_seg->dev_table_size) - : memremap(old_devtb_phys, pci_seg->dev_table_size, MEMREMAP_WB); - - if (!old_devtb) - return false; =20 - pci_seg->old_dev_tbl_cpy =3D iommu_alloc_pages_sz( - GFP_KERNEL | GFP_DMA32, pci_seg->dev_table_size); + /* + * IOMMU Device Table Base Address MMIO register is locked + * if SNP is enabled during kdump, reuse the previous kernel's + * device table. + */ + pci_seg->old_dev_tbl_cpy =3D iommu_memremap(old_devtb_phys, pci_seg->dev_= table_size); if (pci_seg->old_dev_tbl_cpy =3D=3D NULL) { - pr_err("Failed to allocate memory for copying old device table!\n"); - memunmap(old_devtb); + pr_err("Failed to remap memory for reusing old device table!\n"); return false; } =20 - for (devid =3D 0; devid <=3D pci_seg->last_bdf; ++devid) { - pci_seg->old_dev_tbl_cpy[devid] =3D old_devtb[devid]; - dom_id =3D old_devtb[devid].data[1] & DEV_DOMID_MASK; - dte_v =3D old_devtb[devid].data[0] & DTE_FLAG_V; - - if (dte_v && dom_id) { - pci_seg->old_dev_tbl_cpy[devid].data[0] =3D old_devtb[devid].data[0]; - pci_seg->old_dev_tbl_cpy[devid].data[1] =3D old_devtb[devid].data[1]; - /* Reserve the Domain IDs used by previous kernel */ - if (ida_alloc_range(&pdom_ids, dom_id, dom_id, GFP_ATOMIC) !=3D dom_id)= { - pr_err("Failed to reserve domain ID 0x%x\n", dom_id); - memunmap(old_devtb); - return false; - } - /* If gcr3 table existed, mask it out */ - if (old_devtb[devid].data[0] & DTE_FLAG_GV) { - tmp =3D (DTE_GCR3_30_15 | DTE_GCR3_51_31); - pci_seg->old_dev_tbl_cpy[devid].data[1] &=3D ~tmp; - tmp =3D (DTE_GCR3_14_12 | DTE_FLAG_GV); - pci_seg->old_dev_tbl_cpy[devid].data[0] &=3D ~tmp; - } - } - - irq_v =3D old_devtb[devid].data[2] & DTE_IRQ_REMAP_ENABLE; - int_ctl =3D old_devtb[devid].data[2] & DTE_IRQ_REMAP_INTCTL_MASK; - int_tab_len =3D old_devtb[devid].data[2] & DTE_INTTABLEN_MASK; - if (irq_v && (int_ctl || int_tab_len)) { - if ((int_ctl !=3D DTE_IRQ_REMAP_INTCTL) || - (int_tab_len !=3D DTE_INTTABLEN_512 && - int_tab_len !=3D DTE_INTTABLEN_2K)) { - pr_err("Wrong old irq remapping flag: %#x\n", devid); - memunmap(old_devtb); - return false; - } - - pci_seg->old_dev_tbl_cpy[devid].data[2] =3D old_devtb[devid].data[2]; - } - } - memunmap(old_devtb); - return true; } =20 -static bool copy_device_table(void) +static bool reuse_device_table(void) { struct amd_iommu *iommu; struct amd_iommu_pci_seg *pci_seg; @@ -1228,17 +1187,17 @@ static bool copy_device_table(void) if (!amd_iommu_pre_enabled) return false; =20 - pr_warn("Translation is already enabled - trying to copy translation stru= ctures\n"); + pr_warn("Translation is already enabled - trying to reuse translation str= uctures\n"); =20 /* * All IOMMUs within PCI segment shares common device table. - * Hence copy device table only once per PCI segment. + * Hence reuse device table only once per PCI segment. */ for_each_pci_segment(pci_seg) { for_each_iommu(iommu) { if (pci_seg->id !=3D iommu->pci_seg->id) continue; - if (!__copy_device_table(iommu)) + if (!__reuse_device_table(iommu)) return false; break; } @@ -2917,8 +2876,8 @@ static void early_enable_iommu(struct amd_iommu *iomm= u) * This function finally enables all IOMMUs found in the system after * they have been initialized. * - * Or if in kdump kernel and IOMMUs are all pre-enabled, try to copy - * the old content of device table entries. Not this case or copy failed, + * Or if in kdump kernel and IOMMUs are all pre-enabled, try to reuse + * the old content of device table entries. Not this case or reuse failed, * just continue as normal kernel does. */ static void early_enable_iommus(void) @@ -2926,18 +2885,18 @@ static void early_enable_iommus(void) struct amd_iommu *iommu; struct amd_iommu_pci_seg *pci_seg; =20 - if (!copy_device_table()) { + if (!reuse_device_table()) { /* - * If come here because of failure in copying device table from old + * If come here because of failure in reusing device table from old * kernel with all IOMMUs enabled, print error message and try to * free allocated old_dev_tbl_cpy. */ if (amd_iommu_pre_enabled) - pr_err("Failed to copy DEV table from previous kernel.\n"); + pr_err("Failed to reuse DEV table from previous kernel.\n"); =20 for_each_pci_segment(pci_seg) { if (pci_seg->old_dev_tbl_cpy !=3D NULL) { - iommu_free_pages(pci_seg->old_dev_tbl_cpy); + memunmap((void *)pci_seg->old_dev_tbl_cpy); pci_seg->old_dev_tbl_cpy =3D NULL; } } @@ -2947,7 +2906,7 @@ static void early_enable_iommus(void) early_enable_iommu(iommu); } } else { - pr_info("Copied DEV table from previous kernel.\n"); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Jul 2025 19:27:40.7003 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a63fc0e7-81e3-4986-8384-08ddc3d5aa41 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CEB.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH1PR12MB9669 Content-Type: text/plain; charset="utf-8" From: Ashish Kalra If SNP is enabled and initialized in the previous kernel then SNP is already initialized for kdump boot and attempting SNP INIT again during kdump boot causes SNP INIT failure and eventually leads to IOMMU failures. Skip SNP INIT if doing kdump boot. Signed-off-by: Ashish Kalra --- drivers/crypto/ccp/sev-dev.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/crypto/ccp/sev-dev.c b/drivers/crypto/ccp/sev-dev.c index 17edc6bf5622..19df68963602 100644 --- a/drivers/crypto/ccp/sev-dev.c +++ b/drivers/crypto/ccp/sev-dev.c @@ -28,6 +28,7 @@ #include #include #include +#include =20 #include #include @@ -1114,6 +1115,13 @@ static int __sev_snp_init_locked(int *error) if (!cc_platform_has(CC_ATTR_HOST_SEV_SNP)) return -ENODEV; =20 + /* + * Skip SNP INIT for kdump boot as SNP is already initialized if + * SNP is enabled. + */ + if (is_kdump_kernel()) + return 0; + sev =3D psp->sev_data; =20 if (sev->snp_initialized) --=20 2.34.1 From nobody Tue Oct 7 01:53:57 2025 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2073.outbound.protection.outlook.com [40.107.92.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A86EB26D4CF; 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Tue, 15 Jul 2025 14:27:53 -0500 From: Ashish Kalra To: , , , , , CC: , , , , , , , , , , , Subject: [PATCH v3 4/4] iommu/amd: Fix host kdump support for SNP Date: Tue, 15 Jul 2025 19:27:43 +0000 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CE5:EE_|MN2PR12MB4334:EE_ X-MS-Office365-Filtering-Correlation-Id: 5ceb163d-17b0-4473-f862-08ddc3d5b2b1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|7416014|376014|82310400026; X-Microsoft-Antispam-Message-Info: =?utf-8?B?UlNiOTErRUNwaUVSQ1RVQ1hNUXlVZ3pnVXl6K0tkZHJCOUcwSWtBR2FiTEhw?= =?utf-8?B?UEMrS3FpcUllZjIvZFFQTUpKaFNwRk9ocTlyNXhhU3JDb2pIM1lLWjBPV011?= =?utf-8?B?ckw2cFlLNVZsb3A4SS8vWlRQNit0Z2JCMVhHT0NsUmY3VUQ0bnkxNlJGb3VH?= =?utf-8?B?Q2VXUXpPditnT09QWG9sUy83UXJzaHpPOXRnY29oRGppNzAzSXJmWjhEcFQ4?= =?utf-8?B?T1h5allCTEM3WUljTERQaXNTaHl2M1JlbWtnUE0rSUxPR0ZHK3RlUHFwb1Rw?= =?utf-8?B?SThVeG1oV1pROEVYZ0U5WE1pZTZFYmFUN3NjUm9iaVpJNHpNKytGOVRNZXQ5?= =?utf-8?B?ajlCejE5YlZWcWQySzN3N3lTS1hiQmtyNTc0YW52dGdFdnh5ZVpKM2kwWStu?= =?utf-8?B?cXJJUER6b2NxWlRjRkRGdzNoQXdkY1d6Q1FsdHJldkhUVm04ZzRwajFnVDEz?= =?utf-8?B?ZTBpdEdQZnNGOTNQS2JLN1I3YXVHWGtheXM2RHoyK0JQdk95MWExeGpsTStZ?= =?utf-8?B?NG90U0JPS3FENE1Veis2TEdyMFRTUHlHeFppV0Z4a0YrWDQ4c3V2R0Q2N1lQ?= =?utf-8?B?RWFjTUhmVmdxSFFKdGRMWFBONTFzU1JRZ0JiY3hnTFcyMVZTL3BLZ1B4SEhZ?= =?utf-8?B?V1BKZzcwWGFXTGd1MlA5bDN3VDhEcHZnclNzS0JCU3A3WitIa1h6RURFS0pK?= =?utf-8?B?N1JpVU5kSWZVeC9aWW5GTGZ0UTNMdkEzVEh0RXkybitja1FINm1SQUlMeTBk?= =?utf-8?B?M0hxeDlvMlNDQjMzelZNOEtZTnFuY1JoUG5UNE0vSmpvd1BwWm9zWDRnNDlj?= =?utf-8?B?VGtCRXpacllZRWwwVnA0L0NSbnphWE9KSlc3cHdrcW01bUh3K2dPamxmdmg1?= =?utf-8?B?YXJPQ0N1VG50ZExlTHEzVlkwZVRPRW9ic1hKcXRrUXVNT1lTMHZRV2N3bXN5?= =?utf-8?B?N0tONFhNZk1mejZQNU9aZ21VTkpjTC9ZQUFXbTN3RS9adTZteW5XbW5sSFY5?= =?utf-8?B?N21vWWtGRHdaa1h5RDdXc1ZoSUFYYUJUMFpDbitSQnE3SktUbTVnMk1YMDFh?= =?utf-8?B?bE1ySS9HZGFLVDZYbDNHMHZ0UzEzSm80bmFFRlY4WlFic2VkUDJJa05TajRL?= =?utf-8?B?UWhRQlZtY3pRb2MzQ0UvWGRMdHNwQU84TWtqRHNRZW9GZWx0RVdLZVZEVnpQ?= =?utf-8?B?UmFCZDM5eWRNUzdhbkRxT2dxeGc1bmhHdkJSZzJOZkp4Y3dBME1JSSs4Yzgx?= =?utf-8?B?N2hneVFDMCtjT2hFbTJVQW55YzZuRWlZS3U5TVVoVCtyYXZQcCs5cytzMXFy?= =?utf-8?B?UkpRWHFNanVBM0lFV3FFUTE3U0NPOHplTGR2REtYOVV0TjB0MnpjRDZYM2c3?= =?utf-8?B?dk5KcVVVRm1DSU5tN2JsemNaNVJxMUFQRTNRS0JwVXduZjFyN09uMjdsRFJw?= =?utf-8?B?djhxUGVVVHkrbEh0UHBHbzY5TTNZRC9zbUpQRi9UV0toMVU1NmxDV0FzR3Jw?= =?utf-8?B?T3hudjUyQjc2SmcwUlRnN3hKNFpyWXAzVzRZZ1dkc3c3eVdJN2Vhb1pRMHdj?= =?utf-8?B?ZUZWYUZYelpDSUJSVXpROFNHQ1ZqaGtvbkRJeEJGU0lNSGlnbDRPS0RGN0Qw?= =?utf-8?B?Q05XdmpiaE40bUpuVGFZRHJ5QmxqeEZ4alBTWEdNOGJrVmZBQ1ZQUUprZTVD?= =?utf-8?B?RjAvUnBPZExPL1FuTE1sRGVBME52NWlqeDlOUVY0SmhLMlJBdnlrNzFpbEh0?= =?utf-8?B?ejdsWXFRdXVqRWV5VjNqKzd6Y0RIejEwQWFFS2pDTWRYV3BwL3pYTEFFY0li?= =?utf-8?B?V1BwV0YrUVdDYzBBM1hxZVZ4M1YwNUY1Y3dMRkJWZnJyOHlTRm44dUk0ZWZ2?= =?utf-8?B?OSs0aVR1VmRwQy9VbExvS2lkaW5ZSHdSRHZIaVFWT1FjK2hrMGhzSVVDTXB4?= =?utf-8?B?ekJEbEpod3RZWW1XY0k5NHZ4TkgvQVBwMy9naFlnRTgvNWZCQ0ovQ1lLQ2Ur?= =?utf-8?B?NHlSTFBDZldLT0RiRy9Xd1Vwa3BzSXFNZUVaOUtOejdHRkQ3QVZLRUovRUs4?= =?utf-8?Q?0Cz+IW?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(7416014)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Jul 2025 19:27:54.8574 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5ceb163d-17b0-4473-f862-08ddc3d5b2b1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE5.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4334 From: Ashish Kalra When a crash is triggered the kernel attempts to shut down SEV-SNP using the SNP_SHUTDOWN_EX command. If active SNP VMs are present, SNP_SHUTDOWN_EX fails as firmware checks all encryption-capable ASIDs to ensure none are in use and that a DF_FLUSH is not required. If a DF_FLUSH is required, the firmware returns DFFLUSH_REQUIRED, causing SNP_SHUTDOWN_EX to fail. This casues the kdump kernel to boot with IOMMU SNP enforcement still enabled and IOMMU completion wait buffers (CWBs), command buffers, device tables and event buffer registers remain locked and exclusive to the previous kernel. Attempts to allocate and use new buffers in the kdump kernel fail, as the hardware ignores writes to the locked MMIO registers (per AMD IOMMU spec Section 2.12.2.1). As a result, the kdump kernel cannot initialize the IOMMU or enable IRQ remapping which is required for proper operation. This results in repeated "Completion-Wait loop timed out" errors and a second kernel panic: "Kernel panic - not syncing: timer doesn't work through Interrupt-remapped IO-APIC" The following MMIO registers are locked and ignore writes after failed SNP shutdown: Device Table Base Address Register Command Buffer Base Address Register Event Buffer Base Address Register Completion Store Base Register/Exclusion Base Register Completion Store Limit Register/Exclusion Range Limit Register Instead of allocating new buffers, re-use the previous kernel=E2=80=99s pag= es for completion wait buffers, command buffers, event buffers and device tables and operate with the already enabled SNP configuration and existing data structures. This approach is now used for kdump boot regardless of whether SNP is enabled during kdump. The fix enables successful crashkernel/kdump operation on SNP hosts even when SNP_SHUTDOWN_EX fails. Fixes: c3b86e61b756 ("x86/cpufeatures: Enable/unmask SEV-SNP CPU feature") Signed-off-by: Ashish Kalra --- drivers/iommu/amd/init.c | 28 +++++++++++++++++++--------- 1 file changed, 19 insertions(+), 9 deletions(-) diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index 18bd869a82d9..3f24fd775d6e 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -818,11 +818,16 @@ static void iommu_enable_command_buffer(struct amd_io= mmu *iommu) =20 BUG_ON(iommu->cmd_buf =3D=3D NULL); =20 - entry =3D iommu_virt_to_phys(iommu->cmd_buf); - entry |=3D MMIO_CMD_SIZE_512; - - memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET, - &entry, sizeof(entry)); + if (!is_kdump_kernel()) { + /* + * Command buffer is re-used for kdump kernel and setting + * of MMIO register is not required. + */ + entry =3D iommu_virt_to_phys(iommu->cmd_buf); + entry |=3D MMIO_CMD_SIZE_512; + memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET, + &entry, sizeof(entry)); + } =20 amd_iommu_reset_cmd_buffer(iommu); } @@ -873,10 +878,15 @@ static void iommu_enable_event_buffer(struct amd_iomm= u *iommu) =20 BUG_ON(iommu->evt_buf =3D=3D NULL); =20 - entry =3D iommu_virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK; - - memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET, - &entry, sizeof(entry)); + if (!is_kdump_kernel()) { + /* + * Event buffer is re-used for kdump kernel and setting + * of MMIO register is not required. + */ + entry =3D iommu_virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK; + memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET, + &entry, sizeof(entry)); + } =20 /* set head and tail to zero manually */ writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); --=20 2.34.1