From nobody Tue Oct 7 09:53:13 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F10D6303DF4; Thu, 10 Jul 2025 20:07:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752178081; cv=none; b=gJioLY+YbAMYPhmrQ/NDx3DHgdMbInlLRNm5kvRSJD9BqWf2ToG/hTQpaeRVo1ds+2RUyptYC2lXxm/WlLwagZz2/xaQ6noaRoSbnAIT4fnGM8trkg3lBuU1/jSgZeLI9wj8IBoQ0vIj19nOpqD36ABQLJXtJ4ZBPxQBls84QMc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752178081; c=relaxed/simple; bh=Zv0CC3WYKH/36O9O0t/SOoiKrmvlfng/rt5RJxB0L+A=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=mdmqT3BIpm+W+bRs/mgl3YHnbqs8YZE9qj79Lv3yOW+nExv6IgoflYjmBW2B8RFk/nNQaFrXUXhpGCTQ5r/CSdhRrHswsg7FxR5PfwMWKzrXksPmpKUp6yIT/B/LhfCLnjz10CpDM8kCrwN9m7qlOAy7WmZQOl9hHZKLuLyKtqM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=mIKsCFcy; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="mIKsCFcy" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1752178080; x=1783714080; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Zv0CC3WYKH/36O9O0t/SOoiKrmvlfng/rt5RJxB0L+A=; b=mIKsCFcymSpO5x63OUtpavnqF/B+sgxjmkPorh7bE+zYvz9mnJhTZsnY RjhQCGsIMD+x2/AiXhlUoIBV6u6FWqJ+Shiv8tQISQKjH57apQtQVbWUF QZf9G1HjfZQ1//t23u4/lXR8S1goBdITrkBD2WZRDq0itaubAnDAC3syT gfMCfXofNZWZbw1pdWFkv/7HRtkZMMfCl3LefkgS7e5AzH/nnIPOvlflh VjGbbiHuCcO+MDh1OI6wbmkIkRwU+BEYaPDpkALABEXQSfu7piRyac1d4 2tb6qC1XprfhNS4YmvQ1QDqfALw0wGJ3c83qzrpWALxMYwTiumltboSK6 Q==; X-CSE-ConnectionGUID: VcY24SkbRKSMnNSaLxS1vA== X-CSE-MsgGUID: zr4ioYhrTsmq9eXidwg21Q== X-IronPort-AV: E=Sophos;i="6.16,301,1744095600"; d="scan'208";a="44448156" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 10 Jul 2025 13:07:51 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Thu, 10 Jul 2025 13:07:30 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Thu, 10 Jul 2025 13:07:30 -0700 From: To: , , , , CC: , , , , Subject: [PATCH v3 01/32] clk: at91: pmc: add macros for clk_parent_data Date: Thu, 10 Jul 2025 13:06:54 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Add helpers to set parent_data objects in platform specific drivers. Signed-off-by: Claudiu Beznea [ryan.wanner@microchip.com: enclose complex macro with parentheses.] Signed-off-by: Ryan Wanner Reviewed-by: Brian Masney --- drivers/clk/at91/pmc.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index 4fb29ca111f7..0b721a65b77f 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -15,6 +15,12 @@ =20 #include =20 +#define AT91_CLK_PD_NAME(n, i) ((struct clk_parent_data){ \ + .hw =3D NULL, .name =3D (n), .fw_name =3D (n), .index =3D (i), \ +}) + +#define AT91_CLK_PD_HW(h) ((struct clk_parent_data){ .hw =3D (h) }) + extern spinlock_t pmc_pcr_lock; =20 struct pmc_data { --=20 2.43.0 From nobody Tue Oct 7 09:53:13 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7DE9D2FD892; Thu, 10 Jul 2025 20:08:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752178083; cv=none; b=l2RbruYCHCzZJcEAK8GOhJ5GOS2WGaiV2UFdsnsBVvkcaaFAmHg37tzRyHMWntJGl4S2KR41t0jq5TOrfY3pGFqdYQA7v8RosHHBdatF6SQCklcet9DDJBMTsPPmiU2fifJ/W6HqAtHXeEQhDrqd3gaETdkocIKQUyP+KHPwj1k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752178083; c=relaxed/simple; bh=9aK4jdZmF1ToqNiZetoB/6dP7GUhww2O/JrrrKTukA8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=bWwd6IfBoLiAKJS0/iNiFRwn8vmaihjpNhQ5G2AP6K7uEOiRcJOA8Ca5IzGrPf5BOQsFOomO5k1JITCS2ju7HghZbBQnZAbdasPvIfItgSZF19UtyCZsmMo57i+il1VG2+G4vyzQboimlT8JXL5EpHCwra8tliLVcWb6Bum0AdA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=Ylb/ntb0; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="Ylb/ntb0" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1752178080; x=1783714080; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9aK4jdZmF1ToqNiZetoB/6dP7GUhww2O/JrrrKTukA8=; b=Ylb/ntb00jkwPklDqgwMUMtJlhoFX6iAvl9Y9boKMihsBnPVDzl8E+tf xTvdgBrxuN64V1YzmUZdlNeQyOqu8RwVeSpDnqk4skt/YeHapHORDukSs cZmI54PUfzEP+YBf940zIetFj+YXnhCpyjAWM3bpzcsh7zuC8TLA8TaXF V1h4w+fCPXH7YGlrGMItFNCeuWCWd1z2NVm8dvUB/gqWY8YKGWmF2M7T/ lvwH+7rkgzNy6q7nSCsl1u/QLJ1cETiMHvdOyTlH/DEeEMlE0Rjwgj7Ob tjY5G4rf0C8floMcFG4eGwGyMrog+1INt5IZF3RZBjYOkjQnTF7Q2LwZv A==; X-CSE-ConnectionGUID: VcY24SkbRKSMnNSaLxS1vA== X-CSE-MsgGUID: NpbT3xu2Tfe2nS8n08xCCg== X-IronPort-AV: E=Sophos;i="6.16,301,1744095600"; d="scan'208";a="44448157" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 10 Jul 2025 13:07:51 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Thu, 10 Jul 2025 13:07:30 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Thu, 10 Jul 2025 13:07:30 -0700 From: To: , , , , CC: , , , , , Ryan Wanner Subject: [PATCH v3 02/32] clk: at91: pmc: Move macro to header file Date: Thu, 10 Jul 2025 13:06:55 -0700 Message-ID: <6776f06473d3be71882ef938a4314947f565e26f.1752176711.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Ryan Wanner Move this macro to the header file as it is used by more than one driver file. Signed-off-by: Ryan Wanner Reviewed-by: Brian Masney --- drivers/clk/at91/pmc.h | 3 +++ drivers/clk/at91/sama7d65.c | 3 --- drivers/clk/at91/sama7g5.c | 3 --- 3 files changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index 0b721a65b77f..63d4c425bed5 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -21,6 +21,9 @@ =20 #define AT91_CLK_PD_HW(h) ((struct clk_parent_data){ .hw =3D (h) }) =20 +/* Used to create an array entry identifying a PLL by its components. */ +#define PLL_IDS_TO_ARR_ENTRY(_id, _comp) { PLL_ID_##_id, PLL_COMPID_##_com= p} + extern spinlock_t pmc_pcr_lock; =20 struct pmc_data { diff --git a/drivers/clk/at91/sama7d65.c b/drivers/clk/at91/sama7d65.c index a5d40df8b2f2..b74813a288a8 100644 --- a/drivers/clk/at91/sama7d65.c +++ b/drivers/clk/at91/sama7d65.c @@ -428,9 +428,6 @@ static struct sama7d65_pll { }, }; =20 -/* Used to create an array entry identifying a PLL by its components. */ -#define PLL_IDS_TO_ARR_ENTRY(_id, _comp) { PLL_ID_##_id, PLL_COMPID_##_com= p} - /* * Master clock (MCK[0..9]) description * @n: clock name diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index 8385badc1c70..bf6092fea217 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -341,9 +341,6 @@ static struct sama7g5_pll { }, }; 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Thu, 10 Jul 2025 13:07:30 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Thu, 10 Jul 2025 13:07:30 -0700 From: To: , , , , CC: , , , , , Ryan Wanner Subject: [PATCH v3 03/32] clk: at91: sam9x75: switch to parent_hw and parent_data Date: Thu, 10 Jul 2025 13:06:56 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Ryan Wanner Switch SAM9X75 clocks to use parent_hw and parent_data. Having parent_hw instead of parent names improves to clock registration speed and re-parenting. The USBCLK will be updated in subsequent patches that update the clock registration functions to use parent_hw and parent_data. Signed-off-by: Ryan Wanner --- drivers/clk/at91/sam9x7.c | 308 +++++++++++++++++++++----------------- 1 file changed, 173 insertions(+), 135 deletions(-) diff --git a/drivers/clk/at91/sam9x7.c b/drivers/clk/at91/sam9x7.c index cbb8b220f16b..31184e11165a 100644 --- a/drivers/clk/at91/sam9x7.c +++ b/drivers/clk/at91/sam9x7.c @@ -33,10 +33,22 @@ enum pll_ids { PLL_ID_UPLL, PLL_ID_AUDIO, PLL_ID_LVDS, - PLL_ID_PLLA_DIV2, PLL_ID_MAX, }; =20 +/* + * PLL component identifier + * @PLL_COMPID_FRAC: Fractional PLL component identifier + * @PLL_COMPID_DIV0: 1st PLL divider component identifier + * @PLL_COMPID_DIV1: 2nd PLL divider component identifier + */ +enum pll_component_id { + PLL_COMPID_FRAC, + PLL_COMPID_DIV0, + PLL_COMPID_DIV1, + PLL_COMPID_MAX, +}; + /** * enum pll_type - PLL type identifiers * @PLL_TYPE_FRAC: fractional PLL identifier @@ -180,6 +192,18 @@ static const struct clk_pll_layout pll_divio_layout = =3D { .endiv_shift =3D 30, }; =20 +/* + * SAM9X7 PLL possible parents + * @SAM9X7_PLL_PARENT_MAINCK: MAINCK is PLL a parent + * @SAM9X7_PLL_PARENT_MAIN_XTAL: MAIN XTAL is a PLL parent + * @SAM9X7_PLL_PARENT_FRACCK: Frac PLL is a PLL parent (for PLL dividers) + */ +enum sam9x7_pll_parent { + SAM9X7_PLL_PARENT_MAINCK, + SAM9X7_PLL_PARENT_MAIN_XTAL, + SAM9X7_PLL_PARENT_FRACCK +}; + /* * PLL clocks description * @n: clock name @@ -187,22 +211,24 @@ static const struct clk_pll_layout pll_divio_layout = =3D { * @l: clock layout * @t: clock type * @c: pll characteristics + * @hw: pointer to clk_hw * @f: clock flags * @eid: export index in sam9x7->chws[] array */ -static const struct { +static struct { const char *n; - const char *p; const struct clk_pll_layout *l; u8 t; const struct clk_pll_characteristics *c; + struct clk_hw *hw; unsigned long f; + enum sam9x7_pll_parent p; u8 eid; -} sam9x7_plls[][3] =3D { +} sam9x7_plls[][PLL_COMPID_MAX] =3D { [PLL_ID_PLLA] =3D { - { + [PLL_COMPID_FRAC] =3D { .n =3D "plla_fracck", - .p =3D "mainck", + .p =3D SAM9X7_PLL_PARENT_MAINCK, .l =3D &plla_frac_layout, .t =3D PLL_TYPE_FRAC, /* @@ -213,9 +239,9 @@ static const struct { .c =3D &plla_characteristics, }, =20 - { + [PLL_COMPID_DIV0] =3D { .n =3D "plla_divpmcck", - .p =3D "plla_fracck", + .p =3D SAM9X7_PLL_PARENT_FRACCK, .l =3D &pll_divpmc_layout, .t =3D PLL_TYPE_DIV, /* This feeds CPU. It should not be disabled */ @@ -223,21 +249,35 @@ static const struct { .eid =3D PMC_PLLACK, .c =3D &plla_characteristics, }, + + [PLL_COMPID_DIV1] =3D { + .n =3D "plla_div2pmcck", + .p =3D SAM9X7_PLL_PARENT_FRACCK, + .l =3D &plladiv2_divpmc_layout, + /* + * This may feed critical parts of the system like timers. + * It should not be disabled. + */ + .f =3D CLK_IS_CRITICAL | CLK_SET_RATE_GATE, + .c =3D &plladiv2_characteristics, + .eid =3D PMC_PLLADIV2, + .t =3D PLL_TYPE_DIV, + }, }, =20 [PLL_ID_UPLL] =3D { - { + [PLL_COMPID_FRAC] =3D { .n =3D "upll_fracck", - .p =3D "main_osc", + .p =3D SAM9X7_PLL_PARENT_MAIN_XTAL, .l =3D &pll_frac_layout, .t =3D PLL_TYPE_FRAC, .f =3D CLK_SET_RATE_GATE, .c =3D &upll_characteristics, }, =20 - { + [PLL_COMPID_DIV0] =3D { .n =3D "upll_divpmcck", - .p =3D "upll_fracck", + .p =3D SAM9X7_PLL_PARENT_FRACCK, .l =3D &pll_divpmc_layout, .t =3D PLL_TYPE_DIV, .f =3D CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | @@ -248,18 +288,18 @@ static const struct { }, =20 [PLL_ID_AUDIO] =3D { - { + [PLL_COMPID_FRAC] =3D { .n =3D "audiopll_fracck", - .p =3D "main_osc", + .p =3D SAM9X7_PLL_PARENT_MAIN_XTAL, .l =3D &pll_frac_layout, .f =3D CLK_SET_RATE_GATE, .c =3D &audiopll_characteristics, .t =3D PLL_TYPE_FRAC, }, =20 - { + [PLL_COMPID_DIV0] =3D { .n =3D "audiopll_divpmcck", - .p =3D "audiopll_fracck", + .p =3D SAM9X7_PLL_PARENT_FRACCK, .l =3D &pll_divpmc_layout, .f =3D CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | CLK_SET_RATE_PARENT, @@ -268,9 +308,9 @@ static const struct { .t =3D PLL_TYPE_DIV, }, =20 - { + [PLL_COMPID_DIV1] =3D { .n =3D "audiopll_diviock", - .p =3D "audiopll_fracck", + .p =3D SAM9X7_PLL_PARENT_FRACCK, .l =3D &pll_divio_layout, .f =3D CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | CLK_SET_RATE_PARENT, @@ -281,18 +321,18 @@ static const struct { }, =20 [PLL_ID_LVDS] =3D { - { + [PLL_COMPID_FRAC] =3D { .n =3D "lvdspll_fracck", - .p =3D "main_osc", + .p =3D SAM9X7_PLL_PARENT_MAIN_XTAL, .l =3D &pll_frac_layout, .f =3D CLK_SET_RATE_GATE, .c =3D &lvdspll_characteristics, .t =3D PLL_TYPE_FRAC, }, =20 - { + [PLL_COMPID_DIV0] =3D { .n =3D "lvdspll_divpmcck", - .p =3D "lvdspll_fracck", + .p =3D SAM9X7_PLL_PARENT_FRACCK, .l =3D &pll_divpmc_layout, .f =3D CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | CLK_SET_RATE_PARENT, @@ -301,22 +341,6 @@ static const struct { .t =3D PLL_TYPE_DIV, }, }, - - [PLL_ID_PLLA_DIV2] =3D { - { - .n =3D "plla_div2pmcck", - .p =3D "plla_fracck", - .l =3D &plladiv2_divpmc_layout, - /* - * This may feed critical parts of the system like timers. - * It should not be disabled. - */ - .f =3D CLK_IS_CRITICAL | CLK_SET_RATE_GATE, - .c =3D &plladiv2_characteristics, - .eid =3D PMC_PLLADIV2, - .t =3D PLL_TYPE_DIV, - }, - }, }; =20 static const struct clk_programmable_layout sam9x7_programmable_layout =3D= { @@ -334,9 +358,9 @@ static const struct clk_pcr_layout sam9x7_pcr_layout = =3D { .pid_mask =3D GENMASK(6, 0), }; =20 -static const struct { +static struct { char *n; - char *p; + struct clk_hw *parent_hw; u8 id; unsigned long flags; } sam9x7_systemck[] =3D { @@ -344,10 +368,10 @@ static const struct { * ddrck feeds DDR controller and is enabled by bootloader thus we need * to keep it enabled in case there is no Linux consumer for it. */ - { .n =3D "ddrck", .p =3D "masterck_div", .id =3D 2, .flags =3D CLK_IS_CR= ITICAL }, - { .n =3D "uhpck", .p =3D "usbck", .id =3D 6 }, - { .n =3D "pck0", .p =3D "prog0", .id =3D 8 }, - { .n =3D "pck1", .p =3D "prog1", .id =3D 9 }, + { .n =3D "ddrck", .id =3D 2, .flags =3D CLK_IS_CRITICAL }, + { .n =3D "uhpck", .id =3D 6 }, + { .n =3D "pck0", .id =3D 8 }, + { .n =3D "pck1", .id =3D 9 }, }; =20 /* @@ -420,7 +444,8 @@ static const struct { /* * Generic clock description * @n: clock name - * @pp: PLL parents + * @pp: PLL parents (entry formed by PLL components identifiers + * (see enum pll_component_id)) * @pp_mux_table: PLL parents mux table * @r: clock output range * @pp_chg_id: id in parent array of changeable PLL parent @@ -429,7 +454,10 @@ static const struct { */ static const struct { const char *n; - const char *pp[8]; + struct { + int pll_id; + int pll_compid; + } pp[8]; const char pp_mux_table[8]; struct clk_range r; int pp_chg_id; @@ -439,7 +467,7 @@ static const struct { { .n =3D "flex0_gclk", .id =3D 5, - .pp =3D { "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table =3D { 8, }, .pp_count =3D 1, .pp_chg_id =3D INT_MIN, @@ -448,7 +476,7 @@ static const struct { { .n =3D "flex1_gclk", .id =3D 6, - .pp =3D { "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table =3D { 8, }, .pp_count =3D 1, .pp_chg_id =3D INT_MIN, @@ -457,7 +485,7 @@ static const struct { { .n =3D "flex2_gclk", .id =3D 7, - .pp =3D { "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table =3D { 8, }, .pp_count =3D 1, .pp_chg_id =3D INT_MIN, @@ -466,7 +494,7 @@ static const struct { { .n =3D "flex3_gclk", .id =3D 8, - .pp =3D { "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table =3D { 8, }, .pp_count =3D 1, .pp_chg_id =3D INT_MIN, @@ -475,7 +503,7 @@ static const struct { { .n =3D "flex6_gclk", .id =3D 9, - .pp =3D { "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table =3D { 8, }, .pp_count =3D 1, .pp_chg_id =3D INT_MIN, @@ -484,7 +512,7 @@ static const struct { { .n =3D "flex7_gclk", .id =3D 10, - .pp =3D { "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table =3D { 8, }, .pp_count =3D 1, .pp_chg_id =3D INT_MIN, @@ -493,7 +521,7 @@ static const struct { { .n =3D "flex8_gclk", .id =3D 11, - .pp =3D { "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table =3D { 8, }, .pp_count =3D 1, .pp_chg_id =3D INT_MIN, @@ -503,7 +531,7 @@ static const struct { .n =3D "sdmmc0_gclk", .id =3D 12, .r =3D { .max =3D 105000000 }, - .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), PLL_IDS_TO_ARR_ENTRY(PLLA, = DIV1), }, .pp_mux_table =3D { 6, 8, }, .pp_count =3D 2, .pp_chg_id =3D INT_MIN, @@ -512,7 +540,7 @@ static const struct { { .n =3D "flex4_gclk", .id =3D 13, - .pp =3D { "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table =3D { 8, }, .pp_count =3D 1, .pp_chg_id =3D INT_MIN, @@ -521,7 +549,7 @@ static const struct { { .n =3D "flex5_gclk", .id =3D 14, - .pp =3D { "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table =3D { 8, }, .pp_count =3D 1, .pp_chg_id =3D INT_MIN, @@ -530,7 +558,7 @@ static const struct { { .n =3D "flex9_gclk", .id =3D 15, - .pp =3D { "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table =3D { 8, }, .pp_count =3D 1, .pp_chg_id =3D INT_MIN, @@ -539,7 +567,7 @@ static const struct { { .n =3D "flex10_gclk", .id =3D 16, - .pp =3D { "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table =3D { 8, }, .pp_count =3D 1, .pp_chg_id =3D INT_MIN, @@ -548,7 +576,7 @@ static const struct { { .n =3D "tcb0_gclk", .id =3D 17, - .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), PLL_IDS_TO_ARR_ENTRY(PLLA, = DIV1), }, .pp_mux_table =3D { 6, 8, }, .pp_count =3D 2, .pp_chg_id =3D INT_MIN, @@ -557,7 +585,7 @@ static const struct { { .n =3D "adc_gclk", .id =3D 19, - .pp =3D { "upll_divpmcck", "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(UPLL, DIV0), PLL_IDS_TO_ARR_ENTRY(PLLA, D= IV1), }, .pp_mux_table =3D { 5, 8, }, .pp_count =3D 2, .pp_chg_id =3D INT_MIN, @@ -567,7 +595,7 @@ static const struct { .n =3D "lcd_gclk", .id =3D 25, .r =3D { .max =3D 75000000 }, - .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), PLL_IDS_TO_ARR_ENTRY(PLLA, = DIV1), }, .pp_mux_table =3D { 6, 8, }, .pp_count =3D 2, .pp_chg_id =3D INT_MIN, @@ -577,7 +605,7 @@ static const struct { .n =3D "sdmmc1_gclk", .id =3D 26, .r =3D { .max =3D 105000000 }, - .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), PLL_IDS_TO_ARR_ENTRY(PLLA, = DIV1), }, .pp_mux_table =3D { 6, 8, }, .pp_count =3D 2, .pp_chg_id =3D INT_MIN, @@ -587,7 +615,7 @@ static const struct { .n =3D "mcan0_gclk", .id =3D 29, .r =3D { .max =3D 80000000 }, - .pp =3D { "upll_divpmcck", "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(UPLL, DIV0), PLL_IDS_TO_ARR_ENTRY(PLLA, D= IV1), }, .pp_mux_table =3D { 5, 8, }, .pp_count =3D 2, .pp_chg_id =3D INT_MIN, @@ -597,7 +625,7 @@ static const struct { .n =3D "mcan1_gclk", .id =3D 30, .r =3D { .max =3D 80000000 }, - .pp =3D { "upll_divpmcck", "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(UPLL, DIV0), PLL_IDS_TO_ARR_ENTRY(PLLA, D= IV1), }, .pp_mux_table =3D { 5, 8, }, .pp_count =3D 2, .pp_chg_id =3D INT_MIN, @@ -606,7 +634,7 @@ static const struct { { .n =3D "flex11_gclk", .id =3D 32, - .pp =3D { "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table =3D { 8, }, .pp_count =3D 1, .pp_chg_id =3D INT_MIN, @@ -615,7 +643,7 @@ static const struct { { .n =3D "flex12_gclk", .id =3D 33, - .pp =3D { "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table =3D { 8, }, .pp_count =3D 1, .pp_chg_id =3D INT_MIN, @@ -625,7 +653,7 @@ static const struct { .n =3D "i2s_gclk", .id =3D 34, .r =3D { .max =3D 100000000 }, - .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), PLL_IDS_TO_ARR_ENTRY(PLLA, = DIV1), }, .pp_mux_table =3D { 6, 8, }, .pp_count =3D 2, .pp_chg_id =3D INT_MIN, @@ -635,7 +663,7 @@ static const struct { .n =3D "qspi_gclk", .id =3D 35, .r =3D { .max =3D 200000000 }, - .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), PLL_IDS_TO_ARR_ENTRY(PLLA, = DIV1), }, .pp_mux_table =3D { 6, 8, }, .pp_count =3D 2, .pp_chg_id =3D INT_MIN, @@ -644,7 +672,7 @@ static const struct { { .n =3D "pit64b0_gclk", .id =3D 37, - .pp =3D { "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table =3D { 8, }, .pp_count =3D 1, .pp_chg_id =3D INT_MIN, @@ -654,7 +682,7 @@ static const struct { .n =3D "classd_gclk", .id =3D 42, .r =3D { .max =3D 100000000 }, - .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), PLL_IDS_TO_ARR_ENTRY(PLLA, = DIV1), }, .pp_mux_table =3D { 6, 8, }, .pp_count =3D 2, .pp_chg_id =3D INT_MIN, @@ -663,7 +691,7 @@ static const struct { { .n =3D "tcb1_gclk", .id =3D 45, - .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), PLL_IDS_TO_ARR_ENTRY(PLLA, = DIV1), }, .pp_mux_table =3D { 6, 8, }, .pp_count =3D 2, .pp_chg_id =3D INT_MIN, @@ -672,7 +700,7 @@ static const struct { { .n =3D "dbgu_gclk", .id =3D 47, - .pp =3D { "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table =3D { 8, }, .pp_count =3D 1, .pp_chg_id =3D INT_MIN, @@ -682,7 +710,7 @@ static const struct { .n =3D "mipiphy_gclk", .id =3D 55, .r =3D { .max =3D 27000000 }, - .pp =3D { "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table =3D { 8, }, .pp_count =3D 1, .pp_chg_id =3D INT_MIN, @@ -691,7 +719,7 @@ static const struct { { .n =3D "pit64b1_gclk", .id =3D 58, - .pp =3D { "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table =3D { 8, }, .pp_count =3D 1, .pp_chg_id =3D INT_MIN, @@ -700,7 +728,7 @@ static const struct { { .n =3D "gmac_gclk", .id =3D 67, - .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), PLL_IDS_TO_ARR_ENTRY(PLLA, = DIV1), }, .pp_mux_table =3D { 6, 8, }, .pp_count =3D 2, .pp_chg_id =3D INT_MIN, @@ -710,32 +738,24 @@ static const struct { static void __init sam9x7_pmc_setup(struct device_node *np) { struct clk_range range =3D CLK_RANGE(0, 0); - const char *td_slck_name, *md_slck_name, *mainxtal_name; + const char *main_xtal_name =3D "main_xtal"; struct pmc_data *sam9x7_pmc; const char *parent_names[9]; void **clk_mux_buffer =3D NULL; int clk_mux_buffer_size =3D 0; - struct clk_hw *main_osc_hw; struct regmap *regmap; - struct clk_hw *hw; + struct clk_hw *hw, *main_rc_hw, *main_osc_hw, *main_xtal_hw; + struct clk_hw *td_slck_hw, *md_slck_hw, *usbck_hw; + static struct clk_parent_data parent_data; + struct clk_hw *parent_hws[9]; int i, j; =20 - i =3D of_property_match_string(np, "clock-names", "td_slck"); - if (i < 0) - return; - - td_slck_name =3D of_clk_get_parent_name(np, i); - - i =3D of_property_match_string(np, "clock-names", "md_slck"); - if (i < 0) - return; - - md_slck_name =3D of_clk_get_parent_name(np, i); + td_slck_hw =3D __clk_get_hw(of_clk_get_by_name(np, "td_slck")); + md_slck_hw =3D __clk_get_hw(of_clk_get_by_name(np, "md_slck")); + main_xtal_hw =3D __clk_get_hw(of_clk_get_by_name(np, main_xtal_name)); =20 - i =3D of_property_match_string(np, "clock-names", "main_xtal"); - if (i < 0) + if (!td_slck_hw || !md_slck_hw || !main_xtal_hw) return; - mainxtal_name =3D of_clk_get_parent_name(np, i); =20 regmap =3D device_node_to_regmap(np); if (IS_ERR(regmap)) @@ -754,26 +774,27 @@ static void __init sam9x7_pmc_setup(struct device_nod= e *np) if (!clk_mux_buffer) goto err_free; =20 - hw =3D at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000, - 50000000); - if (IS_ERR(hw)) + main_rc_hw =3D at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000= 000, + 50000000); + if (IS_ERR(main_rc_hw)) goto err_free; =20 - hw =3D at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL= , 0); - if (IS_ERR(hw)) + parent_data.name =3D main_xtal_name; + parent_data.fw_name =3D main_xtal_name; + main_osc_hw =3D at91_clk_register_main_osc(regmap, "main_osc", NULL, &par= ent_data, 0); + if (IS_ERR(main_osc_hw)) goto err_free; - main_osc_hw =3D hw; =20 - parent_names[0] =3D "main_rc_osc"; - parent_names[1] =3D "main_osc"; - hw =3D at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL= , 2); + parent_hws[0] =3D main_rc_hw; + parent_hws[1] =3D main_osc_hw; + hw =3D at91_clk_register_sam9x5_main(regmap, "mainck", NULL, parent_hws, = 2); if (IS_ERR(hw)) goto err_free; =20 sam9x7_pmc->chws[PMC_MAIN] =3D hw; =20 for (i =3D 0; i < PLL_ID_MAX; i++) { - for (j =3D 0; j < 3; j++) { + for (j =3D 0; j < PLL_COMPID_MAX; j++) { struct clk_hw *parent_hw; =20 if (!sam9x7_plls[i][j].n) @@ -781,19 +802,23 @@ static void __init sam9x7_pmc_setup(struct device_nod= e *np) =20 switch (sam9x7_plls[i][j].t) { case PLL_TYPE_FRAC: - if (!strcmp(sam9x7_plls[i][j].p, "mainck")) + switch (sam9x7_plls[i][j].p) { + case SAM9X7_PLL_PARENT_MAINCK: parent_hw =3D sam9x7_pmc->chws[PMC_MAIN]; - else if (!strcmp(sam9x7_plls[i][j].p, "main_osc")) - parent_hw =3D main_osc_hw; - else - parent_hw =3D __clk_get_hw(of_clk_get_by_name - (np, sam9x7_plls[i][j].p)); + break; + case SAM9X7_PLL_PARENT_MAIN_XTAL: + parent_hw =3D main_xtal_hw; + break; + default: + /* Should not happen. */ + parent_hw =3D NULL; + break; + } =20 hw =3D sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, sam9x7_plls[i][j].n, - sam9x7_plls[i][j].p, - parent_hw, i, + NULL, parent_hw, i, sam9x7_plls[i][j].c, sam9x7_plls[i][j].l, sam9x7_plls[i][j].f); @@ -803,7 +828,7 @@ static void __init sam9x7_pmc_setup(struct device_node = *np) hw =3D sam9x60_clk_register_div_pll(regmap, &pmc_pll_lock, sam9x7_plls[i][j].n, - sam9x7_plls[i][j].p, NULL, i, + NULL, sam9x7_plls[i][0].hw, i, sam9x7_plls[i][j].c, sam9x7_plls[i][j].l, sam9x7_plls[i][j].f, 0); @@ -816,23 +841,24 @@ static void __init sam9x7_pmc_setup(struct device_nod= e *np) if (IS_ERR(hw)) goto err_free; =20 + sam9x7_plls[i][j].hw =3D hw; if (sam9x7_plls[i][j].eid) sam9x7_pmc->chws[sam9x7_plls[i][j].eid] =3D hw; } } =20 - parent_names[0] =3D md_slck_name; - parent_names[1] =3D "mainck"; - parent_names[2] =3D "plla_divpmcck"; - parent_names[3] =3D "upll_divpmcck"; + parent_hws[0] =3D md_slck_hw; + parent_hws[1] =3D sam9x7_pmc->chws[PMC_MAIN]; + parent_hws[2] =3D sam9x7_plls[PLL_ID_PLLA][PLL_COMPID_DIV0].hw; + parent_hws[3] =3D sam9x7_plls[PLL_ID_UPLL][PLL_COMPID_DIV0].hw; hw =3D at91_clk_register_master_pres(regmap, "masterck_pres", 4, - parent_names, NULL, &sam9x7_master_layout, + NULL, parent_hws, &sam9x7_master_layout, &mck_characteristics, &mck_lock); if (IS_ERR(hw)) goto err_free; =20 hw =3D at91_clk_register_master_div(regmap, "masterck_div", - "masterck_pres", NULL, &sam9x7_master_layout, + NULL, hw, &sam9x7_master_layout, &mck_characteristics, &mck_lock, CLK_SET_RATE_GATE, 0); if (IS_ERR(hw)) @@ -843,24 +869,24 @@ static void __init sam9x7_pmc_setup(struct device_nod= e *np) parent_names[0] =3D "plla_divpmcck"; parent_names[1] =3D "upll_divpmcck"; parent_names[2] =3D "main_osc"; - hw =3D sam9x60_clk_register_usb(regmap, "usbck", parent_names, 3); - if (IS_ERR(hw)) + usbck_hw =3D sam9x60_clk_register_usb(regmap, "usbck", parent_names, 3); + if (IS_ERR(usbck_hw)) goto err_free; =20 - parent_names[0] =3D md_slck_name; - parent_names[1] =3D td_slck_name; - parent_names[2] =3D "mainck"; - parent_names[3] =3D "masterck_div"; - parent_names[4] =3D "plla_divpmcck"; - parent_names[5] =3D "upll_divpmcck"; - parent_names[6] =3D "audiopll_divpmcck"; + parent_hws[0] =3D md_slck_hw; + parent_hws[1] =3D td_slck_hw; + parent_hws[2] =3D sam9x7_pmc->chws[PMC_MAIN]; + parent_hws[3] =3D sam9x7_pmc->chws[PMC_MCK]; + parent_hws[4] =3D sam9x7_plls[PLL_ID_PLLA][PLL_COMPID_DIV0].hw; + parent_hws[5] =3D sam9x7_plls[PLL_ID_UPLL][PLL_COMPID_DIV0].hw; + parent_hws[6] =3D sam9x7_plls[PLL_ID_AUDIO][PLL_COMPID_DIV0].hw; for (i =3D 0; i < 2; i++) { char name[6]; =20 snprintf(name, sizeof(name), "prog%d", i); =20 hw =3D at91_clk_register_programmable(regmap, name, - parent_names, NULL, 7, i, + NULL, parent_hws, 7, i, &sam9x7_programmable_layout, NULL); if (IS_ERR(hw)) @@ -869,9 +895,14 @@ static void __init sam9x7_pmc_setup(struct device_node= *np) sam9x7_pmc->pchws[i] =3D hw; } =20 + /* Set systemck parent hws. */ + sam9x7_systemck[0].parent_hw =3D sam9x7_pmc->chws[PMC_MCK]; + sam9x7_systemck[1].parent_hw =3D usbck_hw; + sam9x7_systemck[2].parent_hw =3D sam9x7_pmc->pchws[0]; + sam9x7_systemck[3].parent_hw =3D sam9x7_pmc->pchws[1]; for (i =3D 0; i < ARRAY_SIZE(sam9x7_systemck); i++) { hw =3D at91_clk_register_system(regmap, sam9x7_systemck[i].n, - sam9x7_systemck[i].p, NULL, + NULL, sam9x7_systemck[i].parent_hw, sam9x7_systemck[i].id, sam9x7_systemck[i].flags); if (IS_ERR(hw)) @@ -884,7 +915,7 @@ static void __init sam9x7_pmc_setup(struct device_node = *np) hw =3D at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, &sam9x7_pcr_layout, sam9x7_periphck[i].n, - "masterck_div", NULL, + NULL, sam9x7_pmc->chws[PMC_MCK], sam9x7_periphck[i].id, &range, INT_MIN, sam9x7_periphck[i].f); @@ -894,12 +925,13 @@ static void __init sam9x7_pmc_setup(struct device_nod= e *np) sam9x7_pmc->phws[sam9x7_periphck[i].id] =3D hw; } =20 - parent_names[0] =3D md_slck_name; - parent_names[1] =3D td_slck_name; - parent_names[2] =3D "mainck"; - parent_names[3] =3D "masterck_div"; + parent_hws[0] =3D md_slck_hw; + parent_hws[1] =3D td_slck_hw; + parent_hws[2] =3D sam9x7_pmc->chws[PMC_MAIN]; + parent_hws[3] =3D sam9x7_pmc->chws[PMC_MCK]; for (i =3D 0; i < ARRAY_SIZE(sam9x7_gck); i++) { u8 num_parents =3D 4 + sam9x7_gck[i].pp_count; + struct clk_hw *tmp_parent_hws[6]; u32 *mux_table; =20 mux_table =3D kmalloc_array(num_parents, sizeof(*mux_table), @@ -910,13 +942,19 @@ static void __init sam9x7_pmc_setup(struct device_nod= e *np) PMC_INIT_TABLE(mux_table, 4); PMC_FILL_TABLE(&mux_table[4], sam9x7_gck[i].pp_mux_table, sam9x7_gck[i].pp_count); - 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As clk-sam9x60-pll need to know parent's rate at initialization we pass it now from SoC specific drivers. This will lead in the end at removing __clk_get_hw() in SoC specific drivers (that will be solved by subsequent commits). Signed-off-by: Claudiu Beznea [ryan.wanner@microchip.com: Add SAMA7D65 and SAM9X75 SoCs to the change set= .] Signed-off-by: Ryan Wanner --- drivers/clk/at91/clk-sam9x60-pll.c | 14 +++++--------- drivers/clk/at91/pmc.h | 5 +++-- drivers/clk/at91/sam9x60.c | 8 +++++--- drivers/clk/at91/sam9x7.c | 17 ++++++++++++----- drivers/clk/at91/sama7d65.c | 16 +++++++++++----- drivers/clk/at91/sama7g5.c | 17 ++++++++++++----- 6 files changed, 48 insertions(+), 29 deletions(-) diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9= x60-pll.c index cefd9948e103..03a7d00dcc6d 100644 --- a/drivers/clk/at91/clk-sam9x60-pll.c +++ b/drivers/clk/at91/clk-sam9x60-pll.c @@ -630,19 +630,19 @@ static const struct clk_ops sam9x60_fixed_div_pll_ops= =3D { =20 struct clk_hw * __init sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock, - const char *name, const char *parent_name, - struct clk_hw *parent_hw, u8 id, + const char *name, const struct clk_parent_data *parent_data, + unsigned long parent_rate, u8 id, const struct clk_pll_characteristics *characteristics, const struct clk_pll_layout *layout, u32 flags) { struct sam9x60_frac *frac; struct clk_hw *hw; struct clk_init_data init =3D {}; - unsigned long parent_rate, irqflags; + unsigned long irqflags; unsigned int val; int ret; =20 - if (id > PLL_MAX_ID || !lock || !parent_hw) + if (id > PLL_MAX_ID || !lock || !parent_data) return ERR_PTR(-EINVAL); =20 frac =3D kzalloc(sizeof(*frac), GFP_KERNEL); @@ -650,10 +650,7 @@ sam9x60_clk_register_frac_pll(struct regmap *regmap, s= pinlock_t *lock, return ERR_PTR(-ENOMEM); =20 init.name =3D name; - if (parent_name) - init.parent_names =3D &parent_name; - else - init.parent_hws =3D (const struct clk_hw **)&parent_hw; + init.parent_data =3D (const struct clk_parent_data *)parent_data; init.num_parents =3D 1; if (flags & CLK_SET_RATE_GATE) init.ops =3D &sam9x60_frac_pll_ops; @@ -684,7 +681,6 @@ sam9x60_clk_register_frac_pll(struct regmap *regmap, sp= inlock_t *lock, * its rate leading to enabling this PLL with unsupported * rate. This will lead to PLL not being locked at all. */ - parent_rate =3D clk_hw_get_rate(parent_hw); if (!parent_rate) { hw =3D ERR_PTR(-EINVAL); goto free; diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index 63d4c425bed5..b43f6652417f 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -255,8 +255,9 @@ sam9x60_clk_register_div_pll(struct regmap *regmap, spi= nlock_t *lock, =20 struct clk_hw * __init sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock, - const char *name, const char *parent_name, - struct clk_hw *parent_hw, u8 id, + const char *name, + const struct clk_parent_data *parent_data, + unsigned long parent_rate, u8 id, const struct clk_pll_characteristics *characteristics, const struct clk_pll_layout *layout, u32 flags); =20 diff --git a/drivers/clk/at91/sam9x60.c b/drivers/clk/at91/sam9x60.c index db6db9e2073e..fd53e54abf88 100644 --- a/drivers/clk/at91/sam9x60.c +++ b/drivers/clk/at91/sam9x60.c @@ -240,7 +240,8 @@ static void __init sam9x60_pmc_setup(struct device_node= *np) sam9x60_pmc->chws[PMC_MAIN] =3D hw; =20 hw =3D sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, "pllack_fracc= k", - "mainck", sam9x60_pmc->chws[PMC_MAIN], + &AT91_CLK_PD_HW(sam9x60_pmc->chws[PMC_MAIN]), + clk_hw_get_rate(sam9x60_pmc->chws[PMC_MAIN]), 0, &plla_characteristics, &pll_frac_layout, /* @@ -266,8 +267,9 @@ static void __init sam9x60_pmc_setup(struct device_node= *np) sam9x60_pmc->chws[PMC_PLLACK] =3D hw; =20 hw =3D sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, "upllck_fracc= k", - "main_osc", main_osc_hw, 1, - &upll_characteristics, + &AT91_CLK_PD_HW(main_osc_hw), + clk_hw_get_rate(main_osc_hw), + 1, &upll_characteristics, &pll_frac_layout, CLK_SET_RATE_GATE); if (IS_ERR(hw)) goto err_free; diff --git a/drivers/clk/at91/sam9x7.c b/drivers/clk/at91/sam9x7.c index 31184e11165a..edd5fd3a1fa5 100644 --- a/drivers/clk/at91/sam9x7.c +++ b/drivers/clk/at91/sam9x7.c @@ -739,6 +739,7 @@ static void __init sam9x7_pmc_setup(struct device_node = *np) { struct clk_range range =3D CLK_RANGE(0, 0); const char *main_xtal_name =3D "main_xtal"; + u8 main_xtal_index =3D 2; struct pmc_data *sam9x7_pmc; const char *parent_names[9]; void **clk_mux_buffer =3D NULL; @@ -795,7 +796,7 @@ static void __init sam9x7_pmc_setup(struct device_node = *np) =20 for (i =3D 0; i < PLL_ID_MAX; i++) { for (j =3D 0; j < PLL_COMPID_MAX; j++) { - struct clk_hw *parent_hw; + unsigned long parent_rate =3D 0; =20 if (!sam9x7_plls[i][j].n) continue; @@ -804,21 +805,27 @@ static void __init sam9x7_pmc_setup(struct device_nod= e *np) case PLL_TYPE_FRAC: switch (sam9x7_plls[i][j].p) { case SAM9X7_PLL_PARENT_MAINCK: - parent_hw =3D sam9x7_pmc->chws[PMC_MAIN]; + parent_data =3D AT91_CLK_PD_NAME("mainck", -1); + hw =3D sam9x7_pmc->chws[PMC_MAIN]; break; case SAM9X7_PLL_PARENT_MAIN_XTAL: - parent_hw =3D main_xtal_hw; + parent_data =3D AT91_CLK_PD_NAME(main_xtal_name, + main_xtal_index); + hw =3D main_xtal_hw; break; default: /* Should not happen. */ - parent_hw =3D NULL; break; } =20 + parent_rate =3D clk_hw_get_rate(hw); + if (!parent_rate) + return; + hw =3D sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, sam9x7_plls[i][j].n, - NULL, parent_hw, i, + &parent_data, parent_rate, i, sam9x7_plls[i][j].c, sam9x7_plls[i][j].l, sam9x7_plls[i][j].f); diff --git a/drivers/clk/at91/sama7d65.c b/drivers/clk/at91/sama7d65.c index b74813a288a8..17725c175d3b 100644 --- a/drivers/clk/at91/sama7d65.c +++ b/drivers/clk/at91/sama7d65.c @@ -1090,6 +1090,7 @@ static const struct clk_pcr_layout sama7d65_pcr_layou= t =3D { static void __init sama7d65_pmc_setup(struct device_node *np) { const char *main_xtal_name =3D "main_xtal"; + u8 main_xtal_index =3D 2; struct pmc_data *sama7d65_pmc; const char *parent_names[11]; void **alloc_mem =3D NULL; @@ -1150,7 +1151,7 @@ static void __init sama7d65_pmc_setup(struct device_n= ode *np) =20 for (i =3D 0; i < PLL_ID_MAX; i++) { for (j =3D 0; j < PLL_COMPID_MAX; j++) { - struct clk_hw *parent_hw; + unsigned long parent_rate =3D 0; =20 if (!sama7d65_plls[i][j].n) continue; @@ -1159,20 +1160,25 @@ static void __init sama7d65_pmc_setup(struct device= _node *np) case PLL_TYPE_FRAC: switch (sama7d65_plls[i][j].p) { case SAMA7D65_PLL_PARENT_MAINCK: - parent_hw =3D sama7d65_pmc->chws[PMC_MAIN]; + parent_data =3D AT91_CLK_PD_NAME("mainck", -1); + hw =3D sama7d65_pmc->chws[PMC_MAIN]; break; case SAMA7D65_PLL_PARENT_MAIN_XTAL: - parent_hw =3D main_xtal_hw; + parent_data =3D AT91_CLK_PD_NAME(main_xtal_name, + main_xtal_index); + hw =3D main_xtal_hw; break; default: /* Should not happen. */ - parent_hw =3D NULL; break; } + parent_rate =3D clk_hw_get_rate(hw); + if (!parent_rate) + return; =20 hw =3D sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, sama7d65_plls[i][j].n, - NULL, parent_hw, i, + &parent_data, parent_rate, i, sama7d65_plls[i][j].c, sama7d65_plls[i][j].l, sama7d65_plls[i][j].f); diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index bf6092fea217..733e4fc6a515 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -970,6 +970,7 @@ static const struct clk_pcr_layout sama7g5_pcr_layout = =3D { static void __init sama7g5_pmc_setup(struct device_node *np) { const char *main_xtal_name =3D "main_xtal"; + u8 main_xtal_index =3D 2; struct pmc_data *sama7g5_pmc; void **alloc_mem =3D NULL; int alloc_mem_size =3D 0; @@ -1029,7 +1030,7 @@ static void __init sama7g5_pmc_setup(struct device_no= de *np) =20 for (i =3D 0; i < PLL_ID_MAX; i++) { for (j =3D 0; j < PLL_COMPID_MAX; j++) { - struct clk_hw *parent_hw; + unsigned long parent_rate =3D 0; =20 if (!sama7g5_plls[i][j].n) continue; @@ -1038,20 +1039,26 @@ static void __init sama7g5_pmc_setup(struct device_= node *np) case PLL_TYPE_FRAC: switch (sama7g5_plls[i][j].p) { case SAMA7G5_PLL_PARENT_MAINCK: - parent_hw =3D sama7g5_pmc->chws[PMC_MAIN]; + parent_data =3D AT91_CLK_PD_NAME("mainck", -1); + hw =3D sama7g5_pmc->chws[PMC_MAIN]; break; case SAMA7G5_PLL_PARENT_MAIN_XTAL: - parent_hw =3D main_xtal_hw; + parent_data =3D AT91_CLK_PD_NAME(main_xtal_name, + main_xtal_index); + hw =3D main_xtal_hw; break; default: /* Should not happen. */ - parent_hw =3D NULL; break; } =20 + parent_rate =3D clk_hw_get_rate(hw); + if (!parent_rate) + return; + hw =3D sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, sama7g5_plls[i][j].n, - NULL, parent_hw, i, + &parent_data, parent_rate, i, sama7g5_plls[i][j].c, sama7g5_plls[i][j].l, sama7g5_plls[i][j].f); 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X-CSE-ConnectionGUID: VcY24SkbRKSMnNSaLxS1vA== X-CSE-MsgGUID: RDyBJja1Qm2UNq4ITe+UrQ== X-IronPort-AV: E=Sophos;i="6.16,301,1744095600"; d="scan'208";a="44448160" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 10 Jul 2025 13:07:52 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Thu, 10 Jul 2025 13:07:30 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Thu, 10 Jul 2025 13:07:30 -0700 From: To: , , , , CC: , , , , Subject: [PATCH v3 05/32] clk: at91: clk-peripheral: switch to clk_parent_data Date: Thu, 10 Jul 2025 13:06:58 -0700 Message-ID: <657143d460ed5f2f726413385895c0c80ddddef9.1752176711.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Use struct clk_parent_data instead of parent_hw for peripheral clocks. Signed-off-by: Claudiu Beznea [ryan.wanner@microchip.com: Add SAMA7D65 and SAM9X7 SoCs to the use the structs.] Signed-off-by: Ryan Wanner --- drivers/clk/at91/clk-peripheral.c | 16 ++++++++-------- drivers/clk/at91/pmc.h | 4 ++-- drivers/clk/at91/sam9x7.c | 2 +- drivers/clk/at91/sama7d65.c | 2 +- drivers/clk/at91/sama7g5.c | 2 +- 5 files changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/clk/at91/clk-peripheral.c b/drivers/clk/at91/clk-perip= heral.c index c173a44c800a..ed97b3c0a66b 100644 --- a/drivers/clk/at91/clk-peripheral.c +++ b/drivers/clk/at91/clk-peripheral.c @@ -97,7 +97,7 @@ static const struct clk_ops peripheral_ops =3D { =20 struct clk_hw * __init at91_clk_register_peripheral(struct regmap *regmap, const char *name, - const char *parent_name, struct clk_hw *parent_hw, + const char *parent_name, struct clk_parent_data *parent_data, u32 id) { struct clk_peripheral *periph; @@ -105,7 +105,7 @@ at91_clk_register_peripheral(struct regmap *regmap, con= st char *name, struct clk_hw *hw; int ret; =20 - if (!name || !(parent_name || parent_hw) || id > PERIPHERAL_ID_MAX) + if (!name || !(parent_name || parent_data) || id > PERIPHERAL_ID_MAX) return ERR_PTR(-EINVAL); =20 periph =3D kzalloc(sizeof(*periph), GFP_KERNEL); @@ -114,8 +114,8 @@ at91_clk_register_peripheral(struct regmap *regmap, con= st char *name, =20 init.name =3D name; init.ops =3D &peripheral_ops; - if (parent_hw) - init.parent_hws =3D (const struct clk_hw **)&parent_hw; + if (parent_data) + init.parent_data =3D (const struct clk_parent_data *)parent_data; else init.parent_names =3D &parent_name; init.num_parents =3D 1; @@ -448,7 +448,7 @@ struct clk_hw * __init at91_clk_register_sam9x5_peripheral(struct regmap *regmap, spinlock_t *loc= k, const struct clk_pcr_layout *layout, const char *name, const char *parent_name, - struct clk_hw *parent_hw, + struct clk_parent_data *parent_data, u32 id, const struct clk_range *range, int chg_pid, unsigned long flags) { @@ -457,7 +457,7 @@ at91_clk_register_sam9x5_peripheral(struct regmap *regm= ap, spinlock_t *lock, struct clk_hw *hw; int ret; =20 - if (!name || !(parent_name || parent_hw)) + if (!name || !(parent_name || parent_data)) return ERR_PTR(-EINVAL); =20 periph =3D kzalloc(sizeof(*periph), GFP_KERNEL); @@ -465,8 +465,8 @@ at91_clk_register_sam9x5_peripheral(struct regmap *regm= ap, spinlock_t *lock, return ERR_PTR(-ENOMEM); =20 init.name =3D name; - if (parent_hw) - init.parent_hws =3D (const struct clk_hw **)&parent_hw; + if (parent_data) + init.parent_data =3D (const struct clk_parent_data *)parent_data; else init.parent_names =3D &parent_name; init.num_parents =3D 1; diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index b43f6652417f..b6f2aca1e1fd 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -226,13 +226,13 @@ at91_clk_sama7g5_register_master(struct regmap *regma= p, =20 struct clk_hw * __init at91_clk_register_peripheral(struct regmap *regmap, const char *name, - const char *parent_name, struct clk_hw *parent_hw, + const char *parent_name, struct clk_parent_data *parent_data, u32 id); struct clk_hw * __init at91_clk_register_sam9x5_peripheral(struct regmap *regmap, spinlock_t *loc= k, const struct clk_pcr_layout *layout, const char *name, const char *parent_name, - struct clk_hw *parent_hw, + struct clk_parent_data *parent_data, u32 id, const struct clk_range *range, int chg_pid, unsigned long flags); =20 diff --git a/drivers/clk/at91/sam9x7.c b/drivers/clk/at91/sam9x7.c index edd5fd3a1fa5..d7dc5f381ebe 100644 --- a/drivers/clk/at91/sam9x7.c +++ b/drivers/clk/at91/sam9x7.c @@ -922,7 +922,7 @@ static void __init sam9x7_pmc_setup(struct device_node = *np) hw =3D at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, &sam9x7_pcr_layout, sam9x7_periphck[i].n, - NULL, sam9x7_pmc->chws[PMC_MCK], + NULL, &AT91_CLK_PD_HW(sam9x7_pmc->chws[PMC_MCK]), sam9x7_periphck[i].id, &range, INT_MIN, sam9x7_periphck[i].f); diff --git a/drivers/clk/at91/sama7d65.c b/drivers/clk/at91/sama7d65.c index 17725c175d3b..372e530f4107 100644 --- a/drivers/clk/at91/sama7d65.c +++ b/drivers/clk/at91/sama7d65.c @@ -1306,7 +1306,7 @@ static void __init sama7d65_pmc_setup(struct device_n= ode *np) &sama7d65_pcr_layout, sama7d65_periphck[i].n, NULL, - sama7d65_mckx[sama7d65_periphck[i].p].hw, + &AT91_CLK_PD_HW(sama7d65_mckx[sama7d65_periphck[i].p].hw), sama7d65_periphck[i].id, &sama7d65_periphck[i].r, sama7d65_periphck[i].chgp ? 0 : diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index 733e4fc6a515..f28fe419ae5e 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -1181,7 +1181,7 @@ static void __init sama7g5_pmc_setup(struct device_no= de *np) &sama7g5_pcr_layout, sama7g5_periphck[i].n, NULL, - sama7g5_mckx[sama7g5_periphck[i].p].hw, + &AT91_CLK_PD_HW(sama7g5_mckx[sama7g5_periphck[i].p].hw), sama7g5_periphck[i].id, &sama7g5_periphck[i].r, sama7g5_periphck[i].chgp ? 0 : --=20 2.43.0 From nobody Tue Oct 7 09:53:13 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CD981307AC6; Thu, 10 Jul 2025 20:08:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752178086; cv=none; b=Al+RnveQJ55zr2/pEkEjkDYcKRvdxlRLQNuiCjccLXHEnKtYdgmHP5Yg9lEFhgvOBC4NkovghOiG0aHWUclnIvxAUuPxosjCCeDBZWlZMgcFqXSlbwpnG2zdbXgDxoFjkmwdHAGAMcbvivN6KcAbFzr6WrwQl33t9Sl+MZyxz8o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752178086; c=relaxed/simple; bh=+MGF8oUECtyGKv0W1oc3OMpdvH9gAxZJGHtBxoptgJs=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=qJgMoliwwS2MswBwNYmmW/kp5jUSL7biaih1O2GNKn07ecJvqxIyB0cVNl/n0/U02eBusVyKYux6Yzyz7diIkVMeuZttl/cGcAFIOAr9yksPHtQt17PAozA1cp2MQeEjWtMYiDj1rCsLKNPuuFvxZEd5aQqPbkDz1gKdlRLL508= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=xLTDIPnH; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="xLTDIPnH" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1752178084; x=1783714084; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+MGF8oUECtyGKv0W1oc3OMpdvH9gAxZJGHtBxoptgJs=; b=xLTDIPnH6KDfG8DJ4g+sIJtSwPlFfTm8hdSI/bFXSSNoFy+d8B+M7oMB /CZ/I7fDI2V9rCDheeZ8REAUEwuolE0aLa8aM9vcqzT0ccRxqJ0ojqyxi BIflImzz/6zCCS4RDM/QoZEmam6k7KQYNk8DTgnrWqsxQi9tHUJhSV5Pv +w9yNDSmc71i6fTGffFJ44bTuvO+dzlkQUDvWrKFHgia+jA+3Jr4jnwNY uoFK85jLa91YmS9osA4r3UgFW1ypFwgZZaehdmmQpyO3pwt02lfpBbwNP G5LF9e8XdAx1/TP4om1KxOzByoQ9vQiS1rPp4Ojvp4nNWdQjFqMWflU9H g==; X-CSE-ConnectionGUID: VcY24SkbRKSMnNSaLxS1vA== X-CSE-MsgGUID: /sT6QqFQRwid3mMhXrBWcQ== X-IronPort-AV: E=Sophos;i="6.16,301,1744095600"; d="scan'208";a="44448161" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 10 Jul 2025 13:07:53 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Thu, 10 Jul 2025 13:07:31 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Thu, 10 Jul 2025 13:07:31 -0700 From: To: , , , , CC: , , , , Subject: [PATCH v3 06/32] clk: at91: clk-main: switch to clk parent data Date: Thu, 10 Jul 2025 13:06:59 -0700 Message-ID: <33cec8a2f82e1bc747aa4315e47d535b7cec5a63.1752176711.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Use struct clk_parent_data instead of parent_hw for the main clock. Signed-off-by: Claudiu Beznea [ryan.wanner@microchip: Add SAMA7D65 and SAM9X75 SoCs to use parent_data.] Signed-off-by: Ryan Wanner --- drivers/clk/at91/clk-main.c | 16 ++++++++-------- drivers/clk/at91/pmc.h | 4 ++-- drivers/clk/at91/sam9x7.c | 21 ++++++++++----------- drivers/clk/at91/sama7d65.c | 21 ++++++++++----------- drivers/clk/at91/sama7g5.c | 21 ++++++++++----------- 5 files changed, 40 insertions(+), 43 deletions(-) diff --git a/drivers/clk/at91/clk-main.c b/drivers/clk/at91/clk-main.c index 9b462becc693..514c5690253f 100644 --- a/drivers/clk/at91/clk-main.c +++ b/drivers/clk/at91/clk-main.c @@ -402,7 +402,7 @@ struct clk_hw * __init at91_clk_register_rm9200_main(struct regmap *regmap, const char *name, const char *parent_name, - struct clk_hw *parent_hw) + struct clk_parent_data *parent_data) { struct clk_rm9200_main *clkmain; struct clk_init_data init =3D {}; @@ -412,7 +412,7 @@ at91_clk_register_rm9200_main(struct regmap *regmap, if (!name) return ERR_PTR(-EINVAL); =20 - if (!(parent_name || parent_hw)) + if (!(parent_name || parent_data)) return ERR_PTR(-EINVAL); =20 clkmain =3D kzalloc(sizeof(*clkmain), GFP_KERNEL); @@ -421,8 +421,8 @@ at91_clk_register_rm9200_main(struct regmap *regmap, =20 init.name =3D name; init.ops =3D &rm9200_main_ops; - if (parent_hw) - init.parent_hws =3D (const struct clk_hw **)&parent_hw; + if (parent_data) + init.parent_data =3D (const struct clk_parent_data *)parent_data; else init.parent_names =3D &parent_name; init.num_parents =3D 1; @@ -552,7 +552,7 @@ struct clk_hw * __init at91_clk_register_sam9x5_main(struct regmap *regmap, const char *name, const char **parent_names, - struct clk_hw **parent_hws, + struct clk_parent_data *parent_data, int num_parents) { struct clk_sam9x5_main *clkmain; @@ -564,7 +564,7 @@ at91_clk_register_sam9x5_main(struct regmap *regmap, if (!name) return ERR_PTR(-EINVAL); =20 - if (!(parent_hws || parent_names) || !num_parents) + if (!(parent_data || parent_names) || !num_parents) return ERR_PTR(-EINVAL); =20 clkmain =3D kzalloc(sizeof(*clkmain), GFP_KERNEL); @@ -573,8 +573,8 @@ at91_clk_register_sam9x5_main(struct regmap *regmap, =20 init.name =3D name; init.ops =3D &sam9x5_main_ops; - if (parent_hws) - init.parent_hws =3D (const struct clk_hw **)parent_hws; + if (parent_data) + init.parent_data =3D (const struct clk_parent_data *)parent_data; else init.parent_names =3D parent_names; init.num_parents =3D num_parents; diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index b6f2aca1e1fd..e32a5e85d08f 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -195,11 +195,11 @@ struct clk_hw * __init at91_clk_register_rm9200_main(struct regmap *regmap, const char *name, const char *parent_name, - struct clk_hw *parent_hw); + struct clk_parent_data *parent_data); struct clk_hw * __init at91_clk_register_sam9x5_main(struct regmap *regmap, const char *name, const char **parent_names, - struct clk_hw **parent_hws, int num_parents); + struct clk_parent_data *parent_data, int num_parents); =20 struct clk_hw * __init at91_clk_register_master_pres(struct regmap *regmap, const char *name, diff --git a/drivers/clk/at91/sam9x7.c b/drivers/clk/at91/sam9x7.c index d7dc5f381ebe..eaae05ba21ad 100644 --- a/drivers/clk/at91/sam9x7.c +++ b/drivers/clk/at91/sam9x7.c @@ -747,7 +747,7 @@ static void __init sam9x7_pmc_setup(struct device_node = *np) struct regmap *regmap; struct clk_hw *hw, *main_rc_hw, *main_osc_hw, *main_xtal_hw; struct clk_hw *td_slck_hw, *md_slck_hw, *usbck_hw; - static struct clk_parent_data parent_data; + struct clk_parent_data parent_data[2]; struct clk_hw *parent_hws[9]; int i, j; =20 @@ -780,15 +780,14 @@ static void __init sam9x7_pmc_setup(struct device_nod= e *np) if (IS_ERR(main_rc_hw)) goto err_free; =20 - parent_data.name =3D main_xtal_name; - parent_data.fw_name =3D main_xtal_name; - main_osc_hw =3D at91_clk_register_main_osc(regmap, "main_osc", NULL, &par= ent_data, 0); + main_osc_hw =3D at91_clk_register_main_osc(regmap, "main_osc", NULL, + &AT91_CLK_PD_NAME(main_xtal_name, main_xtal_index), 0); if (IS_ERR(main_osc_hw)) goto err_free; =20 - parent_hws[0] =3D main_rc_hw; - parent_hws[1] =3D main_osc_hw; - hw =3D at91_clk_register_sam9x5_main(regmap, "mainck", NULL, parent_hws, = 2); + parent_data[0] =3D AT91_CLK_PD_HW(main_rc_hw); + parent_data[1] =3D AT91_CLK_PD_HW(main_osc_hw); + hw =3D at91_clk_register_sam9x5_main(regmap, "mainck", NULL, parent_data,= 2); if (IS_ERR(hw)) goto err_free; =20 @@ -805,12 +804,12 @@ static void __init sam9x7_pmc_setup(struct device_nod= e *np) case PLL_TYPE_FRAC: switch (sam9x7_plls[i][j].p) { case SAM9X7_PLL_PARENT_MAINCK: - parent_data =3D AT91_CLK_PD_NAME("mainck", -1); + parent_data[0] =3D AT91_CLK_PD_NAME("mainck", -1); hw =3D sam9x7_pmc->chws[PMC_MAIN]; break; case SAM9X7_PLL_PARENT_MAIN_XTAL: - parent_data =3D AT91_CLK_PD_NAME(main_xtal_name, - main_xtal_index); + parent_data[0] =3D AT91_CLK_PD_NAME(main_xtal_name, + main_xtal_index); hw =3D main_xtal_hw; break; default: @@ -825,7 +824,7 @@ static void __init sam9x7_pmc_setup(struct device_node = *np) hw =3D sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, sam9x7_plls[i][j].n, - &parent_data, parent_rate, i, + parent_data, parent_rate, i, sam9x7_plls[i][j].c, sam9x7_plls[i][j].l, sam9x7_plls[i][j].f); diff --git a/drivers/clk/at91/sama7d65.c b/drivers/clk/at91/sama7d65.c index 372e530f4107..1d461db0438f 100644 --- a/drivers/clk/at91/sama7d65.c +++ b/drivers/clk/at91/sama7d65.c @@ -1098,7 +1098,7 @@ static void __init sama7d65_pmc_setup(struct device_n= ode *np) struct regmap *regmap; struct clk_hw *hw, *main_rc_hw, *main_osc_hw, *main_xtal_hw; struct clk_hw *td_slck_hw, *md_slck_hw; - static struct clk_parent_data parent_data; + struct clk_parent_data parent_data[2]; struct clk_hw *parent_hws[10]; bool bypass; int i, j; @@ -1134,16 +1134,15 @@ static void __init sama7d65_pmc_setup(struct device= _node *np) =20 bypass =3D of_property_read_bool(np, "atmel,osc-bypass"); =20 - parent_data.name =3D main_xtal_name; - parent_data.fw_name =3D main_xtal_name; main_osc_hw =3D at91_clk_register_main_osc(regmap, "main_osc", NULL, - &parent_data, bypass); + &AT91_CLK_PD_NAME(main_xtal_name, main_xtal_index), + bypass); if (IS_ERR(main_osc_hw)) goto err_free; =20 - parent_hws[0] =3D main_rc_hw; - parent_hws[1] =3D main_osc_hw; - hw =3D at91_clk_register_sam9x5_main(regmap, "mainck", NULL, parent_hws, = 2); + parent_data[0] =3D AT91_CLK_PD_HW(main_rc_hw); + parent_data[1] =3D AT91_CLK_PD_HW(main_osc_hw); + hw =3D at91_clk_register_sam9x5_main(regmap, "mainck", NULL, parent_data,= 2); if (IS_ERR(hw)) goto err_free; =20 @@ -1160,12 +1159,12 @@ static void __init sama7d65_pmc_setup(struct device= _node *np) case PLL_TYPE_FRAC: switch (sama7d65_plls[i][j].p) { case SAMA7D65_PLL_PARENT_MAINCK: - parent_data =3D AT91_CLK_PD_NAME("mainck", -1); + parent_data[0] =3D AT91_CLK_PD_NAME("mainck", -1); hw =3D sama7d65_pmc->chws[PMC_MAIN]; break; case SAMA7D65_PLL_PARENT_MAIN_XTAL: - parent_data =3D AT91_CLK_PD_NAME(main_xtal_name, - main_xtal_index); + parent_data[0] =3D AT91_CLK_PD_NAME(main_xtal_name, + main_xtal_index); hw =3D main_xtal_hw; break; default: @@ -1178,7 +1177,7 @@ static void __init sama7d65_pmc_setup(struct device_n= ode *np) =20 hw =3D sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, sama7d65_plls[i][j].n, - &parent_data, parent_rate, i, + parent_data, parent_rate, i, sama7d65_plls[i][j].c, sama7d65_plls[i][j].l, sama7d65_plls[i][j].f); diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index f28fe419ae5e..f816a5551277 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -977,7 +977,7 @@ static void __init sama7g5_pmc_setup(struct device_node= *np) struct regmap *regmap; struct clk_hw *hw, *main_rc_hw, *main_osc_hw, *main_xtal_hw; struct clk_hw *td_slck_hw, *md_slck_hw; - static struct clk_parent_data parent_data; + struct clk_parent_data parent_data[2]; struct clk_hw *parent_hws[10]; bool bypass; int i, j; @@ -1013,16 +1013,15 @@ static void __init sama7g5_pmc_setup(struct device_= node *np) =20 bypass =3D of_property_read_bool(np, "atmel,osc-bypass"); =20 - parent_data.name =3D main_xtal_name; - parent_data.fw_name =3D main_xtal_name; main_osc_hw =3D at91_clk_register_main_osc(regmap, "main_osc", NULL, - &parent_data, bypass); + &AT91_CLK_PD_NAME(main_xtal_name, main_xtal_index), + bypass); if (IS_ERR(main_osc_hw)) goto err_free; =20 - parent_hws[0] =3D main_rc_hw; - parent_hws[1] =3D main_osc_hw; - hw =3D at91_clk_register_sam9x5_main(regmap, "mainck", NULL, parent_hws, = 2); + parent_data[0] =3D AT91_CLK_PD_HW(main_rc_hw); + parent_data[1] =3D AT91_CLK_PD_HW(main_osc_hw); + hw =3D at91_clk_register_sam9x5_main(regmap, "mainck", NULL, parent_data,= 2); if (IS_ERR(hw)) goto err_free; =20 @@ -1039,12 +1038,12 @@ static void __init sama7g5_pmc_setup(struct device_= node *np) case PLL_TYPE_FRAC: switch (sama7g5_plls[i][j].p) { case SAMA7G5_PLL_PARENT_MAINCK: - parent_data =3D AT91_CLK_PD_NAME("mainck", -1); + parent_data[0] =3D AT91_CLK_PD_NAME("mainck", -1); hw =3D sama7g5_pmc->chws[PMC_MAIN]; break; case SAMA7G5_PLL_PARENT_MAIN_XTAL: - parent_data =3D AT91_CLK_PD_NAME(main_xtal_name, - main_xtal_index); + parent_data[0] =3D AT91_CLK_PD_NAME(main_xtal_name, + main_xtal_index); hw =3D main_xtal_hw; break; default: @@ -1058,7 +1057,7 @@ static void __init sama7g5_pmc_setup(struct device_no= de *np) =20 hw =3D sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, sama7g5_plls[i][j].n, - &parent_data, parent_rate, i, + parent_data, parent_rate, i, sama7g5_plls[i][j].c, sama7g5_plls[i][j].l, sama7g5_plls[i][j].f); --=20 2.43.0 From nobody Tue Oct 7 09:53:13 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CAE473093DC; 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charset="utf-8" From: Claudiu Beznea Use struct clk_parent_data instead of struct parent_hw as this leads to less usage of __clk_get_hw() in SoC specific clock drivers and simpler conversion of existing SoC specific clock drivers from parent_names to modern clk_parent_data structures. Signed-off-by: Claudiu Beznea Signed-off-by: Ryan Wanner --- drivers/clk/at91/clk-utmi.c | 16 ++++++++-------- drivers/clk/at91/pmc.h | 4 ++-- drivers/clk/at91/sama7g5.c | 25 +++++++++++++++---------- 3 files changed, 25 insertions(+), 20 deletions(-) diff --git a/drivers/clk/at91/clk-utmi.c b/drivers/clk/at91/clk-utmi.c index b991180beea1..38ffe4d712a5 100644 --- a/drivers/clk/at91/clk-utmi.c +++ b/drivers/clk/at91/clk-utmi.c @@ -144,7 +144,7 @@ static struct clk_hw * __init at91_clk_register_utmi_internal(struct regmap *regmap_pmc, struct regmap *regmap_sfr, const char *name, const char *parent_name, - struct clk_hw *parent_hw, + struct clk_parent_data *parent_data, const struct clk_ops *ops, unsigned long flags) { struct clk_utmi *utmi; @@ -152,7 +152,7 @@ at91_clk_register_utmi_internal(struct regmap *regmap_p= mc, struct clk_init_data init =3D {}; int ret; =20 - if (!(parent_name || parent_hw)) + if (!(parent_name || parent_data)) return ERR_PTR(-EINVAL); =20 utmi =3D kzalloc(sizeof(*utmi), GFP_KERNEL); @@ -161,8 +161,8 @@ at91_clk_register_utmi_internal(struct regmap *regmap_p= mc, =20 init.name =3D name; init.ops =3D ops; - if (parent_hw) - init.parent_hws =3D (const struct clk_hw **)&parent_hw; + if (parent_data) + init.parent_data =3D (const struct clk_parent_data *)parent_data; else init.parent_names =3D &parent_name; init.num_parents =3D 1; @@ -185,10 +185,10 @@ at91_clk_register_utmi_internal(struct regmap *regmap= _pmc, struct clk_hw * __init at91_clk_register_utmi(struct regmap *regmap_pmc, struct regmap *regmap_sf= r, const char *name, const char *parent_name, - struct clk_hw *parent_hw) + struct clk_parent_data *parent_data) { return at91_clk_register_utmi_internal(regmap_pmc, regmap_sfr, name, - parent_name, parent_hw, &utmi_ops, CLK_SET_RATE_GATE); + parent_name, parent_data, &utmi_ops, CLK_SET_RATE_GATE); } =20 static int clk_utmi_sama7g5_prepare(struct clk_hw *hw) @@ -287,8 +287,8 @@ static const struct clk_ops sama7g5_utmi_ops =3D { =20 struct clk_hw * __init at91_clk_sama7g5_register_utmi(struct regmap *regmap_pmc, const char *name, - const char *parent_name, struct clk_hw *parent_hw) + const char *parent_name, struct clk_parent_data *parent_data) { return at91_clk_register_utmi_internal(regmap_pmc, NULL, name, - parent_name, parent_hw, &sama7g5_utmi_ops, 0); + parent_name, parent_data, &sama7g5_utmi_ops, 0); } diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index e32a5e85d08f..d9a04fddb0b1 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -299,10 +299,10 @@ at91rm9200_clk_register_usb(struct regmap *regmap, co= nst char *name, struct clk_hw * __init at91_clk_register_utmi(struct regmap *regmap_pmc, struct regmap *regmap_sf= r, const char *name, const char *parent_name, - struct clk_hw *parent_hw); + struct clk_parent_data *parent_data); =20 struct clk_hw * __init at91_clk_sama7g5_register_utmi(struct regmap *regmap, const char *name, - const char *parent_name, struct clk_hw *parent_hw); + const char *parent_name, struct clk_parent_data *parent_data); =20 #endif /* __PMC_H_ */ diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index f816a5551277..c4723b875a1d 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -975,30 +975,33 @@ static void __init sama7g5_pmc_setup(struct device_no= de *np) void **alloc_mem =3D NULL; int alloc_mem_size =3D 0; struct regmap *regmap; - struct clk_hw *hw, *main_rc_hw, *main_osc_hw, *main_xtal_hw; + struct clk_hw *hw, *main_rc_hw, *main_osc_hw; struct clk_hw *td_slck_hw, *md_slck_hw; struct clk_parent_data parent_data[2]; struct clk_hw *parent_hws[10]; + struct clk *main_xtal; bool bypass; int i, j; =20 td_slck_hw =3D __clk_get_hw(of_clk_get_by_name(np, "td_slck")); md_slck_hw =3D __clk_get_hw(of_clk_get_by_name(np, "md_slck")); - main_xtal_hw =3D __clk_get_hw(of_clk_get_by_name(np, main_xtal_name)); + if (!td_slck_hw || !md_slck_hw) + return; =20 - if (!td_slck_hw || !md_slck_hw || !main_xtal_hw) + main_xtal =3D of_clk_get(np, main_xtal_index); + if (IS_ERR(main_xtal)) return; =20 regmap =3D device_node_to_regmap(np); if (IS_ERR(regmap)) - return; + goto put_main_xtal; =20 sama7g5_pmc =3D pmc_data_allocate(PMC_MCK1 + 1, nck(sama7g5_systemck), nck(sama7g5_periphck), nck(sama7g5_gck), 8); if (!sama7g5_pmc) - return; + goto put_main_xtal; =20 alloc_mem =3D kmalloc(sizeof(void *) * (ARRAY_SIZE(sama7g5_mckx) + ARRAY_SIZE(sama7g5_gck)), @@ -1039,19 +1042,18 @@ static void __init sama7g5_pmc_setup(struct device_= node *np) switch (sama7g5_plls[i][j].p) { case SAMA7G5_PLL_PARENT_MAINCK: parent_data[0] =3D AT91_CLK_PD_NAME("mainck", -1); - hw =3D sama7g5_pmc->chws[PMC_MAIN]; + parent_rate =3D clk_hw_get_rate(sama7g5_pmc->chws[PMC_MAIN]); break; case SAMA7G5_PLL_PARENT_MAIN_XTAL: parent_data[0] =3D AT91_CLK_PD_NAME(main_xtal_name, main_xtal_index); - hw =3D main_xtal_hw; + parent_rate =3D clk_get_rate(main_xtal); break; default: /* Should not happen. */ break; } =20 - parent_rate =3D clk_hw_get_rate(hw); if (!parent_rate) return; =20 @@ -1135,7 +1137,8 @@ static void __init sama7g5_pmc_setup(struct device_no= de *np) sama7g5_pmc->chws[sama7g5_mckx[i].eid] =3D hw; } =20 - hw =3D at91_clk_sama7g5_register_utmi(regmap, "utmick", NULL, main_xtal_h= w); + hw =3D at91_clk_sama7g5_register_utmi(regmap, "utmick", NULL, + &AT91_CLK_PD_NAME(main_xtal_name, main_xtal_index)); if (IS_ERR(hw)) goto err_free; =20 @@ -1233,7 +1236,7 @@ static void __init sama7g5_pmc_setup(struct device_no= de *np) =20 of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sama7g5_pmc); =20 - return; + goto put_main_xtal; =20 err_free: if (alloc_mem) { @@ -1243,6 +1246,8 @@ static void __init sama7g5_pmc_setup(struct device_no= de *np) } =20 kfree(sama7g5_pmc); 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Thu, 10 Jul 2025 13:07:31 -0700 From: To: , , , , CC: , , , , Subject: [PATCH v3 08/32] clk: at91: clk-master: use clk_parent_data Date: Thu, 10 Jul 2025 13:07:01 -0700 Message-ID: <4b404eaaab4062464a4142e95aaa76d5cba866f0.1752176711.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Use struct clk_parent_data instead of struct parent_hw as this leads to less usage of __clk_get_hw() in SoC specific clock drivers and simpler conversion of existing SoC specific clock drivers from parent_names to modern clk_parent_data structures. The md_slck name and index are added for the SAM9X75 SoC so the clk-master can properly use parent_data. Signed-off-by: Claudiu Beznea [ryan.wanner@microchip.com: Add clk-master changes to SAM9X75 and SAMA7D65 SoCs. As well as add md_slck commit message.] Signed-off-by: Ryan Wanner --- drivers/clk/at91/clk-master.c | 24 ++++++++++++------------ drivers/clk/at91/pmc.h | 6 +++--- drivers/clk/at91/sam9x7.c | 19 ++++++++++--------- drivers/clk/at91/sama7d65.c | 23 ++++++++++------------- drivers/clk/at91/sama7g5.c | 29 +++++++++++++---------------- 5 files changed, 48 insertions(+), 53 deletions(-) diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c index 7a544e429d34..cc4f3beb51e5 100644 --- a/drivers/clk/at91/clk-master.c +++ b/drivers/clk/at91/clk-master.c @@ -473,7 +473,7 @@ static struct clk_hw * __init at91_clk_register_master_internal(struct regmap *regmap, const char *name, int num_parents, const char **parent_names, - struct clk_hw **parent_hws, + struct clk_parent_data *parent_data, const struct clk_master_layout *layout, const struct clk_master_characteristics *characteristics, const struct clk_ops *ops, spinlock_t *lock, u32 flags) @@ -485,7 +485,7 @@ at91_clk_register_master_internal(struct regmap *regmap, unsigned long irqflags; int ret; =20 - if (!name || !num_parents || !(parent_names || parent_hws) || !lock) + if (!name || !num_parents || !(parent_names || parent_data) || !lock) return ERR_PTR(-EINVAL); =20 master =3D kzalloc(sizeof(*master), GFP_KERNEL); @@ -494,8 +494,8 @@ at91_clk_register_master_internal(struct regmap *regmap, =20 init.name =3D name; init.ops =3D ops; - if (parent_hws) - init.parent_hws =3D (const struct clk_hw **)parent_hws; + if (parent_data) + init.parent_data =3D (const struct clk_parent_data *)parent_data; else init.parent_names =3D parent_names; init.num_parents =3D num_parents; @@ -531,13 +531,13 @@ struct clk_hw * __init at91_clk_register_master_pres(struct regmap *regmap, const char *name, int num_parents, const char **parent_names, - struct clk_hw **parent_hws, + struct clk_parent_data *parent_data, const struct clk_master_layout *layout, const struct clk_master_characteristics *characteristics, spinlock_t *lock) { return at91_clk_register_master_internal(regmap, name, num_parents, - parent_names, parent_hws, layout, + parent_names, parent_data, layout, characteristics, &master_pres_ops, lock, CLK_SET_RATE_GATE); @@ -546,7 +546,7 @@ at91_clk_register_master_pres(struct regmap *regmap, struct clk_hw * __init at91_clk_register_master_div(struct regmap *regmap, const char *name, const char *parent_name, - struct clk_hw *parent_hw, const struct clk_master_layout *layout, + struct clk_parent_data *parent_data, const struct clk_master_layout *lay= out, const struct clk_master_characteristics *characteristics, spinlock_t *lock, u32 flags, u32 safe_div) { @@ -560,7 +560,7 @@ at91_clk_register_master_div(struct regmap *regmap, =20 hw =3D at91_clk_register_master_internal(regmap, name, 1, parent_name ? &parent_name : NULL, - parent_hw ? &parent_hw : NULL, layout, + parent_data, layout, characteristics, ops, lock, flags); =20 @@ -812,7 +812,7 @@ struct clk_hw * __init at91_clk_sama7g5_register_master(struct regmap *regmap, const char *name, int num_parents, const char **parent_names, - struct clk_hw **parent_hws, + struct clk_parent_data *parent_data, u32 *mux_table, spinlock_t *lock, u8 id, bool critical, int chg_pid) @@ -824,7 +824,7 @@ at91_clk_sama7g5_register_master(struct regmap *regmap, unsigned int val; int ret; =20 - if (!name || !num_parents || !(parent_names || parent_hws) || !mux_table = || + if (!name || !num_parents || !(parent_names || parent_data) || !mux_table= || !lock || id > MASTER_MAX_ID) return ERR_PTR(-EINVAL); =20 @@ -834,8 +834,8 @@ at91_clk_sama7g5_register_master(struct regmap *regmap, =20 init.name =3D name; init.ops =3D &sama7g5_master_ops; - if (parent_hws) - init.parent_hws =3D (const struct clk_hw **)parent_hws; + if (parent_data) + init.parent_data =3D (const struct clk_parent_data *)parent_data; else init.parent_names =3D parent_names; init.num_parents =3D num_parents; diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index d9a04fddb0b1..54d472276fc9 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -204,14 +204,14 @@ at91_clk_register_sam9x5_main(struct regmap *regmap, = const char *name, struct clk_hw * __init at91_clk_register_master_pres(struct regmap *regmap, const char *name, int num_parents, const char **parent_names, - struct clk_hw **parent_hws, + struct clk_parent_data *parent_data, const struct clk_master_layout *layout, const struct clk_master_characteristics *characteristics, spinlock_t *lock); =20 struct clk_hw * __init at91_clk_register_master_div(struct regmap *regmap, const char *name, - const char *parent_names, struct clk_hw *parent_hw, + const char *parent_names, struct clk_parent_data *parent_data, const struct clk_master_layout *layout, const struct clk_master_characteristics *characteristics, spinlock_t *lock, u32 flags, u32 safe_div); @@ -220,7 +220,7 @@ struct clk_hw * __init at91_clk_sama7g5_register_master(struct regmap *regmap, const char *name, int num_parents, const char **parent_names, - struct clk_hw **parent_hws, u32 *mux_table, + struct clk_parent_data *parent_data, u32 *mux_table, spinlock_t *lock, u8 id, bool critical, int chg_pid); =20 diff --git a/drivers/clk/at91/sam9x7.c b/drivers/clk/at91/sam9x7.c index eaae05ba21ad..945983f72140 100644 --- a/drivers/clk/at91/sam9x7.c +++ b/drivers/clk/at91/sam9x7.c @@ -739,7 +739,8 @@ static void __init sam9x7_pmc_setup(struct device_node = *np) { struct clk_range range =3D CLK_RANGE(0, 0); const char *main_xtal_name =3D "main_xtal"; - u8 main_xtal_index =3D 2; + const char *const md_slck_name =3D "md_slck"; + u8 md_slck_index =3D 1, main_xtal_index =3D 2; struct pmc_data *sam9x7_pmc; const char *parent_names[9]; void **clk_mux_buffer =3D NULL; @@ -747,12 +748,12 @@ static void __init sam9x7_pmc_setup(struct device_nod= e *np) struct regmap *regmap; struct clk_hw *hw, *main_rc_hw, *main_osc_hw, *main_xtal_hw; struct clk_hw *td_slck_hw, *md_slck_hw, *usbck_hw; - struct clk_parent_data parent_data[2]; + struct clk_parent_data parent_data[9]; struct clk_hw *parent_hws[9]; int i, j; =20 td_slck_hw =3D __clk_get_hw(of_clk_get_by_name(np, "td_slck")); - md_slck_hw =3D __clk_get_hw(of_clk_get_by_name(np, "md_slck")); + md_slck_hw =3D __clk_get_hw(of_clk_get_by_name(np, md_slck_name)); main_xtal_hw =3D __clk_get_hw(of_clk_get_by_name(np, main_xtal_name)); =20 if (!td_slck_hw || !md_slck_hw || !main_xtal_hw) @@ -853,18 +854,18 @@ static void __init sam9x7_pmc_setup(struct device_nod= e *np) } } =20 - parent_hws[0] =3D md_slck_hw; - parent_hws[1] =3D sam9x7_pmc->chws[PMC_MAIN]; - parent_hws[2] =3D sam9x7_plls[PLL_ID_PLLA][PLL_COMPID_DIV0].hw; - parent_hws[3] =3D sam9x7_plls[PLL_ID_UPLL][PLL_COMPID_DIV0].hw; + parent_data[0] =3D AT91_CLK_PD_NAME(md_slck_name, md_slck_index); + parent_data[1] =3D AT91_CLK_PD_HW(sam9x7_pmc->chws[PMC_MAIN]); + parent_data[2] =3D AT91_CLK_PD_HW(sam9x7_plls[PLL_ID_PLLA][PLL_COMPID_DIV= 0].hw); + parent_data[3] =3D AT91_CLK_PD_HW(sam9x7_plls[PLL_ID_UPLL][PLL_COMPID_DIV= 0].hw); hw =3D at91_clk_register_master_pres(regmap, "masterck_pres", 4, - NULL, parent_hws, &sam9x7_master_layout, + NULL, parent_data, &sam9x7_master_layout, &mck_characteristics, &mck_lock); if (IS_ERR(hw)) goto err_free; =20 hw =3D at91_clk_register_master_div(regmap, "masterck_div", - NULL, hw, &sam9x7_master_layout, + NULL, &AT91_CLK_PD_HW(hw), &sam9x7_master_layout, &mck_characteristics, &mck_lock, CLK_SET_RATE_GATE, 0); if (IS_ERR(hw)) diff --git a/drivers/clk/at91/sama7d65.c b/drivers/clk/at91/sama7d65.c index 1d461db0438f..174b2317081f 100644 --- a/drivers/clk/at91/sama7d65.c +++ b/drivers/clk/at91/sama7d65.c @@ -1089,16 +1089,16 @@ static const struct clk_pcr_layout sama7d65_pcr_lay= out =3D { =20 static void __init sama7d65_pmc_setup(struct device_node *np) { - const char *main_xtal_name =3D "main_xtal"; - u8 main_xtal_index =3D 2; + u8 td_slck_index =3D 0, md_slck_index =3D 1, main_xtal_index =3D 2; + struct clk_hw *hw, *main_rc_hw, *main_osc_hw, *main_xtal_hw; + const char * const main_xtal_name =3D "main_xtal"; + struct clk_parent_data parent_data[10]; struct pmc_data *sama7d65_pmc; const char *parent_names[11]; void **alloc_mem =3D NULL; int alloc_mem_size =3D 0; struct regmap *regmap; - struct clk_hw *hw, *main_rc_hw, *main_osc_hw, *main_xtal_hw; struct clk_hw *td_slck_hw, *md_slck_hw; - struct clk_parent_data parent_data[2]; struct clk_hw *parent_hws[10]; bool bypass; int i, j; @@ -1207,7 +1207,7 @@ static void __init sama7d65_pmc_setup(struct device_n= ode *np) } =20 hw =3D at91_clk_register_master_div(regmap, "mck0", NULL, - sama7d65_plls[PLL_ID_CPU][1].hw, + &AT91_CLK_PD_HW(sama7d65_plls[PLL_ID_CPU][1].hw), &mck0_layout, &mck0_characteristics, &pmc_mck0_lock, CLK_GET_RATE_NOCACHE, 5); if (IS_ERR(hw)) @@ -1216,12 +1216,11 @@ static void __init sama7d65_pmc_setup(struct device= _node *np) sama7d65_pmc->chws[PMC_MCK] =3D hw; sama7d65_mckx[PCK_PARENT_HW_MCK0].hw =3D hw; =20 - parent_hws[0] =3D md_slck_hw; - parent_hws[1] =3D td_slck_hw; - parent_hws[2] =3D sama7d65_pmc->chws[PMC_MAIN]; + parent_data[0] =3D AT91_CLK_PD_NAME("md_slck", md_slck_index); + parent_data[1] =3D AT91_CLK_PD_NAME("td_slck", td_slck_index); + parent_data[2] =3D AT91_CLK_PD_HW(sama7d65_pmc->chws[PMC_MAIN]); for (i =3D PCK_PARENT_HW_MCK1; i < ARRAY_SIZE(sama7d65_mckx); i++) { u8 num_parents =3D 3 + sama7d65_mckx[i].ep_count; - struct clk_hw *tmp_parent_hws[8]; u32 *mux_table; =20 mux_table =3D kmalloc_array(num_parents, sizeof(*mux_table), @@ -1238,13 +1237,11 @@ static void __init sama7d65_pmc_setup(struct device= _node *np) u8 pll_id =3D sama7d65_mckx[i].ep[j].pll_id; u8 pll_compid =3D sama7d65_mckx[i].ep[j].pll_compid; =20 - tmp_parent_hws[j] =3D sama7d65_plls[pll_id][pll_compid].hw; + parent_data[3 + j] =3D AT91_CLK_PD_HW(sama7d65_plls[pll_id][pll_compid]= .hw); } - PMC_FILL_TABLE(&parent_hws[3], tmp_parent_hws, - sama7d65_mckx[i].ep_count); =20 hw =3D at91_clk_sama7g5_register_master(regmap, sama7d65_mckx[i].n, - num_parents, NULL, parent_hws, + num_parents, NULL, parent_data, mux_table, &pmc_mckX_lock, sama7d65_mckx[i].id, sama7d65_mckx[i].c, diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index c4723b875a1d..263cdfc0858c 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -969,17 +969,17 @@ static const struct clk_pcr_layout sama7g5_pcr_layout= =3D { =20 static void __init sama7g5_pmc_setup(struct device_node *np) { - const char *main_xtal_name =3D "main_xtal"; - u8 main_xtal_index =3D 2; - struct pmc_data *sama7g5_pmc; - void **alloc_mem =3D NULL; - int alloc_mem_size =3D 0; - struct regmap *regmap; + u8 td_slck_index =3D 0, md_slck_index =3D 1, main_xtal_index =3D 2; + const char * const main_xtal_name =3D "main_xtal"; struct clk_hw *hw, *main_rc_hw, *main_osc_hw; + struct clk_parent_data parent_data[10]; struct clk_hw *td_slck_hw, *md_slck_hw; - struct clk_parent_data parent_data[2]; struct clk_hw *parent_hws[10]; + struct pmc_data *sama7g5_pmc; + void **alloc_mem =3D NULL; + int alloc_mem_size =3D 0; struct clk *main_xtal; + struct regmap *regmap; bool bypass; int i, j; =20 @@ -1089,7 +1089,7 @@ static void __init sama7g5_pmc_setup(struct device_no= de *np) } =20 hw =3D at91_clk_register_master_div(regmap, "mck0", NULL, - sama7g5_plls[PLL_ID_CPU][1].hw, + &AT91_CLK_PD_HW(sama7g5_plls[PLL_ID_CPU][1].hw), &mck0_layout, &mck0_characteristics, &pmc_mck0_lock, CLK_GET_RATE_NOCACHE, 5); if (IS_ERR(hw)) @@ -1097,12 +1097,11 @@ static void __init sama7g5_pmc_setup(struct device_= node *np) =20 sama7g5_mckx[PCK_PARENT_HW_MCK0].hw =3D sama7g5_pmc->chws[PMC_MCK] =3D hw; =20 - parent_hws[0] =3D md_slck_hw; - parent_hws[1] =3D td_slck_hw; - parent_hws[2] =3D sama7g5_pmc->chws[PMC_MAIN]; + parent_data[0] =3D AT91_CLK_PD_NAME("md_slck", md_slck_index); + parent_data[1] =3D AT91_CLK_PD_NAME("td_slck", td_slck_index); + parent_data[2] =3D AT91_CLK_PD_HW(sama7g5_pmc->chws[PMC_MAIN]); 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charset="utf-8" From: Claudiu Beznea Use struct clk_parent_data instead of struct parent_hw as this leads to less usage of __clk_get_hw() in SoC specific clock drivers and simpler conversion of existing SoC specific clock drivers from parent_names to modern clk_parent_data structures. Signed-off-by: Claudiu Beznea [ryan.wanner@microchip.com: Add the clk-programmable changes to the SAMA7D65 and SAM9X75 SoCs. Add td_slck_name variable and index for the SAM9X75.] Signed-off-by: Ryan Wanner --- drivers/clk/at91/clk-programmable.c | 8 ++++---- drivers/clk/at91/pmc.h | 2 +- drivers/clk/at91/sam9x7.c | 21 +++++++++++---------- drivers/clk/at91/sama7d65.c | 20 ++++++++++---------- drivers/clk/at91/sama7g5.c | 20 ++++++++++---------- 5 files changed, 36 insertions(+), 35 deletions(-) diff --git a/drivers/clk/at91/clk-programmable.c b/drivers/clk/at91/clk-pro= grammable.c index 1195fb405503..275ca701f294 100644 --- a/drivers/clk/at91/clk-programmable.c +++ b/drivers/clk/at91/clk-programmable.c @@ -215,7 +215,7 @@ static const struct clk_ops programmable_ops =3D { struct clk_hw * __init at91_clk_register_programmable(struct regmap *regmap, const char *name, const char **parent_names, - struct clk_hw **parent_hws, u8 num_parents, u8 id, + struct clk_parent_data *parent_data, u8 num_parents, u8 id, const struct clk_programmable_layout *layout, u32 *mux_table) { @@ -224,7 +224,7 @@ at91_clk_register_programmable(struct regmap *regmap, struct clk_init_data init =3D {}; int ret; =20 - if (id > PROG_ID_MAX || !(parent_names || parent_hws)) + if (id > PROG_ID_MAX || !(parent_names || parent_data)) return ERR_PTR(-EINVAL); =20 prog =3D kzalloc(sizeof(*prog), GFP_KERNEL); @@ -233,8 +233,8 @@ at91_clk_register_programmable(struct regmap *regmap, =20 init.name =3D name; init.ops =3D &programmable_ops; - if (parent_hws) - init.parent_hws =3D (const struct clk_hw **)parent_hws; + if (parent_data) + init.parent_data =3D (const struct clk_parent_data *)parent_data; else init.parent_names =3D parent_names; init.num_parents =3D num_parents; diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index 54d472276fc9..34036f2d0578 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -263,7 +263,7 @@ sam9x60_clk_register_frac_pll(struct regmap *regmap, sp= inlock_t *lock, =20 struct clk_hw * __init at91_clk_register_programmable(struct regmap *regmap, const char *name, - const char **parent_names, struct clk_hw **parent_hws, + const char **parent_names, struct clk_parent_data *parent_data, u8 num_parents, u8 id, const struct clk_programmable_layout *layout, u32 *mux_table); diff --git a/drivers/clk/at91/sam9x7.c b/drivers/clk/at91/sam9x7.c index 945983f72140..86d624cd92b2 100644 --- a/drivers/clk/at91/sam9x7.c +++ b/drivers/clk/at91/sam9x7.c @@ -737,10 +737,11 @@ static const struct { =20 static void __init sam9x7_pmc_setup(struct device_node *np) { + u8 td_slck_index =3D 0, md_slck_index =3D 1, main_xtal_index =3D 2; struct clk_range range =3D CLK_RANGE(0, 0); const char *main_xtal_name =3D "main_xtal"; + const char * const td_slck_name =3D "td_slck"; const char *const md_slck_name =3D "md_slck"; - u8 md_slck_index =3D 1, main_xtal_index =3D 2; struct pmc_data *sam9x7_pmc; const char *parent_names[9]; void **clk_mux_buffer =3D NULL; @@ -752,7 +753,7 @@ static void __init sam9x7_pmc_setup(struct device_node = *np) struct clk_hw *parent_hws[9]; int i, j; =20 - td_slck_hw =3D __clk_get_hw(of_clk_get_by_name(np, "td_slck")); + td_slck_hw =3D __clk_get_hw(of_clk_get_by_name(np, td_slck_name)); md_slck_hw =3D __clk_get_hw(of_clk_get_by_name(np, md_slck_name)); main_xtal_hw =3D __clk_get_hw(of_clk_get_by_name(np, main_xtal_name)); =20 @@ -880,20 +881,20 @@ static void __init sam9x7_pmc_setup(struct device_nod= e *np) if (IS_ERR(usbck_hw)) goto err_free; =20 - parent_hws[0] =3D md_slck_hw; - parent_hws[1] =3D td_slck_hw; - parent_hws[2] =3D sam9x7_pmc->chws[PMC_MAIN]; - parent_hws[3] =3D sam9x7_pmc->chws[PMC_MCK]; - parent_hws[4] =3D sam9x7_plls[PLL_ID_PLLA][PLL_COMPID_DIV0].hw; - parent_hws[5] =3D sam9x7_plls[PLL_ID_UPLL][PLL_COMPID_DIV0].hw; - parent_hws[6] =3D sam9x7_plls[PLL_ID_AUDIO][PLL_COMPID_DIV0].hw; + parent_data[0] =3D AT91_CLK_PD_NAME(md_slck_name, md_slck_index); + parent_data[1] =3D AT91_CLK_PD_NAME(td_slck_name, td_slck_index); + parent_data[2] =3D AT91_CLK_PD_HW(sam9x7_pmc->chws[PMC_MAIN]); + parent_data[3] =3D AT91_CLK_PD_HW(sam9x7_pmc->chws[PMC_MCK]); + parent_data[4] =3D AT91_CLK_PD_HW(sam9x7_plls[PLL_ID_PLLA][PLL_COMPID_DIV= 0].hw); + parent_data[5] =3D AT91_CLK_PD_HW(sam9x7_plls[PLL_ID_UPLL][PLL_COMPID_DIV= 0].hw); + parent_data[6] =3D AT91_CLK_PD_HW(sam9x7_plls[PLL_ID_AUDIO][PLL_COMPID_DI= V0].hw); for (i =3D 0; i < 2; i++) { char name[6]; =20 snprintf(name, sizeof(name), "prog%d", i); =20 hw =3D at91_clk_register_programmable(regmap, name, - NULL, parent_hws, 7, i, + NULL, parent_data, 7, i, &sam9x7_programmable_layout, NULL); if (IS_ERR(hw)) diff --git a/drivers/clk/at91/sama7d65.c b/drivers/clk/at91/sama7d65.c index 174b2317081f..7463719260e0 100644 --- a/drivers/clk/at91/sama7d65.c +++ b/drivers/clk/at91/sama7d65.c @@ -1262,22 +1262,22 @@ static void __init sama7d65_pmc_setup(struct device= _node *np) if (IS_ERR(hw)) goto err_free; =20 - parent_hws[0] =3D md_slck_hw; - parent_hws[1] =3D td_slck_hw; - parent_hws[2] =3D sama7d65_pmc->chws[PMC_MAIN]; - parent_hws[3] =3D sama7d65_plls[PLL_ID_SYS][PLL_COMPID_DIV0].hw; - parent_hws[4] =3D sama7d65_plls[PLL_ID_DDR][PLL_COMPID_DIV0].hw; - parent_hws[5] =3D sama7d65_plls[PLL_ID_GPU][PLL_COMPID_DIV0].hw; - parent_hws[6] =3D sama7d65_plls[PLL_ID_BAUD][PLL_COMPID_DIV0].hw; - parent_hws[7] =3D sama7d65_plls[PLL_ID_AUDIO][PLL_COMPID_DIV0].hw; - parent_hws[8] =3D sama7d65_plls[PLL_ID_ETH][PLL_COMPID_DIV0].hw; + parent_data[0] =3D AT91_CLK_PD_NAME("md_slck", md_slck_index); + parent_data[1] =3D AT91_CLK_PD_NAME("td_slck", td_slck_index); + parent_data[2] =3D AT91_CLK_PD_HW(sama7d65_pmc->chws[PMC_MAIN]); + parent_data[3] =3D AT91_CLK_PD_HW(sama7d65_plls[PLL_ID_SYS][PLL_COMPID_DI= V0].hw); + parent_data[4] =3D AT91_CLK_PD_HW(sama7d65_plls[PLL_ID_DDR][PLL_COMPID_DI= V0].hw); + parent_data[5] =3D AT91_CLK_PD_HW(sama7d65_plls[PLL_ID_GPU][PLL_COMPID_DI= V0].hw); + parent_data[6] =3D AT91_CLK_PD_HW(sama7d65_plls[PLL_ID_BAUD][PLL_COMPID_D= IV0].hw); + parent_data[7] =3D AT91_CLK_PD_HW(sama7d65_plls[PLL_ID_AUDIO][PLL_COMPID_= DIV0].hw); + parent_data[8] =3D AT91_CLK_PD_HW(sama7d65_plls[PLL_ID_ETH][PLL_COMPID_DI= V0].hw); =20 for (i =3D 0; i < 8; i++) { char name[6]; =20 snprintf(name, sizeof(name), "prog%d", i); =20 - hw =3D at91_clk_register_programmable(regmap, name, NULL, parent_hws, + hw =3D at91_clk_register_programmable(regmap, name, NULL, parent_data, 9, i, &programmable_layout, sama7d65_prog_mux_table); diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index 263cdfc0858c..a6824d0accb9 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -1141,21 +1141,21 @@ static void __init sama7g5_pmc_setup(struct device_= node *np) =20 sama7g5_pmc->chws[PMC_UTMI] =3D hw; =20 - parent_hws[0] =3D md_slck_hw; - parent_hws[1] =3D td_slck_hw; - parent_hws[2] =3D sama7g5_pmc->chws[PMC_MAIN]; - parent_hws[3] =3D sama7g5_plls[PLL_ID_SYS][PLL_COMPID_DIV0].hw; - parent_hws[4] =3D sama7g5_plls[PLL_ID_DDR][PLL_COMPID_DIV0].hw; - parent_hws[5] =3D sama7g5_plls[PLL_ID_IMG][PLL_COMPID_DIV0].hw; - parent_hws[6] =3D sama7g5_plls[PLL_ID_BAUD][PLL_COMPID_DIV0].hw; - parent_hws[7] =3D sama7g5_plls[PLL_ID_AUDIO][PLL_COMPID_DIV0].hw; - parent_hws[8] =3D sama7g5_plls[PLL_ID_ETH][PLL_COMPID_DIV0].hw; + parent_data[0] =3D AT91_CLK_PD_NAME("md_slck", md_slck_index); + parent_data[1] =3D AT91_CLK_PD_NAME("td_slck", td_slck_index); + parent_data[2] =3D AT91_CLK_PD_HW(sama7g5_pmc->chws[PMC_MAIN]); + parent_data[3] =3D AT91_CLK_PD_HW(sama7g5_plls[PLL_ID_SYS][PLL_COMPID_DIV= 0].hw); + parent_data[4] =3D AT91_CLK_PD_HW(sama7g5_plls[PLL_ID_DDR][PLL_COMPID_DIV= 0].hw); + parent_data[5] =3D AT91_CLK_PD_HW(sama7g5_plls[PLL_ID_IMG][PLL_COMPID_DIV= 0].hw); + parent_data[6] =3D AT91_CLK_PD_HW(sama7g5_plls[PLL_ID_BAUD][PLL_COMPID_DI= V0].hw); + parent_data[7] =3D AT91_CLK_PD_HW(sama7g5_plls[PLL_ID_AUDIO][PLL_COMPID_D= IV0].hw); + parent_data[8] =3D AT91_CLK_PD_HW(sama7g5_plls[PLL_ID_ETH][PLL_COMPID_DIV= 0].hw); for (i =3D 0; i < 8; i++) { char name[6]; =20 snprintf(name, sizeof(name), "prog%d", i); =20 - hw =3D at91_clk_register_programmable(regmap, name, NULL, parent_hws, + hw =3D at91_clk_register_programmable(regmap, name, NULL, parent_data, 9, i, &programmable_layout, sama7g5_prog_mux_table); --=20 2.43.0 From nobody Tue Oct 7 09:53:13 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED16E309DC6; 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X-CSE-ConnectionGUID: VcY24SkbRKSMnNSaLxS1vA== X-CSE-MsgGUID: PvhPmzYTQ0OL19DYvW8p/A== X-IronPort-AV: E=Sophos;i="6.16,301,1744095600"; d="scan'208";a="44448165" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 10 Jul 2025 13:07:54 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Thu, 10 Jul 2025 13:07:31 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Thu, 10 Jul 2025 13:07:31 -0700 From: To: , , , , CC: , , , , Subject: [PATCH v3 10/32] clk: at91: clk-generated: use clk_parent_data Date: Thu, 10 Jul 2025 13:07:03 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Use struct clk_parent_data instead of struct parent_hw as this leads to less usage of __clk_get_hw() in SoC specific clock drivers and simpler conversion of existing SoC specific clock drivers from parent_names to modern clk_parent_data structures. Signed-off-by: Claudiu Beznea [ryan.wanner@microchip.com: Added SAMA7D65 and SAM9X75 SoCs to the clk-generated changes. Adjust clk name variable order.] Signed-off-by: Ryan Wanner --- drivers/clk/at91/clk-generated.c | 8 ++++---- drivers/clk/at91/pmc.h | 2 +- drivers/clk/at91/sam9x7.c | 26 ++++++++++---------------- drivers/clk/at91/sama7d65.c | 31 +++++++++++++------------------ drivers/clk/at91/sama7g5.c | 30 +++++++++++------------------- 5 files changed, 39 insertions(+), 58 deletions(-) diff --git a/drivers/clk/at91/clk-generated.c b/drivers/clk/at91/clk-genera= ted.c index 4b4edeecc889..d9e00167dbc8 100644 --- a/drivers/clk/at91/clk-generated.c +++ b/drivers/clk/at91/clk-generated.c @@ -319,7 +319,7 @@ struct clk_hw * __init at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock, const struct clk_pcr_layout *layout, const char *name, const char **parent_names, - struct clk_hw **parent_hws, + struct clk_parent_data *parent_data, u32 *mux_table, u8 num_parents, u8 id, const struct clk_range *range, int chg_pid) @@ -329,7 +329,7 @@ at91_clk_register_generated(struct regmap *regmap, spin= lock_t *lock, struct clk_hw *hw; int ret; =20 - if (!(parent_names || parent_hws)) + if (!(parent_names || parent_data)) return ERR_PTR(-ENOMEM); =20 gck =3D kzalloc(sizeof(*gck), GFP_KERNEL); @@ -338,8 +338,8 @@ at91_clk_register_generated(struct regmap *regmap, spin= lock_t *lock, =20 init.name =3D name; init.ops =3D &generated_ops; - if (parent_hws) - init.parent_hws =3D (const struct clk_hw **)parent_hws; + if (parent_data) + init.parent_data =3D (const struct clk_parent_data *)parent_data; else init.parent_names =3D parent_names; init.num_parents =3D num_parents; diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index 34036f2d0578..0646775dfb1d 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -171,7 +171,7 @@ struct clk_hw * __init at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock, const struct clk_pcr_layout *layout, const char *name, const char **parent_names, - struct clk_hw **parent_hws, u32 *mux_table, + struct clk_parent_data *parent_data, u32 *mux_table, u8 num_parents, u8 id, const struct clk_range *range, int chg_pid); =20 diff --git a/drivers/clk/at91/sam9x7.c b/drivers/clk/at91/sam9x7.c index 86d624cd92b2..c4578944611e 100644 --- a/drivers/clk/at91/sam9x7.c +++ b/drivers/clk/at91/sam9x7.c @@ -739,8 +739,8 @@ static void __init sam9x7_pmc_setup(struct device_node = *np) { u8 td_slck_index =3D 0, md_slck_index =3D 1, main_xtal_index =3D 2; struct clk_range range =3D CLK_RANGE(0, 0); - const char *main_xtal_name =3D "main_xtal"; - const char * const td_slck_name =3D "td_slck"; + const char *const main_xtal_name =3D "main_xtal"; + const char *const td_slck_name =3D "td_slck"; const char *const md_slck_name =3D "md_slck"; struct pmc_data *sam9x7_pmc; const char *parent_names[9]; @@ -748,16 +748,13 @@ static void __init sam9x7_pmc_setup(struct device_nod= e *np) int clk_mux_buffer_size =3D 0; struct regmap *regmap; struct clk_hw *hw, *main_rc_hw, *main_osc_hw, *main_xtal_hw; - struct clk_hw *td_slck_hw, *md_slck_hw, *usbck_hw; + struct clk_hw *usbck_hw; struct clk_parent_data parent_data[9]; - struct clk_hw *parent_hws[9]; int i, j; =20 - td_slck_hw =3D __clk_get_hw(of_clk_get_by_name(np, td_slck_name)); - md_slck_hw =3D __clk_get_hw(of_clk_get_by_name(np, md_slck_name)); main_xtal_hw =3D __clk_get_hw(of_clk_get_by_name(np, main_xtal_name)); =20 - if (!td_slck_hw || !md_slck_hw || !main_xtal_hw) + if (!main_xtal_hw) return; =20 regmap =3D device_node_to_regmap(np); @@ -933,13 +930,12 @@ static void __init sam9x7_pmc_setup(struct device_nod= e *np) sam9x7_pmc->phws[sam9x7_periphck[i].id] =3D hw; } =20 - parent_hws[0] =3D md_slck_hw; - parent_hws[1] =3D td_slck_hw; - parent_hws[2] =3D sam9x7_pmc->chws[PMC_MAIN]; - parent_hws[3] =3D sam9x7_pmc->chws[PMC_MCK]; + parent_data[0] =3D AT91_CLK_PD_NAME(md_slck_name, md_slck_index); + parent_data[1] =3D AT91_CLK_PD_NAME(td_slck_name, td_slck_index); + parent_data[2] =3D AT91_CLK_PD_HW(sam9x7_pmc->chws[PMC_MAIN]); + parent_data[3] =3D AT91_CLK_PD_HW(sam9x7_pmc->chws[PMC_MCK]); for (i =3D 0; i < ARRAY_SIZE(sam9x7_gck); i++) { u8 num_parents =3D 4 + sam9x7_gck[i].pp_count; - struct clk_hw *tmp_parent_hws[6]; u32 *mux_table; =20 mux_table =3D kmalloc_array(num_parents, sizeof(*mux_table), @@ -954,15 +950,13 @@ static void __init sam9x7_pmc_setup(struct device_nod= e *np) u8 pll_id =3D sam9x7_gck[i].pp[j].pll_id; u8 pll_compid =3D sam9x7_gck[i].pp[j].pll_compid; =20 - tmp_parent_hws[j] =3D sam9x7_plls[pll_id][pll_compid].hw; + parent_data[4 + j] =3D AT91_CLK_PD_HW(sam9x7_plls[pll_id][pll_compid].h= w); } - PMC_FILL_TABLE(&parent_hws[4], tmp_parent_hws, - sam9x7_gck[i].pp_count); =20 hw =3D at91_clk_register_generated(regmap, &pmc_pcr_lock, &sam9x7_pcr_layout, sam9x7_gck[i].n, - NULL, parent_hws, mux_table, + NULL, parent_data, mux_table, num_parents, sam9x7_gck[i].id, &sam9x7_gck[i].r, diff --git a/drivers/clk/at91/sama7d65.c b/drivers/clk/at91/sama7d65.c index 7463719260e0..4d47d20e65fb 100644 --- a/drivers/clk/at91/sama7d65.c +++ b/drivers/clk/at91/sama7d65.c @@ -1092,22 +1092,20 @@ static void __init sama7d65_pmc_setup(struct device= _node *np) u8 td_slck_index =3D 0, md_slck_index =3D 1, main_xtal_index =3D 2; struct clk_hw *hw, *main_rc_hw, *main_osc_hw, *main_xtal_hw; const char * const main_xtal_name =3D "main_xtal"; + const char * const td_slck_name =3D "td_slck"; + const char * const md_slck_name =3D "md_slck"; struct clk_parent_data parent_data[10]; struct pmc_data *sama7d65_pmc; const char *parent_names[11]; void **alloc_mem =3D NULL; int alloc_mem_size =3D 0; struct regmap *regmap; - struct clk_hw *td_slck_hw, *md_slck_hw; - struct clk_hw *parent_hws[10]; bool bypass; int i, j; =20 - td_slck_hw =3D __clk_get_hw(of_clk_get_by_name(np, "td_slck")); - md_slck_hw =3D __clk_get_hw(of_clk_get_by_name(np, "md_slck")); main_xtal_hw =3D __clk_get_hw(of_clk_get_by_name(np, main_xtal_name)); =20 - if (!td_slck_hw || !md_slck_hw || !main_xtal_hw) + if (!main_xtal_hw) return; =20 regmap =3D device_node_to_regmap(np); @@ -1216,8 +1214,8 @@ static void __init sama7d65_pmc_setup(struct device_n= ode *np) sama7d65_pmc->chws[PMC_MCK] =3D hw; sama7d65_mckx[PCK_PARENT_HW_MCK0].hw =3D hw; =20 - parent_data[0] =3D AT91_CLK_PD_NAME("md_slck", md_slck_index); - parent_data[1] =3D AT91_CLK_PD_NAME("td_slck", td_slck_index); + parent_data[0] =3D AT91_CLK_PD_NAME(md_slck_name, md_slck_index); + parent_data[1] =3D AT91_CLK_PD_NAME(td_slck_name, td_slck_index); parent_data[2] =3D AT91_CLK_PD_HW(sama7d65_pmc->chws[PMC_MAIN]); for (i =3D PCK_PARENT_HW_MCK1; i < ARRAY_SIZE(sama7d65_mckx); i++) { u8 num_parents =3D 3 + sama7d65_mckx[i].ep_count; @@ -1262,8 +1260,8 @@ static void __init sama7d65_pmc_setup(struct device_n= ode *np) if (IS_ERR(hw)) goto err_free; =20 - parent_data[0] =3D AT91_CLK_PD_NAME("md_slck", md_slck_index); - parent_data[1] =3D AT91_CLK_PD_NAME("td_slck", td_slck_index); + parent_data[0] =3D AT91_CLK_PD_NAME(md_slck_name, md_slck_index); + parent_data[1] =3D AT91_CLK_PD_NAME(td_slck_name, td_slck_index); parent_data[2] =3D AT91_CLK_PD_HW(sama7d65_pmc->chws[PMC_MAIN]); parent_data[3] =3D AT91_CLK_PD_HW(sama7d65_plls[PLL_ID_SYS][PLL_COMPID_DI= V0].hw); parent_data[4] =3D AT91_CLK_PD_HW(sama7d65_plls[PLL_ID_DDR][PLL_COMPID_DI= V0].hw); @@ -1313,13 +1311,12 @@ static void __init sama7d65_pmc_setup(struct device= _node *np) sama7d65_pmc->phws[sama7d65_periphck[i].id] =3D hw; } =20 - parent_hws[0] =3D md_slck_hw; - parent_hws[1] =3D td_slck_hw; - parent_hws[2] =3D sama7d65_pmc->chws[PMC_MAIN]; - parent_hws[3] =3D sama7d65_pmc->chws[PMC_MCK1]; + parent_data[0] =3D AT91_CLK_PD_NAME(md_slck_name, md_slck_index); + parent_data[1] =3D AT91_CLK_PD_NAME(td_slck_name, td_slck_index); + parent_data[2] =3D AT91_CLK_PD_HW(sama7d65_pmc->chws[PMC_MAIN]); + parent_data[3] =3D AT91_CLK_PD_HW(sama7d65_pmc->chws[PMC_MCK1]); for (i =3D 0; i < ARRAY_SIZE(sama7d65_gck); i++) { u8 num_parents =3D 4 + sama7d65_gck[i].pp_count; - struct clk_hw *tmp_parent_hws[8]; u32 *mux_table; =20 mux_table =3D kmalloc_array(num_parents, sizeof(*mux_table), @@ -1336,15 +1333,13 @@ static void __init sama7d65_pmc_setup(struct device= _node *np) u8 pll_id =3D sama7d65_gck[i].pp[j].pll_id; u8 pll_compid =3D sama7d65_gck[i].pp[j].pll_compid; =20 - tmp_parent_hws[j] =3D sama7d65_plls[pll_id][pll_compid].hw; + parent_data[4 + j] =3D AT91_CLK_PD_HW(sama7d65_plls[pll_id][pll_compid]= .hw); } - PMC_FILL_TABLE(&parent_hws[4], tmp_parent_hws, - sama7d65_gck[i].pp_count); =20 hw =3D at91_clk_register_generated(regmap, &pmc_pcr_lock, &sama7d65_pcr_layout, sama7d65_gck[i].n, NULL, - parent_hws, mux_table, + parent_data, mux_table, num_parents, sama7d65_gck[i].id, &sama7d65_gck[i].r, diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index a6824d0accb9..505db97e989b 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -971,10 +971,10 @@ static void __init sama7g5_pmc_setup(struct device_no= de *np) { u8 td_slck_index =3D 0, md_slck_index =3D 1, main_xtal_index =3D 2; const char * const main_xtal_name =3D "main_xtal"; + const char * const td_slck_name =3D "td_slck"; + const char * const md_slck_name =3D "md_slck"; struct clk_hw *hw, *main_rc_hw, *main_osc_hw; struct clk_parent_data parent_data[10]; - struct clk_hw *td_slck_hw, *md_slck_hw; - struct clk_hw *parent_hws[10]; struct pmc_data *sama7g5_pmc; void **alloc_mem =3D NULL; int alloc_mem_size =3D 0; @@ -983,11 +983,6 @@ static void __init sama7g5_pmc_setup(struct device_nod= e *np) bool bypass; int i, j; =20 - td_slck_hw =3D __clk_get_hw(of_clk_get_by_name(np, "td_slck")); - md_slck_hw =3D __clk_get_hw(of_clk_get_by_name(np, "md_slck")); - if (!td_slck_hw || !md_slck_hw) - return; - main_xtal =3D of_clk_get(np, main_xtal_index); if (IS_ERR(main_xtal)) return; @@ -1097,8 +1092,8 @@ static void __init sama7g5_pmc_setup(struct device_no= de *np) =20 sama7g5_mckx[PCK_PARENT_HW_MCK0].hw =3D sama7g5_pmc->chws[PMC_MCK] =3D hw; =20 - parent_data[0] =3D AT91_CLK_PD_NAME("md_slck", md_slck_index); - parent_data[1] =3D AT91_CLK_PD_NAME("td_slck", td_slck_index); + parent_data[0] =3D AT91_CLK_PD_NAME(md_slck_name, md_slck_index); + parent_data[1] =3D AT91_CLK_PD_NAME(td_slck_name, td_slck_index); parent_data[2] =3D AT91_CLK_PD_HW(sama7g5_pmc->chws[PMC_MAIN]); for (i =3D PCK_PARENT_HW_MCK1; i < ARRAY_SIZE(sama7g5_mckx); i++) { u8 num_parents =3D 3 + sama7g5_mckx[i].ep_count; @@ -1141,8 +1136,8 @@ static void __init sama7g5_pmc_setup(struct device_no= de *np) =20 sama7g5_pmc->chws[PMC_UTMI] =3D hw; =20 - parent_data[0] =3D AT91_CLK_PD_NAME("md_slck", md_slck_index); - parent_data[1] =3D AT91_CLK_PD_NAME("td_slck", td_slck_index); + parent_data[0] =3D AT91_CLK_PD_NAME(md_slck_name, md_slck_index); + parent_data[1] =3D AT91_CLK_PD_NAME(td_slck_name, td_slck_index); parent_data[2] =3D AT91_CLK_PD_HW(sama7g5_pmc->chws[PMC_MAIN]); parent_data[3] =3D AT91_CLK_PD_HW(sama7g5_plls[PLL_ID_SYS][PLL_COMPID_DIV= 0].hw); parent_data[4] =3D AT91_CLK_PD_HW(sama7g5_plls[PLL_ID_DDR][PLL_COMPID_DIV= 0].hw); @@ -1191,12 +1186,11 @@ static void __init sama7g5_pmc_setup(struct device_= node *np) sama7g5_pmc->phws[sama7g5_periphck[i].id] =3D hw; } =20 - parent_hws[0] =3D md_slck_hw; - parent_hws[1] =3D td_slck_hw; - parent_hws[2] =3D sama7g5_pmc->chws[PMC_MAIN]; + parent_data[0] =3D AT91_CLK_PD_NAME(md_slck_name, md_slck_index); + parent_data[1] =3D AT91_CLK_PD_NAME(td_slck_name, td_slck_index); + parent_data[2] =3D AT91_CLK_PD_HW(sama7g5_pmc->chws[PMC_MAIN]); for (i =3D 0; i < ARRAY_SIZE(sama7g5_gck); i++) { u8 num_parents =3D 3 + sama7g5_gck[i].pp_count; - struct clk_hw *tmp_parent_hws[8]; u32 *mux_table; =20 mux_table =3D kmalloc_array(num_parents, sizeof(*mux_table), @@ -1211,15 +1205,13 @@ static void __init sama7g5_pmc_setup(struct device_= node *np) u8 pll_id =3D sama7g5_gck[i].pp[j].pll_id; u8 pll_compid =3D sama7g5_gck[i].pp[j].pll_compid; =20 - tmp_parent_hws[j] =3D sama7g5_plls[pll_id][pll_compid].hw; + parent_data[3 + j] =3D AT91_CLK_PD_HW(sama7g5_plls[pll_id][pll_compid].= hw); } - PMC_FILL_TABLE(&parent_hws[3], tmp_parent_hws, - sama7g5_gck[i].pp_count); =20 hw =3D at91_clk_register_generated(regmap, &pmc_pcr_lock, &sama7g5_pcr_layout, sama7g5_gck[i].n, NULL, - parent_hws, mux_table, + parent_data, mux_table, num_parents, sama7g5_gck[i].id, &sama7g5_gck[i].r, --=20 2.43.0 From nobody Tue Oct 7 09:53:13 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E5D7B2FE30A; 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X-CSE-ConnectionGUID: VcY24SkbRKSMnNSaLxS1vA== X-CSE-MsgGUID: 08e/WPcvQ9SeoA1j7THfKg== X-IronPort-AV: E=Sophos;i="6.16,301,1744095600"; d="scan'208";a="44448167" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 10 Jul 2025 13:07:55 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Thu, 10 Jul 2025 13:07:31 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Thu, 10 Jul 2025 13:07:31 -0700 From: To: , , , , CC: , , , , Subject: [PATCH v3 11/32] clk: at91: clk-usb: add support for clk_parent_data Date: Thu, 10 Jul 2025 13:07:04 -0700 Message-ID: <47b460245338e9a59b75dd72ea378a47b058a0be.1752176711.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Add support for clk_parent_data in usb clock driver. All the SoC based drivers that rely on clk-usb were adapted to the new API change. The switch itself for SoCs will be done in subsequent patches. Signed-off-by: Claudiu Beznea [ryan.wanner@microchip: Add SAMA7D65 and SAM9X75 SoCs to the changes. Change how the main_xtal and slcks are initialized so they match the parent_data API] Signed-off-by: Ryan Wanner --- drivers/clk/at91/at91rm9200.c | 2 +- drivers/clk/at91/at91sam9260.c | 2 +- drivers/clk/at91/at91sam9g45.c | 2 +- drivers/clk/at91/at91sam9n12.c | 2 +- drivers/clk/at91/at91sam9x5.c | 2 +- drivers/clk/at91/clk-usb.c | 41 ++++++++++++++++++++++------------ drivers/clk/at91/dt-compat.c | 6 ++--- drivers/clk/at91/pmc.h | 11 +++++---- drivers/clk/at91/sam9x60.c | 2 +- drivers/clk/at91/sam9x7.c | 27 +++++++++++----------- drivers/clk/at91/sama5d2.c | 2 +- drivers/clk/at91/sama5d3.c | 2 +- drivers/clk/at91/sama5d4.c | 2 +- drivers/clk/at91/sama7d65.c | 33 ++++++++++++++------------- 14 files changed, 76 insertions(+), 60 deletions(-) diff --git a/drivers/clk/at91/at91rm9200.c b/drivers/clk/at91/at91rm9200.c index 3f19e737ae4d..e5a034f208d8 100644 --- a/drivers/clk/at91/at91rm9200.c +++ b/drivers/clk/at91/at91rm9200.c @@ -157,7 +157,7 @@ static void __init at91rm9200_pmc_setup(struct device_n= ode *np) =20 at91rm9200_pmc->chws[PMC_MCK] =3D hw; =20 - hw =3D at91rm9200_clk_register_usb(regmap, "usbck", "pllbck", usb_div); + hw =3D at91rm9200_clk_register_usb(regmap, "usbck", "pllbck", NULL, usb_d= iv); if (IS_ERR(hw)) goto err_free; =20 diff --git a/drivers/clk/at91/at91sam9260.c b/drivers/clk/at91/at91sam9260.c index 0799a13060ea..ae6f126f204a 100644 --- a/drivers/clk/at91/at91sam9260.c +++ b/drivers/clk/at91/at91sam9260.c @@ -434,7 +434,7 @@ static void __init at91sam926x_pmc_setup(struct device_= node *np, =20 at91sam9260_pmc->chws[PMC_MCK] =3D hw; =20 - hw =3D at91rm9200_clk_register_usb(regmap, "usbck", "pllbck", usb_div); + hw =3D at91rm9200_clk_register_usb(regmap, "usbck", "pllbck", NULL, usb_d= iv); if (IS_ERR(hw)) goto err_free; =20 diff --git a/drivers/clk/at91/at91sam9g45.c b/drivers/clk/at91/at91sam9g45.c index f45a7b80f7d8..684d2bcb36e8 100644 --- a/drivers/clk/at91/at91sam9g45.c +++ b/drivers/clk/at91/at91sam9g45.c @@ -176,7 +176,7 @@ static void __init at91sam9g45_pmc_setup(struct device_= node *np) =20 parent_names[0] =3D "plladivck"; parent_names[1] =3D "utmick"; - hw =3D at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, 2); + hw =3D at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, NULL, 2= ); if (IS_ERR(hw)) goto err_free; =20 diff --git a/drivers/clk/at91/at91sam9n12.c b/drivers/clk/at91/at91sam9n12.c index 751786184ae2..9fc20b177b13 100644 --- a/drivers/clk/at91/at91sam9n12.c +++ b/drivers/clk/at91/at91sam9n12.c @@ -201,7 +201,7 @@ static void __init at91sam9n12_pmc_setup(struct device_= node *np) =20 at91sam9n12_pmc->chws[PMC_MCK] =3D hw; =20 - hw =3D at91sam9n12_clk_register_usb(regmap, "usbck", "pllbck"); + hw =3D at91sam9n12_clk_register_usb(regmap, "usbck", "pllbck", NULL); if (IS_ERR(hw)) goto err_free; =20 diff --git a/drivers/clk/at91/at91sam9x5.c b/drivers/clk/at91/at91sam9x5.c index 3b801d12fac0..5728cfb9036f 100644 --- a/drivers/clk/at91/at91sam9x5.c +++ b/drivers/clk/at91/at91sam9x5.c @@ -222,7 +222,7 @@ static void __init at91sam9x5_pmc_setup(struct device_n= ode *np, =20 parent_names[0] =3D "plladivck"; parent_names[1] =3D "utmick"; - hw =3D at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, 2); + hw =3D at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, NULL, 2= ); if (IS_ERR(hw)) goto err_free; =20 diff --git a/drivers/clk/at91/clk-usb.c b/drivers/clk/at91/clk-usb.c index b0696a928aa9..b2503fad4543 100644 --- a/drivers/clk/at91/clk-usb.c +++ b/drivers/clk/at91/clk-usb.c @@ -221,12 +221,12 @@ static const struct clk_ops at91sam9n12_usb_ops =3D { =20 static struct clk_hw * __init _at91sam9x5_clk_register_usb(struct regmap *regmap, const char *name, - const char **parent_names, u8 num_parents, - u32 usbs_mask) + const char **parent_names, struct clk_parent_data *parent_data, + u8 num_parents, u32 usbs_mask) { struct at91sam9x5_clk_usb *usb; struct clk_hw *hw; - struct clk_init_data init; + struct clk_init_data init =3D {}; int ret; =20 usb =3D kzalloc(sizeof(*usb), GFP_KERNEL); @@ -235,7 +235,10 @@ _at91sam9x5_clk_register_usb(struct regmap *regmap, co= nst char *name, =20 init.name =3D name; init.ops =3D &at91sam9x5_usb_ops; - init.parent_names =3D parent_names; + if (parent_data) + init.parent_data =3D (const struct clk_parent_data *)parent_data; + else + init.parent_names =3D parent_names; init.num_parents =3D num_parents; init.flags =3D CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | CLK_SET_RATE_PARENT; @@ -257,27 +260,30 @@ _at91sam9x5_clk_register_usb(struct regmap *regmap, c= onst char *name, =20 struct clk_hw * __init at91sam9x5_clk_register_usb(struct regmap *regmap, const char *name, - const char **parent_names, u8 num_parents) + const char **parent_names, struct clk_parent_data *parent_data, + u8 num_parents) { return _at91sam9x5_clk_register_usb(regmap, name, parent_names, - num_parents, SAM9X5_USBS_MASK); + parent_data, num_parents, SAM9X5_USBS_MASK); } =20 struct clk_hw * __init sam9x60_clk_register_usb(struct regmap *regmap, const char *name, - const char **parent_names, u8 num_parents) + const char **parent_names, struct clk_parent_data *parent_data, + u8 num_parents) { return _at91sam9x5_clk_register_usb(regmap, name, parent_names, - num_parents, SAM9X60_USBS_MASK); + parent_data, num_parents, + SAM9X60_USBS_MASK); } =20 struct clk_hw * __init at91sam9n12_clk_register_usb(struct regmap *regmap, const char *name, - const char *parent_name) + const char *parent_name, struct clk_parent_data *parent_data) { struct at91sam9x5_clk_usb *usb; struct clk_hw *hw; - struct clk_init_data init; + struct clk_init_data init =3D {}; int ret; =20 usb =3D kzalloc(sizeof(*usb), GFP_KERNEL); @@ -286,7 +292,10 @@ at91sam9n12_clk_register_usb(struct regmap *regmap, co= nst char *name, =20 init.name =3D name; init.ops =3D &at91sam9n12_usb_ops; - init.parent_names =3D &parent_name; + if (parent_data) + init.parent_data =3D (const struct clk_parent_data *)parent_data; + else + init.parent_names =3D &parent_name; init.num_parents =3D 1; init.flags =3D CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT; =20 @@ -390,11 +399,12 @@ static const struct clk_ops at91rm9200_usb_ops =3D { =20 struct clk_hw * __init at91rm9200_clk_register_usb(struct regmap *regmap, const char *name, - const char *parent_name, const u32 *divisors) + const char *parent_name, struct clk_parent_data *parent_data, + const u32 *divisors) { struct at91rm9200_clk_usb *usb; struct clk_hw *hw; - struct clk_init_data init; + struct clk_init_data init =3D {}; int ret; =20 usb =3D kzalloc(sizeof(*usb), GFP_KERNEL); @@ -403,7 +413,10 @@ at91rm9200_clk_register_usb(struct regmap *regmap, con= st char *name, =20 init.name =3D name; init.ops =3D &at91rm9200_usb_ops; - init.parent_names =3D &parent_name; + if (parent_data) + init.parent_data =3D (const struct clk_parent_data *)parent_data; + else + init.parent_names =3D &parent_name; init.num_parents =3D 1; init.flags =3D CLK_SET_RATE_PARENT; =20 diff --git a/drivers/clk/at91/dt-compat.c b/drivers/clk/at91/dt-compat.c index f5a5f9ba7634..7883198f6a98 100644 --- a/drivers/clk/at91/dt-compat.c +++ b/drivers/clk/at91/dt-compat.c @@ -946,7 +946,7 @@ static void __init of_at91sam9x5_clk_usb_setup(struct d= evice_node *np) if (IS_ERR(regmap)) return; =20 - hw =3D at91sam9x5_clk_register_usb(regmap, name, parent_names, + hw =3D at91sam9x5_clk_register_usb(regmap, name, parent_names, NULL, num_parents); if (IS_ERR(hw)) return; @@ -976,7 +976,7 @@ static void __init of_at91sam9n12_clk_usb_setup(struct = device_node *np) if (IS_ERR(regmap)) return; =20 - hw =3D at91sam9n12_clk_register_usb(regmap, name, parent_name); + hw =3D at91sam9n12_clk_register_usb(regmap, name, parent_name, NULL); if (IS_ERR(hw)) return; =20 @@ -1009,7 +1009,7 @@ static void __init of_at91rm9200_clk_usb_setup(struct= device_node *np) of_node_put(parent_np); if (IS_ERR(regmap)) return; - hw =3D at91rm9200_clk_register_usb(regmap, name, parent_name, divisors); + hw =3D at91rm9200_clk_register_usb(regmap, name, parent_name, NULL, divis= ors); if (IS_ERR(hw)) return; =20 diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index 0646775dfb1d..c66ee44255d7 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -285,16 +285,19 @@ at91_clk_register_system(struct regmap *regmap, const= char *name, =20 struct clk_hw * __init at91sam9x5_clk_register_usb(struct regmap *regmap, const char *name, - const char **parent_names, u8 num_parents); + const char **parent_names, struct clk_parent_data *parent_data, + u8 num_parents); struct clk_hw * __init at91sam9n12_clk_register_usb(struct regmap *regmap, const char *name, - const char *parent_name); + const char *parent_name, struct clk_parent_data *parent_data); struct clk_hw * __init sam9x60_clk_register_usb(struct regmap *regmap, const char *name, - const char **parent_names, u8 num_parents); + const char **parent_names, struct clk_parent_data *parent_data, + u8 num_parents); struct clk_hw * __init at91rm9200_clk_register_usb(struct regmap *regmap, const char *name, - const char *parent_name, const u32 *divisors); + const char *parent_name, struct clk_parent_data *parent_data, + const u32 *divisors); =20 struct clk_hw * __init at91_clk_register_utmi(struct regmap *regmap_pmc, struct regmap *regmap_sf= r, diff --git a/drivers/clk/at91/sam9x60.c b/drivers/clk/at91/sam9x60.c index fd53e54abf88..eb38da77d69a 100644 --- a/drivers/clk/at91/sam9x60.c +++ b/drivers/clk/at91/sam9x60.c @@ -306,7 +306,7 @@ static void __init sam9x60_pmc_setup(struct device_node= *np) parent_names[0] =3D "pllack_divck"; parent_names[1] =3D "upllck_divck"; parent_names[2] =3D "main_osc"; - hw =3D sam9x60_clk_register_usb(regmap, "usbck", parent_names, 3); + hw =3D sam9x60_clk_register_usb(regmap, "usbck", parent_names, NULL, 3); if (IS_ERR(hw)) goto err_free; =20 diff --git a/drivers/clk/at91/sam9x7.c b/drivers/clk/at91/sam9x7.c index c4578944611e..fdff799f0a22 100644 --- a/drivers/clk/at91/sam9x7.c +++ b/drivers/clk/at91/sam9x7.c @@ -738,23 +738,21 @@ static const struct { static void __init sam9x7_pmc_setup(struct device_node *np) { u8 td_slck_index =3D 0, md_slck_index =3D 1, main_xtal_index =3D 2; + struct clk_hw *hw, *main_rc_hw, *main_osc_hw, *usbck_hw; struct clk_range range =3D CLK_RANGE(0, 0); const char *const main_xtal_name =3D "main_xtal"; const char *const td_slck_name =3D "td_slck"; const char *const md_slck_name =3D "md_slck"; struct pmc_data *sam9x7_pmc; - const char *parent_names[9]; void **clk_mux_buffer =3D NULL; int clk_mux_buffer_size =3D 0; + struct clk *main_xtal; struct regmap *regmap; - struct clk_hw *hw, *main_rc_hw, *main_osc_hw, *main_xtal_hw; - struct clk_hw *usbck_hw; struct clk_parent_data parent_data[9]; int i, j; =20 - main_xtal_hw =3D __clk_get_hw(of_clk_get_by_name(np, main_xtal_name)); - - if (!main_xtal_hw) + main_xtal =3D of_clk_get(np, main_xtal_index); + if (IS_ERR(main_xtal)) return; =20 regmap =3D device_node_to_regmap(np); @@ -804,19 +802,18 @@ static void __init sam9x7_pmc_setup(struct device_nod= e *np) switch (sam9x7_plls[i][j].p) { case SAM9X7_PLL_PARENT_MAINCK: parent_data[0] =3D AT91_CLK_PD_NAME("mainck", -1); - hw =3D sam9x7_pmc->chws[PMC_MAIN]; + parent_rate =3D clk_hw_get_rate(sam9x7_pmc->chws[PMC_MAIN]); break; case SAM9X7_PLL_PARENT_MAIN_XTAL: parent_data[0] =3D AT91_CLK_PD_NAME(main_xtal_name, main_xtal_index); - hw =3D main_xtal_hw; + parent_rate =3D clk_get_rate(main_xtal); break; default: /* Should not happen. */ break; } =20 - parent_rate =3D clk_hw_get_rate(hw); if (!parent_rate) return; =20 @@ -871,10 +868,10 @@ static void __init sam9x7_pmc_setup(struct device_nod= e *np) =20 sam9x7_pmc->chws[PMC_MCK] =3D hw; =20 - parent_names[0] =3D "plla_divpmcck"; - parent_names[1] =3D "upll_divpmcck"; - parent_names[2] =3D "main_osc"; - usbck_hw =3D sam9x60_clk_register_usb(regmap, "usbck", parent_names, 3); + parent_data[0] =3D AT91_CLK_PD_HW(sam9x7_plls[PLL_ID_PLLA][PLL_COMPID_DIV= 0].hw); + parent_data[1] =3D AT91_CLK_PD_HW(sam9x7_plls[PLL_ID_UPLL][PLL_COMPID_DIV= 0].hw); + parent_data[2] =3D AT91_CLK_PD_HW(main_osc_hw); + usbck_hw =3D sam9x60_clk_register_usb(regmap, "usbck", NULL, parent_data,= 3); if (IS_ERR(usbck_hw)) goto err_free; =20 @@ -971,7 +968,7 @@ static void __init sam9x7_pmc_setup(struct device_node = *np) of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sam9x7_pmc); kfree(clk_mux_buffer); =20 - return; + goto put_main_xtal; =20 err_free: if (clk_mux_buffer) { @@ -980,6 +977,8 @@ static void __init sam9x7_pmc_setup(struct device_node = *np) kfree(clk_mux_buffer); } kfree(sam9x7_pmc); +put_main_xtal: + clk_put(main_xtal); } =20 /* Some clks are used for a clocksource */ diff --git a/drivers/clk/at91/sama5d2.c b/drivers/clk/at91/sama5d2.c index c16594fce90c..8bbc34e22cda 100644 --- a/drivers/clk/at91/sama5d2.c +++ b/drivers/clk/at91/sama5d2.c @@ -284,7 +284,7 @@ static void __init sama5d2_pmc_setup(struct device_node= *np) =20 parent_names[0] =3D "plladivck"; parent_names[1] =3D "utmick"; - hw =3D at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, 2); + hw =3D at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, NULL, 2= ); if (IS_ERR(hw)) goto err_free; =20 diff --git a/drivers/clk/at91/sama5d3.c b/drivers/clk/at91/sama5d3.c index 522ce6031446..05d0cdd22bc4 100644 --- a/drivers/clk/at91/sama5d3.c +++ b/drivers/clk/at91/sama5d3.c @@ -201,7 +201,7 @@ static void __init sama5d3_pmc_setup(struct device_node= *np) =20 parent_names[0] =3D "plladivck"; parent_names[1] =3D "utmick"; - hw =3D at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, 2); + hw =3D at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, NULL, 2= ); if (IS_ERR(hw)) goto err_free; =20 diff --git a/drivers/clk/at91/sama5d4.c b/drivers/clk/at91/sama5d4.c index 160c0bddb6a3..da84b4cef827 100644 --- a/drivers/clk/at91/sama5d4.c +++ b/drivers/clk/at91/sama5d4.c @@ -222,7 +222,7 @@ static void __init sama5d4_pmc_setup(struct device_node= *np) =20 parent_names[0] =3D "plladivck"; parent_names[1] =3D "utmick"; - hw =3D at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, 2); + hw =3D at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, NULL, 2= ); if (IS_ERR(hw)) goto err_free; =20 diff --git a/drivers/clk/at91/sama7d65.c b/drivers/clk/at91/sama7d65.c index 4d47d20e65fb..f10faabc7ffe 100644 --- a/drivers/clk/at91/sama7d65.c +++ b/drivers/clk/at91/sama7d65.c @@ -1090,34 +1090,33 @@ static const struct clk_pcr_layout sama7d65_pcr_lay= out =3D { static void __init sama7d65_pmc_setup(struct device_node *np) { u8 td_slck_index =3D 0, md_slck_index =3D 1, main_xtal_index =3D 2; - struct clk_hw *hw, *main_rc_hw, *main_osc_hw, *main_xtal_hw; + struct clk_hw *hw, *main_rc_hw, *main_osc_hw, *usbck_hw; const char * const main_xtal_name =3D "main_xtal"; const char * const td_slck_name =3D "td_slck"; const char * const md_slck_name =3D "md_slck"; struct clk_parent_data parent_data[10]; struct pmc_data *sama7d65_pmc; - const char *parent_names[11]; void **alloc_mem =3D NULL; int alloc_mem_size =3D 0; + struct clk *main_xtal; struct regmap *regmap; bool bypass; int i, j; =20 - main_xtal_hw =3D __clk_get_hw(of_clk_get_by_name(np, main_xtal_name)); - - if (!main_xtal_hw) + main_xtal =3D of_clk_get(np, main_xtal_index); + if (IS_ERR(main_xtal)) return; =20 regmap =3D device_node_to_regmap(np); if (IS_ERR(regmap)) - return; + goto put_main_xtal; =20 sama7d65_pmc =3D pmc_data_allocate(PMC_INDEX_MAX, nck(sama7d65_systemck), nck(sama7d65_periphck), nck(sama7d65_gck), 8); if (!sama7d65_pmc) - return; + goto put_main_xtal; =20 alloc_mem =3D kmalloc(sizeof(void *) * (ARRAY_SIZE(sama7d65_mckx) + ARRAY_SIZE(sama7d65_gck)), @@ -1158,18 +1157,18 @@ static void __init sama7d65_pmc_setup(struct device= _node *np) switch (sama7d65_plls[i][j].p) { case SAMA7D65_PLL_PARENT_MAINCK: parent_data[0] =3D AT91_CLK_PD_NAME("mainck", -1); - hw =3D sama7d65_pmc->chws[PMC_MAIN]; + parent_rate =3D clk_hw_get_rate(sama7d65_pmc->chws[PMC_MAIN]); break; case SAMA7D65_PLL_PARENT_MAIN_XTAL: parent_data[0] =3D AT91_CLK_PD_NAME(main_xtal_name, main_xtal_index); - hw =3D main_xtal_hw; + parent_rate =3D clk_get_rate(main_xtal); break; default: /* Should not happen. */ break; } - parent_rate =3D clk_hw_get_rate(hw); + if (!parent_rate) return; =20 @@ -1253,11 +1252,11 @@ static void __init sama7d65_pmc_setup(struct device= _node *np) sama7d65_pmc->chws[sama7d65_mckx[i].eid] =3D hw; } =20 - parent_names[0] =3D "syspll_divpmcck"; - parent_names[1] =3D "usbpll_divpmcck"; - parent_names[2] =3D "main_osc"; - hw =3D sam9x60_clk_register_usb(regmap, "usbck", parent_names, 3); - if (IS_ERR(hw)) + parent_data[0] =3D AT91_CLK_PD_HW(sama7d65_plls[PLL_ID_SYS][PLL_COMPID_DI= V0].hw); + parent_data[1] =3D AT91_CLK_PD_HW(sama7d65_plls[PLL_ID_USB][PLL_COMPID_DI= V0].hw); + parent_data[2] =3D AT91_CLK_PD_HW(main_osc_hw); + usbck_hw =3D sam9x60_clk_register_usb(regmap, "usbck", NULL, parent_data,= 3); + if (IS_ERR(usbck_hw)) goto err_free; =20 parent_data[0] =3D AT91_CLK_PD_NAME(md_slck_name, md_slck_index); @@ -1353,7 +1352,7 @@ static void __init sama7d65_pmc_setup(struct device_n= ode *np) of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sama7d65_pmc); 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Thu, 10 Jul 2025 13:07:31 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Thu, 10 Jul 2025 13:07:31 -0700 From: To: , , , , CC: , , , , Subject: [PATCH v3 12/32] clk: at91: clk-system: use clk_parent_data Date: Thu, 10 Jul 2025 13:07:05 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Use struct clk_parent_data instead of struct parent_hw as this leads to less usage of __clk_get_hw() in SoC specific clock drivers and simpler conversion of existing SoC specific clock drivers from parent_names to modern clk_parent_data structures. Signed-off-by: Claudiu Beznea [ryan.wanner@microchip: Update SAM9X75 clk-system to use parent_data.] Signed-off-by: Ryan Wanner --- drivers/clk/at91/clk-system.c | 8 ++++---- drivers/clk/at91/pmc.h | 2 +- drivers/clk/at91/sam9x7.c | 2 +- drivers/clk/at91/sama7g5.c | 2 +- 4 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/clk/at91/clk-system.c b/drivers/clk/at91/clk-system.c index 90eed39d0785..55f8e46fe9c7 100644 --- a/drivers/clk/at91/clk-system.c +++ b/drivers/clk/at91/clk-system.c @@ -105,7 +105,7 @@ static const struct clk_ops system_ops =3D { =20 struct clk_hw * __init at91_clk_register_system(struct regmap *regmap, const char *name, - const char *parent_name, struct clk_hw *parent_hw, u8 id, + const char *parent_name, struct clk_parent_data *parent_data, u8 id, unsigned long flags) { struct clk_system *sys; @@ -113,7 +113,7 @@ at91_clk_register_system(struct regmap *regmap, const c= har *name, struct clk_init_data init =3D {}; int ret; =20 - if (!(parent_name || parent_hw) || id > SYSTEM_MAX_ID) + if (!(parent_name || parent_data) || id > SYSTEM_MAX_ID) return ERR_PTR(-EINVAL); =20 sys =3D kzalloc(sizeof(*sys), GFP_KERNEL); @@ -122,8 +122,8 @@ at91_clk_register_system(struct regmap *regmap, const c= har *name, =20 init.name =3D name; init.ops =3D &system_ops; - if (parent_hw) - init.parent_hws =3D (const struct clk_hw **)&parent_hw; + if (parent_data) + init.parent_data =3D (const struct clk_parent_data *)parent_data; else init.parent_names =3D &parent_name; init.num_parents =3D 1; diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index c66ee44255d7..87ab1211576f 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -280,7 +280,7 @@ at91sam9x5_clk_register_smd(struct regmap *regmap, cons= t char *name, =20 struct clk_hw * __init at91_clk_register_system(struct regmap *regmap, const char *name, - const char *parent_name, struct clk_hw *parent_hw, + const char *parent_name, struct clk_parent_data *parent_data, u8 id, unsigned long flags); =20 struct clk_hw * __init diff --git a/drivers/clk/at91/sam9x7.c b/drivers/clk/at91/sam9x7.c index fdff799f0a22..56243f6f7e65 100644 --- a/drivers/clk/at91/sam9x7.c +++ b/drivers/clk/at91/sam9x7.c @@ -904,7 +904,7 @@ static void __init sam9x7_pmc_setup(struct device_node = *np) sam9x7_systemck[3].parent_hw =3D sam9x7_pmc->pchws[1]; for (i =3D 0; i < ARRAY_SIZE(sam9x7_systemck); i++) { hw =3D at91_clk_register_system(regmap, sam9x7_systemck[i].n, - NULL, sam9x7_systemck[i].parent_hw, + NULL, &AT91_CLK_PD_HW(sam9x7_systemck[i].parent_hw), sam9x7_systemck[i].id, sam9x7_systemck[i].flags); if (IS_ERR(hw)) diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index 505db97e989b..954202e0e8f9 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -1162,7 +1162,7 @@ static void __init sama7g5_pmc_setup(struct device_no= de *np) =20 for (i =3D 0; i < ARRAY_SIZE(sama7g5_systemck); i++) { hw =3D at91_clk_register_system(regmap, sama7g5_systemck[i].n, - NULL, sama7g5_pmc->pchws[i], + NULL, &AT91_CLK_PD_HW(sama7g5_pmc->pchws[i]), sama7g5_systemck[i].id, 0); if (IS_ERR(hw)) goto err_free; --=20 2.43.0 From nobody Tue Oct 7 09:53:13 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CD84F2FCFF9; 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charset="utf-8" From: Ryan Wanner Switch the system clocks to use parent_hw and parent_data. Having this allows the driver to conform to the new clk-system API. The parent registration is after the USBCK registration due to one of the system clocks being dependent on USBCK. Signed-off-by: Ryan Wanner --- drivers/clk/at91/sama7d65.c | 37 +++++++++++++++++++++++-------------- 1 file changed, 23 insertions(+), 14 deletions(-) diff --git a/drivers/clk/at91/sama7d65.c b/drivers/clk/at91/sama7d65.c index f10faabc7ffe..1553dc3152a4 100644 --- a/drivers/clk/at91/sama7d65.c +++ b/drivers/clk/at91/sama7d65.c @@ -533,23 +533,23 @@ static struct { /* * System clock description * @n: clock name - * @p: clock parent name + * @p: clock parent hw * @id: clock id */ -static const struct { +static struct { const char *n; - const char *p; + struct clk_hw *parent_hw; u8 id; } sama7d65_systemck[] =3D { - { .n =3D "uhpck", .p =3D "usbck", .id =3D 6 }, - { .n =3D "pck0", .p =3D "prog0", .id =3D 8, }, - { .n =3D "pck1", .p =3D "prog1", .id =3D 9, }, - { .n =3D "pck2", .p =3D "prog2", .id =3D 10, }, - { .n =3D "pck3", .p =3D "prog3", .id =3D 11, }, - { .n =3D "pck4", .p =3D "prog4", .id =3D 12, }, - { .n =3D "pck5", .p =3D "prog5", .id =3D 13, }, - { .n =3D "pck6", .p =3D "prog6", .id =3D 14, }, - { .n =3D "pck7", .p =3D "prog7", .id =3D 15, }, + { .n =3D "uhpck", .id =3D 6 }, + { .n =3D "pck0", .id =3D 8, }, + { .n =3D "pck1", .id =3D 9, }, + { .n =3D "pck2", .id =3D 10, }, + { .n =3D "pck3", .id =3D 11, }, + { .n =3D "pck4", .id =3D 12, }, + { .n =3D "pck5", .id =3D 13, }, + { .n =3D "pck6", .id =3D 14, }, + { .n =3D "pck7", .id =3D 15, }, }; =20 /* Mux table for programmable clocks. */ @@ -1283,10 +1283,19 @@ static void __init sama7d65_pmc_setup(struct device= _node *np) =20 sama7d65_pmc->pchws[i] =3D hw; } - + /* Set systemck parent hws. */ + sama7d65_systemck[0].parent_hw =3D usbck_hw; + sama7d65_systemck[1].parent_hw =3D sama7d65_pmc->pchws[0]; + sama7d65_systemck[2].parent_hw =3D sama7d65_pmc->pchws[1]; + sama7d65_systemck[3].parent_hw =3D sama7d65_pmc->pchws[2]; + sama7d65_systemck[4].parent_hw =3D sama7d65_pmc->pchws[3]; + sama7d65_systemck[5].parent_hw =3D sama7d65_pmc->pchws[4]; + sama7d65_systemck[6].parent_hw =3D sama7d65_pmc->pchws[5]; + sama7d65_systemck[7].parent_hw =3D sama7d65_pmc->pchws[6]; + sama7d65_systemck[8].parent_hw =3D sama7d65_pmc->pchws[7]; for (i =3D 0; i < ARRAY_SIZE(sama7d65_systemck); i++) { hw =3D at91_clk_register_system(regmap, sama7d65_systemck[i].n, - sama7d65_systemck[i].p, NULL, + NULL, &AT91_CLK_PD_HW(sama7d65_systemck[i].parent_hw), sama7d65_systemck[i].id, 0); if (IS_ERR(hw)) goto err_free; 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charset="utf-8" From: Claudiu Beznea Add support for parent_hw in pll clock driver. With this parent-child relation is described with pointers rather than strings making registration a bit faster. All the SoC based drivers that rely on clk-pll were adapted to the new API change. The switch itself for SoCs will be done in subsequent patches. Signed-off-by: Claudiu Beznea Signed-off-by: Ryan Wanner --- drivers/clk/at91/at91rm9200.c | 4 ++-- drivers/clk/at91/at91sam9260.c | 4 ++-- drivers/clk/at91/at91sam9g45.c | 2 +- drivers/clk/at91/at91sam9n12.c | 4 ++-- drivers/clk/at91/at91sam9rl.c | 2 +- drivers/clk/at91/at91sam9x5.c | 2 +- drivers/clk/at91/clk-pll.c | 9 ++++++--- drivers/clk/at91/dt-compat.c | 2 +- drivers/clk/at91/pmc.h | 2 +- drivers/clk/at91/sama5d2.c | 2 +- drivers/clk/at91/sama5d3.c | 2 +- drivers/clk/at91/sama5d4.c | 2 +- 12 files changed, 20 insertions(+), 17 deletions(-) diff --git a/drivers/clk/at91/at91rm9200.c b/drivers/clk/at91/at91rm9200.c index e5a034f208d8..623e232ec9c6 100644 --- a/drivers/clk/at91/at91rm9200.c +++ b/drivers/clk/at91/at91rm9200.c @@ -119,7 +119,7 @@ static void __init at91rm9200_pmc_setup(struct device_n= ode *np) =20 at91rm9200_pmc->chws[PMC_MAIN] =3D hw; =20 - hw =3D at91_clk_register_pll(regmap, "pllack", "mainck", 0, + hw =3D at91_clk_register_pll(regmap, "pllack", "mainck", NULL, 0, &at91rm9200_pll_layout, &rm9200_pll_characteristics); if (IS_ERR(hw)) @@ -127,7 +127,7 @@ static void __init at91rm9200_pmc_setup(struct device_n= ode *np) =20 at91rm9200_pmc->chws[PMC_PLLACK] =3D hw; =20 - hw =3D at91_clk_register_pll(regmap, "pllbck", "mainck", 1, + hw =3D at91_clk_register_pll(regmap, "pllbck", "mainck", NULL, 1, &at91rm9200_pll_layout, &rm9200_pll_characteristics); if (IS_ERR(hw)) diff --git a/drivers/clk/at91/at91sam9260.c b/drivers/clk/at91/at91sam9260.c index ae6f126f204a..f39deb3ec00a 100644 --- a/drivers/clk/at91/at91sam9260.c +++ b/drivers/clk/at91/at91sam9260.c @@ -395,7 +395,7 @@ static void __init at91sam926x_pmc_setup(struct device_= node *np, slck_name =3D slowxtal_name; } =20 - hw =3D at91_clk_register_pll(regmap, "pllack", "mainck", 0, + hw =3D at91_clk_register_pll(regmap, "pllack", "mainck", NULL, 0, data->plla_layout, data->plla_characteristics); if (IS_ERR(hw)) @@ -403,7 +403,7 @@ static void __init at91sam926x_pmc_setup(struct device_= node *np, =20 at91sam9260_pmc->chws[PMC_PLLACK] =3D hw; =20 - hw =3D at91_clk_register_pll(regmap, "pllbck", "mainck", 1, + hw =3D at91_clk_register_pll(regmap, "pllbck", "mainck", NULL, 1, data->pllb_layout, data->pllb_characteristics); if (IS_ERR(hw)) diff --git a/drivers/clk/at91/at91sam9g45.c b/drivers/clk/at91/at91sam9g45.c index 684d2bcb36e8..3436a09a6e8a 100644 --- a/drivers/clk/at91/at91sam9g45.c +++ b/drivers/clk/at91/at91sam9g45.c @@ -134,7 +134,7 @@ static void __init at91sam9g45_pmc_setup(struct device_= node *np) =20 at91sam9g45_pmc->chws[PMC_MAIN] =3D hw; =20 - hw =3D at91_clk_register_pll(regmap, "pllack", "mainck", 0, + hw =3D at91_clk_register_pll(regmap, "pllack", "mainck", NULL, 0, &at91rm9200_pll_layout, &plla_characteristics); if (IS_ERR(hw)) goto err_free; diff --git a/drivers/clk/at91/at91sam9n12.c b/drivers/clk/at91/at91sam9n12.c index 9fc20b177b13..80ccd4a49df3 100644 --- a/drivers/clk/at91/at91sam9n12.c +++ b/drivers/clk/at91/at91sam9n12.c @@ -160,7 +160,7 @@ static void __init at91sam9n12_pmc_setup(struct device_= node *np) =20 at91sam9n12_pmc->chws[PMC_MAIN] =3D hw; =20 - hw =3D at91_clk_register_pll(regmap, "pllack", "mainck", 0, + hw =3D at91_clk_register_pll(regmap, "pllack", "mainck", NULL, 0, &at91rm9200_pll_layout, &plla_characteristics); if (IS_ERR(hw)) goto err_free; @@ -171,7 +171,7 @@ static void __init at91sam9n12_pmc_setup(struct device_= node *np) =20 at91sam9n12_pmc->chws[PMC_PLLACK] =3D hw; =20 - hw =3D at91_clk_register_pll(regmap, "pllbck", "mainck", 1, + hw =3D at91_clk_register_pll(regmap, "pllbck", "mainck", NULL, 1, &at91rm9200_pll_layout, &pllb_characteristics); if (IS_ERR(hw)) goto err_free; diff --git a/drivers/clk/at91/at91sam9rl.c b/drivers/clk/at91/at91sam9rl.c index 969f809e7d65..0e8657aac491 100644 --- a/drivers/clk/at91/at91sam9rl.c +++ b/drivers/clk/at91/at91sam9rl.c @@ -101,7 +101,7 @@ static void __init at91sam9rl_pmc_setup(struct device_n= ode *np) =20 at91sam9rl_pmc->chws[PMC_MAIN] =3D hw; =20 - hw =3D at91_clk_register_pll(regmap, "pllack", "mainck", 0, + hw =3D at91_clk_register_pll(regmap, "pllack", "mainck", NULL, 0, &at91rm9200_pll_layout, &sam9rl_plla_characteristics); if (IS_ERR(hw)) diff --git a/drivers/clk/at91/at91sam9x5.c b/drivers/clk/at91/at91sam9x5.c index 5728cfb9036f..6b8c755fefdf 100644 --- a/drivers/clk/at91/at91sam9x5.c +++ b/drivers/clk/at91/at91sam9x5.c @@ -182,7 +182,7 @@ static void __init at91sam9x5_pmc_setup(struct device_n= ode *np, =20 at91sam9x5_pmc->chws[PMC_MAIN] =3D hw; =20 - hw =3D at91_clk_register_pll(regmap, "pllack", "mainck", 0, + hw =3D at91_clk_register_pll(regmap, "pllack", "mainck", NULL, 0, &at91rm9200_pll_layout, &plla_characteristics); if (IS_ERR(hw)) goto err_free; diff --git a/drivers/clk/at91/clk-pll.c b/drivers/clk/at91/clk-pll.c index 249d6a53cedf..f973c3b1bbec 100644 --- a/drivers/clk/at91/clk-pll.c +++ b/drivers/clk/at91/clk-pll.c @@ -310,13 +310,13 @@ static const struct clk_ops pll_ops =3D { =20 struct clk_hw * __init at91_clk_register_pll(struct regmap *regmap, const char *name, - const char *parent_name, u8 id, + const char *parent_name, struct clk_parent_data *parent_data, u8 i= d, const struct clk_pll_layout *layout, const struct clk_pll_characteristics *characteristics) { struct clk_pll *pll; struct clk_hw *hw; - struct clk_init_data init; + struct clk_init_data init =3D {}; int offset =3D PLL_REG(id); unsigned int pllr; int ret; @@ -330,7 +330,10 @@ at91_clk_register_pll(struct regmap *regmap, const cha= r *name, =20 init.name =3D name; init.ops =3D &pll_ops; - init.parent_names =3D &parent_name; + if (parent_data) + init.parent_data =3D (const struct clk_parent_data *)parent_data; + else + init.parent_names =3D &parent_name; init.num_parents =3D 1; init.flags =3D CLK_SET_RATE_GATE; =20 diff --git a/drivers/clk/at91/dt-compat.c b/drivers/clk/at91/dt-compat.c index 7883198f6a98..2c5faa3b1cfd 100644 --- a/drivers/clk/at91/dt-compat.c +++ b/drivers/clk/at91/dt-compat.c @@ -665,7 +665,7 @@ of_at91_clk_pll_setup(struct device_node *np, if (!characteristics) return; =20 - hw =3D at91_clk_register_pll(regmap, name, parent_name, id, layout, + hw =3D at91_clk_register_pll(regmap, name, parent_name, NULL, id, layout, characteristics); if (IS_ERR(hw)) goto out_free_characteristics; diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index 87ab1211576f..0feaf8497b60 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -238,7 +238,7 @@ at91_clk_register_sam9x5_peripheral(struct regmap *regm= ap, spinlock_t *lock, =20 struct clk_hw * __init at91_clk_register_pll(struct regmap *regmap, const char *name, - const char *parent_name, u8 id, + const char *parent_name, struct clk_parent_data *parent_data, u8 i= d, const struct clk_pll_layout *layout, const struct clk_pll_characteristics *characteristics); struct clk_hw * __init diff --git a/drivers/clk/at91/sama5d2.c b/drivers/clk/at91/sama5d2.c index 8bbc34e22cda..bc62b9ed4ea0 100644 --- a/drivers/clk/at91/sama5d2.c +++ b/drivers/clk/at91/sama5d2.c @@ -215,7 +215,7 @@ static void __init sama5d2_pmc_setup(struct device_node= *np) =20 sama5d2_pmc->chws[PMC_MAIN] =3D hw; =20 - hw =3D at91_clk_register_pll(regmap, "pllack", "mainck", 0, + hw =3D at91_clk_register_pll(regmap, "pllack", "mainck", NULL, 0, &sama5d3_pll_layout, &plla_characteristics); if (IS_ERR(hw)) goto err_free; diff --git a/drivers/clk/at91/sama5d3.c b/drivers/clk/at91/sama5d3.c index 05d0cdd22bc4..9d86c350a1e7 100644 --- a/drivers/clk/at91/sama5d3.c +++ b/drivers/clk/at91/sama5d3.c @@ -161,7 +161,7 @@ static void __init sama5d3_pmc_setup(struct device_node= *np) if (IS_ERR(hw)) goto err_free; =20 - hw =3D at91_clk_register_pll(regmap, "pllack", "mainck", 0, + hw =3D at91_clk_register_pll(regmap, "pllack", "mainck", NULL, 0, &sama5d3_pll_layout, &plla_characteristics); if (IS_ERR(hw)) goto err_free; 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10 Jul 2025 13:07:37 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Thu, 10 Jul 2025 13:07:32 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Thu, 10 Jul 2025 13:07:32 -0700 From: To: , , , , CC: , , , , Subject: [PATCH v3 15/32] clk: at91: clk-audio-pll: add support for parent_hw Date: Thu, 10 Jul 2025 13:07:08 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Add support for parent_hw in audio pll clock drivers. With this parent-child relation is described with pointers rather than strings making registration a bit faster. All the SoC based drivers that rely on clk-audio-pll were adapted to the new API change. The switch itself for SoCs will be done in subsequent patches. Signed-off-by: Claudiu Beznea Signed-off-by: Ryan Wanner --- drivers/clk/at91/clk-audio-pll.c | 28 ++++++++++++++++++++-------- drivers/clk/at91/dt-compat.c | 6 +++--- drivers/clk/at91/pmc.h | 6 +++--- drivers/clk/at91/sama5d2.c | 6 +++--- 4 files changed, 29 insertions(+), 17 deletions(-) diff --git a/drivers/clk/at91/clk-audio-pll.c b/drivers/clk/at91/clk-audio-= pll.c index a92da64c12e1..da9b2e699dcc 100644 --- a/drivers/clk/at91/clk-audio-pll.c +++ b/drivers/clk/at91/clk-audio-pll.c @@ -450,7 +450,8 @@ static const struct clk_ops audio_pll_pmc_ops =3D { =20 struct clk_hw * __init at91_clk_register_audio_pll_frac(struct regmap *regmap, const char *name, - const char *parent_name) + const char *parent_name, + struct clk_parent_data *parent_data) { struct clk_audio_frac *frac_ck; struct clk_init_data init =3D {}; @@ -462,7 +463,10 @@ at91_clk_register_audio_pll_frac(struct regmap *regmap= , const char *name, =20 init.name =3D name; init.ops =3D &audio_pll_frac_ops; - init.parent_names =3D &parent_name; + if (parent_data) + init.parent_data =3D (const struct clk_parent_data *)parent_data; + else + init.parent_names =3D &parent_name; init.num_parents =3D 1; init.flags =3D CLK_SET_RATE_GATE; =20 @@ -480,10 +484,11 @@ at91_clk_register_audio_pll_frac(struct regmap *regma= p, const char *name, =20 struct clk_hw * __init at91_clk_register_audio_pll_pad(struct regmap *regmap, const char *name, - const char *parent_name) + const char *parent_name, + struct clk_parent_data *parent_data) { struct clk_audio_pad *apad_ck; - struct clk_init_data init; + struct clk_init_data init =3D {}; int ret; =20 apad_ck =3D kzalloc(sizeof(*apad_ck), GFP_KERNEL); @@ -492,7 +497,10 @@ at91_clk_register_audio_pll_pad(struct regmap *regmap,= const char *name, =20 init.name =3D name; init.ops =3D &audio_pll_pad_ops; - init.parent_names =3D &parent_name; + if (parent_data) + init.parent_data =3D (const struct clk_parent_data *)parent_data; + else + init.parent_names =3D &parent_name; init.num_parents =3D 1; init.flags =3D CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | CLK_SET_RATE_PARENT; @@ -511,10 +519,11 @@ at91_clk_register_audio_pll_pad(struct regmap *regmap= , const char *name, =20 struct clk_hw * __init at91_clk_register_audio_pll_pmc(struct regmap *regmap, const char *name, - const char *parent_name) + const char *parent_name, + struct clk_parent_data *parent_data) { struct clk_audio_pmc *apmc_ck; - struct clk_init_data init; + struct clk_init_data init =3D {}; int ret; =20 apmc_ck =3D kzalloc(sizeof(*apmc_ck), GFP_KERNEL); @@ -523,7 +532,10 @@ at91_clk_register_audio_pll_pmc(struct regmap *regmap,= const char *name, =20 init.name =3D name; init.ops =3D &audio_pll_pmc_ops; - init.parent_names =3D &parent_name; + if (parent_data) + init.parent_data =3D (const struct clk_parent_data *)parent_data; + else + init.parent_names =3D &parent_name; init.num_parents =3D 1; init.flags =3D CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | CLK_SET_RATE_PARENT; diff --git a/drivers/clk/at91/dt-compat.c b/drivers/clk/at91/dt-compat.c index 2c5faa3b1cfd..22bcaa3b28dd 100644 --- a/drivers/clk/at91/dt-compat.c +++ b/drivers/clk/at91/dt-compat.c @@ -43,7 +43,7 @@ static void __init of_sama5d2_clk_audio_pll_frac_setup(st= ruct device_node *np) =20 parent_name =3D of_clk_get_parent_name(np, 0); =20 - hw =3D at91_clk_register_audio_pll_frac(regmap, name, parent_name); + hw =3D at91_clk_register_audio_pll_frac(regmap, name, parent_name, NULL); if (IS_ERR(hw)) return; =20 @@ -69,7 +69,7 @@ static void __init of_sama5d2_clk_audio_pll_pad_setup(str= uct device_node *np) =20 parent_name =3D of_clk_get_parent_name(np, 0); =20 - hw =3D at91_clk_register_audio_pll_pad(regmap, name, parent_name); + hw =3D at91_clk_register_audio_pll_pad(regmap, name, parent_name, NULL); if (IS_ERR(hw)) return; =20 @@ -95,7 +95,7 @@ static void __init of_sama5d2_clk_audio_pll_pmc_setup(str= uct device_node *np) =20 parent_name =3D of_clk_get_parent_name(np, 0); =20 - hw =3D at91_clk_register_audio_pll_pmc(regmap, name, parent_name); + hw =3D at91_clk_register_audio_pll_pmc(regmap, name, parent_name, NULL); if (IS_ERR(hw)) return; =20 diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index 0feaf8497b60..519d71652619 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -157,15 +157,15 @@ struct clk_hw *of_clk_hw_pmc_get(struct of_phandle_ar= gs *clkspec, void *data); =20 struct clk_hw * __init at91_clk_register_audio_pll_frac(struct regmap *regmap, const char *name, - const char *parent_name); + const char *parent_name, struct clk_parent_data *parent_data); =20 struct clk_hw * __init at91_clk_register_audio_pll_pad(struct regmap *regmap, const char *name, - const char *parent_name); + const char *parent_name, struct clk_parent_data *parent_data); =20 struct clk_hw * __init at91_clk_register_audio_pll_pmc(struct regmap *regmap, const char *name, - const char *parent_name); + const char *parent_name, struct clk_parent_data *parent_data); =20 struct clk_hw * __init at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock, diff --git a/drivers/clk/at91/sama5d2.c b/drivers/clk/at91/sama5d2.c index bc62b9ed4ea0..d2af421abddc 100644 --- a/drivers/clk/at91/sama5d2.c +++ b/drivers/clk/at91/sama5d2.c @@ -227,19 +227,19 @@ static void __init sama5d2_pmc_setup(struct device_no= de *np) sama5d2_pmc->chws[PMC_PLLACK] =3D hw; =20 hw =3D at91_clk_register_audio_pll_frac(regmap, "audiopll_fracck", - "mainck"); + "mainck", NULL); if (IS_ERR(hw)) goto err_free; =20 hw =3D at91_clk_register_audio_pll_pad(regmap, "audiopll_padck", - "audiopll_fracck"); + "audiopll_fracck", NULL); if (IS_ERR(hw)) goto err_free; =20 sama5d2_pmc->chws[PMC_AUDIOPINCK] =3D hw; =20 hw =3D at91_clk_register_audio_pll_pmc(regmap, "audiopll_pmcck", - "audiopll_fracck"); + "audiopll_fracck", NULL); if (IS_ERR(hw)) goto err_free; =20 --=20 2.43.0 From nobody Tue Oct 7 09:53:13 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6AAE22FD88B; Thu, 10 Jul 2025 20:07:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752178068; cv=none; b=CBQR82VOMzR9tZFeyntpJdptw32z9t1vGOeKjH8EUXPh6MHXDV1w4hyDVk+yPNYHN60Gbdcm9FxHNSdTXUnDyFgrgBIhUpAvlilBmURU5OZIEHSyMjLL5SHXQLiL91XaZfcEUkDDEU4D8GSrWJX0qEULP7JXclCIe7VuHdKMe5Y= ARC-Message-Signature: i=1; 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Thu, 10 Jul 2025 13:07:32 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Thu, 10 Jul 2025 13:07:32 -0700 From: To: , , , , CC: , , , , Subject: [PATCH v3 16/32] clk: at91: clk-plldiv: add support for parent_hw Date: Thu, 10 Jul 2025 13:07:09 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Add support for parent_hw in plldiv clock driver. With this parent-child relation is described with pointers rather than strings making registration a bit faster. All the SoC based drivers that rely on clk-plldiv were adapted to the new API change. The switch itself for SoCs will be done in subsequent patches. Signed-off-by: Claudiu Beznea Signed-off-by: Ryan Wanner --- drivers/clk/at91/at91sam9g45.c | 2 +- drivers/clk/at91/at91sam9n12.c | 2 +- drivers/clk/at91/at91sam9x5.c | 2 +- drivers/clk/at91/clk-plldiv.c | 11 +++++++---- drivers/clk/at91/dt-compat.c | 2 +- drivers/clk/at91/pmc.h | 2 +- drivers/clk/at91/sama5d2.c | 2 +- drivers/clk/at91/sama5d3.c | 2 +- drivers/clk/at91/sama5d4.c | 2 +- 9 files changed, 15 insertions(+), 12 deletions(-) diff --git a/drivers/clk/at91/at91sam9g45.c b/drivers/clk/at91/at91sam9g45.c index 3436a09a6e8a..cb98d22c2e30 100644 --- a/drivers/clk/at91/at91sam9g45.c +++ b/drivers/clk/at91/at91sam9g45.c @@ -139,7 +139,7 @@ static void __init at91sam9g45_pmc_setup(struct device_= node *np) if (IS_ERR(hw)) goto err_free; =20 - hw =3D at91_clk_register_plldiv(regmap, "plladivck", "pllack"); + hw =3D at91_clk_register_plldiv(regmap, "plladivck", "pllack", NULL); if (IS_ERR(hw)) goto err_free; =20 diff --git a/drivers/clk/at91/at91sam9n12.c b/drivers/clk/at91/at91sam9n12.c index 80ccd4a49df3..34dd7645f964 100644 --- a/drivers/clk/at91/at91sam9n12.c +++ b/drivers/clk/at91/at91sam9n12.c @@ -165,7 +165,7 @@ static void __init at91sam9n12_pmc_setup(struct device_= node *np) if (IS_ERR(hw)) goto err_free; =20 - hw =3D at91_clk_register_plldiv(regmap, "plladivck", "pllack"); + hw =3D at91_clk_register_plldiv(regmap, "plladivck", "pllack", NULL); if (IS_ERR(hw)) goto err_free; =20 diff --git a/drivers/clk/at91/at91sam9x5.c b/drivers/clk/at91/at91sam9x5.c index 6b8c755fefdf..37280852f086 100644 --- a/drivers/clk/at91/at91sam9x5.c +++ b/drivers/clk/at91/at91sam9x5.c @@ -187,7 +187,7 @@ static void __init at91sam9x5_pmc_setup(struct device_n= ode *np, if (IS_ERR(hw)) goto err_free; =20 - hw =3D at91_clk_register_plldiv(regmap, "plladivck", "pllack"); + hw =3D at91_clk_register_plldiv(regmap, "plladivck", "pllack", NULL); if (IS_ERR(hw)) goto err_free; =20 diff --git a/drivers/clk/at91/clk-plldiv.c b/drivers/clk/at91/clk-plldiv.c index ba3a1839a96d..c5d0c6e27397 100644 --- a/drivers/clk/at91/clk-plldiv.c +++ b/drivers/clk/at91/clk-plldiv.c @@ -72,11 +72,11 @@ static const struct clk_ops plldiv_ops =3D { =20 struct clk_hw * __init at91_clk_register_plldiv(struct regmap *regmap, const char *name, - const char *parent_name) + const char *parent_name, struct clk_parent_data *parent_data) { struct clk_plldiv *plldiv; struct clk_hw *hw; - struct clk_init_data init; + struct clk_init_data init =3D {}; int ret; =20 plldiv =3D kzalloc(sizeof(*plldiv), GFP_KERNEL); @@ -85,8 +85,11 @@ at91_clk_register_plldiv(struct regmap *regmap, const ch= ar *name, =20 init.name =3D name; init.ops =3D &plldiv_ops; - init.parent_names =3D parent_name ? &parent_name : NULL; - init.num_parents =3D parent_name ? 1 : 0; + if (parent_data) + init.parent_data =3D (const struct clk_parent_data *)parent_data; + else + init.parent_names =3D &parent_name; + init.num_parents =3D 1; init.flags =3D CLK_SET_RATE_GATE; =20 plldiv->hw.init =3D &init; diff --git a/drivers/clk/at91/dt-compat.c b/drivers/clk/at91/dt-compat.c index 22bcaa3b28dd..3285e3110b58 100644 --- a/drivers/clk/at91/dt-compat.c +++ b/drivers/clk/at91/dt-compat.c @@ -724,7 +724,7 @@ of_at91sam9x5_clk_plldiv_setup(struct device_node *np) if (IS_ERR(regmap)) return; =20 - hw =3D at91_clk_register_plldiv(regmap, name, parent_name); + hw =3D at91_clk_register_plldiv(regmap, name, parent_name, NULL); if (IS_ERR(hw)) return; =20 diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index 519d71652619..df2deb134a8d 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -243,7 +243,7 @@ at91_clk_register_pll(struct regmap *regmap, const char= *name, const struct clk_pll_characteristics *characteristics); struct clk_hw * __init at91_clk_register_plldiv(struct regmap *regmap, const char *name, - const char *parent_name); + const char *parent_name, struct clk_parent_data *parent_data); =20 struct clk_hw * __init sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock, diff --git a/drivers/clk/at91/sama5d2.c b/drivers/clk/at91/sama5d2.c index d2af421abddc..7904f2122ed7 100644 --- a/drivers/clk/at91/sama5d2.c +++ b/drivers/clk/at91/sama5d2.c @@ -220,7 +220,7 @@ static void __init sama5d2_pmc_setup(struct device_node= *np) if (IS_ERR(hw)) goto err_free; =20 - hw =3D at91_clk_register_plldiv(regmap, "plladivck", "pllack"); + hw =3D at91_clk_register_plldiv(regmap, "plladivck", "pllack", NULL); if (IS_ERR(hw)) goto err_free; =20 diff --git a/drivers/clk/at91/sama5d3.c b/drivers/clk/at91/sama5d3.c index 9d86c350a1e7..7f2ac8f648dd 100644 --- a/drivers/clk/at91/sama5d3.c +++ b/drivers/clk/at91/sama5d3.c @@ -166,7 +166,7 @@ static void __init sama5d3_pmc_setup(struct device_node= *np) if (IS_ERR(hw)) goto err_free; =20 - hw =3D at91_clk_register_plldiv(regmap, "plladivck", "pllack"); + hw =3D at91_clk_register_plldiv(regmap, "plladivck", "pllack", NULL); if (IS_ERR(hw)) goto err_free; =20 diff --git a/drivers/clk/at91/sama5d4.c b/drivers/clk/at91/sama5d4.c index 8491b1e0391d..7cda8032653e 100644 --- a/drivers/clk/at91/sama5d4.c +++ b/drivers/clk/at91/sama5d4.c @@ -181,7 +181,7 @@ static void __init sama5d4_pmc_setup(struct device_node= *np) if (IS_ERR(hw)) goto err_free; =20 - hw =3D at91_clk_register_plldiv(regmap, "plladivck", "pllack"); + hw =3D at91_clk_register_plldiv(regmap, "plladivck", "pllack", NULL); if (IS_ERR(hw)) goto err_free; =20 --=20 2.43.0 From nobody Tue Oct 7 09:53:13 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CAD7A2FD876; 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charset="utf-8" From: Claudiu Beznea Add support for parent_hw in h32mx clock driver. With this parent-child relation is described with pointers rather than strings making registration a bit faster. All the SoC based drivers that rely on clk-h32mx were adapted to the new API change. The switch itself for SoCs will be done in subsequent patches. Signed-off-by: Claudiu Beznea Signed-off-by: Ryan Wanner --- drivers/clk/at91/clk-h32mx.c | 11 +++++++---- drivers/clk/at91/dt-compat.c | 2 +- drivers/clk/at91/pmc.h | 2 +- drivers/clk/at91/sama5d2.c | 2 +- drivers/clk/at91/sama5d4.c | 2 +- 5 files changed, 11 insertions(+), 8 deletions(-) diff --git a/drivers/clk/at91/clk-h32mx.c b/drivers/clk/at91/clk-h32mx.c index 1e6c12eeda10..4b709f9bd831 100644 --- a/drivers/clk/at91/clk-h32mx.c +++ b/drivers/clk/at91/clk-h32mx.c @@ -83,10 +83,10 @@ static const struct clk_ops h32mx_ops =3D { =20 struct clk_hw * __init at91_clk_register_h32mx(struct regmap *regmap, const char *name, - const char *parent_name) + const char *parent_name, struct clk_parent_data *parent_data) { struct clk_sama5d4_h32mx *h32mxclk; - struct clk_init_data init; + struct clk_init_data init =3D {}; int ret; =20 h32mxclk =3D kzalloc(sizeof(*h32mxclk), GFP_KERNEL); @@ -95,8 +95,11 @@ at91_clk_register_h32mx(struct regmap *regmap, const cha= r *name, =20 init.name =3D name; init.ops =3D &h32mx_ops; - init.parent_names =3D parent_name ? &parent_name : NULL; - init.num_parents =3D parent_name ? 1 : 0; + if (parent_data) + init.parent_data =3D (const struct clk_parent_data *)parent_data; + else + init.parent_names =3D &parent_name; + init.num_parents =3D 1; init.flags =3D CLK_SET_RATE_GATE; =20 h32mxclk->hw.init =3D &init; diff --git a/drivers/clk/at91/dt-compat.c b/drivers/clk/at91/dt-compat.c index 3285e3110b58..ccdeba3a1130 100644 --- a/drivers/clk/at91/dt-compat.c +++ b/drivers/clk/at91/dt-compat.c @@ -201,7 +201,7 @@ static void __init of_sama5d4_clk_h32mx_setup(struct de= vice_node *np) =20 parent_name =3D of_clk_get_parent_name(np, 0); =20 - hw =3D at91_clk_register_h32mx(regmap, name, parent_name); + hw =3D at91_clk_register_h32mx(regmap, name, parent_name, NULL); if (IS_ERR(hw)) return; =20 diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index df2deb134a8d..fe42700df6db 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -177,7 +177,7 @@ at91_clk_register_generated(struct regmap *regmap, spin= lock_t *lock, =20 struct clk_hw * __init at91_clk_register_h32mx(struct regmap *regmap, const char *name, - const char *parent_name); + const char *parent_name, struct clk_parent_data *parent_data); =20 struct clk_hw * __init at91_clk_i2s_mux_register(struct regmap *regmap, const char *name, diff --git a/drivers/clk/at91/sama5d2.c b/drivers/clk/at91/sama5d2.c index 7904f2122ed7..8c7ff0108b41 100644 --- a/drivers/clk/at91/sama5d2.c +++ b/drivers/clk/at91/sama5d2.c @@ -276,7 +276,7 @@ static void __init sama5d2_pmc_setup(struct device_node= *np) =20 sama5d2_pmc->chws[PMC_MCK] =3D hw; =20 - hw =3D at91_clk_register_h32mx(regmap, "h32mxck", "masterck_div"); + hw =3D at91_clk_register_h32mx(regmap, "h32mxck", "masterck_div", NULL); if (IS_ERR(hw)) goto err_free; =20 diff --git a/drivers/clk/at91/sama5d4.c b/drivers/clk/at91/sama5d4.c index 7cda8032653e..04c848cd7001 100644 --- a/drivers/clk/at91/sama5d4.c +++ b/drivers/clk/at91/sama5d4.c @@ -214,7 +214,7 @@ static void __init sama5d4_pmc_setup(struct device_node= *np) =20 sama5d4_pmc->chws[PMC_MCK] =3D hw; =20 - hw =3D at91_clk_register_h32mx(regmap, "h32mxck", "masterck_div"); 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Thu, 10 Jul 2025 13:07:32 -0700 From: To: , , , , CC: , , , , Subject: [PATCH v3 18/32] clk: at91: clk-i2s-mux: add support for parent_hw Date: Thu, 10 Jul 2025 13:07:11 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Add support for parent_hw in i2s mux clock driver. With this parent-child relation is described with pointers rather than strings making registration a bit faster. All the SoC based drivers that rely on clk-i2s-mux were adapted to the new API change. The switch itself for SoCs will be done in subsequent patches. Signed-off-by: Claudiu Beznea Signed-off-by: Ryan Wanner --- drivers/clk/at91/clk-i2s-mux.c | 6 +++++- drivers/clk/at91/dt-compat.c | 2 +- drivers/clk/at91/pmc.h | 1 + drivers/clk/at91/sama5d2.c | 4 ++-- 4 files changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/clk/at91/clk-i2s-mux.c b/drivers/clk/at91/clk-i2s-mux.c index fe6ce172b8b0..04d9fcf940fb 100644 --- a/drivers/clk/at91/clk-i2s-mux.c +++ b/drivers/clk/at91/clk-i2s-mux.c @@ -51,6 +51,7 @@ static const struct clk_ops clk_i2s_mux_ops =3D { struct clk_hw * __init at91_clk_i2s_mux_register(struct regmap *regmap, const char *name, const char * const *parent_names, + struct clk_parent_data *parent_data, unsigned int num_parents, u8 bus_id) { struct clk_init_data init =3D {}; @@ -63,7 +64,10 @@ at91_clk_i2s_mux_register(struct regmap *regmap, const c= har *name, =20 init.name =3D name; init.ops =3D &clk_i2s_mux_ops; - init.parent_names =3D parent_names; + if (parent_data) + init.parent_data =3D (const struct clk_parent_data *)parent_data; + else + init.parent_names =3D parent_names; init.num_parents =3D num_parents; =20 i2s_ck->hw.init =3D &init; diff --git a/drivers/clk/at91/dt-compat.c b/drivers/clk/at91/dt-compat.c index ccdeba3a1130..2b1aa834f111 100644 --- a/drivers/clk/at91/dt-compat.c +++ b/drivers/clk/at91/dt-compat.c @@ -239,7 +239,7 @@ static void __init of_sama5d2_clk_i2s_mux_setup(struct = device_node *np) continue; =20 hw =3D at91_clk_i2s_mux_register(regmap_sfr, i2s_mux_np->name, - parent_names, 2, bus_id); + parent_names, NULL, 2, bus_id); if (IS_ERR(hw)) continue; =20 diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index fe42700df6db..a380054d580d 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -182,6 +182,7 @@ at91_clk_register_h32mx(struct regmap *regmap, const ch= ar *name, struct clk_hw * __init at91_clk_i2s_mux_register(struct regmap *regmap, const char *name, const char * const *parent_names, + struct clk_parent_data *parent_data, unsigned int num_parents, u8 bus_id); =20 struct clk_hw * __init diff --git a/drivers/clk/at91/sama5d2.c b/drivers/clk/at91/sama5d2.c index 8c7ff0108b41..f5d6c7a96cf2 100644 --- a/drivers/clk/at91/sama5d2.c +++ b/drivers/clk/at91/sama5d2.c @@ -372,7 +372,7 @@ static void __init sama5d2_pmc_setup(struct device_node= *np) parent_names[0] =3D "i2s0_clk"; parent_names[1] =3D "i2s0_gclk"; hw =3D at91_clk_i2s_mux_register(regmap_sfr, "i2s0_muxclk", - parent_names, 2, 0); + parent_names, NULL, 2, 0); if (IS_ERR(hw)) goto err_free; =20 @@ -381,7 +381,7 @@ static void __init sama5d2_pmc_setup(struct device_node= *np) parent_names[0] =3D "i2s1_clk"; parent_names[1] =3D "i2s1_gclk"; hw =3D at91_clk_i2s_mux_register(regmap_sfr, "i2s1_muxclk", - parent_names, 2, 1); + parent_names, NULL, 2, 1); if (IS_ERR(hw)) goto err_free; =20 --=20 2.43.0 From nobody Tue Oct 7 09:53:13 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3725F2FE310; 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charset="utf-8" From: Claudiu Beznea Add support for parent_hw in smd clock drivers. With this parent-child relation is described with pointers rather than strings making registration a bit faster. All the SoC based drivers that rely on clk-smd were adapted to the new API change. The switch itself for SoCs will be done in subsequent patches. Signed-off-by: Claudiu Beznea Signed-off-by: Ryan Wanner --- drivers/clk/at91/at91sam9x5.c | 2 +- drivers/clk/at91/clk-smd.c | 10 +++++++--- drivers/clk/at91/dt-compat.c | 2 +- drivers/clk/at91/pmc.h | 3 ++- drivers/clk/at91/sama5d3.c | 2 +- drivers/clk/at91/sama5d4.c | 2 +- 6 files changed, 13 insertions(+), 8 deletions(-) diff --git a/drivers/clk/at91/at91sam9x5.c b/drivers/clk/at91/at91sam9x5.c index 37280852f086..13331e015dd7 100644 --- a/drivers/clk/at91/at91sam9x5.c +++ b/drivers/clk/at91/at91sam9x5.c @@ -226,7 +226,7 @@ static void __init at91sam9x5_pmc_setup(struct device_n= ode *np, if (IS_ERR(hw)) goto err_free; =20 - hw =3D at91sam9x5_clk_register_smd(regmap, "smdclk", parent_names, 2); + hw =3D at91sam9x5_clk_register_smd(regmap, "smdclk", parent_names, NULL, = 2); if (IS_ERR(hw)) goto err_free; =20 diff --git a/drivers/clk/at91/clk-smd.c b/drivers/clk/at91/clk-smd.c index 09c649c8598e..d53dc32b36be 100644 --- a/drivers/clk/at91/clk-smd.c +++ b/drivers/clk/at91/clk-smd.c @@ -111,11 +111,12 @@ static const struct clk_ops at91sam9x5_smd_ops =3D { =20 struct clk_hw * __init at91sam9x5_clk_register_smd(struct regmap *regmap, const char *name, - const char **parent_names, u8 num_parents) + const char **parent_names, struct clk_parent_data *parent_data, + u8 num_parents) { struct at91sam9x5_clk_smd *smd; struct clk_hw *hw; - struct clk_init_data init; + struct clk_init_data init =3D {}; int ret; =20 smd =3D kzalloc(sizeof(*smd), GFP_KERNEL); @@ -124,7 +125,10 @@ at91sam9x5_clk_register_smd(struct regmap *regmap, con= st char *name, =20 init.name =3D name; init.ops =3D &at91sam9x5_smd_ops; - init.parent_names =3D parent_names; + if (parent_data) + init.parent_data =3D (const struct clk_parent_data *)parent_data; + else + init.parent_names =3D parent_names; init.num_parents =3D num_parents; init.flags =3D CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE; =20 diff --git a/drivers/clk/at91/dt-compat.c b/drivers/clk/at91/dt-compat.c index 2b1aa834f111..5afd7c9f53fd 100644 --- a/drivers/clk/at91/dt-compat.c +++ b/drivers/clk/at91/dt-compat.c @@ -859,7 +859,7 @@ static void __init of_at91sam9x5_clk_smd_setup(struct d= evice_node *np) if (IS_ERR(regmap)) return; =20 - hw =3D at91sam9x5_clk_register_smd(regmap, name, parent_names, + hw =3D at91sam9x5_clk_register_smd(regmap, name, parent_names, NULL, num_parents); if (IS_ERR(hw)) return; diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index a380054d580d..e5ab2fb3bc89 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -277,7 +277,8 @@ at91_clk_register_sam9260_slow(struct regmap *regmap, =20 struct clk_hw * __init at91sam9x5_clk_register_smd(struct regmap *regmap, const char *name, - const char **parent_names, u8 num_parents); + const char **parent_names, struct clk_parent_data *parent_data, + u8 num_parents); =20 struct clk_hw * __init at91_clk_register_system(struct regmap *regmap, const char *name, diff --git a/drivers/clk/at91/sama5d3.c b/drivers/clk/at91/sama5d3.c index 7f2ac8f648dd..8326bb6a291c 100644 --- a/drivers/clk/at91/sama5d3.c +++ b/drivers/clk/at91/sama5d3.c @@ -205,7 +205,7 @@ static void __init sama5d3_pmc_setup(struct device_node= *np) if (IS_ERR(hw)) goto err_free; =20 - hw =3D at91sam9x5_clk_register_smd(regmap, "smdclk", parent_names, 2); + hw =3D at91sam9x5_clk_register_smd(regmap, "smdclk", parent_names, NULL, = 2); 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10 Jul 2025 13:07:38 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Thu, 10 Jul 2025 13:07:33 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Thu, 10 Jul 2025 13:07:33 -0700 From: To: , , , , CC: , , , , Subject: [PATCH v3 20/32] clk: at91: clk-slow: add support for parent_hw Date: Thu, 10 Jul 2025 13:07:13 -0700 Message-ID: <1450fe7c64df3fb1b3123633c5edce6708a5a5d6.1752176711.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Add support for parent_hw in slow clock drivers. With this parent-child relation is described with pointers rather than strings making registration a bit faster. All the SoC based drivers that rely on clk-slow were adapted to the new API change. The switch itself for SoCs will be done in subsequent patches. Signed-off-by: Claudiu Beznea Signed-off-by: Ryan Wanner --- drivers/clk/at91/at91sam9260.c | 2 +- drivers/clk/at91/clk-slow.c | 8 ++++++-- drivers/clk/at91/dt-compat.c | 2 +- drivers/clk/at91/pmc.h | 1 + 4 files changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/clk/at91/at91sam9260.c b/drivers/clk/at91/at91sam9260.c index f39deb3ec00a..55350331b07e 100644 --- a/drivers/clk/at91/at91sam9260.c +++ b/drivers/clk/at91/at91sam9260.c @@ -385,7 +385,7 @@ static void __init at91sam926x_pmc_setup(struct device_= node *np, parent_names[0] =3D "slow_rc_osc"; parent_names[1] =3D "slow_xtal"; hw =3D at91_clk_register_sam9260_slow(regmap, "slck", - parent_names, 2); + parent_names, NULL, 2); if (IS_ERR(hw)) goto err_free; =20 diff --git a/drivers/clk/at91/clk-slow.c b/drivers/clk/at91/clk-slow.c index ac9f7a48b76e..5b7fc6210e09 100644 --- a/drivers/clk/at91/clk-slow.c +++ b/drivers/clk/at91/clk-slow.c @@ -39,11 +39,12 @@ struct clk_hw * __init at91_clk_register_sam9260_slow(struct regmap *regmap, const char *name, const char **parent_names, + struct clk_parent_data *parent_data, int num_parents) { struct clk_sam9260_slow *slowck; struct clk_hw *hw; - struct clk_init_data init; + struct clk_init_data init =3D {}; int ret; =20 if (!name) @@ -58,7 +59,10 @@ at91_clk_register_sam9260_slow(struct regmap *regmap, =20 init.name =3D name; init.ops =3D &sam9260_slow_ops; - init.parent_names =3D parent_names; + if (parent_data) + init.parent_data =3D (const struct clk_parent_data *)&parent_data; + else + init.parent_names =3D parent_names; init.num_parents =3D num_parents; init.flags =3D 0; =20 diff --git a/drivers/clk/at91/dt-compat.c b/drivers/clk/at91/dt-compat.c index 5afd7c9f53fd..fa8658d3be7b 100644 --- a/drivers/clk/at91/dt-compat.c +++ b/drivers/clk/at91/dt-compat.c @@ -823,7 +823,7 @@ static void __init of_at91sam9260_clk_slow_setup(struct= device_node *np) =20 of_property_read_string(np, "clock-output-names", &name); =20 - hw =3D at91_clk_register_sam9260_slow(regmap, name, parent_names, + hw =3D at91_clk_register_sam9260_slow(regmap, name, parent_names, NULL, num_parents); if (IS_ERR(hw)) return; diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index e5ab2fb3bc89..24c32e42f264 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -273,6 +273,7 @@ struct clk_hw * __init at91_clk_register_sam9260_slow(struct regmap *regmap, const char *name, const char **parent_names, + struct clk_parent_data *parent_data, int num_parents); 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charset="utf-8" From: Claudiu Beznea Switch old dt-compat clocks to use parent_hw and parent_data. Having parent_hw instead of parent names improves to clock registration speed and re-parenting. Signed-off-by: Claudiu Beznea Signed-off-by: Ryan Wanner --- drivers/clk/at91/dt-compat.c | 80 +++++++++++++++++++++++++----------- 1 file changed, 56 insertions(+), 24 deletions(-) diff --git a/drivers/clk/at91/dt-compat.c b/drivers/clk/at91/dt-compat.c index fa8658d3be7b..15f65a19d991 100644 --- a/drivers/clk/at91/dt-compat.c +++ b/drivers/clk/at91/dt-compat.c @@ -43,7 +43,8 @@ static void __init of_sama5d2_clk_audio_pll_frac_setup(st= ruct device_node *np) =20 parent_name =3D of_clk_get_parent_name(np, 0); =20 - hw =3D at91_clk_register_audio_pll_frac(regmap, name, parent_name, NULL); + hw =3D at91_clk_register_audio_pll_frac(regmap, name, NULL, + &AT91_CLK_PD_NAME(parent_name, 0)); if (IS_ERR(hw)) return; =20 @@ -69,7 +70,8 @@ static void __init of_sama5d2_clk_audio_pll_pad_setup(str= uct device_node *np) =20 parent_name =3D of_clk_get_parent_name(np, 0); =20 - hw =3D at91_clk_register_audio_pll_pad(regmap, name, parent_name, NULL); + hw =3D at91_clk_register_audio_pll_pad(regmap, name, NULL, + &AT91_CLK_PD_NAME(parent_name, 0)); if (IS_ERR(hw)) return; =20 @@ -95,7 +97,7 @@ static void __init of_sama5d2_clk_audio_pll_pmc_setup(str= uct device_node *np) =20 parent_name =3D of_clk_get_parent_name(np, 0); =20 - hw =3D at91_clk_register_audio_pll_pmc(regmap, name, parent_name, NULL); + hw =3D at91_clk_register_audio_pll_pmc(regmap, name, NULL, &AT91_CLK_PD_N= AME(parent_name, 0)); if (IS_ERR(hw)) return; =20 @@ -129,6 +131,7 @@ static void __init of_sama5d2_clk_generated_setup(struc= t device_node *np) struct clk_hw *hw; unsigned int num_parents; const char *parent_names[GENERATED_SOURCE_MAX]; + struct clk_parent_data parent_data[GENERATED_SOURCE_MAX]; struct device_node *gcknp, *parent_np; struct clk_range range =3D CLK_RANGE(0, 0); struct regmap *regmap; @@ -149,6 +152,8 @@ static void __init of_sama5d2_clk_generated_setup(struc= t device_node *np) if (IS_ERR(regmap)) return; =20 + for (unsigned int i =3D 0; i < num_parents; i++) + parent_data[i] =3D AT91_CLK_PD_NAME(parent_names[i], i); for_each_child_of_node(np, gcknp) { int chg_pid =3D INT_MIN; =20 @@ -171,7 +176,7 @@ static void __init of_sama5d2_clk_generated_setup(struc= t device_node *np) =20 hw =3D at91_clk_register_generated(regmap, &pmc_pcr_lock, &dt_pcr_layout, name, - parent_names, NULL, NULL, + NULL, parent_data, NULL, num_parents, id, &range, chg_pid); if (IS_ERR(hw)) @@ -201,7 +206,7 @@ static void __init of_sama5d4_clk_h32mx_setup(struct de= vice_node *np) =20 parent_name =3D of_clk_get_parent_name(np, 0); =20 - hw =3D at91_clk_register_h32mx(regmap, name, parent_name, NULL); + hw =3D at91_clk_register_h32mx(regmap, name, NULL, &AT91_CLK_PD_NAME(pare= nt_name, 0)); if (IS_ERR(hw)) return; =20 @@ -228,6 +233,8 @@ static void __init of_sama5d2_clk_i2s_mux_setup(struct = device_node *np) return; =20 for_each_child_of_node(np, i2s_mux_np) { + struct clk_parent_data parent_data[2]; + if (of_property_read_u8(i2s_mux_np, "reg", &bus_id)) continue; =20 @@ -238,8 +245,10 @@ static void __init of_sama5d2_clk_i2s_mux_setup(struct= device_node *np) if (ret !=3D 2) continue; =20 + parent_data[0] =3D AT91_CLK_PD_NAME(parent_names[0], 0); + parent_data[1] =3D AT91_CLK_PD_NAME(parent_names[1], 1); hw =3D at91_clk_i2s_mux_register(regmap_sfr, i2s_mux_np->name, - parent_names, NULL, 2, bus_id); + NULL, parent_data, 2, bus_id); if (IS_ERR(hw)) continue; =20 @@ -269,7 +278,8 @@ static void __init of_at91rm9200_clk_main_osc_setup(str= uct device_node *np) if (IS_ERR(regmap)) return; =20 - hw =3D at91_clk_register_main_osc(regmap, name, parent_name, NULL, bypass= ); + hw =3D at91_clk_register_main_osc(regmap, name, NULL, + &AT91_CLK_PD_NAME(parent_name, 0), bypass); if (IS_ERR(hw)) return; =20 @@ -323,7 +333,7 @@ static void __init of_at91rm9200_clk_main_setup(struct = device_node *np) if (IS_ERR(regmap)) return; =20 - hw =3D at91_clk_register_rm9200_main(regmap, name, parent_name, NULL); + hw =3D at91_clk_register_rm9200_main(regmap, name, NULL, &AT91_CLK_PD_NAM= E(parent_name, 0)); if (IS_ERR(hw)) return; =20 @@ -336,6 +346,7 @@ static void __init of_at91sam9x5_clk_main_setup(struct = device_node *np) { struct clk_hw *hw; const char *parent_names[2]; + struct clk_parent_data parent_data[2]; unsigned int num_parents; const char *name =3D np->name; struct regmap *regmap; @@ -354,7 +365,9 @@ static void __init of_at91sam9x5_clk_main_setup(struct = device_node *np) =20 of_property_read_string(np, "clock-output-names", &name); =20 - hw =3D at91_clk_register_sam9x5_main(regmap, name, parent_names, NULL, + parent_data[0] =3D AT91_CLK_PD_NAME(parent_names[0], 0); + parent_data[1] =3D AT91_CLK_PD_NAME(parent_names[1], 1); + hw =3D at91_clk_register_sam9x5_main(regmap, name, NULL, parent_data, num_parents); if (IS_ERR(hw)) return; @@ -396,6 +409,7 @@ of_at91_clk_master_setup(struct device_node *np, struct clk_hw *hw; unsigned int num_parents; const char *parent_names[MASTER_SOURCE_MAX]; + struct clk_parent_data parent_data[MASTER_SOURCE_MAX]; const char *name =3D np->name; struct clk_master_characteristics *characteristics; struct regmap *regmap; @@ -419,13 +433,15 @@ of_at91_clk_master_setup(struct device_node *np, if (IS_ERR(regmap)) return; =20 + for (unsigned int i =3D 0; i < MASTER_SOURCE_MAX; i++) + parent_data[i] =3D AT91_CLK_PD_NAME(parent_names[i], i); hw =3D at91_clk_register_master_pres(regmap, "masterck_pres", num_parents, - parent_names, NULL, layout, + NULL, parent_data, layout, characteristics, &mck_lock); if (IS_ERR(hw)) goto out_free_characteristics; =20 - hw =3D at91_clk_register_master_div(regmap, name, "masterck_pres", NULL, + hw =3D at91_clk_register_master_div(regmap, name, NULL, &AT91_CLK_PD_HW(h= w), layout, characteristics, &mck_lock, CLK_SET_RATE_GATE, 0); if (IS_ERR(hw)) @@ -489,8 +505,8 @@ of_at91_clk_periph_setup(struct device_node *np, u8 typ= e) name =3D periphclknp->name; =20 if (type =3D=3D PERIPHERAL_AT91RM9200) { - hw =3D at91_clk_register_peripheral(regmap, name, - parent_name, NULL, id); + hw =3D at91_clk_register_peripheral(regmap, name, NULL, + &AT91_CLK_PD_NAME(parent_name, 0), id); } else { struct clk_range range =3D CLK_RANGE(0, 0); unsigned long flags =3D 0; @@ -511,8 +527,8 @@ of_at91_clk_periph_setup(struct device_node *np, u8 typ= e) &pmc_pcr_lock, &dt_pcr_layout, name, - parent_name, NULL, + &AT91_CLK_PD_NAME(parent_name, 0), id, &range, INT_MIN, flags); @@ -665,7 +681,8 @@ of_at91_clk_pll_setup(struct device_node *np, if (!characteristics) return; =20 - hw =3D at91_clk_register_pll(regmap, name, parent_name, NULL, id, layout, + hw =3D at91_clk_register_pll(regmap, name, NULL, &AT91_CLK_PD_NAME(parent= _name, 0), + id, layout, characteristics); if (IS_ERR(hw)) goto out_free_characteristics; @@ -724,7 +741,7 @@ of_at91sam9x5_clk_plldiv_setup(struct device_node *np) if (IS_ERR(regmap)) return; =20 - hw =3D at91_clk_register_plldiv(regmap, name, parent_name, NULL); + hw =3D at91_clk_register_plldiv(regmap, name, NULL, &AT91_CLK_PD_NAME(par= ent_name, 0)); if (IS_ERR(hw)) return; =20 @@ -743,6 +760,7 @@ of_at91_clk_prog_setup(struct device_node *np, struct clk_hw *hw; unsigned int num_parents; const char *parent_names[PROG_SOURCE_MAX]; + struct clk_parent_data parent_data[PROG_SOURCE_MAX]; const char *name; struct device_node *progclknp, *parent_np; struct regmap *regmap; @@ -763,6 +781,8 @@ of_at91_clk_prog_setup(struct device_node *np, if (IS_ERR(regmap)) return; =20 + for (unsigned int i =3D 0; i < PROG_SOURCE_MAX; i++) + parent_data[i] =3D AT91_CLK_PD_NAME(parent_names[i], i); for_each_child_of_node(np, progclknp) { if (of_property_read_u32(progclknp, "reg", &id)) continue; @@ -771,7 +791,7 @@ of_at91_clk_prog_setup(struct device_node *np, name =3D progclknp->name; =20 hw =3D at91_clk_register_programmable(regmap, name, - parent_names, NULL, num_parents, + NULL, parent_data, num_parents, id, layout, mux_table); if (IS_ERR(hw)) continue; @@ -805,6 +825,7 @@ static void __init of_at91sam9260_clk_slow_setup(struct= device_node *np) { struct clk_hw *hw; const char *parent_names[2]; + struct clk_parent_data parent_data[2]; unsigned int num_parents; const char *name =3D np->name; struct regmap *regmap; @@ -823,7 +844,9 @@ static void __init of_at91sam9260_clk_slow_setup(struct= device_node *np) =20 of_property_read_string(np, "clock-output-names", &name); =20 - hw =3D at91_clk_register_sam9260_slow(regmap, name, parent_names, NULL, + parent_data[0] =3D AT91_CLK_PD_NAME(parent_names[0], 0); + parent_data[1] =3D AT91_CLK_PD_NAME(parent_names[1], 1); + hw =3D at91_clk_register_sam9260_slow(regmap, name, NULL, parent_data, num_parents); if (IS_ERR(hw)) return; @@ -841,6 +864,7 @@ static void __init of_at91sam9x5_clk_smd_setup(struct d= evice_node *np) struct clk_hw *hw; unsigned int num_parents; const char *parent_names[SMD_SOURCE_MAX]; + struct clk_parent_data parent_data[SMD_SOURCE_MAX]; const char *name =3D np->name; struct regmap *regmap; struct device_node *parent_np; @@ -859,7 +883,9 @@ static void __init of_at91sam9x5_clk_smd_setup(struct d= evice_node *np) if (IS_ERR(regmap)) return; =20 - hw =3D at91sam9x5_clk_register_smd(regmap, name, parent_names, NULL, + for (unsigned int i =3D 0; i < SMD_SOURCE_MAX; i++) + parent_data[i] =3D AT91_CLK_PD_NAME(parent_names[i], i); + hw =3D at91sam9x5_clk_register_smd(regmap, name, NULL, parent_data, num_parents); if (IS_ERR(hw)) return; @@ -909,7 +935,8 @@ static void __init of_at91rm9200_clk_sys_setup(struct d= evice_node *np) if (!strcmp(sysclknp->name, "ddrck")) flags =3D CLK_IS_CRITICAL; =20 - hw =3D at91_clk_register_system(regmap, name, parent_name, NULL, + hw =3D at91_clk_register_system(regmap, name, NULL, + &AT91_CLK_PD_NAME(parent_name, 0), id, flags); if (IS_ERR(hw)) continue; @@ -928,6 +955,7 @@ static void __init of_at91sam9x5_clk_usb_setup(struct d= evice_node *np) struct clk_hw *hw; unsigned int num_parents; const char *parent_names[USB_SOURCE_MAX]; + struct clk_parent_data parent_data[USB_SOURCE_MAX]; const char *name =3D np->name; struct regmap *regmap; struct device_node *parent_np; @@ -946,7 +974,9 @@ static void __init of_at91sam9x5_clk_usb_setup(struct d= evice_node *np) if (IS_ERR(regmap)) return; =20 - hw =3D at91sam9x5_clk_register_usb(regmap, name, parent_names, NULL, + for (unsigned int i =3D 0; i < USB_SOURCE_MAX; i++) + parent_data[i] =3D AT91_CLK_PD_NAME(parent_names[i], i); + hw =3D at91sam9x5_clk_register_usb(regmap, name, NULL, parent_data, num_parents); if (IS_ERR(hw)) return; @@ -976,7 +1006,7 @@ static void __init of_at91sam9n12_clk_usb_setup(struct= device_node *np) if (IS_ERR(regmap)) return; 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charset="utf-8" From: Claudiu Beznea Switch SAM9X60 clocks to use modern parent_hw and parent_data. Signed-off-by: Claudiu Beznea Signed-off-by: Ryan Wanner --- drivers/clk/at91/sam9x60.c | 109 +++++++++++++++++-------------------- 1 file changed, 51 insertions(+), 58 deletions(-) diff --git a/drivers/clk/at91/sam9x60.c b/drivers/clk/at91/sam9x60.c index eb38da77d69a..b2e86e600a9f 100644 --- a/drivers/clk/at91/sam9x60.c +++ b/drivers/clk/at91/sam9x60.c @@ -79,9 +79,9 @@ static const struct clk_pcr_layout sam9x60_pcr_layout =3D= { .pid_mask =3D GENMASK(6, 0), }; =20 -static const struct { +static struct { char *n; - char *p; + struct clk_hw *parent_hw; unsigned long flags; u8 id; } sam9x60_systemck[] =3D { @@ -89,11 +89,11 @@ static const struct { * ddrck feeds DDR controller and is enabled by bootloader thus we need * to keep it enabled in case there is no Linux consumer for it. */ - { .n =3D "ddrck", .p =3D "masterck_div", .id =3D 2, .flags =3D CLK_IS_CR= ITICAL }, - { .n =3D "uhpck", .p =3D "usbck", .id =3D 6 }, - { .n =3D "pck0", .p =3D "prog0", .id =3D 8 }, - { .n =3D "pck1", .p =3D "prog1", .id =3D 9 }, - { .n =3D "qspick", .p =3D "masterck_div", .id =3D 19 }, + { .n =3D "ddrck", .id =3D 2, .flags =3D CLK_IS_CRITICAL }, + { .n =3D "uhpck", .id =3D 6 }, + { .n =3D "pck0", .id =3D 8 }, + { .n =3D "pck1", .id =3D 9 }, + { .n =3D "qspick", .id =3D 19 }, }; =20 static const struct { @@ -184,32 +184,17 @@ static const struct { =20 static void __init sam9x60_pmc_setup(struct device_node *np) { + const char *td_slck_name =3D "td_slck", *md_slck_name =3D "md_slck"; + u8 td_slck_index =3D 0, md_slck_index =3D 1, main_xtal_index =3D 2; + struct clk_hw *hw, *main_rc_hw, *main_osc_hw; + const char *main_xtal_name =3D "main_xtal"; struct clk_range range =3D CLK_RANGE(0, 0); - const char *td_slck_name, *md_slck_name, *mainxtal_name; + struct clk_parent_data parent_data[6]; struct pmc_data *sam9x60_pmc; - const char *parent_names[6]; - struct clk_hw *main_osc_hw; + struct clk_hw *usbck_hw; struct regmap *regmap; - struct clk_hw *hw; int i; =20 - i =3D of_property_match_string(np, "clock-names", "td_slck"); - if (i < 0) - return; - - td_slck_name =3D of_clk_get_parent_name(np, i); - - i =3D of_property_match_string(np, "clock-names", "md_slck"); - if (i < 0) - return; - - md_slck_name =3D of_clk_get_parent_name(np, i); - - i =3D of_property_match_string(np, "clock-names", "main_xtal"); - if (i < 0) - return; - mainxtal_name =3D of_clk_get_parent_name(np, i); - regmap =3D device_node_to_regmap(np); if (IS_ERR(regmap)) return; @@ -221,19 +206,20 @@ static void __init sam9x60_pmc_setup(struct device_no= de *np) if (!sam9x60_pmc) return; =20 - hw =3D at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000, - 50000000); - if (IS_ERR(hw)) + main_rc_hw =3D at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000= 000, + 50000000); + if (IS_ERR(main_rc_hw)) goto err_free; =20 - hw =3D at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL= , 0); + main_osc_hw =3D at91_clk_register_main_osc(regmap, "main_osc", NULL, + &AT91_CLK_PD_NAME(main_xtal_name, main_xtal_index), + 0); if (IS_ERR(hw)) goto err_free; - main_osc_hw =3D hw; =20 - parent_names[0] =3D "main_rc_osc"; - parent_names[1] =3D "main_osc"; - hw =3D at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL= , 2); + parent_data[0] =3D AT91_CLK_PD_HW(main_rc_hw); + parent_data[1] =3D AT91_CLK_PD_HW(main_osc_hw); + hw =3D at91_clk_register_sam9x5_main(regmap, "mainck", NULL, parent_data,= 2); if (IS_ERR(hw)) goto err_free; =20 @@ -254,7 +240,7 @@ static void __init sam9x60_pmc_setup(struct device_node= *np) goto err_free; =20 hw =3D sam9x60_clk_register_div_pll(regmap, &pmc_pll_lock, "pllack_divck", - "pllack_fracck", NULL, 0, &plla_characteristics, + NULL, hw, 0, &plla_characteristics, &pll_div_layout, /* * This feeds CPU. It should not @@ -275,7 +261,7 @@ static void __init sam9x60_pmc_setup(struct device_node= *np) goto err_free; =20 hw =3D sam9x60_clk_register_div_pll(regmap, &pmc_pll_lock, "upllck_divck", - "upllck_fracck", NULL, 1, &upll_characteristics, + NULL, hw, 1, &upll_characteristics, &pll_div_layout, CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | @@ -285,17 +271,17 @@ static void __init sam9x60_pmc_setup(struct device_no= de *np) =20 sam9x60_pmc->chws[PMC_UTMI] =3D hw; =20 - parent_names[0] =3D md_slck_name; - parent_names[1] =3D "mainck"; - parent_names[2] =3D "pllack_divck"; + parent_data[0] =3D AT91_CLK_PD_NAME(md_slck_name, md_slck_index); + parent_data[1] =3D AT91_CLK_PD_HW(sam9x60_pmc->chws[PMC_MAIN]); + parent_data[2] =3D AT91_CLK_PD_HW(sam9x60_pmc->chws[PMC_PLLACK]); hw =3D at91_clk_register_master_pres(regmap, "masterck_pres", 3, - parent_names, NULL, &sam9x60_master_layout, + NULL, parent_data, &sam9x60_master_layout, &mck_characteristics, &mck_lock); if (IS_ERR(hw)) goto err_free; =20 hw =3D at91_clk_register_master_div(regmap, "masterck_div", - "masterck_pres", NULL, &sam9x60_master_layout, + NULL, &AT91_CLK_PD_HW(hw), &sam9x60_master_layout, &mck_characteristics, &mck_lock, CLK_SET_RATE_GATE, 0); if (IS_ERR(hw)) @@ -303,26 +289,26 @@ static void __init sam9x60_pmc_setup(struct device_no= de *np) =20 sam9x60_pmc->chws[PMC_MCK] =3D hw; =20 - parent_names[0] =3D "pllack_divck"; - parent_names[1] =3D "upllck_divck"; - parent_names[2] =3D "main_osc"; - hw =3D sam9x60_clk_register_usb(regmap, "usbck", parent_names, NULL, 3); - if (IS_ERR(hw)) + parent_data[0] =3D AT91_CLK_PD_HW(sam9x60_pmc->chws[PMC_PLLACK]); + parent_data[1] =3D AT91_CLK_PD_HW(sam9x60_pmc->chws[PMC_UTMI]); + parent_data[2] =3D AT91_CLK_PD_HW(main_osc_hw); + usbck_hw =3D sam9x60_clk_register_usb(regmap, "usbck", NULL, parent_data,= 3); + if (IS_ERR(usbck_hw)) goto err_free; =20 - parent_names[0] =3D md_slck_name; - parent_names[1] =3D td_slck_name; - parent_names[2] =3D "mainck"; - parent_names[3] =3D "masterck_div"; - parent_names[4] =3D "pllack_divck"; - parent_names[5] =3D "upllck_divck"; + parent_data[0] =3D AT91_CLK_PD_NAME(md_slck_name, md_slck_index); + parent_data[1] =3D AT91_CLK_PD_NAME(td_slck_name, td_slck_index); + parent_data[2] =3D AT91_CLK_PD_HW(sam9x60_pmc->chws[PMC_MAIN]); + parent_data[3] =3D AT91_CLK_PD_HW(sam9x60_pmc->chws[PMC_MCK]); + parent_data[4] =3D AT91_CLK_PD_HW(sam9x60_pmc->chws[PMC_PLLACK]); + parent_data[5] =3D AT91_CLK_PD_HW(sam9x60_pmc->chws[PMC_UTMI]); for (i =3D 0; i < 2; i++) { char name[6]; =20 snprintf(name, sizeof(name), "prog%d", i); =20 hw =3D at91_clk_register_programmable(regmap, name, - parent_names, NULL, 6, i, + NULL, parent_data, 6, i, &sam9x60_programmable_layout, NULL); if (IS_ERR(hw)) @@ -331,9 +317,15 @@ static void __init sam9x60_pmc_setup(struct device_nod= e *np) sam9x60_pmc->pchws[i] =3D hw; } =20 + /* Set systemck parent hws. */ + sam9x60_systemck[0].parent_hw =3D sam9x60_pmc->chws[PMC_MCK]; + sam9x60_systemck[1].parent_hw =3D usbck_hw; + sam9x60_systemck[2].parent_hw =3D sam9x60_pmc->pchws[0]; + sam9x60_systemck[3].parent_hw =3D sam9x60_pmc->pchws[1]; + sam9x60_systemck[4].parent_hw =3D sam9x60_pmc->chws[PMC_MCK]; for (i =3D 0; i < ARRAY_SIZE(sam9x60_systemck); i++) { hw =3D at91_clk_register_system(regmap, sam9x60_systemck[i].n, - sam9x60_systemck[i].p, NULL, + NULL, &AT91_CLK_PD_HW(sam9x60_systemck[i].parent_hw), sam9x60_systemck[i].id, sam9x60_systemck[i].flags); if (IS_ERR(hw)) @@ -346,7 +338,8 @@ static void __init sam9x60_pmc_setup(struct device_node= *np) hw =3D at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, &sam9x60_pcr_layout, sam9x60_periphck[i].n, - "masterck_div", NULL, + NULL, + &AT91_CLK_PD_HW(sam9x60_pmc->chws[PMC_MCK]), sam9x60_periphck[i].id, &range, INT_MIN, sam9x60_periphck[i].flags); @@ -360,7 +353,7 @@ static void __init sam9x60_pmc_setup(struct device_node= *np) hw =3D at91_clk_register_generated(regmap, &pmc_pcr_lock, &sam9x60_pcr_layout, sam9x60_gck[i].n, - parent_names, NULL, NULL, 6, + NULL, parent_data, NULL, 6, sam9x60_gck[i].id, &sam9x60_gck[i].r, INT_MIN); if (IS_ERR(hw)) --=20 2.43.0 From nobody Tue Oct 7 09:53:13 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A28892FE37B; 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charset="utf-8" From: Claudiu Beznea Switch SAMA5D2 clocks to use parent_hw and parent_data. Having parent_hw instead of parent names improves to clock registration speed and re-parenting. Signed-off-by: Claudiu Beznea [ryan.wanner@microchip.com: Adjust commit message.] Signed-off-by: Ryan Wanner --- drivers/clk/at91/sama5d2.c | 168 +++++++++++++++++++------------------ 1 file changed, 86 insertions(+), 82 deletions(-) diff --git a/drivers/clk/at91/sama5d2.c b/drivers/clk/at91/sama5d2.c index f5d6c7a96cf2..538ffb8deedb 100644 --- a/drivers/clk/at91/sama5d2.c +++ b/drivers/clk/at91/sama5d2.c @@ -37,9 +37,9 @@ static const struct clk_pcr_layout sama5d2_pcr_layout =3D= { .pid_mask =3D GENMASK(6, 0), }; =20 -static const struct { +static struct { char *n; - char *p; + struct clk_hw *parent_hw; unsigned long flags; u8 id; } sama5d2_systemck[] =3D { @@ -47,14 +47,14 @@ static const struct { * ddrck feeds DDR controller and is enabled by bootloader thus we need * to keep it enabled in case there is no Linux consumer for it. */ - { .n =3D "ddrck", .p =3D "masterck_div", .id =3D 2, .flags =3D CLK_IS_CRI= TICAL }, - { .n =3D "lcdck", .p =3D "masterck_div", .id =3D 3 }, - { .n =3D "uhpck", .p =3D "usbck", .id =3D 6 }, - { .n =3D "udpck", .p =3D "usbck", .id =3D 7 }, - { .n =3D "pck0", .p =3D "prog0", .id =3D 8 }, - { .n =3D "pck1", .p =3D "prog1", .id =3D 9 }, - { .n =3D "pck2", .p =3D "prog2", .id =3D 10 }, - { .n =3D "iscck", .p =3D "masterck_div", .id =3D 18 }, + { .n =3D "ddrck", .id =3D 2, .flags =3D CLK_IS_CRITICAL }, + { .n =3D "lcdck", .id =3D 3 }, + { .n =3D "uhpck", .id =3D 6 }, + { .n =3D "udpck", .id =3D 7 }, + { .n =3D "pck0", .id =3D 8 }, + { .n =3D "pck1", .id =3D 9 }, + { .n =3D "pck2", .id =3D 10 }, + { .n =3D "iscck", .id =3D 18 }, }; =20 static const struct { @@ -164,25 +164,15 @@ static const struct clk_programmable_layout sama5d2_p= rogrammable_layout =3D { =20 static void __init sama5d2_pmc_setup(struct device_node *np) { + struct clk_hw *hw, *audio_fracck_hw, *usbck_hw, *main_rc_hw, *main_osc_hw; + const char *slow_clk_name =3D "slowck", *main_xtal_name =3D "main_xtal"; + u8 slow_clk_index =3D 0, main_xtal_index =3D 1; struct clk_range range =3D CLK_RANGE(0, 0); - const char *slck_name, *mainxtal_name; - struct pmc_data *sama5d2_pmc; - const char *parent_names[6]; + struct clk_parent_data parent_data[6]; struct regmap *regmap, *regmap_sfr; - struct clk_hw *hw; - int i; + struct pmc_data *sama5d2_pmc; bool bypass; - - i =3D of_property_match_string(np, "clock-names", "slow_clk"); - if (i < 0) - return; - - slck_name =3D of_clk_get_parent_name(np, i); - - i =3D of_property_match_string(np, "clock-names", "main_xtal"); - if (i < 0) - return; - mainxtal_name =3D of_clk_get_parent_name(np, i); + int i; =20 regmap =3D device_node_to_regmap(np); if (IS_ERR(regmap)) @@ -195,51 +185,52 @@ static void __init sama5d2_pmc_setup(struct device_no= de *np) if (!sama5d2_pmc) return; =20 - hw =3D at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000, - 100000000); - if (IS_ERR(hw)) + main_rc_hw =3D at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000= 000, + 100000000); + if (IS_ERR(main_rc_hw)) goto err_free; =20 bypass =3D of_property_read_bool(np, "atmel,osc-bypass"); =20 - hw =3D at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL, - bypass); - if (IS_ERR(hw)) + main_osc_hw =3D at91_clk_register_main_osc(regmap, "main_osc", NULL, + &AT91_CLK_PD_NAME(main_xtal_name, main_xtal_index), + bypass); + if (IS_ERR(main_osc_hw)) goto err_free; =20 - parent_names[0] =3D "main_rc_osc"; - parent_names[1] =3D "main_osc"; - hw =3D at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL= , 2); + parent_data[0] =3D AT91_CLK_PD_HW(main_rc_hw); + parent_data[1] =3D AT91_CLK_PD_HW(main_osc_hw); + hw =3D at91_clk_register_sam9x5_main(regmap, "mainck", NULL, parent_data,= 2); if (IS_ERR(hw)) goto err_free; =20 sama5d2_pmc->chws[PMC_MAIN] =3D hw; - - hw =3D at91_clk_register_pll(regmap, "pllack", "mainck", NULL, 0, + hw =3D at91_clk_register_pll(regmap, "pllack", NULL, + &AT91_CLK_PD_HW(sama5d2_pmc->chws[PMC_MAIN]), 0, &sama5d3_pll_layout, &plla_characteristics); if (IS_ERR(hw)) goto err_free; =20 - hw =3D at91_clk_register_plldiv(regmap, "plladivck", "pllack", NULL); + hw =3D at91_clk_register_plldiv(regmap, "plladivck", NULL, &AT91_CLK_PD_H= W(hw)); if (IS_ERR(hw)) goto err_free; =20 sama5d2_pmc->chws[PMC_PLLACK] =3D hw; =20 - hw =3D at91_clk_register_audio_pll_frac(regmap, "audiopll_fracck", - "mainck", NULL); - if (IS_ERR(hw)) + audio_fracck_hw =3D at91_clk_register_audio_pll_frac(regmap, "audiopll_fr= acck", NULL, + &AT91_CLK_PD_HW(sama5d2_pmc->chws[PMC_MAIN])); + if (IS_ERR(audio_fracck_hw)) goto err_free; =20 - hw =3D at91_clk_register_audio_pll_pad(regmap, "audiopll_padck", - "audiopll_fracck", NULL); + hw =3D at91_clk_register_audio_pll_pad(regmap, "audiopll_padck", NULL, + &AT91_CLK_PD_HW(audio_fracck_hw)); if (IS_ERR(hw)) goto err_free; =20 sama5d2_pmc->chws[PMC_AUDIOPINCK] =3D hw; =20 - hw =3D at91_clk_register_audio_pll_pmc(regmap, "audiopll_pmcck", - "audiopll_fracck", NULL); + hw =3D at91_clk_register_audio_pll_pmc(regmap, "audiopll_pmcck", NULL, + &AT91_CLK_PD_HW(audio_fracck_hw)); if (IS_ERR(hw)) goto err_free; =20 @@ -249,25 +240,26 @@ static void __init sama5d2_pmc_setup(struct device_no= de *np) if (IS_ERR(regmap_sfr)) regmap_sfr =3D NULL; =20 - hw =3D at91_clk_register_utmi(regmap, regmap_sfr, "utmick", "mainck", NUL= L); + hw =3D at91_clk_register_utmi(regmap, regmap_sfr, "utmick", NULL, + &AT91_CLK_PD_HW(sama5d2_pmc->chws[PMC_MAIN])); if (IS_ERR(hw)) goto err_free; =20 sama5d2_pmc->chws[PMC_UTMI] =3D hw; =20 - parent_names[0] =3D slck_name; - parent_names[1] =3D "mainck"; - parent_names[2] =3D "plladivck"; - parent_names[3] =3D "utmick"; + parent_data[0] =3D AT91_CLK_PD_NAME(slow_clk_name, slow_clk_index); + parent_data[1] =3D AT91_CLK_PD_HW(sama5d2_pmc->chws[PMC_MAIN]); + parent_data[2] =3D AT91_CLK_PD_HW(sama5d2_pmc->chws[PMC_PLLACK]); + parent_data[3] =3D AT91_CLK_PD_HW(sama5d2_pmc->chws[PMC_UTMI]); hw =3D at91_clk_register_master_pres(regmap, "masterck_pres", 4, - parent_names, NULL, + NULL, parent_data, &at91sam9x5_master_layout, &mck_characteristics, &mck_lock); if (IS_ERR(hw)) goto err_free; =20 - hw =3D at91_clk_register_master_div(regmap, "masterck_div", - "masterck_pres", NULL, + hw =3D at91_clk_register_master_div(regmap, "masterck_div", NULL, + &AT91_CLK_PD_HW(hw), &at91sam9x5_master_layout, &mck_characteristics, &mck_lock, CLK_SET_RATE_GATE, 0); @@ -276,31 +268,32 @@ static void __init sama5d2_pmc_setup(struct device_no= de *np) =20 sama5d2_pmc->chws[PMC_MCK] =3D hw; =20 - hw =3D at91_clk_register_h32mx(regmap, "h32mxck", "masterck_div", NULL); + hw =3D at91_clk_register_h32mx(regmap, "h32mxck", NULL, + &AT91_CLK_PD_HW(sama5d2_pmc->chws[PMC_MCK])); if (IS_ERR(hw)) goto err_free; =20 sama5d2_pmc->chws[PMC_MCK2] =3D hw; =20 - parent_names[0] =3D "plladivck"; - parent_names[1] =3D "utmick"; - hw =3D at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, NULL, 2= ); - if (IS_ERR(hw)) + parent_data[0] =3D AT91_CLK_PD_HW(sama5d2_pmc->chws[PMC_PLLACK]); + parent_data[1] =3D AT91_CLK_PD_HW(sama5d2_pmc->chws[PMC_UTMI]); + usbck_hw =3D at91sam9x5_clk_register_usb(regmap, "usbck", NULL, parent_da= ta, 2); + if (IS_ERR(usbck_hw)) goto err_free; =20 - parent_names[0] =3D slck_name; - parent_names[1] =3D "mainck"; - parent_names[2] =3D "plladivck"; - parent_names[3] =3D "utmick"; - parent_names[4] =3D "masterck_div"; - parent_names[5] =3D "audiopll_pmcck"; + parent_data[0] =3D AT91_CLK_PD_NAME(slow_clk_name, slow_clk_index); + parent_data[1] =3D AT91_CLK_PD_HW(sama5d2_pmc->chws[PMC_MAIN]); + parent_data[2] =3D AT91_CLK_PD_HW(sama5d2_pmc->chws[PMC_PLLACK]); + parent_data[3] =3D AT91_CLK_PD_HW(sama5d2_pmc->chws[PMC_UTMI]); + parent_data[4] =3D AT91_CLK_PD_HW(sama5d2_pmc->chws[PMC_MCK]); + parent_data[5] =3D AT91_CLK_PD_HW(sama5d2_pmc->chws[PMC_AUDIOPLLCK]); for (i =3D 0; i < 3; i++) { char name[6]; =20 snprintf(name, sizeof(name), "prog%d", i); =20 hw =3D at91_clk_register_programmable(regmap, name, - parent_names, NULL, 6, i, + NULL, parent_data, 6, i, &sama5d2_programmable_layout, NULL); if (IS_ERR(hw)) @@ -309,9 +302,18 @@ static void __init sama5d2_pmc_setup(struct device_nod= e *np) sama5d2_pmc->pchws[i] =3D hw; } =20 + /* Set systemck parent hws. */ + sama5d2_systemck[0].parent_hw =3D sama5d2_pmc->chws[PMC_MCK]; + sama5d2_systemck[1].parent_hw =3D sama5d2_pmc->chws[PMC_MCK]; + sama5d2_systemck[2].parent_hw =3D usbck_hw; + sama5d2_systemck[3].parent_hw =3D usbck_hw; + sama5d2_systemck[4].parent_hw =3D sama5d2_pmc->pchws[0]; + sama5d2_systemck[5].parent_hw =3D sama5d2_pmc->pchws[1]; + sama5d2_systemck[6].parent_hw =3D sama5d2_pmc->pchws[2]; + sama5d2_systemck[7].parent_hw =3D sama5d2_pmc->chws[PMC_MCK]; for (i =3D 0; i < ARRAY_SIZE(sama5d2_systemck); i++) { - hw =3D at91_clk_register_system(regmap, sama5d2_systemck[i].n, - sama5d2_systemck[i].p, NULL, + hw =3D at91_clk_register_system(regmap, sama5d2_systemck[i].n, NULL, + &AT91_CLK_PD_HW(sama5d2_systemck[i].parent_hw), sama5d2_systemck[i].id, sama5d2_systemck[i].flags); if (IS_ERR(hw)) @@ -324,7 +326,8 @@ static void __init sama5d2_pmc_setup(struct device_node= *np) hw =3D at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, &sama5d2_pcr_layout, sama5d2_periphck[i].n, - "masterck_div", NULL, + NULL, + &AT91_CLK_PD_HW(sama5d2_pmc->chws[PMC_MCK]), sama5d2_periphck[i].id, &range, INT_MIN, sama5d2_periphck[i].flags); @@ -338,7 +341,8 @@ static void __init sama5d2_pmc_setup(struct device_node= *np) hw =3D at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, &sama5d2_pcr_layout, sama5d2_periph32ck[i].n, - "h32mxck", NULL, + NULL, + &AT91_CLK_PD_HW(sama5d2_pmc->chws[PMC_MCK2]), sama5d2_periph32ck[i].id, &sama5d2_periph32ck[i].r, INT_MIN, 0); @@ -348,17 +352,17 @@ static void __init sama5d2_pmc_setup(struct device_no= de *np) sama5d2_pmc->phws[sama5d2_periph32ck[i].id] =3D hw; } =20 - parent_names[0] =3D slck_name; - parent_names[1] =3D "mainck"; - parent_names[2] =3D "plladivck"; - parent_names[3] =3D "utmick"; - parent_names[4] =3D "masterck_div"; - parent_names[5] =3D "audiopll_pmcck"; + parent_data[0] =3D AT91_CLK_PD_NAME(slow_clk_name, slow_clk_index); + parent_data[1] =3D AT91_CLK_PD_HW(sama5d2_pmc->chws[PMC_MAIN]); + parent_data[2] =3D AT91_CLK_PD_HW(sama5d2_pmc->chws[PMC_PLLACK]); + parent_data[3] =3D AT91_CLK_PD_HW(sama5d2_pmc->chws[PMC_UTMI]); + parent_data[4] =3D AT91_CLK_PD_HW(sama5d2_pmc->chws[PMC_MCK]); + parent_data[5] =3D AT91_CLK_PD_HW(sama5d2_pmc->chws[PMC_AUDIOPLLCK]); for (i =3D 0; i < ARRAY_SIZE(sama5d2_gck); i++) { hw =3D at91_clk_register_generated(regmap, &pmc_pcr_lock, &sama5d2_pcr_layout, sama5d2_gck[i].n, - parent_names, NULL, NULL, 6, + NULL, parent_data, NULL, 6, sama5d2_gck[i].id, &sama5d2_gck[i].r, sama5d2_gck[i].chg_pid); @@ -369,19 +373,19 @@ static void __init sama5d2_pmc_setup(struct device_no= de *np) } =20 if (regmap_sfr) { - parent_names[0] =3D "i2s0_clk"; - parent_names[1] =3D "i2s0_gclk"; + parent_data[0] =3D AT91_CLK_PD_HW(sama5d2_pmc->phws[54]); /* i2s0_clk */ + parent_data[1] =3D AT91_CLK_PD_HW(sama5d2_pmc->ghws[54]); /* i2s0_gclk */ hw =3D at91_clk_i2s_mux_register(regmap_sfr, "i2s0_muxclk", - parent_names, NULL, 2, 0); + NULL, parent_data, 2, 0); if (IS_ERR(hw)) goto err_free; =20 sama5d2_pmc->chws[PMC_I2S0_MUX] =3D hw; =20 - parent_names[0] =3D "i2s1_clk"; - parent_names[1] =3D "i2s1_gclk"; + parent_data[0] =3D AT91_CLK_PD_HW(sama5d2_pmc->phws[55]); /* i2s1_clk */ + parent_data[1] =3D AT91_CLK_PD_HW(sama5d2_pmc->ghws[55]); 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Thu, 10 Jul 2025 13:07:33 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Thu, 10 Jul 2025 13:07:33 -0700 From: To: , , , , CC: , , , , Subject: [PATCH v3 24/32] clk: at91: sama5d3: switch to parent_hw and parent_data Date: Thu, 10 Jul 2025 13:07:17 -0700 Message-ID: <8b9b4447d93f048bc95ab083c9fbe1d5ccd8acd1.1752176711.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Switch SAMA5D3 clocks to use parent_hw and parent_data. Having parent_hw instead of parent names improves to clock registration speed and re-parenting. Signed-off-by: Claudiu Beznea Signed-off-by: Ryan Wanner --- drivers/clk/at91/sama5d3.c | 122 +++++++++++++++++++------------------ 1 file changed, 63 insertions(+), 59 deletions(-) diff --git a/drivers/clk/at91/sama5d3.c b/drivers/clk/at91/sama5d3.c index 8326bb6a291c..e5b061783b09 100644 --- a/drivers/clk/at91/sama5d3.c +++ b/drivers/clk/at91/sama5d3.c @@ -37,9 +37,9 @@ static const struct clk_pcr_layout sama5d3_pcr_layout =3D= { .div_mask =3D GENMASK(17, 16), }; =20 -static const struct { +static struct { char *n; - char *p; + struct clk_hw *parent_hw; unsigned long flags; u8 id; } sama5d3_systemck[] =3D { @@ -47,14 +47,14 @@ static const struct { * ddrck feeds DDR controller and is enabled by bootloader thus we need * to keep it enabled in case there is no Linux consumer for it. */ - { .n =3D "ddrck", .p =3D "masterck_div", .id =3D 2, .flags =3D CLK_IS_CRI= TICAL }, - { .n =3D "lcdck", .p =3D "masterck_div", .id =3D 3 }, - { .n =3D "smdck", .p =3D "smdclk", .id =3D 4 }, - { .n =3D "uhpck", .p =3D "usbck", .id =3D 6 }, - { .n =3D "udpck", .p =3D "usbck", .id =3D 7 }, - { .n =3D "pck0", .p =3D "prog0", .id =3D 8 }, - { .n =3D "pck1", .p =3D "prog1", .id =3D 9 }, - { .n =3D "pck2", .p =3D "prog2", .id =3D 10 }, + { .n =3D "ddrck", .id =3D 2, .flags =3D CLK_IS_CRITICAL }, + { .n =3D "lcdck", .id =3D 3 }, + { .n =3D "smdck", .id =3D 4 }, + { .n =3D "uhpck", .id =3D 6 }, + { .n =3D "udpck", .id =3D 7 }, + { .n =3D "pck0", .id =3D 8 }, + { .n =3D "pck1", .id =3D 9 }, + { .n =3D "pck2", .id =3D 10 }, }; =20 static const struct { @@ -114,24 +114,15 @@ static const struct { =20 static void __init sama5d3_pmc_setup(struct device_node *np) { - const char *slck_name, *mainxtal_name; + const char *slow_clk_name =3D "slowck", *main_xtal_name =3D "main_xtal"; + struct clk_hw *main_rc_hw, *main_osc_hw, *mainck_hw; + u8 slow_clk_index =3D 0, main_xtal_index =3D 1; + struct clk_hw *smdck_hw, *usbck_hw, *hw; + struct clk_parent_data parent_data[5]; struct pmc_data *sama5d3_pmc; - const char *parent_names[5]; struct regmap *regmap; - struct clk_hw *hw; - int i; bool bypass; - - i =3D of_property_match_string(np, "clock-names", "slow_clk"); - if (i < 0) - return; - - slck_name =3D of_clk_get_parent_name(np, i); - - i =3D of_property_match_string(np, "clock-names", "main_xtal"); - if (i < 0) - return; - mainxtal_name =3D of_clk_get_parent_name(np, i); + int i; =20 regmap =3D device_node_to_regmap(np); if (IS_ERR(regmap)) @@ -143,54 +134,55 @@ static void __init sama5d3_pmc_setup(struct device_no= de *np) if (!sama5d3_pmc) return; =20 - hw =3D at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000, - 50000000); - if (IS_ERR(hw)) + main_rc_hw =3D at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000= 000, + 50000000); + if (IS_ERR(main_rc_hw)) goto err_free; =20 bypass =3D of_property_read_bool(np, "atmel,osc-bypass"); =20 - hw =3D at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL, - bypass); - if (IS_ERR(hw)) + main_osc_hw =3D at91_clk_register_main_osc(regmap, "main_osc", NULL, + &AT91_CLK_PD_NAME(main_xtal_name, main_xtal_index), + bypass); + if (IS_ERR(main_osc_hw)) goto err_free; =20 - parent_names[0] =3D "main_rc_osc"; - parent_names[1] =3D "main_osc"; - hw =3D at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL= , 2); - if (IS_ERR(hw)) + parent_data[0] =3D AT91_CLK_PD_HW(main_rc_hw); + parent_data[1] =3D AT91_CLK_PD_HW(main_osc_hw); + mainck_hw =3D at91_clk_register_sam9x5_main(regmap, "mainck", NULL, paren= t_data, 2); + if (IS_ERR(mainck_hw)) goto err_free; =20 - hw =3D at91_clk_register_pll(regmap, "pllack", "mainck", NULL, 0, + hw =3D at91_clk_register_pll(regmap, "pllack", NULL, &AT91_CLK_PD_HW(main= ck_hw), 0, &sama5d3_pll_layout, &plla_characteristics); if (IS_ERR(hw)) goto err_free; =20 - hw =3D at91_clk_register_plldiv(regmap, "plladivck", "pllack", NULL); + hw =3D at91_clk_register_plldiv(regmap, "plladivck", NULL, &AT91_CLK_PD_H= W(hw)); if (IS_ERR(hw)) goto err_free; =20 sama5d3_pmc->chws[PMC_PLLACK] =3D hw; =20 - hw =3D at91_clk_register_utmi(regmap, NULL, "utmick", "mainck", NULL); + hw =3D at91_clk_register_utmi(regmap, NULL, "utmick", NULL, &AT91_CLK_PD_= HW(mainck_hw)); if (IS_ERR(hw)) goto err_free; =20 sama5d3_pmc->chws[PMC_UTMI] =3D hw; =20 - parent_names[0] =3D slck_name; - parent_names[1] =3D "mainck"; - parent_names[2] =3D "plladivck"; - parent_names[3] =3D "utmick"; + parent_data[0] =3D AT91_CLK_PD_NAME(slow_clk_name, slow_clk_index); + parent_data[1] =3D AT91_CLK_PD_HW(mainck_hw); + parent_data[2] =3D AT91_CLK_PD_HW(sama5d3_pmc->chws[PMC_PLLACK]); + parent_data[3] =3D AT91_CLK_PD_HW(sama5d3_pmc->chws[PMC_UTMI]); hw =3D at91_clk_register_master_pres(regmap, "masterck_pres", 4, - parent_names, NULL, + NULL, parent_data, &at91sam9x5_master_layout, &mck_characteristics, &mck_lock); if (IS_ERR(hw)) goto err_free; =20 hw =3D at91_clk_register_master_div(regmap, "masterck_div", - "masterck_pres", NULL, + NULL, &AT91_CLK_PD_HW(hw), &at91sam9x5_master_layout, &mck_characteristics, &mck_lock, CLK_SET_RATE_GATE, 0); @@ -199,28 +191,30 @@ static void __init sama5d3_pmc_setup(struct device_no= de *np) =20 sama5d3_pmc->chws[PMC_MCK] =3D hw; =20 - parent_names[0] =3D "plladivck"; - parent_names[1] =3D "utmick"; - hw =3D at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, NULL, 2= ); - if (IS_ERR(hw)) + parent_data[0] =3D AT91_CLK_PD_HW(sama5d3_pmc->chws[PMC_PLLACK]); + parent_data[1] =3D AT91_CLK_PD_HW(sama5d3_pmc->chws[PMC_UTMI]); + usbck_hw =3D at91sam9x5_clk_register_usb(regmap, "usbck", NULL, parent_da= ta, 2); + if (IS_ERR(usbck_hw)) goto err_free; =20 - hw =3D at91sam9x5_clk_register_smd(regmap, "smdclk", parent_names, NULL, = 2); - if (IS_ERR(hw)) + parent_data[0] =3D AT91_CLK_PD_HW(sama5d3_pmc->chws[PMC_PLLACK]); + parent_data[1] =3D AT91_CLK_PD_HW(sama5d3_pmc->chws[PMC_UTMI]); + smdck_hw =3D at91sam9x5_clk_register_smd(regmap, "smdclk", NULL, parent_d= ata, 2); + if (IS_ERR(smdck_hw)) goto err_free; =20 - parent_names[0] =3D slck_name; - parent_names[1] =3D "mainck"; - parent_names[2] =3D "plladivck"; - parent_names[3] =3D "utmick"; - parent_names[4] =3D "masterck_div"; + parent_data[0] =3D AT91_CLK_PD_NAME(slow_clk_name, slow_clk_index); + parent_data[1] =3D AT91_CLK_PD_HW(mainck_hw); + parent_data[2] =3D AT91_CLK_PD_HW(sama5d3_pmc->chws[PMC_PLLACK]); + parent_data[3] =3D AT91_CLK_PD_HW(sama5d3_pmc->chws[PMC_UTMI]); + parent_data[4] =3D AT91_CLK_PD_HW(sama5d3_pmc->chws[PMC_MCK]); for (i =3D 0; i < 3; i++) { char name[6]; =20 snprintf(name, sizeof(name), "prog%d", i); =20 hw =3D at91_clk_register_programmable(regmap, name, - parent_names, NULL, 5, i, + NULL, parent_data, 5, i, &at91sam9x5_programmable_layout, NULL); if (IS_ERR(hw)) @@ -229,9 +223,18 @@ static void __init sama5d3_pmc_setup(struct device_nod= e *np) sama5d3_pmc->pchws[i] =3D hw; } =20 + /* Set systemck parent hws. */ + sama5d3_systemck[0].parent_hw =3D sama5d3_pmc->chws[PMC_MCK]; + sama5d3_systemck[1].parent_hw =3D sama5d3_pmc->chws[PMC_MCK]; + sama5d3_systemck[2].parent_hw =3D smdck_hw; + sama5d3_systemck[3].parent_hw =3D usbck_hw; + sama5d3_systemck[4].parent_hw =3D usbck_hw; + sama5d3_systemck[5].parent_hw =3D sama5d3_pmc->pchws[0]; + sama5d3_systemck[6].parent_hw =3D sama5d3_pmc->pchws[1]; + sama5d3_systemck[7].parent_hw =3D sama5d3_pmc->pchws[2]; for (i =3D 0; i < ARRAY_SIZE(sama5d3_systemck); i++) { - hw =3D at91_clk_register_system(regmap, sama5d3_systemck[i].n, - sama5d3_systemck[i].p, NULL, + hw =3D at91_clk_register_system(regmap, sama5d3_systemck[i].n, NULL, + &AT91_CLK_PD_HW(sama5d3_systemck[i].parent_hw), sama5d3_systemck[i].id, sama5d3_systemck[i].flags); if (IS_ERR(hw)) @@ -244,7 +247,8 @@ static void __init sama5d3_pmc_setup(struct device_node= *np) hw =3D at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, &sama5d3_pcr_layout, sama5d3_periphck[i].n, - "masterck_div", NULL, + NULL, + &AT91_CLK_PD_HW(sama5d3_pmc->chws[PMC_MCK]), sama5d3_periphck[i].id, &sama5d3_periphck[i].r, INT_MIN, --=20 2.43.0 From nobody Tue Oct 7 09:53:13 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5F40F2FEE2D; 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charset="utf-8" From: Claudiu Beznea Switch SAMA5D4 clocks to use parent_hw and parent_data. Having parent_hw instead of parent names improves to clock registration speed and re-parenting. Signed-off-by: Claudiu Beznea Signed-off-by: Ryan Wanner --- drivers/clk/at91/sama5d4.c | 129 +++++++++++++++++++------------------ 1 file changed, 66 insertions(+), 63 deletions(-) diff --git a/drivers/clk/at91/sama5d4.c b/drivers/clk/at91/sama5d4.c index 1ff9286148da..a06fea1a7a02 100644 --- a/drivers/clk/at91/sama5d4.c +++ b/drivers/clk/at91/sama5d4.c @@ -36,9 +36,9 @@ static const struct clk_pcr_layout sama5d4_pcr_layout =3D= { .pid_mask =3D GENMASK(6, 0), }; =20 -static const struct { +static struct { char *n; - char *p; + struct clk_hw *parent_hw; unsigned long flags; u8 id; } sama5d4_systemck[] =3D { @@ -46,14 +46,14 @@ static const struct { * ddrck feeds DDR controller and is enabled by bootloader thus we need * to keep it enabled in case there is no Linux consumer for it. */ - { .n =3D "ddrck", .p =3D "masterck_div", .id =3D 2, .flags =3D CLK_IS_CRI= TICAL }, - { .n =3D "lcdck", .p =3D "masterck_div", .id =3D 3 }, - { .n =3D "smdck", .p =3D "smdclk", .id =3D 4 }, - { .n =3D "uhpck", .p =3D "usbck", .id =3D 6 }, - { .n =3D "udpck", .p =3D "usbck", .id =3D 7 }, - { .n =3D "pck0", .p =3D "prog0", .id =3D 8 }, - { .n =3D "pck1", .p =3D "prog1", .id =3D 9 }, - { .n =3D "pck2", .p =3D "prog2", .id =3D 10 }, + { .n =3D "ddrck", .id =3D 2, .flags =3D CLK_IS_CRITICAL }, + { .n =3D "lcdck", .id =3D 3 }, + { .n =3D "smdck", .id =3D 4 }, + { .n =3D "uhpck", .id =3D 6 }, + { .n =3D "udpck", .id =3D 7 }, + { .n =3D "pck0", .id =3D 8 }, + { .n =3D "pck1", .id =3D 9 }, + { .n =3D "pck2", .id =3D 10 }, }; =20 static const struct { @@ -128,25 +128,16 @@ static const struct { =20 static void __init sama5d4_pmc_setup(struct device_node *np) { + const char *slow_clk_name =3D "slowck", *main_xtal_name =3D "main_xtal"; + struct clk_hw *main_rc_hw, *main_osc_hw, *mainck_hw; + u8 slow_clk_index =3D 0, main_xtal_index =3D 1; + struct clk_hw *smdck_hw, *usbck_hw, *hw; struct clk_range range =3D CLK_RANGE(0, 0); - const char *slck_name, *mainxtal_name; + struct clk_parent_data parent_data[5]; struct pmc_data *sama5d4_pmc; - const char *parent_names[5]; struct regmap *regmap; - struct clk_hw *hw; - int i; bool bypass; - - i =3D of_property_match_string(np, "clock-names", "slow_clk"); - if (i < 0) - return; - - slck_name =3D of_clk_get_parent_name(np, i); - - i =3D of_property_match_string(np, "clock-names", "main_xtal"); - if (i < 0) - return; - mainxtal_name =3D of_clk_get_parent_name(np, i); + int i; =20 regmap =3D device_node_to_regmap(np); if (IS_ERR(regmap)) @@ -158,54 +149,54 @@ static void __init sama5d4_pmc_setup(struct device_no= de *np) if (!sama5d4_pmc) return; =20 - hw =3D at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000, - 100000000); - if (IS_ERR(hw)) + main_rc_hw =3D at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000= 000, + 100000000); + if (IS_ERR(main_rc_hw)) goto err_free; =20 bypass =3D of_property_read_bool(np, "atmel,osc-bypass"); =20 - hw =3D at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL, - bypass); - if (IS_ERR(hw)) + main_osc_hw =3D at91_clk_register_main_osc(regmap, "main_osc", NULL, + &AT91_CLK_PD_NAME(main_xtal_name, main_xtal_index), + bypass); + if (IS_ERR(main_osc_hw)) goto err_free; =20 - parent_names[0] =3D "main_rc_osc"; - parent_names[1] =3D "main_osc"; - hw =3D at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL= , 2); + parent_data[0] =3D AT91_CLK_PD_HW(main_rc_hw); + parent_data[1] =3D AT91_CLK_PD_HW(main_osc_hw); + mainck_hw =3D at91_clk_register_sam9x5_main(regmap, "mainck", NULL, paren= t_data, 2); if (IS_ERR(hw)) goto err_free; =20 - hw =3D at91_clk_register_pll(regmap, "pllack", "mainck", NULL, 0, + hw =3D at91_clk_register_pll(regmap, "pllack", NULL, &AT91_CLK_PD_HW(main= ck_hw), 0, &sama5d3_pll_layout, &plla_characteristics); if (IS_ERR(hw)) goto err_free; =20 - hw =3D at91_clk_register_plldiv(regmap, "plladivck", "pllack", NULL); + hw =3D at91_clk_register_plldiv(regmap, "plladivck", NULL, &AT91_CLK_PD_H= W(hw)); if (IS_ERR(hw)) goto err_free; =20 sama5d4_pmc->chws[PMC_PLLACK] =3D hw; =20 - hw =3D at91_clk_register_utmi(regmap, NULL, "utmick", "mainck", NULL); + hw =3D at91_clk_register_utmi(regmap, NULL, "utmick", NULL, &AT91_CLK_PD_= HW(mainck_hw)); if (IS_ERR(hw)) goto err_free; =20 sama5d4_pmc->chws[PMC_UTMI] =3D hw; =20 - parent_names[0] =3D slck_name; - parent_names[1] =3D "mainck"; - parent_names[2] =3D "plladivck"; - parent_names[3] =3D "utmick"; + parent_data[0] =3D AT91_CLK_PD_NAME(slow_clk_name, slow_clk_index); + parent_data[1] =3D AT91_CLK_PD_HW(mainck_hw); + parent_data[2] =3D AT91_CLK_PD_HW(sama5d4_pmc->chws[PMC_PLLACK]); + parent_data[3] =3D AT91_CLK_PD_HW(sama5d4_pmc->chws[PMC_UTMI]); hw =3D at91_clk_register_master_pres(regmap, "masterck_pres", 4, - parent_names, NULL, + NULL, parent_data, &at91sam9x5_master_layout, &mck_characteristics, &mck_lock); if (IS_ERR(hw)) goto err_free; =20 - hw =3D at91_clk_register_master_div(regmap, "masterck_div", - "masterck_pres", NULL, + hw =3D at91_clk_register_master_div(regmap, "masterck_div", NULL, &AT91_C= LK_PD_HW(hw), &at91sam9x5_master_layout, &mck_characteristics, &mck_lock, CLK_SET_RATE_GATE, 0); @@ -214,36 +205,37 @@ static void __init sama5d4_pmc_setup(struct device_no= de *np) =20 sama5d4_pmc->chws[PMC_MCK] =3D hw; =20 - hw =3D at91_clk_register_h32mx(regmap, "h32mxck", "masterck_div", NULL); + hw =3D at91_clk_register_h32mx(regmap, "h32mxck", NULL, + &AT91_CLK_PD_HW(sama5d4_pmc->chws[PMC_MCK])); if (IS_ERR(hw)) goto err_free; =20 sama5d4_pmc->chws[PMC_MCK2] =3D hw; =20 - parent_names[0] =3D "plladivck"; - parent_names[1] =3D "utmick"; - hw =3D at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, NULL, 2= ); - if (IS_ERR(hw)) + parent_data[0] =3D AT91_CLK_PD_HW(sama5d4_pmc->chws[PMC_PLLACK]); + parent_data[1] =3D AT91_CLK_PD_HW(sama5d4_pmc->chws[PMC_UTMI]); + usbck_hw =3D at91sam9x5_clk_register_usb(regmap, "usbck", NULL, parent_da= ta, 2); + if (IS_ERR(usbck_hw)) goto err_free; =20 - parent_names[0] =3D "plladivck"; - parent_names[1] =3D "utmick"; - hw =3D at91sam9x5_clk_register_smd(regmap, "smdclk", parent_names, NULL, = 2); - if (IS_ERR(hw)) + parent_data[0] =3D AT91_CLK_PD_HW(sama5d4_pmc->chws[PMC_PLLACK]); + parent_data[1] =3D AT91_CLK_PD_HW(sama5d4_pmc->chws[PMC_UTMI]); + smdck_hw =3D at91sam9x5_clk_register_smd(regmap, "smdclk", NULL, parent_d= ata, 2); + if (IS_ERR(smdck_hw)) goto err_free; =20 - parent_names[0] =3D slck_name; - parent_names[1] =3D "mainck"; - parent_names[2] =3D "plladivck"; - parent_names[3] =3D "utmick"; - parent_names[4] =3D "masterck_div"; + parent_data[0] =3D AT91_CLK_PD_NAME(slow_clk_name, slow_clk_index); + parent_data[1] =3D AT91_CLK_PD_HW(mainck_hw); + parent_data[2] =3D AT91_CLK_PD_HW(sama5d4_pmc->chws[PMC_PLLACK]); + parent_data[3] =3D AT91_CLK_PD_HW(sama5d4_pmc->chws[PMC_UTMI]); + parent_data[4] =3D AT91_CLK_PD_HW(sama5d4_pmc->chws[PMC_MCK]); for (i =3D 0; i < 3; i++) { char name[6]; =20 snprintf(name, sizeof(name), "prog%d", i); =20 hw =3D at91_clk_register_programmable(regmap, name, - parent_names, NULL, 5, i, + NULL, parent_data, 5, i, &at91sam9x5_programmable_layout, NULL); if (IS_ERR(hw)) @@ -252,9 +244,18 @@ static void __init sama5d4_pmc_setup(struct device_nod= e *np) sama5d4_pmc->pchws[i] =3D hw; } =20 + /* Set systemck parent hws. */ + sama5d4_systemck[0].parent_hw =3D sama5d4_pmc->chws[PMC_MCK]; + sama5d4_systemck[1].parent_hw =3D sama5d4_pmc->chws[PMC_MCK]; + sama5d4_systemck[2].parent_hw =3D smdck_hw; + sama5d4_systemck[3].parent_hw =3D usbck_hw; + sama5d4_systemck[4].parent_hw =3D usbck_hw; + sama5d4_systemck[5].parent_hw =3D sama5d4_pmc->pchws[0]; + sama5d4_systemck[6].parent_hw =3D sama5d4_pmc->pchws[1]; + sama5d4_systemck[7].parent_hw =3D sama5d4_pmc->pchws[2]; for (i =3D 0; i < ARRAY_SIZE(sama5d4_systemck); i++) { - hw =3D at91_clk_register_system(regmap, sama5d4_systemck[i].n, - sama5d4_systemck[i].p, NULL, + hw =3D at91_clk_register_system(regmap, sama5d4_systemck[i].n, NULL, + &AT91_CLK_PD_HW(sama5d4_systemck[i].parent_hw), sama5d4_systemck[i].id, sama5d4_systemck[i].flags); if (IS_ERR(hw)) @@ -267,7 +268,8 @@ static void __init sama5d4_pmc_setup(struct device_node= *np) hw =3D at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, &sama5d4_pcr_layout, sama5d4_periphck[i].n, - "masterck_div", NULL, + NULL, + &AT91_CLK_PD_HW(sama5d4_pmc->chws[PMC_MCK]), sama5d4_periphck[i].id, &range, INT_MIN, sama5d4_periphck[i].flags); @@ -281,7 +283,8 @@ static void __init sama5d4_pmc_setup(struct device_node= *np) hw =3D at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, &sama5d4_pcr_layout, sama5d4_periph32ck[i].n, - "h32mxck", NULL, + NULL, + &AT91_CLK_PD_HW(sama5d4_pmc->chws[PMC_MCK2]), sama5d4_periph32ck[i].id, &range, INT_MIN, 0); if (IS_ERR(hw)) --=20 2.43.0 From nobody Tue Oct 7 09:53:13 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 299FD2FF463; Thu, 10 Jul 2025 20:07:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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d="scan'208";a="275215684" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 10 Jul 2025 13:07:40 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Thu, 10 Jul 2025 13:07:34 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Thu, 10 Jul 2025 13:07:34 -0700 From: To: , , , , CC: , , , , Subject: [PATCH v3 26/32] clk: at91: at91sam9x5: switch to parent_hw and parent_data Date: Thu, 10 Jul 2025 13:07:19 -0700 Message-ID: <95cbe3653752bc3c0b6f068949706313e3778fe5.1752176711.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Switch AT91SAM9X5 clocks to use parent_hw and parent_data. Having parent_hw instead of parent names improves to clock registration speed and re-parenting. Signed-off-by: Claudiu Beznea Signed-off-by: Ryan Wanner --- drivers/clk/at91/at91sam9x5.c | 125 ++++++++++++++++++---------------- 1 file changed, 65 insertions(+), 60 deletions(-) diff --git a/drivers/clk/at91/at91sam9x5.c b/drivers/clk/at91/at91sam9x5.c index 13331e015dd7..f6138622ab50 100644 --- a/drivers/clk/at91/at91sam9x5.c +++ b/drivers/clk/at91/at91sam9x5.c @@ -38,9 +38,9 @@ static const struct clk_pll_characteristics plla_characte= ristics =3D { .out =3D plla_out, }; =20 -static const struct { +static struct { char *n; - char *p; + struct clk_hw *parent_hw; unsigned long flags; u8 id; } at91sam9x5_systemck[] =3D { @@ -48,12 +48,12 @@ static const struct { * ddrck feeds DDR controller and is enabled by bootloader thus we need * to keep it enabled in case there is no Linux consumer for it. */ - { .n =3D "ddrck", .p =3D "masterck_div", .id =3D 2, .flags =3D CLK_IS_CRI= TICAL }, - { .n =3D "smdck", .p =3D "smdclk", .id =3D 4 }, - { .n =3D "uhpck", .p =3D "usbck", .id =3D 6 }, - { .n =3D "udpck", .p =3D "usbck", .id =3D 7 }, - { .n =3D "pck0", .p =3D "prog0", .id =3D 8 }, - { .n =3D "pck1", .p =3D "prog1", .id =3D 9 }, + { .n =3D "ddrck", .id =3D 2, .flags =3D CLK_IS_CRITICAL }, + { .n =3D "smdck", .id =3D 4 }, + { .n =3D "uhpck", .id =3D 6 }, + { .n =3D "udpck", .id =3D 7 }, + { .n =3D "pck0", .id =3D 8 }, + { .n =3D "pck1", .id =3D 9 }, }; =20 static const struct clk_pcr_layout at91sam9x5_pcr_layout =3D { @@ -133,25 +133,16 @@ static void __init at91sam9x5_pmc_setup(struct device= _node *np, const struct pck *extra_pcks, bool has_lcdck) { + const char *slow_clk_name =3D "slowck", *main_xtal_name =3D "main_xtal"; + struct clk_hw *main_rc_hw, *main_osc_hw, *hw; + u8 slow_clk_index =3D 0, main_xtal_index =3D 0; struct clk_range range =3D CLK_RANGE(0, 0); - const char *slck_name, *mainxtal_name; + struct clk_parent_data parent_data[6]; + struct clk_hw *smdck_hw, *usbck_hw; struct pmc_data *at91sam9x5_pmc; - const char *parent_names[6]; struct regmap *regmap; - struct clk_hw *hw; - int i; bool bypass; - - i =3D of_property_match_string(np, "clock-names", "slow_clk"); - if (i < 0) - return; - - slck_name =3D of_clk_get_parent_name(np, i); - - i =3D of_property_match_string(np, "clock-names", "main_xtal"); - if (i < 0) - return; - mainxtal_name =3D of_clk_get_parent_name(np, i); + int i; =20 regmap =3D device_node_to_regmap(np); if (IS_ERR(regmap)) @@ -162,56 +153,59 @@ static void __init at91sam9x5_pmc_setup(struct device= _node *np, if (!at91sam9x5_pmc) return; =20 - hw =3D at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000, - 50000000); - if (IS_ERR(hw)) + main_rc_hw =3D at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000= 000, + 50000000); + if (IS_ERR(main_rc_hw)) goto err_free; =20 bypass =3D of_property_read_bool(np, "atmel,osc-bypass"); =20 - hw =3D at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL, - bypass); - if (IS_ERR(hw)) + main_osc_hw =3D at91_clk_register_main_osc(regmap, "main_osc", NULL, + &AT91_CLK_PD_NAME(main_xtal_name, main_xtal_index), + bypass); + if (IS_ERR(main_osc_hw)) goto err_free; =20 - parent_names[0] =3D "main_rc_osc"; - parent_names[1] =3D "main_osc"; - hw =3D at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL= , 2); + parent_data[0] =3D AT91_CLK_PD_HW(main_rc_hw); + parent_data[1] =3D AT91_CLK_PD_HW(main_osc_hw); + hw =3D at91_clk_register_sam9x5_main(regmap, "mainck", NULL, parent_data,= 2); if (IS_ERR(hw)) goto err_free; =20 at91sam9x5_pmc->chws[PMC_MAIN] =3D hw; =20 - hw =3D at91_clk_register_pll(regmap, "pllack", "mainck", NULL, 0, + hw =3D at91_clk_register_pll(regmap, "pllack", NULL, + &AT91_CLK_PD_HW(at91sam9x5_pmc->chws[PMC_MAIN]), 0, &at91rm9200_pll_layout, &plla_characteristics); if (IS_ERR(hw)) goto err_free; =20 - hw =3D at91_clk_register_plldiv(regmap, "plladivck", "pllack", NULL); + hw =3D at91_clk_register_plldiv(regmap, "plladivck", NULL, &AT91_CLK_PD_H= W(hw)); if (IS_ERR(hw)) goto err_free; =20 at91sam9x5_pmc->chws[PMC_PLLACK] =3D hw; =20 - hw =3D at91_clk_register_utmi(regmap, NULL, "utmick", "mainck", NULL); + hw =3D at91_clk_register_utmi(regmap, NULL, "utmick", NULL, + &AT91_CLK_PD_HW(at91sam9x5_pmc->chws[PMC_MAIN])); if (IS_ERR(hw)) goto err_free; =20 at91sam9x5_pmc->chws[PMC_UTMI] =3D hw; =20 - parent_names[0] =3D slck_name; - parent_names[1] =3D "mainck"; - parent_names[2] =3D "plladivck"; - parent_names[3] =3D "utmick"; + parent_data[0] =3D AT91_CLK_PD_NAME(slow_clk_name, slow_clk_index); + parent_data[1] =3D AT91_CLK_PD_HW(at91sam9x5_pmc->chws[PMC_MAIN]); + parent_data[2] =3D AT91_CLK_PD_HW(at91sam9x5_pmc->chws[PMC_PLLACK]); + parent_data[3] =3D AT91_CLK_PD_HW(at91sam9x5_pmc->chws[PMC_UTMI]); hw =3D at91_clk_register_master_pres(regmap, "masterck_pres", 4, - parent_names, NULL, + NULL, parent_data, &at91sam9x5_master_layout, &mck_characteristics, &mck_lock); if (IS_ERR(hw)) goto err_free; =20 - hw =3D at91_clk_register_master_div(regmap, "masterck_div", - "masterck_pres", NULL, + hw =3D at91_clk_register_master_div(regmap, "masterck_div", NULL, + &AT91_CLK_PD_HW(hw), &at91sam9x5_master_layout, &mck_characteristics, &mck_lock, CLK_SET_RATE_GATE, 0); @@ -220,28 +214,30 @@ static void __init at91sam9x5_pmc_setup(struct device= _node *np, =20 at91sam9x5_pmc->chws[PMC_MCK] =3D hw; =20 - parent_names[0] =3D "plladivck"; - parent_names[1] =3D "utmick"; - hw =3D at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, NULL, 2= ); - if (IS_ERR(hw)) + parent_data[0] =3D AT91_CLK_PD_HW(at91sam9x5_pmc->chws[PMC_PLLACK]); + parent_data[1] =3D AT91_CLK_PD_HW(at91sam9x5_pmc->chws[PMC_UTMI]); + usbck_hw =3D at91sam9x5_clk_register_usb(regmap, "usbck", NULL, parent_da= ta, 2); + if (IS_ERR(usbck_hw)) goto err_free; =20 - hw =3D at91sam9x5_clk_register_smd(regmap, "smdclk", parent_names, NULL, = 2); - if (IS_ERR(hw)) + parent_data[0] =3D AT91_CLK_PD_HW(at91sam9x5_pmc->chws[PMC_PLLACK]); + parent_data[1] =3D AT91_CLK_PD_HW(at91sam9x5_pmc->chws[PMC_UTMI]); + smdck_hw =3D at91sam9x5_clk_register_smd(regmap, "smdclk", NULL, parent_d= ata, 2); + if (IS_ERR(smdck_hw)) goto err_free; =20 - parent_names[0] =3D slck_name; - parent_names[1] =3D "mainck"; - parent_names[2] =3D "plladivck"; - parent_names[3] =3D "utmick"; - parent_names[4] =3D "masterck_div"; + parent_data[0] =3D AT91_CLK_PD_NAME(slow_clk_name, slow_clk_index); + parent_data[1] =3D AT91_CLK_PD_HW(at91sam9x5_pmc->chws[PMC_MAIN]); + parent_data[2] =3D AT91_CLK_PD_HW(at91sam9x5_pmc->chws[PMC_PLLACK]); + parent_data[3] =3D AT91_CLK_PD_HW(at91sam9x5_pmc->chws[PMC_UTMI]); + parent_data[4] =3D AT91_CLK_PD_HW(at91sam9x5_pmc->chws[PMC_MCK]); for (i =3D 0; i < 2; i++) { char name[6]; =20 snprintf(name, sizeof(name), "prog%d", i); =20 hw =3D at91_clk_register_programmable(regmap, name, - parent_names, NULL, 5, i, + NULL, parent_data, 5, i, &at91sam9x5_programmable_layout, NULL); if (IS_ERR(hw)) @@ -250,9 +246,16 @@ static void __init at91sam9x5_pmc_setup(struct device_= node *np, at91sam9x5_pmc->pchws[i] =3D hw; } =20 + /* Set systemck parent hws. */ + at91sam9x5_systemck[0].parent_hw =3D at91sam9x5_pmc->chws[PMC_MCK]; + at91sam9x5_systemck[1].parent_hw =3D smdck_hw; + at91sam9x5_systemck[2].parent_hw =3D usbck_hw; + at91sam9x5_systemck[3].parent_hw =3D usbck_hw; + at91sam9x5_systemck[4].parent_hw =3D at91sam9x5_pmc->pchws[0]; + at91sam9x5_systemck[5].parent_hw =3D at91sam9x5_pmc->pchws[1]; for (i =3D 0; i < ARRAY_SIZE(at91sam9x5_systemck); i++) { - hw =3D at91_clk_register_system(regmap, at91sam9x5_systemck[i].n, - at91sam9x5_systemck[i].p, NULL, + hw =3D at91_clk_register_system(regmap, at91sam9x5_systemck[i].n, NULL, + &AT91_CLK_PD_HW(at91sam9x5_systemck[i].parent_hw), at91sam9x5_systemck[i].id, at91sam9x5_systemck[i].flags); if (IS_ERR(hw)) @@ -262,8 +265,8 @@ static void __init at91sam9x5_pmc_setup(struct device_n= ode *np, } =20 if (has_lcdck) { - hw =3D at91_clk_register_system(regmap, "lcdck", "masterck_div", - NULL, 3, 0); + hw =3D at91_clk_register_system(regmap, "lcdck", NULL, + &AT91_CLK_PD_HW(at91sam9x5_pmc->chws[PMC_MCK]), 3, 0); if (IS_ERR(hw)) goto err_free; =20 @@ -274,7 +277,8 @@ static void __init at91sam9x5_pmc_setup(struct device_n= ode *np, hw =3D at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, &at91sam9x5_pcr_layout, at91sam9x5_periphck[i].n, - "masterck_div", NULL, + NULL, + &AT91_CLK_PD_HW(at91sam9x5_pmc->chws[PMC_MCK]), at91sam9x5_periphck[i].id, &range, INT_MIN, 0); if (IS_ERR(hw)) @@ -287,7 +291,8 @@ static void __init at91sam9x5_pmc_setup(struct device_n= ode *np, hw =3D at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, &at91sam9x5_pcr_layout, extra_pcks[i].n, - "masterck_div", NULL, + NULL, + &AT91_CLK_PD_HW(at91sam9x5_pmc->chws[PMC_MCK]), extra_pcks[i].id, &range, INT_MIN, 0); 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charset="utf-8" From: Claudiu Beznea Switch AT91RM9200 clocks to use parent_hw and parent_data. Having parent_hw instead of parent names improves to clock registration speed and re-parenting. Signed-off-by: Claudiu Beznea Signed-off-by: Ryan Wanner --- drivers/clk/at91/at91rm9200.c | 95 ++++++++++++++++++----------------- 1 file changed, 49 insertions(+), 46 deletions(-) diff --git a/drivers/clk/at91/at91rm9200.c b/drivers/clk/at91/at91rm9200.c index 623e232ec9c6..b834ca5ed092 100644 --- a/drivers/clk/at91/at91rm9200.c +++ b/drivers/clk/at91/at91rm9200.c @@ -11,7 +11,7 @@ static DEFINE_SPINLOCK(rm9200_mck_lock); =20 struct sck { char *n; - char *p; + struct clk_hw *parent_hw; u8 id; }; =20 @@ -39,13 +39,13 @@ static const struct clk_pll_characteristics rm9200_pll_= characteristics =3D { .out =3D rm9200_pll_out, }; =20 -static const struct sck at91rm9200_systemck[] =3D { - { .n =3D "udpck", .p =3D "usbck", .id =3D 1 }, - { .n =3D "uhpck", .p =3D "usbck", .id =3D 4 }, - { .n =3D "pck0", .p =3D "prog0", .id =3D 8 }, - { .n =3D "pck1", .p =3D "prog1", .id =3D 9 }, - { .n =3D "pck2", .p =3D "prog2", .id =3D 10 }, - { .n =3D "pck3", .p =3D "prog3", .id =3D 11 }, +static struct sck at91rm9200_systemck[] =3D { + { .n =3D "udpck", .id =3D 1 }, + { .n =3D "uhpck", .id =3D 4 }, + { .n =3D "pck0", .id =3D 8 }, + { .n =3D "pck1", .id =3D 9 }, + { .n =3D "pck2", .id =3D 10 }, + { .n =3D "pck3", .id =3D 11 }, }; =20 static const struct pck at91rm9200_periphck[] =3D { @@ -76,25 +76,15 @@ static const struct pck at91rm9200_periphck[] =3D { =20 static void __init at91rm9200_pmc_setup(struct device_node *np) { - const char *slowxtal_name, *mainxtal_name; + const char *slow_clk_name =3D "slowck", *main_xtal_name =3D "main_xtal"; + struct clk_hw *usbck_hw, *main_osc_hw, *hw; + u8 slow_clk_index =3D 0, main_xtal_index =3D 1; + struct clk_parent_data parent_data[6]; struct pmc_data *at91rm9200_pmc; u32 usb_div[] =3D { 1, 2, 0, 0 }; - const char *parent_names[6]; struct regmap *regmap; - struct clk_hw *hw; - int i; bool bypass; - - i =3D of_property_match_string(np, "clock-names", "slow_xtal"); - if (i < 0) - return; - - slowxtal_name =3D of_clk_get_parent_name(np, i); - - i =3D of_property_match_string(np, "clock-names", "main_xtal"); - if (i < 0) - return; - mainxtal_name =3D of_clk_get_parent_name(np, i); + int i; =20 regmap =3D device_node_to_regmap(np); if (IS_ERR(regmap)) @@ -108,18 +98,21 @@ static void __init at91rm9200_pmc_setup(struct device_= node *np) =20 bypass =3D of_property_read_bool(np, "atmel,osc-bypass"); =20 - hw =3D at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL, - bypass); - if (IS_ERR(hw)) + main_osc_hw =3D at91_clk_register_main_osc(regmap, "main_osc", NULL, + &AT91_CLK_PD_NAME(main_xtal_name, main_xtal_index), + bypass); + if (IS_ERR(main_osc_hw)) goto err_free; =20 - hw =3D at91_clk_register_rm9200_main(regmap, "mainck", "main_osc", NULL); + hw =3D at91_clk_register_rm9200_main(regmap, "mainck", NULL, + &AT91_CLK_PD_HW(main_osc_hw)); if (IS_ERR(hw)) goto err_free; =20 at91rm9200_pmc->chws[PMC_MAIN] =3D hw; =20 - hw =3D at91_clk_register_pll(regmap, "pllack", "mainck", NULL, 0, + hw =3D at91_clk_register_pll(regmap, "pllack", NULL, + &AT91_CLK_PD_HW(at91rm9200_pmc->chws[PMC_MAIN]), 0, &at91rm9200_pll_layout, &rm9200_pll_characteristics); if (IS_ERR(hw)) @@ -127,7 +120,8 @@ static void __init at91rm9200_pmc_setup(struct device_n= ode *np) =20 at91rm9200_pmc->chws[PMC_PLLACK] =3D hw; =20 - hw =3D at91_clk_register_pll(regmap, "pllbck", "mainck", NULL, 1, + hw =3D at91_clk_register_pll(regmap, "pllbck", NULL, + &AT91_CLK_PD_HW(at91rm9200_pmc->chws[PMC_MAIN]), 1, &at91rm9200_pll_layout, &rm9200_pll_characteristics); if (IS_ERR(hw)) @@ -135,20 +129,19 @@ static void __init at91rm9200_pmc_setup(struct device= _node *np) =20 at91rm9200_pmc->chws[PMC_PLLBCK] =3D hw; =20 - parent_names[0] =3D slowxtal_name; - parent_names[1] =3D "mainck"; - parent_names[2] =3D "pllack"; - parent_names[3] =3D "pllbck"; + parent_data[0] =3D AT91_CLK_PD_NAME(slow_clk_name, slow_clk_index); + parent_data[1] =3D AT91_CLK_PD_HW(at91rm9200_pmc->chws[PMC_MAIN]); + parent_data[2] =3D AT91_CLK_PD_HW(at91rm9200_pmc->chws[PMC_PLLACK]); + parent_data[3] =3D AT91_CLK_PD_HW(at91rm9200_pmc->chws[PMC_PLLBCK]); hw =3D at91_clk_register_master_pres(regmap, "masterck_pres", 4, - parent_names, NULL, + NULL, parent_data, &at91rm9200_master_layout, &rm9200_mck_characteristics, &rm9200_mck_lock); if (IS_ERR(hw)) goto err_free; =20 - hw =3D at91_clk_register_master_div(regmap, "masterck_div", - "masterck_pres", NULL, + hw =3D at91_clk_register_master_div(regmap, "masterck_div", NULL, &AT91_C= LK_PD_HW(hw), &at91rm9200_master_layout, &rm9200_mck_characteristics, &rm9200_mck_lock, CLK_SET_RATE_GATE, 0); @@ -157,21 +150,23 @@ static void __init at91rm9200_pmc_setup(struct device= _node *np) =20 at91rm9200_pmc->chws[PMC_MCK] =3D hw; =20 - hw =3D at91rm9200_clk_register_usb(regmap, "usbck", "pllbck", NULL, usb_d= iv); - if (IS_ERR(hw)) + usbck_hw =3D at91rm9200_clk_register_usb(regmap, "usbck", NULL, + &AT91_CLK_PD_HW(at91rm9200_pmc->chws[PMC_PLLBCK]), + usb_div); + if (IS_ERR(usbck_hw)) goto err_free; =20 - parent_names[0] =3D slowxtal_name; - parent_names[1] =3D "mainck"; - parent_names[2] =3D "pllack"; - parent_names[3] =3D "pllbck"; + parent_data[0] =3D AT91_CLK_PD_NAME(slow_clk_name, slow_clk_index); + parent_data[1] =3D AT91_CLK_PD_HW(at91rm9200_pmc->chws[PMC_MAIN]); + parent_data[2] =3D AT91_CLK_PD_HW(at91rm9200_pmc->chws[PMC_PLLACK]); + parent_data[3] =3D AT91_CLK_PD_HW(at91rm9200_pmc->chws[PMC_PLLBCK]); for (i =3D 0; i < 4; i++) { char name[6]; =20 snprintf(name, sizeof(name), "prog%d", i); =20 hw =3D at91_clk_register_programmable(regmap, name, - parent_names, NULL, 4, i, + NULL, parent_data, 4, i, &at91rm9200_programmable_layout, NULL); if (IS_ERR(hw)) @@ -180,9 +175,16 @@ static void __init at91rm9200_pmc_setup(struct device_= node *np) at91rm9200_pmc->pchws[i] =3D hw; } =20 + /* Set systemck parent hws. */ + at91rm9200_systemck[0].parent_hw =3D usbck_hw; + at91rm9200_systemck[1].parent_hw =3D usbck_hw; + at91rm9200_systemck[2].parent_hw =3D at91rm9200_pmc->pchws[0]; + at91rm9200_systemck[3].parent_hw =3D at91rm9200_pmc->pchws[1]; + at91rm9200_systemck[4].parent_hw =3D at91rm9200_pmc->pchws[2]; + at91rm9200_systemck[5].parent_hw =3D at91rm9200_pmc->pchws[3]; for (i =3D 0; i < ARRAY_SIZE(at91rm9200_systemck); i++) { - hw =3D at91_clk_register_system(regmap, at91rm9200_systemck[i].n, - at91rm9200_systemck[i].p, NULL, + hw =3D at91_clk_register_system(regmap, at91rm9200_systemck[i].n, NULL, + &AT91_CLK_PD_HW(at91rm9200_systemck[i].parent_hw), at91rm9200_systemck[i].id, 0); if (IS_ERR(hw)) goto err_free; @@ -193,7 +195,8 @@ static void __init at91rm9200_pmc_setup(struct device_n= ode *np) for (i =3D 0; i < ARRAY_SIZE(at91rm9200_periphck); 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Thu, 10 Jul 2025 13:07:34 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Thu, 10 Jul 2025 13:07:34 -0700 From: To: , , , , CC: , , , , Subject: [PATCH v3 28/32] clk: at91: at91sam9260: switch to parent_hw and parent_data Date: Thu, 10 Jul 2025 13:07:21 -0700 Message-ID: <77dc4ee8366f568bbb1b1a4f5fc74df82ede9f4a.1752176711.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Switch AT91SAM92600 clocks to use parent_hw and parent_data. Having parent_hw instead of parent names improves to clock registration speed and re-parenting. Signed-off-by: Claudiu Beznea Signed-off-by: Ryan Wanner --- drivers/clk/at91/at91sam9260.c | 136 +++++++++++++++++---------------- 1 file changed, 70 insertions(+), 66 deletions(-) diff --git a/drivers/clk/at91/at91sam9260.c b/drivers/clk/at91/at91sam9260.c index 55350331b07e..827ae743b657 100644 --- a/drivers/clk/at91/at91sam9260.c +++ b/drivers/clk/at91/at91sam9260.c @@ -9,7 +9,7 @@ =20 struct sck { char *n; - char *p; + struct clk_hw *parent_hw; u8 id; }; =20 @@ -24,7 +24,7 @@ struct at91sam926x_data { const struct clk_pll_layout *pllb_layout; const struct clk_pll_characteristics *pllb_characteristics; const struct clk_master_characteristics *mck_characteristics; - const struct sck *sck; + struct sck *sck; const struct pck *pck; u8 num_sck; u8 num_pck; @@ -72,11 +72,11 @@ static const struct clk_pll_characteristics sam9260_pll= b_characteristics =3D { .out =3D sam9260_pllb_out, }; =20 -static const struct sck at91sam9260_systemck[] =3D { - { .n =3D "uhpck", .p =3D "usbck", .id =3D 6 }, - { .n =3D "udpck", .p =3D "usbck", .id =3D 7 }, - { .n =3D "pck0", .p =3D "prog0", .id =3D 8 }, - { .n =3D "pck1", .p =3D "prog1", .id =3D 9 }, +static struct sck at91sam9260_systemck[] =3D { + { .n =3D "uhpck", .id =3D 6 }, + { .n =3D "udpck", .id =3D 7 }, + { .n =3D "pck0", .id =3D 8 }, + { .n =3D "pck1", .id =3D 9 }, }; =20 static const struct pck at91sam9260_periphck[] =3D { @@ -213,15 +213,15 @@ static const struct clk_pll_characteristics sam9261_p= llb_characteristics =3D { .out =3D sam9261_pllb_out, }; =20 -static const struct sck at91sam9261_systemck[] =3D { - { .n =3D "uhpck", .p =3D "usbck", .id =3D 6 }, - { .n =3D "udpck", .p =3D "usbck", .id =3D 7 }, - { .n =3D "pck0", .p =3D "prog0", .id =3D 8 }, - { .n =3D "pck1", .p =3D "prog1", .id =3D 9 }, - { .n =3D "pck2", .p =3D "prog2", .id =3D 10 }, - { .n =3D "pck3", .p =3D "prog3", .id =3D 11 }, - { .n =3D "hclk0", .p =3D "masterck_div", .id =3D 16 }, - { .n =3D "hclk1", .p =3D "masterck_div", .id =3D 17 }, +static struct sck at91sam9261_systemck[] =3D { + { .n =3D "uhpck", .id =3D 6 }, + { .n =3D "udpck", .id =3D 7 }, + { .n =3D "pck0", .id =3D 8 }, + { .n =3D "pck1", .id =3D 9 }, + { .n =3D "pck2", .id =3D 10 }, + { .n =3D "pck3", .id =3D 11 }, + { .n =3D "hclk0", .id =3D 16 }, + { .n =3D "hclk1", .id =3D 17 }, }; =20 static const struct pck at91sam9261_periphck[] =3D { @@ -277,13 +277,13 @@ static const struct clk_pll_characteristics sam9263_p= ll_characteristics =3D { .out =3D sam9260_plla_out, }; =20 -static const struct sck at91sam9263_systemck[] =3D { - { .n =3D "uhpck", .p =3D "usbck", .id =3D 6 }, - { .n =3D "udpck", .p =3D "usbck", .id =3D 7 }, - { .n =3D "pck0", .p =3D "prog0", .id =3D 8 }, - { .n =3D "pck1", .p =3D "prog1", .id =3D 9 }, - { .n =3D "pck2", .p =3D "prog2", .id =3D 10 }, - { .n =3D "pck3", .p =3D "prog3", .id =3D 11 }, +static struct sck at91sam9263_systemck[] =3D { + { .n =3D "uhpck", .id =3D 6 }, + { .n =3D "udpck", .id =3D 7 }, + { .n =3D "pck0", .id =3D 8 }, + { .n =3D "pck1", .id =3D 9 }, + { .n =3D "pck2", .id =3D 10 }, + { .n =3D "pck3", .id =3D 11 }, }; =20 static const struct pck at91sam9263_periphck[] =3D { @@ -329,26 +329,15 @@ static struct at91sam926x_data at91sam9263_data =3D { static void __init at91sam926x_pmc_setup(struct device_node *np, struct at91sam926x_data *data) { - const char *slowxtal_name, *mainxtal_name; + const char *slow_clk_name =3D "slowck", *main_xtal_name =3D "main_xtal"; + u8 slow_clk_index =3D 0, main_xtal_index =3D 1; + struct clk_parent_data parent_data[4]; struct pmc_data *at91sam9260_pmc; u32 usb_div[] =3D { 1, 2, 4, 0 }; - const char *parent_names[6]; - const char *slck_name; + struct clk_hw *usbck_hw, *hw; struct regmap *regmap; - struct clk_hw *hw; - int i; bool bypass; - - i =3D of_property_match_string(np, "clock-names", "slow_xtal"); - if (i < 0) - return; - - slowxtal_name =3D of_clk_get_parent_name(np, i); - - i =3D of_property_match_string(np, "clock-names", "main_xtal"); - if (i < 0) - return; - mainxtal_name =3D of_clk_get_parent_name(np, i); + int i; =20 regmap =3D device_node_to_regmap(np); if (IS_ERR(regmap)) @@ -363,12 +352,13 @@ static void __init at91sam926x_pmc_setup(struct devic= e_node *np, =20 bypass =3D of_property_read_bool(np, "atmel,osc-bypass"); =20 - hw =3D at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL, + hw =3D at91_clk_register_main_osc(regmap, "main_osc", NULL, + &AT91_CLK_PD_NAME(main_xtal_name, main_xtal_index), bypass); if (IS_ERR(hw)) goto err_free; =20 - hw =3D at91_clk_register_rm9200_main(regmap, "mainck", "main_osc", NULL); + hw =3D at91_clk_register_rm9200_main(regmap, "mainck", NULL, &AT91_CLK_PD= _HW(hw)); if (IS_ERR(hw)) goto err_free; =20 @@ -382,20 +372,17 @@ static void __init at91sam926x_pmc_setup(struct devic= e_node *np, if (IS_ERR(hw)) goto err_free; =20 - parent_names[0] =3D "slow_rc_osc"; - parent_names[1] =3D "slow_xtal"; - hw =3D at91_clk_register_sam9260_slow(regmap, "slck", - parent_names, NULL, 2); + parent_data[0] =3D AT91_CLK_PD_HW(hw); + parent_data[1] =3D AT91_CLK_PD_NAME(slow_clk_name, slow_clk_index); + hw =3D at91_clk_register_sam9260_slow(regmap, "slck", NULL, parent_data,= 2); if (IS_ERR(hw)) goto err_free; =20 at91sam9260_pmc->chws[PMC_SLOW] =3D hw; - slck_name =3D "slck"; - } else { - slck_name =3D slowxtal_name; } =20 - hw =3D at91_clk_register_pll(regmap, "pllack", "mainck", NULL, 0, + hw =3D at91_clk_register_pll(regmap, "pllack", NULL, + &AT91_CLK_PD_HW(at91sam9260_pmc->chws[PMC_MAIN]), 0, data->plla_layout, data->plla_characteristics); if (IS_ERR(hw)) @@ -403,7 +390,8 @@ static void __init at91sam926x_pmc_setup(struct device_= node *np, =20 at91sam9260_pmc->chws[PMC_PLLACK] =3D hw; =20 - hw =3D at91_clk_register_pll(regmap, "pllbck", "mainck", NULL, 1, + hw =3D at91_clk_register_pll(regmap, "pllbck", NULL, + &AT91_CLK_PD_HW(at91sam9260_pmc->chws[PMC_MAIN]), 1, data->pllb_layout, data->pllb_characteristics); if (IS_ERR(hw)) @@ -411,12 +399,12 @@ static void __init at91sam926x_pmc_setup(struct devic= e_node *np, =20 at91sam9260_pmc->chws[PMC_PLLBCK] =3D hw; =20 - parent_names[0] =3D slck_name; - parent_names[1] =3D "mainck"; - parent_names[2] =3D "pllack"; - parent_names[3] =3D "pllbck"; + parent_data[0] =3D AT91_CLK_PD_NAME(slow_clk_name, slow_clk_index); + parent_data[1] =3D AT91_CLK_PD_HW(at91sam9260_pmc->chws[PMC_MAIN]); + parent_data[2] =3D AT91_CLK_PD_HW(at91sam9260_pmc->chws[PMC_PLLACK]); + parent_data[3] =3D AT91_CLK_PD_HW(at91sam9260_pmc->chws[PMC_PLLACK]); hw =3D at91_clk_register_master_pres(regmap, "masterck_pres", 4, - parent_names, NULL, + NULL, parent_data, &at91rm9200_master_layout, data->mck_characteristics, &at91sam9260_mck_lock); @@ -424,7 +412,7 @@ static void __init at91sam926x_pmc_setup(struct device_= node *np, goto err_free; =20 hw =3D at91_clk_register_master_div(regmap, "masterck_div", - "masterck_pres", NULL, + NULL, &AT91_CLK_PD_HW(hw), &at91rm9200_master_layout, data->mck_characteristics, &at91sam9260_mck_lock, @@ -434,21 +422,23 @@ static void __init at91sam926x_pmc_setup(struct devic= e_node *np, =20 at91sam9260_pmc->chws[PMC_MCK] =3D hw; =20 - hw =3D at91rm9200_clk_register_usb(regmap, "usbck", "pllbck", NULL, usb_d= iv); - if (IS_ERR(hw)) + usbck_hw =3D at91rm9200_clk_register_usb(regmap, "usbck", NULL, + &AT91_CLK_PD_HW(at91sam9260_pmc->chws[PMC_PLLBCK]), + usb_div); + if (IS_ERR(usbck_hw)) goto err_free; =20 - parent_names[0] =3D slck_name; - parent_names[1] =3D "mainck"; - parent_names[2] =3D "pllack"; - parent_names[3] =3D "pllbck"; + parent_data[0] =3D AT91_CLK_PD_NAME(slow_clk_name, slow_clk_index); + parent_data[1] =3D AT91_CLK_PD_HW(at91sam9260_pmc->chws[PMC_MAIN]); + parent_data[2] =3D AT91_CLK_PD_HW(at91sam9260_pmc->chws[PMC_PLLACK]); + parent_data[3] =3D AT91_CLK_PD_HW(at91sam9260_pmc->chws[PMC_PLLBCK]); for (i =3D 0; i < data->num_progck; i++) { char name[6]; =20 snprintf(name, sizeof(name), "prog%d", i); =20 hw =3D at91_clk_register_programmable(regmap, name, - parent_names, NULL, 4, i, + NULL, parent_data, 4, i, &at91rm9200_programmable_layout, NULL); if (IS_ERR(hw)) @@ -457,9 +447,22 @@ static void __init at91sam926x_pmc_setup(struct device= _node *np, at91sam9260_pmc->pchws[i] =3D hw; } =20 + /* Set systemck parent hws. */ + data->sck[0].parent_hw =3D usbck_hw; + data->sck[1].parent_hw =3D usbck_hw; + data->sck[2].parent_hw =3D at91sam9260_pmc->pchws[0]; + data->sck[3].parent_hw =3D at91sam9260_pmc->pchws[1]; + if (data->num_sck =3D=3D 6) { + data->sck[4].parent_hw =3D at91sam9260_pmc->pchws[2]; + data->sck[5].parent_hw =3D at91sam9260_pmc->pchws[3]; + } + if (data->num_sck =3D=3D 8) { + data->sck[6].parent_hw =3D at91sam9260_pmc->chws[PMC_MCK]; + data->sck[7].parent_hw =3D at91sam9260_pmc->chws[PMC_MCK]; + } for (i =3D 0; i < data->num_sck; i++) { - hw =3D at91_clk_register_system(regmap, data->sck[i].n, - data->sck[i].p, NULL, + hw =3D at91_clk_register_system(regmap, data->sck[i].n, NULL, + &AT91_CLK_PD_HW(data->sck[i].parent_hw), data->sck[i].id, 0); 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Thu, 10 Jul 2025 13:07:34 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Thu, 10 Jul 2025 13:07:34 -0700 From: To: , , , , CC: , , , , Subject: [PATCH v3 29/32] clk: at91: at91sam9g45: switch to parent_hw and parent_data Date: Thu, 10 Jul 2025 13:07:22 -0700 Message-ID: <21100b0a61e22028b471555c6684c545ff3a9400.1752176711.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Switch AT91SAM9G45 clocks to use parent_hw and parent_data. Having parent_hw instead of parent names improves to clock registration speed and re-parenting. Signed-off-by: Claudiu Beznea Signed-off-by: Ryan Wanner --- drivers/clk/at91/at91sam9g45.c | 89 +++++++++++++++++----------------- 1 file changed, 44 insertions(+), 45 deletions(-) diff --git a/drivers/clk/at91/at91sam9g45.c b/drivers/clk/at91/at91sam9g45.c index cb98d22c2e30..54cc4e1bbdc3 100644 --- a/drivers/clk/at91/at91sam9g45.c +++ b/drivers/clk/at91/at91sam9g45.c @@ -37,9 +37,9 @@ static const struct clk_pll_characteristics plla_characte= ristics =3D { .out =3D plla_out, }; =20 -static const struct { +static struct { char *n; - char *p; + struct clk_hw *parent_hw; unsigned long flags; u8 id; } at91sam9g45_systemck[] =3D { @@ -47,10 +47,10 @@ static const struct { * ddrck feeds DDR controller and is enabled by bootloader thus we need * to keep it enabled in case there is no Linux consumer for it. */ - { .n =3D "ddrck", .p =3D "masterck_div", .id =3D 2, .flags =3D CLK_IS_CRI= TICAL }, - { .n =3D "uhpck", .p =3D "usbck", .id =3D 6 }, - { .n =3D "pck0", .p =3D "prog0", .id =3D 8 }, - { .n =3D "pck1", .p =3D "prog1", .id =3D 9 }, + { .n =3D "ddrck", .id =3D 2, .flags =3D CLK_IS_CRITICAL }, + { .n =3D "uhpck", .id =3D 6 }, + { .n =3D "pck0", .id =3D 8 }, + { .n =3D "pck1", .id =3D 9 }, }; =20 struct pck { @@ -92,24 +92,14 @@ static const struct pck at91sam9g45_periphck[] =3D { =20 static void __init at91sam9g45_pmc_setup(struct device_node *np) { - const char *slck_name, *mainxtal_name; + const char *slow_clk_name =3D "slowck", *main_xtal_name =3D "main_xtal"; + u8 slow_clk_index =3D 0, main_xtal_index =3D 1; + struct clk_parent_data parent_data[5]; struct pmc_data *at91sam9g45_pmc; - const char *parent_names[6]; + struct clk_hw *usbck_hw, *hw; struct regmap *regmap; - struct clk_hw *hw; - int i; bool bypass; - - i =3D of_property_match_string(np, "clock-names", "slow_clk"); - if (i < 0) - return; - - slck_name =3D of_clk_get_parent_name(np, i); - - i =3D of_property_match_string(np, "clock-names", "main_xtal"); - if (i < 0) - return; - mainxtal_name =3D of_clk_get_parent_name(np, i); + int i; =20 regmap =3D device_node_to_regmap(np); if (IS_ERR(regmap)) @@ -123,40 +113,43 @@ static void __init at91sam9g45_pmc_setup(struct devic= e_node *np) =20 bypass =3D of_property_read_bool(np, "atmel,osc-bypass"); =20 - hw =3D at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL, + hw =3D at91_clk_register_main_osc(regmap, "main_osc", NULL, + &AT91_CLK_PD_NAME(main_xtal_name, main_xtal_index), bypass); if (IS_ERR(hw)) goto err_free; =20 - hw =3D at91_clk_register_rm9200_main(regmap, "mainck", "main_osc", NULL); + hw =3D at91_clk_register_rm9200_main(regmap, "mainck", NULL, &AT91_CLK_PD= _HW(hw)); if (IS_ERR(hw)) goto err_free; =20 at91sam9g45_pmc->chws[PMC_MAIN] =3D hw; =20 - hw =3D at91_clk_register_pll(regmap, "pllack", "mainck", NULL, 0, + hw =3D at91_clk_register_pll(regmap, "pllack", NULL, + &AT91_CLK_PD_HW(at91sam9g45_pmc->chws[PMC_MAIN]), 0, &at91rm9200_pll_layout, &plla_characteristics); if (IS_ERR(hw)) goto err_free; =20 - hw =3D at91_clk_register_plldiv(regmap, "plladivck", "pllack", NULL); + hw =3D at91_clk_register_plldiv(regmap, "plladivck", NULL, &AT91_CLK_PD_H= W(hw)); if (IS_ERR(hw)) goto err_free; =20 at91sam9g45_pmc->chws[PMC_PLLACK] =3D hw; =20 - hw =3D at91_clk_register_utmi(regmap, NULL, "utmick", "mainck", NULL); + hw =3D at91_clk_register_utmi(regmap, NULL, "utmick", NULL, + &AT91_CLK_PD_HW(at91sam9g45_pmc->chws[PMC_MAIN])); if (IS_ERR(hw)) goto err_free; =20 at91sam9g45_pmc->chws[PMC_UTMI] =3D hw; =20 - parent_names[0] =3D slck_name; - parent_names[1] =3D "mainck"; - parent_names[2] =3D "plladivck"; - parent_names[3] =3D "utmick"; + parent_data[0] =3D AT91_CLK_PD_NAME(slow_clk_name, slow_clk_index); + parent_data[1] =3D AT91_CLK_PD_HW(at91sam9g45_pmc->chws[PMC_MAIN]); + parent_data[2] =3D AT91_CLK_PD_HW(at91sam9g45_pmc->chws[PMC_PLLACK]); + parent_data[3] =3D AT91_CLK_PD_HW(at91sam9g45_pmc->chws[PMC_UTMI]); hw =3D at91_clk_register_master_pres(regmap, "masterck_pres", 4, - parent_names, NULL, + NULL, parent_data, &at91rm9200_master_layout, &mck_characteristics, &at91sam9g45_mck_lock); @@ -164,7 +157,7 @@ static void __init at91sam9g45_pmc_setup(struct device_= node *np) goto err_free; =20 hw =3D at91_clk_register_master_div(regmap, "masterck_div", - "masterck_pres", NULL, + NULL, &AT91_CLK_PD_HW(hw), &at91rm9200_master_layout, &mck_characteristics, &at91sam9g45_mck_lock, @@ -174,24 +167,24 @@ static void __init at91sam9g45_pmc_setup(struct devic= e_node *np) =20 at91sam9g45_pmc->chws[PMC_MCK] =3D hw; =20 - parent_names[0] =3D "plladivck"; - parent_names[1] =3D "utmick"; - hw =3D at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, NULL, 2= ); - if (IS_ERR(hw)) + parent_data[0] =3D AT91_CLK_PD_HW(at91sam9g45_pmc->chws[PMC_PLLACK]); + parent_data[1] =3D AT91_CLK_PD_HW(at91sam9g45_pmc->chws[PMC_UTMI]); + usbck_hw =3D at91sam9x5_clk_register_usb(regmap, "usbck", NULL, parent_da= ta, 2); + if (IS_ERR(usbck_hw)) goto err_free; =20 - parent_names[0] =3D slck_name; - parent_names[1] =3D "mainck"; - parent_names[2] =3D "plladivck"; - parent_names[3] =3D "utmick"; - parent_names[4] =3D "masterck_div"; + parent_data[0] =3D AT91_CLK_PD_NAME(slow_clk_name, slow_clk_index); + parent_data[1] =3D AT91_CLK_PD_HW(at91sam9g45_pmc->chws[PMC_MAIN]); + parent_data[2] =3D AT91_CLK_PD_HW(at91sam9g45_pmc->chws[PMC_PLLACK]); + parent_data[3] =3D AT91_CLK_PD_HW(at91sam9g45_pmc->chws[PMC_UTMI]); + parent_data[4] =3D AT91_CLK_PD_HW(at91sam9g45_pmc->chws[PMC_MCK]); for (i =3D 0; i < 2; i++) { char name[6]; =20 snprintf(name, sizeof(name), "prog%d", i); =20 hw =3D at91_clk_register_programmable(regmap, name, - parent_names, NULL, 5, i, + NULL, parent_data, 5, i, &at91sam9g45_programmable_layout, NULL); if (IS_ERR(hw)) @@ -200,9 +193,14 @@ static void __init at91sam9g45_pmc_setup(struct device= _node *np) at91sam9g45_pmc->pchws[i] =3D hw; } =20 + /* Set systemck parent hws. */ + at91sam9g45_systemck[0].parent_hw =3D at91sam9g45_pmc->chws[PMC_MCK]; + at91sam9g45_systemck[1].parent_hw =3D usbck_hw; + at91sam9g45_systemck[2].parent_hw =3D at91sam9g45_pmc->pchws[0]; + at91sam9g45_systemck[3].parent_hw =3D at91sam9g45_pmc->pchws[1]; for (i =3D 0; i < ARRAY_SIZE(at91sam9g45_systemck); i++) { - hw =3D at91_clk_register_system(regmap, at91sam9g45_systemck[i].n, - at91sam9g45_systemck[i].p, NULL, + hw =3D at91_clk_register_system(regmap, at91sam9g45_systemck[i].n, NULL, + &AT91_CLK_PD_HW(at91sam9g45_systemck[i].parent_hw), at91sam9g45_systemck[i].id, at91sam9g45_systemck[i].flags); if (IS_ERR(hw)) @@ -214,7 +212,8 @@ static void __init at91sam9g45_pmc_setup(struct device_= node *np) for (i =3D 0; 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Thu, 10 Jul 2025 13:07:34 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Thu, 10 Jul 2025 13:07:34 -0700 From: To: , , , , CC: , , , , Subject: [PATCH v3 30/32] clk: at91: at91sam9n12: switch to parent_hw and parent_data Date: Thu, 10 Jul 2025 13:07:23 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Switch AT91SAM9N12 clocks to use parent_hw and parent_data. Having parent_hw instead of parent names improves to clock registration speed and re-parenting. Signed-off-by: Claudiu Beznea Signed-off-by: Ryan Wanner --- drivers/clk/at91/at91sam9n12.c | 106 +++++++++++++++++---------------- 1 file changed, 54 insertions(+), 52 deletions(-) diff --git a/drivers/clk/at91/at91sam9n12.c b/drivers/clk/at91/at91sam9n12.c index 34dd7645f964..88950003a58e 100644 --- a/drivers/clk/at91/at91sam9n12.c +++ b/drivers/clk/at91/at91sam9n12.c @@ -51,9 +51,9 @@ static const struct clk_pll_characteristics pllb_characte= ristics =3D { .out =3D pllb_out, }; =20 -static const struct { +static struct { char *n; - char *p; + struct clk_hw *parent_hw; unsigned long flags; u8 id; } at91sam9n12_systemck[] =3D { @@ -61,12 +61,12 @@ static const struct { * ddrck feeds DDR controller and is enabled by bootloader thus we need * to keep it enabled in case there is no Linux consumer for it. */ - { .n =3D "ddrck", .p =3D "masterck_div", .id =3D 2, .flags =3D CLK_IS_CRI= TICAL }, - { .n =3D "lcdck", .p =3D "masterck_div", .id =3D 3 }, - { .n =3D "uhpck", .p =3D "usbck", .id =3D 6 }, - { .n =3D "udpck", .p =3D "usbck", .id =3D 7 }, - { .n =3D "pck0", .p =3D "prog0", .id =3D 8 }, - { .n =3D "pck1", .p =3D "prog1", .id =3D 9 }, + { .n =3D "ddrck", .id =3D 2, .flags =3D CLK_IS_CRITICAL }, + { .n =3D "lcdck", .id =3D 3 }, + { .n =3D "uhpck", .id =3D 6 }, + { .n =3D "udpck", .id =3D 7 }, + { .n =3D "pck0", .id =3D 8 }, + { .n =3D "pck1", .id =3D 9 }, }; =20 static const struct clk_pcr_layout at91sam9n12_pcr_layout =3D { @@ -111,25 +111,15 @@ static const struct pck at91sam9n12_periphck[] =3D { =20 static void __init at91sam9n12_pmc_setup(struct device_node *np) { + const char *slow_clk_name =3D "slowck", *main_xtal_name =3D "main_xtal"; + struct clk_hw *usbck_hw, *hw, *main_rc_hw, *main_osc_hw; + u8 slow_clk_index =3D 0, main_xtal_index =3D 1; struct clk_range range =3D CLK_RANGE(0, 0); - const char *slck_name, *mainxtal_name; + struct clk_parent_data parent_data[5]; struct pmc_data *at91sam9n12_pmc; - const char *parent_names[6]; struct regmap *regmap; - struct clk_hw *hw; - int i; bool bypass; - - i =3D of_property_match_string(np, "clock-names", "slow_clk"); - if (i < 0) - return; - - slck_name =3D of_clk_get_parent_name(np, i); - - i =3D of_property_match_string(np, "clock-names", "main_xtal"); - if (i < 0) - return; - mainxtal_name =3D of_clk_get_parent_name(np, i); + int i; =20 regmap =3D device_node_to_regmap(np); if (IS_ERR(regmap)) @@ -140,50 +130,53 @@ static void __init at91sam9n12_pmc_setup(struct devic= e_node *np) if (!at91sam9n12_pmc) return; =20 - hw =3D at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000, - 50000000); - if (IS_ERR(hw)) + main_rc_hw =3D at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000= 000, + 50000000); + if (IS_ERR(main_rc_hw)) goto err_free; =20 bypass =3D of_property_read_bool(np, "atmel,osc-bypass"); =20 - hw =3D at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL, - bypass); - if (IS_ERR(hw)) + main_osc_hw =3D at91_clk_register_main_osc(regmap, "main_osc", NULL, + &AT91_CLK_PD_NAME(main_xtal_name, main_xtal_index), + bypass); + if (IS_ERR(main_osc_hw)) goto err_free; =20 - parent_names[0] =3D "main_rc_osc"; - parent_names[1] =3D "main_osc"; - hw =3D at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL= , 2); + parent_data[0] =3D AT91_CLK_PD_HW(main_rc_hw); + parent_data[1] =3D AT91_CLK_PD_HW(main_osc_hw); + hw =3D at91_clk_register_sam9x5_main(regmap, "mainck", NULL, parent_data,= 2); if (IS_ERR(hw)) goto err_free; =20 at91sam9n12_pmc->chws[PMC_MAIN] =3D hw; =20 - hw =3D at91_clk_register_pll(regmap, "pllack", "mainck", NULL, 0, + hw =3D at91_clk_register_pll(regmap, "pllack", NULL, + &AT91_CLK_PD_HW(at91sam9n12_pmc->chws[PMC_MAIN]), 0, &at91rm9200_pll_layout, &plla_characteristics); if (IS_ERR(hw)) goto err_free; =20 - hw =3D at91_clk_register_plldiv(regmap, "plladivck", "pllack", NULL); + hw =3D at91_clk_register_plldiv(regmap, "plladivck", NULL, &AT91_CLK_PD_H= W(hw)); if (IS_ERR(hw)) goto err_free; =20 at91sam9n12_pmc->chws[PMC_PLLACK] =3D hw; =20 - hw =3D at91_clk_register_pll(regmap, "pllbck", "mainck", NULL, 1, + hw =3D at91_clk_register_pll(regmap, "pllbck", NULL, + &AT91_CLK_PD_HW(at91sam9n12_pmc->chws[PMC_MAIN]), 1, &at91rm9200_pll_layout, &pllb_characteristics); if (IS_ERR(hw)) goto err_free; =20 at91sam9n12_pmc->chws[PMC_PLLBCK] =3D hw; =20 - parent_names[0] =3D slck_name; - parent_names[1] =3D "mainck"; - parent_names[2] =3D "plladivck"; - parent_names[3] =3D "pllbck"; + parent_data[0] =3D AT91_CLK_PD_NAME(slow_clk_name, slow_clk_index); + parent_data[1] =3D AT91_CLK_PD_HW(at91sam9n12_pmc->chws[PMC_MAIN]); + parent_data[2] =3D AT91_CLK_PD_HW(at91sam9n12_pmc->chws[PMC_PLLACK]); + parent_data[3] =3D AT91_CLK_PD_HW(at91sam9n12_pmc->chws[PMC_PLLBCK]); hw =3D at91_clk_register_master_pres(regmap, "masterck_pres", 4, - parent_names, NULL, + NULL, parent_data, &at91sam9x5_master_layout, &mck_characteristics, &at91sam9n12_mck_lock); @@ -191,7 +184,7 @@ static void __init at91sam9n12_pmc_setup(struct device_= node *np) goto err_free; =20 hw =3D at91_clk_register_master_div(regmap, "masterck_div", - "masterck_pres", NULL, + NULL, &AT91_CLK_PD_HW(hw), &at91sam9x5_master_layout, &mck_characteristics, &at91sam9n12_mck_lock, @@ -201,22 +194,23 @@ static void __init at91sam9n12_pmc_setup(struct devic= e_node *np) =20 at91sam9n12_pmc->chws[PMC_MCK] =3D hw; =20 - hw =3D at91sam9n12_clk_register_usb(regmap, "usbck", "pllbck", NULL); - if (IS_ERR(hw)) + usbck_hw =3D at91sam9n12_clk_register_usb(regmap, "usbck", NULL, + &AT91_CLK_PD_HW(at91sam9n12_pmc->chws[PMC_PLLBCK])); + if (IS_ERR(usbck_hw)) goto err_free; =20 - parent_names[0] =3D slck_name; - parent_names[1] =3D "mainck"; - parent_names[2] =3D "plladivck"; - parent_names[3] =3D "pllbck"; - parent_names[4] =3D "masterck_div"; + parent_data[0] =3D AT91_CLK_PD_NAME(slow_clk_name, slow_clk_index); + parent_data[1] =3D AT91_CLK_PD_HW(at91sam9n12_pmc->chws[PMC_MAIN]); + parent_data[2] =3D AT91_CLK_PD_HW(at91sam9n12_pmc->chws[PMC_PLLACK]); + parent_data[3] =3D AT91_CLK_PD_HW(at91sam9n12_pmc->chws[PMC_PLLBCK]); + parent_data[4] =3D AT91_CLK_PD_HW(at91sam9n12_pmc->chws[PMC_MCK]); for (i =3D 0; i < 2; i++) { char name[6]; =20 snprintf(name, sizeof(name), "prog%d", i); =20 hw =3D at91_clk_register_programmable(regmap, name, - parent_names, NULL, 5, i, + NULL, parent_data, 5, i, &at91sam9x5_programmable_layout, NULL); if (IS_ERR(hw)) @@ -225,9 +219,16 @@ static void __init at91sam9n12_pmc_setup(struct device= _node *np) at91sam9n12_pmc->pchws[i] =3D hw; } =20 + /* Set systemck parent hws. */ + at91sam9n12_systemck[0].parent_hw =3D at91sam9n12_pmc->chws[PMC_MCK]; + at91sam9n12_systemck[1].parent_hw =3D at91sam9n12_pmc->chws[PMC_MCK]; + at91sam9n12_systemck[2].parent_hw =3D usbck_hw; + at91sam9n12_systemck[3].parent_hw =3D usbck_hw; + at91sam9n12_systemck[4].parent_hw =3D at91sam9n12_pmc->pchws[0]; + at91sam9n12_systemck[5].parent_hw =3D at91sam9n12_pmc->pchws[1]; for (i =3D 0; i < ARRAY_SIZE(at91sam9n12_systemck); i++) { - hw =3D at91_clk_register_system(regmap, at91sam9n12_systemck[i].n, - at91sam9n12_systemck[i].p, NULL, + hw =3D at91_clk_register_system(regmap, at91sam9n12_systemck[i].n, NULL, + &AT91_CLK_PD_HW(at91sam9n12_systemck[i].parent_hw), at91sam9n12_systemck[i].id, at91sam9n12_systemck[i].flags); if (IS_ERR(hw)) @@ -240,7 +241,8 @@ static void __init at91sam9n12_pmc_setup(struct device_= node *np) hw =3D at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, &at91sam9n12_pcr_layout, at91sam9n12_periphck[i].n, - "masterck_div", NULL, + NULL, + &AT91_CLK_PD_HW(at91sam9n12_pmc->chws[PMC_MCK]), at91sam9n12_periphck[i].id, &range, INT_MIN, 0); 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X-CSE-ConnectionGUID: qOQSLemoQZOGUxBCHa7nXg== X-CSE-MsgGUID: k/ggPkAwQgao9E5iDykMoA== X-IronPort-AV: E=Sophos;i="6.16,301,1744095600"; d="scan'208";a="275215689" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 10 Jul 2025 13:07:41 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Thu, 10 Jul 2025 13:07:34 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Thu, 10 Jul 2025 13:07:34 -0700 From: To: , , , , CC: , , , , Subject: [PATCH v3 31/32] clk: at91: at91sam9rl: switch to clk_parent_data Date: Thu, 10 Jul 2025 13:07:24 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Switch AT91SAM9RL clocks to use parent_hw and parent_data. Having parent_hw instead of parent names improves to clock registration speed and re-parenting. Signed-off-by: Claudiu Beznea Signed-off-by: Ryan Wanner --- drivers/clk/at91/at91sam9rl.c | 63 ++++++++++++++++------------------- 1 file changed, 28 insertions(+), 35 deletions(-) diff --git a/drivers/clk/at91/at91sam9rl.c b/drivers/clk/at91/at91sam9rl.c index 0e8657aac491..5b342b707213 100644 --- a/drivers/clk/at91/at91sam9rl.c +++ b/drivers/clk/at91/at91sam9rl.c @@ -28,13 +28,12 @@ static const struct clk_pll_characteristics sam9rl_plla= _characteristics =3D { .out =3D sam9rl_plla_out, }; =20 -static const struct { +static struct { char *n; - char *p; u8 id; } at91sam9rl_systemck[] =3D { - { .n =3D "pck0", .p =3D "prog0", .id =3D 8 }, - { .n =3D "pck1", .p =3D "prog1", .id =3D 9 }, + { .n =3D "pck0", .id =3D 8 }, + { .n =3D "pck1", .id =3D 9 }, }; =20 static const struct { @@ -67,24 +66,14 @@ static const struct { =20 static void __init at91sam9rl_pmc_setup(struct device_node *np) { - const char *slck_name, *mainxtal_name; + const char *slow_clk_name =3D "slowck", *main_xtal_name =3D "main_xtal"; + u8 slow_clk_index =3D 0, main_xtal_index =3D 1; + struct clk_parent_data parent_data[6]; struct pmc_data *at91sam9rl_pmc; - const char *parent_names[6]; struct regmap *regmap; struct clk_hw *hw; int i; =20 - i =3D of_property_match_string(np, "clock-names", "slow_clk"); - if (i < 0) - return; - - slck_name =3D of_clk_get_parent_name(np, i); - - i =3D of_property_match_string(np, "clock-names", "main_xtal"); - if (i < 0) - return; - mainxtal_name =3D of_clk_get_parent_name(np, i); - regmap =3D device_node_to_regmap(np); if (IS_ERR(regmap)) return; @@ -95,13 +84,15 @@ static void __init at91sam9rl_pmc_setup(struct device_n= ode *np) if (!at91sam9rl_pmc) return; =20 - hw =3D at91_clk_register_rm9200_main(regmap, "mainck", mainxtal_name, NUL= L); + hw =3D at91_clk_register_rm9200_main(regmap, "mainck", NULL, + &AT91_CLK_PD_NAME(main_xtal_name, main_xtal_index)); if (IS_ERR(hw)) goto err_free; =20 at91sam9rl_pmc->chws[PMC_MAIN] =3D hw; =20 - hw =3D at91_clk_register_pll(regmap, "pllack", "mainck", NULL, 0, + hw =3D at91_clk_register_pll(regmap, "pllack", NULL, + &AT91_CLK_PD_HW(at91sam9rl_pmc->chws[PMC_MAIN]), 0, &at91rm9200_pll_layout, &sam9rl_plla_characteristics); if (IS_ERR(hw)) @@ -109,18 +100,19 @@ static void __init at91sam9rl_pmc_setup(struct device= _node *np) =20 at91sam9rl_pmc->chws[PMC_PLLACK] =3D hw; =20 - hw =3D at91_clk_register_utmi(regmap, NULL, "utmick", "mainck", NULL); + hw =3D at91_clk_register_utmi(regmap, NULL, "utmick", NULL, + &AT91_CLK_PD_HW(at91sam9rl_pmc->chws[PMC_MAIN])); if (IS_ERR(hw)) goto err_free; =20 at91sam9rl_pmc->chws[PMC_UTMI] =3D hw; =20 - parent_names[0] =3D slck_name; - parent_names[1] =3D "mainck"; - parent_names[2] =3D "pllack"; - parent_names[3] =3D "utmick"; + parent_data[0] =3D AT91_CLK_PD_NAME(slow_clk_name, slow_clk_index); + parent_data[1] =3D AT91_CLK_PD_HW(at91sam9rl_pmc->chws[PMC_MAIN]); + parent_data[2] =3D AT91_CLK_PD_HW(at91sam9rl_pmc->chws[PMC_PLLACK]); + parent_data[3] =3D AT91_CLK_PD_HW(at91sam9rl_pmc->chws[PMC_UTMI]); hw =3D at91_clk_register_master_pres(regmap, "masterck_pres", 4, - parent_names, NULL, + NULL, parent_data, &at91rm9200_master_layout, &sam9rl_mck_characteristics, &sam9rl_mck_lock); @@ -128,7 +120,7 @@ static void __init at91sam9rl_pmc_setup(struct device_n= ode *np) goto err_free; =20 hw =3D at91_clk_register_master_div(regmap, "masterck_div", - "masterck_pres", NULL, + NULL, &AT91_CLK_PD_HW(hw), &at91rm9200_master_layout, &sam9rl_mck_characteristics, &sam9rl_mck_lock, CLK_SET_RATE_GATE, 0); @@ -137,18 +129,18 @@ static void __init at91sam9rl_pmc_setup(struct device= _node *np) =20 at91sam9rl_pmc->chws[PMC_MCK] =3D hw; =20 - parent_names[0] =3D slck_name; - parent_names[1] =3D "mainck"; - parent_names[2] =3D "pllack"; - parent_names[3] =3D "utmick"; - parent_names[4] =3D "masterck_div"; + parent_data[0] =3D AT91_CLK_PD_NAME(slow_clk_name, slow_clk_index); + parent_data[1] =3D AT91_CLK_PD_HW(at91sam9rl_pmc->chws[PMC_MAIN]); + parent_data[2] =3D AT91_CLK_PD_HW(at91sam9rl_pmc->chws[PMC_PLLACK]); + parent_data[3] =3D AT91_CLK_PD_HW(at91sam9rl_pmc->chws[PMC_UTMI]); + parent_data[4] =3D AT91_CLK_PD_HW(at91sam9rl_pmc->chws[PMC_MCK]); for (i =3D 0; i < 2; i++) { char name[6]; =20 snprintf(name, sizeof(name), "prog%d", i); =20 hw =3D at91_clk_register_programmable(regmap, name, - parent_names, NULL, 5, i, + NULL, parent_data, 5, i, &at91rm9200_programmable_layout, NULL); if (IS_ERR(hw)) @@ -158,8 +150,8 @@ static void __init at91sam9rl_pmc_setup(struct device_n= ode *np) } =20 for (i =3D 0; i < ARRAY_SIZE(at91sam9rl_systemck); i++) { - hw =3D at91_clk_register_system(regmap, at91sam9rl_systemck[i].n, - at91sam9rl_systemck[i].p, NULL, + hw =3D at91_clk_register_system(regmap, at91sam9rl_systemck[i].n, NULL, + &AT91_CLK_PD_HW(at91sam9rl_pmc->pchws[0]), at91sam9rl_systemck[i].id, 0); if (IS_ERR(hw)) goto err_free; @@ -170,7 +162,8 @@ static void __init at91sam9rl_pmc_setup(struct device_n= ode *np) for (i =3D 0; i < ARRAY_SIZE(at91sam9rl_periphck); i++) { hw =3D at91_clk_register_peripheral(regmap, at91sam9rl_periphck[i].n, - "masterck_div", NULL, + NULL, + &AT91_CLK_PD_HW(at91sam9rl_pmc->chws[PMC_MCK]), at91sam9rl_periphck[i].id); if (IS_ERR(hw)) goto err_free; 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charset="utf-8" From: Ryan Wanner Clean up variable formatting as well as add an extra space to improve readability. Signed-off-by: Ryan Wanner --- drivers/clk/at91/sam9x7.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/clk/at91/sam9x7.c b/drivers/clk/at91/sam9x7.c index 56243f6f7e65..ce6ad2a0be98 100644 --- a/drivers/clk/at91/sam9x7.c +++ b/drivers/clk/at91/sam9x7.c @@ -739,16 +739,16 @@ static void __init sam9x7_pmc_setup(struct device_nod= e *np) { u8 td_slck_index =3D 0, md_slck_index =3D 1, main_xtal_index =3D 2; struct clk_hw *hw, *main_rc_hw, *main_osc_hw, *usbck_hw; - struct clk_range range =3D CLK_RANGE(0, 0); const char *const main_xtal_name =3D "main_xtal"; const char *const td_slck_name =3D "td_slck"; const char *const md_slck_name =3D "md_slck"; + struct clk_range range =3D CLK_RANGE(0, 0); + struct clk_parent_data parent_data[9]; struct pmc_data *sam9x7_pmc; void **clk_mux_buffer =3D NULL; int clk_mux_buffer_size =3D 0; struct clk *main_xtal; struct regmap *regmap; - struct clk_parent_data parent_data[9]; int i, j; =20 main_xtal =3D of_clk_get(np, main_xtal_index); @@ -943,6 +943,7 @@ static void __init sam9x7_pmc_setup(struct device_node = *np) PMC_INIT_TABLE(mux_table, 4); PMC_FILL_TABLE(&mux_table[4], sam9x7_gck[i].pp_mux_table, sam9x7_gck[i].pp_count); + for (j =3D 0; j < sam9x7_gck[i].pp_count; j++) { u8 pll_id =3D sam9x7_gck[i].pp[j].pll_id; u8 pll_compid =3D sam9x7_gck[i].pp[j].pll_compid; --=20 2.43.0