From nobody Wed Oct 8 07:40:06 2025 Received: from mail-qv1-f50.google.com (mail-qv1-f50.google.com [209.85.219.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AFC4F72613; Mon, 30 Jun 2025 18:21:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.219.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751307700; cv=none; b=pdbIg2h/Vb51lZ8erN74jW2J4KxATm1Jv1Iom7q8rBs3kezhzKHdflVgm5SYYbEaTsbQtOUUMJKK0/lAuKS73XBT+/O5MwAIFCwEjOpFKYsuDugxIigHXUDdpBkm/z7nHb3XoY8N/Pms18oc0ppa6njaMZZqLemBVUMQQiL9gH8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751307700; c=relaxed/simple; bh=tpbE2FvztANs2/izJnOECYoMP2X5oOScRQHxOIydI1k=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=N/Ta5DgVLaSt4dCNTFwN4clmXKKt1RRRSrQ8WmZWJVyw6E14vZL7uW3LL7UaAg/Tqlg6o/IZlOB9aJXGGxpsF1I7bxH2Oc1ZpAD+ITdgoi2jjJh7LPbaDV1hvLOq+N82mBArN+2XKjrp0veNO1mDH3BwdJQ2jRBRGKU7lF9spq8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=haeEScmh; arc=none smtp.client-ip=209.85.219.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="haeEScmh" Received: by mail-qv1-f50.google.com with SMTP id 6a1803df08f44-6f8aa9e6ffdso55627516d6.3; Mon, 30 Jun 2025 11:21:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1751307697; x=1751912497; darn=vger.kernel.org; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=mt5O7/7JEumjsAyKxjvlFipcH+4/5yB2S8im+OQhNPo=; b=haeEScmhx3fr373xFvjSOJeOmxFhG3ZDl9mo5+fQVCBOl/b7Amj1nboZZfx26dq0S2 6Y4WOxQkT5fRyL4l1uk8AsHk0jpZoFhglXStKAtlIanJ5b+bvksaiTfCArx1D+uHGSq+ X1ADfz/wr6O4QLQM+sJDWyIzx0AiN2nJVvnEFWfl1mIQdcAZM+oH/ZwUIxWEhng0ksSU /hZp6xC9OFM220vdnpP9JwiyYPbawVMqRLbyEsvJADYG/T+sNwKVptO9KXTmnKqTZxsg 81DoRsnJ4YmPYh4JHqrh7eCGof325kNIyuyUPjmcTWblVD/aEP6XhVT36MA7BFode9Bz +0TA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751307697; x=1751912497; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=mt5O7/7JEumjsAyKxjvlFipcH+4/5yB2S8im+OQhNPo=; b=dXP1/VT+E3msBOajRz7hs9gCSoJHK8zb6ECdUzo0m2ZjEqLCJlNKetFtBBqyOrzdht x2DyNPQdAOyw+f0ebroDxcu4beS6OTcHn6ymSaG5NxBzqYkXrR5gyrW1V9pHJR7ndqsU Q3kk+yt48DO7nDLCOr/ExhRWl3uNNUgjOQvv8s9qJqZmswXD2oW8qiCidzInWPmj8Xjt 6sPc8rTfaEXcyZsksrih8hhNx9IE1HchtDVqxqNzAcBdcIbgXT3fIcDrRc6sXyS2vS8z kVp0NDI59Mg2uMxGiy5UEOc7ehh9FQKw/yGyieL6dTvVc2sb+/eVsXlHgnlxQKFbHqUO YJ7w== X-Forwarded-Encrypted: i=1; AJvYcCV47NsyRoqLe0tgMhbGFSJtB1HhH4AL95HmemZazw3tVCnO8IUB4PeDAIQNQJASHUNJWbrNTGrd4TxcJrM=@vger.kernel.org, AJvYcCW7g9V3Yldrhxi+wJMXI5RC7OG5cEs33dJsHjNLZ/R+p0BVvczngYKlW+hvP71/YhIZm2yhxsniJkY1@vger.kernel.org X-Gm-Message-State: AOJu0Yxt2wpK9zCpFZLMBQb2YrCWhtRKqcP+swHRaARPWC12XRDdoWl8 isFGHyeaeI5HFeB9iw4xOKEnAdj8unG5+NB4q1ZqhUk0KOZZkivDeFTy X-Gm-Gg: ASbGncsKQM1Xs+iiRV0iTRBD6i9UYT6UM2unPvuLHi36kpVc93EEHW2LpHpQJ4d51Ro BmCYnOpkbHrYdYw8ItuxPbhOSZsfvlVNl20xseuGAokul9oejiQgKKSJ+5VN/nZ47GEhmCbUHqc R1+Kwix+/DX/42Br8JnZoy/XYT8uxKb/dfaDJTavQYXky0hvbr5eX2k0TLszeqodp2zQVAt5Tej ZJAJAXH7lf1cjcmlw2dNgO5qU4oO0+xCVtlpx94b/1gCE5CQGxyaJP6u+LoAvyazxntVXmvbjn+ 8issEcvEEaKIWuYDFXz5Mjq72pgmid9OulX24weN89zSGcs5RsHezXkK4XAV X-Google-Smtp-Source: AGHT+IFqsmBLHnSOIjXduuu6Gtg+JRUwYRfr6dqhcQB+Kjp/XASyizyvYC3WINP5R9Ajnd7huyBUVA== X-Received: by 2002:a0c:f093:0:b0:700:bc46:5355 with SMTP id 6a1803df08f44-700bc46546cmr135954696d6.28.1751307697397; Mon, 30 Jun 2025 11:21:37 -0700 (PDT) Received: from geday ([2804:7f2:800b:4851::dead:c001]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6fd772ff09csm71481116d6.95.2025.06.30.11.21.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jun 2025 11:21:36 -0700 (PDT) Date: Mon, 30 Jun 2025 15:21:30 -0300 From: Geraldo Nascimento To: linux-rockchip@lists.infradead.org Cc: Shawn Lin , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , Rick wertenbroek , Neil Armstrong , Valmantas Paliksa , linux-phy@lists.infradead.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v8 1/4] PCI: rockchip: Use standard PCIe defines Message-ID: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Current code uses custom-defined register offsets and bitfields for standard PCIe registers. Change to using standard PCIe defines. Since we are now using standard PCIe defines, drop unused custom-defined ones, which are now referenced from offset at added Capabilities Register. Suggested-By: Bjorn Helgaas Signed-off-by: Geraldo Nascimento --- drivers/pci/controller/pcie-rockchip-ep.c | 4 +- drivers/pci/controller/pcie-rockchip-host.c | 44 ++++++++++----------- drivers/pci/controller/pcie-rockchip.h | 12 +----- 3 files changed, 25 insertions(+), 35 deletions(-) diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/contro= ller/pcie-rockchip-ep.c index 55416b8311dd..300cd85fa035 100644 --- a/drivers/pci/controller/pcie-rockchip-ep.c +++ b/drivers/pci/controller/pcie-rockchip-ep.c @@ -518,9 +518,9 @@ static void rockchip_pcie_ep_retrain_link(struct rockch= ip_pcie *rockchip) { u32 status; =20 - status =3D rockchip_pcie_read(rockchip, PCIE_EP_CONFIG_LCS); + status =3D rockchip_pcie_read(rockchip, PCIE_EP_CONFIG_BASE + PCI_EXP_LNK= CTL); status |=3D PCI_EXP_LNKCTL_RL; - rockchip_pcie_write(rockchip, status, PCIE_EP_CONFIG_LCS); + rockchip_pcie_write(rockchip, status, PCIE_EP_CONFIG_BASE + PCI_EXP_LNKCT= L); } =20 static bool rockchip_pcie_ep_link_up(struct rockchip_pcie *rockchip) diff --git a/drivers/pci/controller/pcie-rockchip-host.c b/drivers/pci/cont= roller/pcie-rockchip-host.c index b9e7a8710cf0..65653218b9ab 100644 --- a/drivers/pci/controller/pcie-rockchip-host.c +++ b/drivers/pci/controller/pcie-rockchip-host.c @@ -40,18 +40,18 @@ static void rockchip_pcie_enable_bw_int(struct rockchip= _pcie *rockchip) { u32 status; =20 - status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS); + status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCT= L); status |=3D (PCI_EXP_LNKCTL_LBMIE | PCI_EXP_LNKCTL_LABIE); - rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS); + rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL); } =20 static void rockchip_pcie_clr_bw_int(struct rockchip_pcie *rockchip) { u32 status; =20 - status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS); + status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCT= L); status |=3D (PCI_EXP_LNKSTA_LBMS | PCI_EXP_LNKSTA_LABS) << 16; - rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS); + rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL); } =20 static void rockchip_pcie_update_txcredit_mui(struct rockchip_pcie *rockch= ip) @@ -269,7 +269,7 @@ static void rockchip_pcie_set_power_limit(struct rockch= ip_pcie *rockchip) scale =3D 3; /* 0.001x */ curr =3D curr / 1000; /* convert to mA */ power =3D (curr * 3300) / 1000; /* milliwatt */ - while (power > PCIE_RC_CONFIG_DCR_CSPL_LIMIT) { + while (power > FIELD_MAX(PCI_EXP_DEVCAP_PWR_VAL)) { if (!scale) { dev_warn(rockchip->dev, "invalid power supply\n"); return; @@ -278,10 +278,10 @@ static void rockchip_pcie_set_power_limit(struct rock= chip_pcie *rockchip) power =3D power / 10; } =20 - status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_DCR); - status |=3D (power << PCIE_RC_CONFIG_DCR_CSPL_SHIFT) | - (scale << PCIE_RC_CONFIG_DCR_CPLS_SHIFT); - rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_DCR); + status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_DEVCA= P); + status |=3D FIELD_PREP(PCI_EXP_DEVCAP_PWR_VAL, power); + status |=3D FIELD_PREP(PCI_EXP_DEVCAP_PWR_SCL, scale); + rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_DEVCAP); } =20 /** @@ -309,14 +309,14 @@ static int rockchip_pcie_host_init_port(struct rockch= ip_pcie *rockchip) rockchip_pcie_set_power_limit(rockchip); =20 /* Set RC's clock architecture as common clock */ - status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS); + status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCT= L); status |=3D PCI_EXP_LNKSTA_SLC << 16; - rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS); + rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL); =20 /* Set RC's RCB to 128 */ - status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS); + status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCT= L); status |=3D PCI_EXP_LNKCTL_RCB; - rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS); + rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL); =20 /* Enable Gen1 training */ rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE, @@ -341,9 +341,9 @@ static int rockchip_pcie_host_init_port(struct rockchip= _pcie *rockchip) * Enable retrain for gen2. This should be configured only after * gen1 finished. */ - status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS); + status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKC= TL); status |=3D PCI_EXP_LNKCTL_RL; - rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS); + rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL= ); =20 err =3D readl_poll_timeout(rockchip->apb_base + PCIE_CORE_CTRL, status, PCIE_LINK_IS_GEN2(status), 20, @@ -380,15 +380,15 @@ static int rockchip_pcie_host_init_port(struct rockch= ip_pcie *rockchip) =20 /* Clear L0s from RC's link cap */ if (of_property_read_bool(dev->of_node, "aspm-no-l0s")) { - status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LINK_CAP); - status &=3D ~PCIE_RC_CONFIG_LINK_CAP_L0S; - rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LINK_CAP); + status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKC= AP); + status &=3D ~PCI_EXP_LNKCAP_ASPM_L0S; + rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCAP= ); } =20 - status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_DCSR); - status &=3D ~PCIE_RC_CONFIG_DCSR_MPS_MASK; - status |=3D PCIE_RC_CONFIG_DCSR_MPS_256; - rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_DCSR); + status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_DEVCT= L); + status &=3D ~PCI_EXP_DEVCTL_PAYLOAD; + status |=3D PCI_EXP_DEVCTL_PAYLOAD_256B; + rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_DEVCTL); =20 return 0; err_power_off_phy: diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controlle= r/pcie-rockchip.h index 5864a20323f2..f5cbf3c9d2d9 100644 --- a/drivers/pci/controller/pcie-rockchip.h +++ b/drivers/pci/controller/pcie-rockchip.h @@ -155,17 +155,7 @@ #define PCIE_EP_CONFIG_DID_VID (PCIE_EP_CONFIG_BASE + 0x00) #define PCIE_EP_CONFIG_LCS (PCIE_EP_CONFIG_BASE + 0xd0) #define PCIE_RC_CONFIG_RID_CCR (PCIE_RC_CONFIG_BASE + 0x08) -#define PCIE_RC_CONFIG_DCR (PCIE_RC_CONFIG_BASE + 0xc4) -#define PCIE_RC_CONFIG_DCR_CSPL_SHIFT 18 -#define PCIE_RC_CONFIG_DCR_CSPL_LIMIT 0xff -#define PCIE_RC_CONFIG_DCR_CPLS_SHIFT 26 -#define PCIE_RC_CONFIG_DCSR (PCIE_RC_CONFIG_BASE + 0xc8) -#define PCIE_RC_CONFIG_DCSR_MPS_MASK GENMASK(7, 5) -#define PCIE_RC_CONFIG_DCSR_MPS_256 (0x1 << 5) -#define PCIE_RC_CONFIG_LINK_CAP (PCIE_RC_CONFIG_BASE + 0xcc) -#define PCIE_RC_CONFIG_LINK_CAP_L0S BIT(10) -#define PCIE_RC_CONFIG_LCS (PCIE_RC_CONFIG_BASE + 0xd0) -#define PCIE_EP_CONFIG_LCS (PCIE_EP_CONFIG_BASE + 0xd0) +#define PCIE_RC_CONFIG_CR (PCIE_RC_CONFIG_BASE + 0xc0) #define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 (PCIE_RC_CONFIG_BASE + 0x90c) #define PCIE_RC_CONFIG_THP_CAP (PCIE_RC_CONFIG_BASE + 0x274) #define PCIE_RC_CONFIG_THP_CAP_NEXT_MASK GENMASK(31, 20) --=20 2.49.0 From nobody Wed Oct 8 07:40:06 2025 Received: from mail-qk1-f178.google.com (mail-qk1-f178.google.com [209.85.222.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 890DB19994F; Mon, 30 Jun 2025 18:21:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.222.178 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751307715; cv=none; b=BzG6qorG3pynIAsDdKYwX4rujKp/wT55YtLM1VLDtwjej0GeEpwqseVFF9/EmjGhruvwxTIetU7SFQX2eUph3G3o82peFPbg5zFSIDw/9FfPy5k1sSI05N3zg4bx4/aFiC4QCLWy5EWfEYEqgIYR3gKux3MdwaSeFrt8MuS9r+E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751307715; c=relaxed/simple; bh=TMyeQZWAOAuTwvIXse5kaD0KDoeWmnfqoNhsSOfoCv0=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=gKKU1FtLTCNDbm98im/M5W5dGcx0wMOl7KG+q3erVjRBr6UbMMrkSe6RjOmW3EChWjh/EIF45cTNiXe1P/mScx5Ny/1Q18kVZ6Hc8h4QbPLQVreTKISsdRVjUWncfXTKQgk6RiUJ140DYBmnl4JjeAR8ndJo0AFIvSmzCmfwQTQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=O7grCwGu; arc=none smtp.client-ip=209.85.222.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="O7grCwGu" Received: by mail-qk1-f178.google.com with SMTP id af79cd13be357-7d402c901cbso437817185a.3; Mon, 30 Jun 2025 11:21:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1751307712; x=1751912512; darn=vger.kernel.org; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=rtc4GJjYIzCc3h+Hv3COhOArvofrVT3IhU2L5CEaYbA=; b=O7grCwGuem3TmJHIbXQFr12Tt4n/5zBjaa0WZiUm6IoL4+ZQ+ri6910rscLRDwOra2 suYmMg2LSEd+DSZWtQElK5EQuyUmUEmTNoJh6HsWqainBylxL1tDEixqKJ3fQMZmraPY VWg2bYDjJsegqwPrzJRg3HXesQk6+hc/96VsZGMp2ui0zaK8OE+ZexnXD/0/ABPO1si8 pduzLHG52Xl8vUONZBNzPbyPJW+PhHjxnKz12C/IoyLb0O25A+MFGkT1VXqeG+LlDp3a 5C5sAD49BJJtAKG54sZYQ8AqivAgqvGTK9yT9qg+6aaZzR3yVLsVxijMhajrVg0XSJtm GSkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751307712; x=1751912512; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=rtc4GJjYIzCc3h+Hv3COhOArvofrVT3IhU2L5CEaYbA=; b=Ap39uUXnGq9sDbWf/B1VqMp3Bfl42Z5h6rarnbMm9jl/68IOO7v2lViewzwyAI6LJq n+pVYkI+TRUu49dmQMA5yVMDjcn+e9zGSvpxNTdOVNv5S2pCfGD3tt95omWwOyu+VSj8 F4NutuywNqYirYEzeUvePkD6HKsy47gwWX54FDmQBLzSOJMRV9mlUY5KznKxcDQECdJx Qq5YtwiYjmFJNFhAj/tPXPTUYwpwiUZdY+vcSzJDRAZqrXmAm/R0qtVQ1+xFpmhD/n1p lOZTQpx8wkAS6Em2BCSExn+n8Ec9tn5adU6LYp+oGxOfgVbIoVcc+WoX2D/By69tI4eJ ovvw== X-Forwarded-Encrypted: i=1; AJvYcCUsEkbspo2Var1PtfaSKqTIq3WLe0V5diwS8eJMuVQ4StqG8zKKp9OItYDlfyqyni40tojm/+0XERaS@vger.kernel.org, AJvYcCXgDqBvL7Xtoh+W4BmpvX9Kqtc3VMOH4V1C0xyl58j0l+0mEMgr9arGNwijgGusZRtLGy7oBKIjz5C3jfg=@vger.kernel.org X-Gm-Message-State: AOJu0YzR+eocnXIER/Z+Hj35aNYiLP8G8wk+3M9r4yKvn9eRhgVmDXSh iMr3Ezt/V+EfEJrKdRehhiCop9UyBORgMCZfO8igSHFoQEfw1LKN2CTi X-Gm-Gg: ASbGnctDiRfE8MVOso1aY3c1x1XfmbyToMcVCvSm215aqKzyslNLlSfPuy3tPRuksb8 IT4gRDmmOKeVEMNUqPD1eijNx5Fi7OZuH9Pa+xe1cysO5fjwwV3FlNPbVgRbLa2V4RltdH8oaOl +XZY9okvgGCML4DdHXDSIAMJsjWf/EMx65G4GUHVb9UwXs85736iCfBOrp9xquoC/Yc+zHBeOWu nB+wE4bFo7XOwFkBVgSAJbTW2g7DW3N0ddkdOaCLwMwgXm+zth4CnyA+84Gz3Ku+W/4KcLnTOBH zPDcCaoQOFMJpz8lT/FwBzrxc3qca42HpMUcmShtAbg4beg83w== X-Google-Smtp-Source: AGHT+IGFXYnf/fQlbC+mgz+nw0wr9dI6eGoPSadvUYNWqwtuJXJ0qea9pKfxGAKJwViMNZt8vtKyPQ== X-Received: by 2002:a05:620a:2910:b0:7d3:8da2:e9e2 with SMTP id af79cd13be357-7d443990ab8mr2006431585a.27.1751307712420; Mon, 30 Jun 2025 11:21:52 -0700 (PDT) Received: from geday ([2804:7f2:800b:4851::dead:c001]) by smtp.gmail.com with ESMTPSA id af79cd13be357-7d443201824sm635775485a.53.2025.06.30.11.21.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jun 2025 11:21:52 -0700 (PDT) Date: Mon, 30 Jun 2025 15:21:45 -0300 From: Geraldo Nascimento To: linux-rockchip@lists.infradead.org Cc: Shawn Lin , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , Rick wertenbroek , Neil Armstrong , Valmantas Paliksa , linux-phy@lists.infradead.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v8 2/4] PCI: rockchip: Set Target Link Speed before retraining Message-ID: <0afa6bc47b7f50e2e81b0b47d51c66feb0fb565f.1751307390.git.geraldogabriel@gmail.com> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Current code may fail 5.0GT/s retraining if Target Link Speed is set to 2.5 GT/s in Link Control and Status Register 2. Set it to 5.0 GT/s accordingly. Tested-by: Robin Murphy Signed-off-by: Geraldo Nascimento --- drivers/pci/controller/pcie-rockchip-host.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/pci/controller/pcie-rockchip-host.c b/drivers/pci/cont= roller/pcie-rockchip-host.c index 65653218b9ab..25890f6c0e17 100644 --- a/drivers/pci/controller/pcie-rockchip-host.c +++ b/drivers/pci/controller/pcie-rockchip-host.c @@ -341,6 +341,10 @@ static int rockchip_pcie_host_init_port(struct rockchi= p_pcie *rockchip) * Enable retrain for gen2. This should be configured only after * gen1 finished. */ + status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKC= TL2); + status &=3D ~PCI_EXP_LNKCTL2_TLS; + status |=3D PCI_EXP_LNKCTL2_TLS_5_0GT; + rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL= 2);=09 status =3D rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKC= TL); status |=3D PCI_EXP_LNKCTL_RL; rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL= ); --=20 2.49.0 From nobody Wed Oct 8 07:40:06 2025 Received: from mail-qk1-f177.google.com (mail-qk1-f177.google.com [209.85.222.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C974219994F; Mon, 30 Jun 2025 18:22:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.222.177 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751307731; cv=none; b=Ur6b0bagglpokkulcLSduyuqOEtwfEpt666ZhBz6c2RI2UHOozI0P8pQM3GyN790qiHEO4qY9zUL3GGb1ATGW7v7lmAIbPBH/pSHZSo3ARF5rEyUmsrqoZKrb/l1raWXyFKtEfko/abUZie8xCAyyAOnDf4FAwBaYZMch+7esZ8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751307731; c=relaxed/simple; bh=oAZISEWKYtSLKKLeFTIvOInH3R5sB+cLBcS8i1Z7lWU=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=G3kGEwxN3jScGrD0PeLuIpr15t8Uubizu/5OTu4oS3uMqyiKqDHDZ6zTlLIbcAnK2QZa3Z5LjM1OeDKFce9o+qART+S43hQuJK8GblDhpL2fAF1CrW6cTLonz1irOEHrASmlYU94ZBiLMO/TLyEHGNgpr8oq3eyIjuYE+F9FHPo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=dlfNXbtS; arc=none smtp.client-ip=209.85.222.177 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="dlfNXbtS" Received: by mail-qk1-f177.google.com with SMTP id af79cd13be357-7d467a1d9e4so1473885a.0; Mon, 30 Jun 2025 11:22:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1751307729; x=1751912529; darn=vger.kernel.org; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=hXeS77/kGdjI+bypW2RtRvB0CsC580lSSASyDeC37uE=; b=dlfNXbtS7iEZrQUOS3RcnTm575ikmxZQoaaCXaYwRLat591T5uPRegd9CGPl3jmVWX GLA6YPhTf8RQP8p8Hr+TRViO37eamQjB9Vh9sCTTEYdqYEsqI4++XhUnrLEczaPMkrNa SCM2eX8eaYN4AM5mSJv9fXpHvPNfNjNr1NE5HzP9NVHAmcJ6pZ4Pt+ZE4Id5QHxjAhDV f6bFQDoVrHWy6DE0nzD5sNVlXG8cz2eNuP02X3nVst+NgP991U6RXZZBYwFTFoamRKnA cPUdZ8ri6oc/9a3NOU/cLU1T/YIKD8kr2MapTpHbuJFQ4fhYmDNb7PeYRVB7Ouk4Xw+G +ryA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751307729; x=1751912529; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=hXeS77/kGdjI+bypW2RtRvB0CsC580lSSASyDeC37uE=; b=ZtmrW6yJ/7kg0gxRDxI9Be65go/Gj+1DD2lD7HFm9G0dW2TRjxGLxjCh76nrFLCwYA imFj5UVuJSW0BLXf7DqkHWdDfvVbqjmlqI9ywekE0k/V4y9uJ1PnhQZKvFhUaV8pbwdj o9iURMT/1ccG1x+bYnAzYz76XtaxIvL0r5uG7KwBmMg07dyD+lY7zLVeXEKx5Njg1o2m xBkG125B4cJsZ7KJzOza0IiXd0QZiEomNHV/ahfKUpbC25kb6bAy+aE1Z8gDJ9riiwl6 SpBhRVu8mAH04aguw457bUbKO0xvEhpwSpxShgPGyzVf1/MVpPkdc31z6hP35PPu2FyY 8hRw== X-Forwarded-Encrypted: i=1; AJvYcCUFiZtv4pG1OiGXqYNkutz5BsgVyZDe6Q2w5xQHz2QPWEAZx1/5qzwiVX16UjAhwIq9l4lt+oyTo5zOP50=@vger.kernel.org, AJvYcCX16hP4ktnTpKS5BdprQqfXjWVSUG5G4BcgvVT/coV0Pzw1Au3C8ICQA64Me0Qx3MbbzgNeE4/W1pgl@vger.kernel.org X-Gm-Message-State: AOJu0YyOK0Hyjmotk8fJfu9oBqZQsFSmi+nsJjpjqWyYws37OdOYDZrR spXqpjdjI0BEeVZcfV1WPuzsg+ckgKFjn+UQhqaiiSbJuS/toZau9Fb9 X-Gm-Gg: ASbGnctlada6NkHTAEdw7LySar+DZlRdSvQYYZbrUm/U59Yq0P4uAOHGbSRVVkqjwsY cgHYEiaMJCPFZJ37sWkB0FDQIzyGmeC30jPDRRHpgH6BQP3AqUnTYDyHp5LuTzge95QYwzBrMJX JH6E3D9Y061EB3za8yfYLKkBwKxn/pB6EKHsisyw8aiwVWwiUjT2aHjn8oL1r7uKijwE3W8mvr3 uJWtgNHNZp+pjAUQqksDdcUE5ry2Td9/jWVag+HWb1IfoGYS7Gwa1isXjclQoi0MMMQsNDWrjpW Q2TFrwfDMzjEmr8UnS9WpIGYrshUAaN4oiF3LVbQ6+FeBNR4uA== X-Google-Smtp-Source: AGHT+IEnm8oFpdWAiHPxW8hDpcLXgQQ87NpyPWpQOIa8k1ocotGVAZeJxuGqw1MnkmYiEaJ1w2Cfrg== X-Received: by 2002:a05:620a:290f:b0:7d4:4484:751d with SMTP id af79cd13be357-7d466de3918mr75448485a.18.1751307728715; Mon, 30 Jun 2025 11:22:08 -0700 (PDT) Received: from geday ([2804:7f2:800b:4851::dead:c001]) by smtp.gmail.com with ESMTPSA id af79cd13be357-7d4431346absm642198185a.23.2025.06.30.11.22.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jun 2025 11:22:08 -0700 (PDT) Date: Mon, 30 Jun 2025 15:22:01 -0300 From: Geraldo Nascimento To: linux-rockchip@lists.infradead.org Cc: Shawn Lin , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , Rick wertenbroek , Neil Armstrong , Valmantas Paliksa , linux-phy@lists.infradead.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v8 3/4] phy: rockchip-pcie: Enable all four lanes if required Message-ID: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Current code enables only Lane 0 because pwr_cnt will be incremented on first call to the function. Let's reorder the enablement code to enable all 4 lanes through GRF. Reviewed-by: Neil Armstrong Reviewed-by: Robin Murphy Signed-off-by: Valmantas Paliksa Signed-off-by: Geraldo Nascimento --- drivers/phy/rockchip/phy-rockchip-pcie.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-pcie.c b/drivers/phy/rockchi= p/phy-rockchip-pcie.c index bd44af36c67a..f22ffb41cdc2 100644 --- a/drivers/phy/rockchip/phy-rockchip-pcie.c +++ b/drivers/phy/rockchip/phy-rockchip-pcie.c @@ -160,6 +160,12 @@ static int rockchip_pcie_phy_power_on(struct phy *phy) =20 guard(mutex)(&rk_phy->pcie_mutex); =20 + regmap_write(rk_phy->reg_base, + rk_phy->phy_data->pcie_laneoff, + HIWORD_UPDATE(!PHY_LANE_IDLE_OFF, + PHY_LANE_IDLE_MASK, + PHY_LANE_IDLE_A_SHIFT + inst->index)); + if (rk_phy->pwr_cnt++) { return 0; } @@ -176,12 +182,6 @@ static int rockchip_pcie_phy_power_on(struct phy *phy) PHY_CFG_ADDR_MASK, PHY_CFG_ADDR_SHIFT)); =20 - regmap_write(rk_phy->reg_base, - rk_phy->phy_data->pcie_laneoff, - HIWORD_UPDATE(!PHY_LANE_IDLE_OFF, - PHY_LANE_IDLE_MASK, - PHY_LANE_IDLE_A_SHIFT + inst->index)); - /* * No documented timeout value for phy operation below, * so we make it large enough here. And we use loop-break --=20 2.49.0 From nobody Wed Oct 8 07:40:06 2025 Received: from mail-qv1-f41.google.com (mail-qv1-f41.google.com [209.85.219.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 57D3E1C8631; Mon, 30 Jun 2025 18:22:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.219.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751307746; cv=none; b=WUC/h+vyYb5s208SdKivZEPQ8XLYFRNekI63OtVxflFChjqSgM4nIkpFXlvrPQomHP4ifVPH4dGoNPwDCkqaOjwLvvhwu1sQnYn6iHe85+pzPbakctdTpTHaZnneqly38c2v7CpLo39iqwB6XqdywQeUgj9sAlJMzegnFadh4IY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751307746; c=relaxed/simple; bh=CNxK0279ukfbz74d9Orf//2RsynVo3ZY3ta36YHi0ZM=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=ad2YfdfTXlrHGDK7pih/4w76LTX0luC7w4PAukgew2gG//6+pcjRS3Sx5XJtsRttVMZf704rhT70GT2+W/U+7RYZs0jaS4B3BTSG9OdUJ+9FlYcdFjJoERu8JpBDmAVDKVpjgsEiCZAQMIL96edl+401BF8i7lNCXxk3FwlHY0Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=IFrMObeK; arc=none smtp.client-ip=209.85.219.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="IFrMObeK" Received: by mail-qv1-f41.google.com with SMTP id 6a1803df08f44-6fad3400ea3so43584496d6.0; Mon, 30 Jun 2025 11:22:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1751307744; x=1751912544; darn=vger.kernel.org; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=rMkTHKD3jio2hpq8BtE0DToF1CwksemxWLN6Z8dMYEk=; b=IFrMObeKHEOahR/xRmcWFg2dH1j+o7EVj9V2mFrqswyS35GNkkQtXYZENywKbvLviN 13qYjHsO++JaZm3R6KTgQ0H8X6Svq+TFssyWt2+KMqwdYKgwCFSIgRw7xaAyrQImIDU1 OxX4WEtpZdL2Obq3pVm10s6hgwkCgNLGU8xHgvO3GPbhTMpQvaP4vtPYmBY9MzAICjmT VCgJZxgx6JP+oEXOf4cPGwhuQ/p9pbVwOzdyhopoa/t3AB5mPl0LvrznpVpO7/WrBCVi PUEdx17K7W9TVG+NyeIWQ37nvDNtnJkNzQ0091O47Z8a6X+gXGdeZv/1UuysMmqTdOOU +xgQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1751307744; x=1751912544; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=rMkTHKD3jio2hpq8BtE0DToF1CwksemxWLN6Z8dMYEk=; b=GvOf/1OreHzgrVxOx61TDTsoOryxh5bHtjTGVc7Tnz1oSM/4m+hzSjz7g2W//njjFp v/h4T3g7k4heNwrNpNFnr/7PxYLdWOXLYV7r3x+a9ZQqKAx1QfOCCn6NpaeaNJi9tOqX JcGnW0wT/UjW9wE/YOeVFfwbwtElF8cr90KFnm5DOVz+ai5wG19CmC4R85vXVJn+0E08 HKa1erXk04mXcypgKkkypcQ7LBJbsvzzUklYg9Wi0VWld77Y92ywIsXeJ3s0Q7yBnACP h5KR5JnmLrevYTO28MY/U1w039ZLkiWzeXzbQciQpFZ2PKMuYtY7noFgOMIzf6FU/AqY tcpQ== X-Forwarded-Encrypted: i=1; AJvYcCV9QjsN8P0Aam+uXDPJFxlKeItHP6ZOGM2FVve/fhqeRqstb360gtRUE2/CxXVa92yfd1z8EDnrzi3g@vger.kernel.org, AJvYcCVuKsZk45KZuXhEYxPkK7ZDY6zVj4wvZR9MJM+X5pOSwOPlikEQ9vbEyH9zX8DoJt9TBuVjwaAdFUzqsXI=@vger.kernel.org X-Gm-Message-State: AOJu0YzLtnrxMdCgaM8kwT5hRqBnUUaQatD9BP4zwEPDB6hJcUFn6h3/ 2RHh9QuDS1sAzPGN2voQRq+Fm12qCjZOVuLBItq12Rm+SqHDxvIjz+SD X-Gm-Gg: ASbGncudOiyorxG21v8h+teIMN384DpGmPt6pJWYGVNL/3t61k1wz9rYsZV1/0KgXo4 w6kIHN9WOF0XSzphuiJC++TcR0CYpb5yU7bcckThWcVP1xm64oYdGwBQK96QdpNZH5cvAJmt1wS Bi2BHO0LQoa5iaYMuasf4F5fWE4GyjaTQu8uAYkiQ8oCuQbmfkQPbvgApolkAkjVOsrqbviZA1I L4K+UT28jQCU+AElG232GUtKFCZU4uyi9a4LMW7JV1z5nZfGVTrrAxFEpcXiy4Lb200RlMCXnxV rArSy5rLwqzXT0HwBBrpHrdRvzuiCUaRm/IQnqxDQS/DyuQ17CM3r6+caOLp X-Google-Smtp-Source: AGHT+IGiwj5LxtClCIDG815VfHCCgo1NQzaiahcgS1gasNLfX8v0zIb2JwxXV6ze0QIzIZrdOwwtAQ== X-Received: by 2002:a05:6214:468b:b0:6fc:ff41:8eb7 with SMTP id 6a1803df08f44-700035b783bmr287653906d6.31.1751307744228; Mon, 30 Jun 2025 11:22:24 -0700 (PDT) Received: from geday ([2804:7f2:800b:4851::dead:c001]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6fd771bc01bsm70953466d6.40.2025.06.30.11.22.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jun 2025 11:22:23 -0700 (PDT) Date: Mon, 30 Jun 2025 15:22:17 -0300 From: Geraldo Nascimento To: linux-rockchip@lists.infradead.org Cc: Shawn Lin , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , Rick wertenbroek , Neil Armstrong , Valmantas Paliksa , linux-phy@lists.infradead.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v8 4/4] phy: rockchip-pcie: Properly disable TEST_WRITE strobe signal Message-ID: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" pcie_conf is used to touch TEST_WRITE strobe signal. This signal should be enabled, a little time waited, and then disabled. Current code clearly was copy-pasted and never disables the strobe signal. Adjust the define. While at it, remove PHY_CFG_RD_MASK which has been unused since 64cdc0360811 ("phy: rockchip-pcie: remove unused phy_rd_cfg function"). Reviewed-by: Neil Armstrong Signed-off-by: Geraldo Nascimento --- drivers/phy/rockchip/phy-rockchip-pcie.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-pcie.c b/drivers/phy/rockchi= p/phy-rockchip-pcie.c index f22ffb41cdc2..4e2dfd01adf2 100644 --- a/drivers/phy/rockchip/phy-rockchip-pcie.c +++ b/drivers/phy/rockchip/phy-rockchip-pcie.c @@ -30,9 +30,8 @@ #define PHY_CFG_ADDR_SHIFT 1 #define PHY_CFG_DATA_MASK 0xf #define PHY_CFG_ADDR_MASK 0x3f -#define PHY_CFG_RD_MASK 0x3ff #define PHY_CFG_WR_ENABLE 1 -#define PHY_CFG_WR_DISABLE 1 +#define PHY_CFG_WR_DISABLE 0 #define PHY_CFG_WR_SHIFT 0 #define PHY_CFG_WR_MASK 1 #define PHY_CFG_PLL_LOCK 0x10 --=20 2.49.0