From nobody Wed Oct 8 09:26:32 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 14E51257AFE; Mon, 30 Jun 2025 10:26:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751279187; cv=none; b=XwnbDh4KxNGNIozLsvFQq0idpWfCXJ4N+0MENGP31hPQuU1rT/Qa6n+v4/q+vJ0BXtFDkFPxE6v/hciksxRj6+itfHcoiZMWBu1iSGnWTdhgWITcKaMjA8lEZy5/DVcIan3CmOaeq3/w4x+EbnIPU0dG1ORYmCqp7LZVLSDkB5c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751279187; c=relaxed/simple; bh=bBQTqj9wATbwai5CvTj+asfYGG1tNQD2MXt4GzwC+20=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=YWHkPKYorTscE0jPGhaSU3f74F9FQXrFvbME+8Rk96B30KilmwJMn9c2gfXAs2PIUOIozzPm0Zi9cRep5bXUvisWtFWUNYSZDTsVPeSgbk1tpSxt784So9Z/8uwLfb8USpRqw5JrPdYvVmI6m9fA5ibW4nEwix9M/NTfQAfUY+s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=r0sKDAWt; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=djj0xRdI; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="r0sKDAWt"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="djj0xRdI" From: Nam Cao DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1751279184; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=8ZXndMKqkKbWXcshV9ZDUQfsiDhGhb4IBpm3R0c8Fz0=; b=r0sKDAWtsE//WnhojxxAV5N6XTMPGgUYPFs47iu8OhcxS9opTW3ZuyqC9bQQZuOGU3KnBz 28PMmXCCkYPBIDC6SugJ3fbHTLVXDowndEeJUyB2AhQE6PODMQMZnrA4n+vPdZdNHPOzxL bovNQSypDy5Md3RUsxyOgzM6NgenzqEmwbHTySvrtS9KY5LgfVKGj8faCopcwtwdUygMwJ hcN+XZJXWBAJXEksL0+nj+aMCRYq/AmtwHTcXPVEhasU6EN5AMe/fGKmIRpZolgJg7PQq+ EiSjYXO3rhHTcIikfHVBPZnbM5omQlNaAFY/ccmavuKpnXenUzXpHVYV57fUtg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1751279184; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=8ZXndMKqkKbWXcshV9ZDUQfsiDhGhb4IBpm3R0c8Fz0=; b=djj0xRdIJQaXGL4WHlfd5pVUlPKCfRbCXvKmYzqmotz8pHlDda+OckcIU3oeEB4SUROkPK 8s3gAZUmAwsyGFDA== To: "K . Y . Srinivasan" , Marc Zyngier , Haiyang Zhang , Wei Liu , Dexuan Cui , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H . Peter Anvin" , linux-hyperv@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Nam Cao , kernel test robot Subject: [PATCH v2 1/2] irqchip/irq-msi-lib: Select CONFIG_GENERIC_MSI_IRQ Date: Mon, 30 Jun 2025 12:26:14 +0200 Message-Id: In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" irq-msi-lib directly uses struct msi_domain_info and MSI_FLAG_ALLOC_SIMPLE_MSI_DESCS (and likely more) which are only available when CONFIG_GENERIC_MSI_IRQ=3Dy. However, no dependency is specified. If it happens that CONFIG_IRQ_MSI_LIB=3Dy while CONFIG_GENERIC_MSI_IRQ=3Dn, the kernel fails to build. Specify this dependency and fix the build. Fixes: 72e257c6f058 ("irqchip: Provide irq-msi-lib") Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202506282256.cHlEHrdc-lkp@int= el.com/ Signed-off-by: Nam Cao --- drivers/irqchip/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 0d196e4471426..c3928ef793449 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -74,6 +74,7 @@ config ARM_VIC_NR =20 config IRQ_MSI_LIB bool + select GENERIC_MSI_IRQ =20 config ARMADA_370_XP_IRQ bool --=20 2.39.5 From nobody Wed Oct 8 09:26:32 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5AA3623E358; Mon, 30 Jun 2025 10:26:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751279188; cv=none; b=inhWksVm9AqXFJpogfCuh2ONpCkQnNACTYINpKy4IHmbUcrwwY4Ohcc4tYHout1aoLQ6r9WQTAtnqZtlRKxyuJp2kPNtYxJoamlKj1Gn1XZz0F3FMwZsaq8ATqXm8S0UIzrfIQFZU2rExxjwHvNpWnxlwQlqEgBh6r9vR8Q/dJk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751279188; c=relaxed/simple; bh=SN/vAaTyYzDQhlYaCs17NxtmkAdA7yz8PzP/EMg93rU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=eWuedIjAp2aeVnuM/u0Wkl5bzmu54mEX6vWRis3su42oT/A+kOYYNgMrC7uadhxuyMxrUBhieh0UkiT2G/JvimzC+zjhliyh4z/qaJPyB7jSRU6M2986F7sO4Q3ffLN1Z7FMEdB1BxBXTX6qh4pXkExXRN+abq6XEQgqZoM/Tcs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=iGKH7SSu; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=RpAIem8w; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="iGKH7SSu"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="RpAIem8w" From: Nam Cao DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1751279184; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=yOUQVm3BJSm9B+6JOLgVfo34U1Tc6lgjFygyierZSZw=; b=iGKH7SSu5vTHFP3nzhuB20bzyZTsOW9E1xKpfukwX7bxPa0JrjurRxDvgse5kXbR8G8Dmy izAKLMJjCm7s9YR/V+7/YVOZ24kFGnA/V+JePBHXWCy7rTOcGjS9gxLiiBO30y4dnIpeVW LDxTGsDNqnXl5XUclMq85kBdhNjx2j7nwI0yDwlm7+rkScg3s3guckB5umcMJmBgHme1En 0tDmpGR+3U0O61MOVFrQhqUNk2gy/oQjiWYjBQz5mTG44aMlmz4hVW9ZTGTEYtjY0nd2uD z1Q6c4zEnoo/fnQjuJodGYQIlrMwk1s1rHHEGv4Cgu52piSntrnbsGrGtV7NBg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1751279184; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=yOUQVm3BJSm9B+6JOLgVfo34U1Tc6lgjFygyierZSZw=; b=RpAIem8wcOs3dVEz+DJK+TMZ79X8xVp2FthISR5jXA7X4CbIDrWYRkyCdgBA5efRL1zLbS FOHhJ+FjGVzNCiCQ== To: "K . Y . Srinivasan" , Marc Zyngier , Haiyang Zhang , Wei Liu , Dexuan Cui , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H . Peter Anvin" , linux-hyperv@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Nam Cao Subject: [PATCH v2 2/2] x86/hyperv: Switch to msi_create_parent_irq_domain() Date: Mon, 30 Jun 2025 12:26:15 +0200 Message-Id: <5c0ada725449176dfeeb1f7aa98c324066c39d2c.1751277765.git.namcao@linutronix.de> In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move away from the legacy MSI domain setup, switch to use msi_create_parent_irq_domain(). While doing the conversion, I noticed that hv_irq_compose_msi_msg() is doing more than it is supposed to (composing message content). The interrupt allocation bits should be moved into hv_msi_domain_alloc(). However, I have no hardware to test this change, therefore I leave a TODO note. Signed-off-by: Nam Cao --- arch/x86/hyperv/irqdomain.c | 111 ++++++++++++++++++++++++------------ drivers/hv/Kconfig | 1 + 2 files changed, 77 insertions(+), 35 deletions(-) diff --git a/arch/x86/hyperv/irqdomain.c b/arch/x86/hyperv/irqdomain.c index 31f0d29cbc5e3..9b3b65ffbd2e2 100644 --- a/arch/x86/hyperv/irqdomain.c +++ b/arch/x86/hyperv/irqdomain.c @@ -10,6 +10,7 @@ =20 #include #include +#include #include =20 static int hv_map_interrupt(union hv_device_id device_id, bool level, @@ -276,59 +277,99 @@ static void hv_teardown_msi_irq(struct pci_dev *dev, = struct irq_data *irqd) hv_status_err(status, "\n"); } =20 -static void hv_msi_free_irq(struct irq_domain *domain, - struct msi_domain_info *info, unsigned int virq) -{ - struct irq_data *irqd =3D irq_get_irq_data(virq); - struct msi_desc *desc; - - if (!irqd) - return; - - desc =3D irq_data_get_msi_desc(irqd); - if (!desc || !desc->irq || WARN_ON_ONCE(!dev_is_pci(desc->dev))) - return; - - hv_teardown_msi_irq(to_pci_dev(desc->dev), irqd); -} - /* * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, * which implement the MSI or MSI-X Capability Structure. */ static struct irq_chip hv_pci_msi_controller =3D { .name =3D "HV-PCI-MSI", - .irq_unmask =3D pci_msi_unmask_irq, - .irq_mask =3D pci_msi_mask_irq, .irq_ack =3D irq_chip_ack_parent, - .irq_retrigger =3D irq_chip_retrigger_hierarchy, .irq_compose_msi_msg =3D hv_irq_compose_msi_msg, - .irq_set_affinity =3D msi_domain_set_affinity, - .flags =3D IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MOVE_DEFERRED, + .irq_set_affinity =3D irq_chip_set_affinity_parent, }; =20 -static struct msi_domain_ops pci_msi_domain_ops =3D { - .msi_free =3D hv_msi_free_irq, - .msi_prepare =3D pci_msi_prepare, +static bool hv_init_dev_msi_info(struct device *dev, struct irq_domain *do= main, + struct irq_domain *real_parent, struct msi_domain_info *info) +{ + struct irq_chip *chip =3D info->chip; + + if (!msi_lib_init_dev_msi_info(dev, domain, real_parent, info)) + return false; + + chip->flags |=3D IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MOVE_DEFERRED; + + info->ops->msi_prepare =3D pci_msi_prepare; + + return true; +} + +#define HV_MSI_FLAGS_SUPPORTED (MSI_GENERIC_FLAGS_MASK | MSI_FLAG_PCI_MSIX) +#define HV_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF= _CHIP_OPS) + +static struct msi_parent_ops hv_msi_parent_ops =3D { + .supported_flags =3D HV_MSI_FLAGS_SUPPORTED, + .required_flags =3D HV_MSI_FLAGS_REQUIRED, + .bus_select_token =3D DOMAIN_BUS_NEXUS, + .bus_select_mask =3D MATCH_PCI_MSI, + .chip_flags =3D MSI_CHIP_FLAG_SET_ACK, + .prefix =3D "HV-", + .init_dev_msi_info =3D hv_init_dev_msi_info, }; =20 -static struct msi_domain_info hv_pci_msi_domain_info =3D { - .flags =3D MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | - MSI_FLAG_PCI_MSIX, - .ops =3D &pci_msi_domain_ops, - .chip =3D &hv_pci_msi_controller, - .handler =3D handle_edge_irq, - .handler_name =3D "edge", +static int hv_msi_domain_alloc(struct irq_domain *d, unsigned int virq, un= signed int nr_irqs, + void *arg) +{ + /* + * TODO: The allocation bits of hv_irq_compose_msi_msg(), i.e. everything= except + * entry_to_msi_msg() should be in here. + */ + + int ret; + + ret =3D irq_domain_alloc_irqs_parent(d, virq, nr_irqs, arg); + if (ret) + return ret; + + for (int i =3D 0; i < nr_irqs; ++i) { + irq_domain_set_info(d, virq + i, 0, &hv_pci_msi_controller, NULL, + handle_edge_irq, NULL, "edge"); + } + return 0; +} + +static void hv_msi_domain_free(struct irq_domain *d, unsigned int virq, un= signed int nr_irqs) +{ + for (int i =3D 0; i < nr_irqs; ++i) { + struct irq_data *irqd =3D irq_domain_get_irq_data(d, virq); + struct msi_desc *desc; + + desc =3D irq_data_get_msi_desc(irqd); + if (!desc || !desc->irq || WARN_ON_ONCE(!dev_is_pci(desc->dev))) + continue; + + hv_teardown_msi_irq(to_pci_dev(desc->dev), irqd); + } + irq_domain_free_irqs_top(d, virq, nr_irqs); +} + +static const struct irq_domain_ops hv_msi_domain_ops =3D { + .select =3D msi_lib_irq_domain_select, + .alloc =3D hv_msi_domain_alloc, + .free =3D hv_msi_domain_free, }; =20 struct irq_domain * __init hv_create_pci_msi_domain(void) { struct irq_domain *d =3D NULL; - struct fwnode_handle *fn; =20 - fn =3D irq_domain_alloc_named_fwnode("HV-PCI-MSI"); - if (fn) - d =3D pci_msi_create_irq_domain(fn, &hv_pci_msi_domain_info, x86_vector_= domain); + struct irq_domain_info info =3D { + .fwnode =3D irq_domain_alloc_named_fwnode("HV-PCI-MSI"), + .ops =3D &hv_msi_domain_ops, + .parent =3D x86_vector_domain, + }; + + if (info.fwnode) + d =3D msi_create_parent_irq_domain(&info, &hv_msi_parent_ops); =20 /* No point in going further if we can't get an irq domain */ BUG_ON(!d); diff --git a/drivers/hv/Kconfig b/drivers/hv/Kconfig index 1cd188b73b743..e62a0f8b34198 100644 --- a/drivers/hv/Kconfig +++ b/drivers/hv/Kconfig @@ -10,6 +10,7 @@ config HYPERV select X86_HV_CALLBACK_VECTOR if X86 select OF_EARLY_FLATTREE if OF select SYSFB if !HYPERV_VTL_MODE + select IRQ_MSI_LIB if X86 help Select this option to run Linux as a Hyper-V client operating system. --=20 2.39.5