From nobody Wed Oct 8 20:52:50 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DC8F92EE965; Tue, 24 Jun 2025 15:08:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777726; cv=none; b=epKXhwwtPHt5RoWQc03p2l8DJS34Sm13ULmYZYofM0Pnjnn3KqE+4GJy2y6wWZiEuPC5DO96pnG9hQy41ByQmTlJI/6HKaYj/HbMSVX6WEmXmnPtrGC+w3ZBrzzTG2xxmMUFBkMsKWQVPuDjwdHH8GzQA/sr7a0GlBaaekDplmU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777726; c=relaxed/simple; bh=Zv0CC3WYKH/36O9O0t/SOoiKrmvlfng/rt5RJxB0L+A=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=hEeFB+vEqwEyoWL2sznSFj+qlNxg0//+5vzeQFbsQG7NDT3l1FOMjWT3b4iB4jSfRGZHWI2LMIANL4fjKx47LL7H7ypwjLOWFdP3uENa/3e1MzOwLrbUPtNnehuy9ELKvMscK9BqXvAbj6STJgZBPgVeoZYyse4hTqOuNRPo6hY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=sVs1Pb6W; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="sVs1Pb6W" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1750777724; x=1782313724; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Zv0CC3WYKH/36O9O0t/SOoiKrmvlfng/rt5RJxB0L+A=; b=sVs1Pb6Wcp/rqjcSfkgmnsgP8Y9aGPjipS+NKcVkxa8f19QsFmTVFvM9 l6QELAUpSHBqMq5Urwa/6znPv7hC94IVcL7Alun3OkbiDci3fbukPpl+L s9AMlljJm+++UX/GL3uGmt0hLwz4sGXktCig1ORvPlCLoZKAQ8WVlyY/n GdP0Bpn5Y6M4x3egOJ7EGTA2xCeNUQrEjseU0a06un0QGVK7PmH2wMq6r 8F6VMAb1qTbSTgpv5rdXNzmpmCuvOGjKIyiqZ1aunhSKpA+TzG8rvFKl8 zHJ3Ufq5W4cGdg7RUrI9KgAb2We2FueFB38iKxI46Y1wI7Mtn5y6IGU24 Q==; X-CSE-ConnectionGUID: 4+RzxTN1Qsa6vG3Bpty4nA== X-CSE-MsgGUID: 2Bnf9nTNT1y4Lw1rqdmKEQ== X-IronPort-AV: E=Sophos;i="6.16,262,1744095600"; d="scan'208";a="42688169" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 24 Jun 2025 08:08:42 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Tue, 24 Jun 2025 08:08:36 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Tue, 24 Jun 2025 08:08:36 -0700 From: To: , , , , CC: , , , , Subject: [PATCH v2 01/32] clk: at91: pmc: add macros for clk_parent_data Date: Tue, 24 Jun 2025 08:07:58 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Add helpers to set parent_data objects in platform specific drivers. Signed-off-by: Claudiu Beznea [ryan.wanner@microchip.com: enclose complex macro with parentheses.] Signed-off-by: Ryan Wanner --- drivers/clk/at91/pmc.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index 4fb29ca111f7..0b721a65b77f 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -15,6 +15,12 @@ =20 #include =20 +#define AT91_CLK_PD_NAME(n, i) ((struct clk_parent_data){ \ + .hw =3D NULL, .name =3D (n), .fw_name =3D (n), .index =3D (i), \ +}) + +#define AT91_CLK_PD_HW(h) ((struct clk_parent_data){ .hw =3D (h) }) + extern spinlock_t pmc_pcr_lock; =20 struct pmc_data { --=20 2.43.0 From nobody Wed Oct 8 20:52:50 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 20EBD2EF2A7; Tue, 24 Jun 2025 15:08:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777727; cv=none; b=FMQEFx7qQkFNg9pyEGsSFF4W3AqIPE9Th0GpNJfAMFtDGrxZAIHcvUvP0lu9x9jQgO/YMdDLqZkAvXw02pUUSa6gzD4i+IcUCLMPIdbzkjUko6qFCZlLfm+p4MJiMMPZEI4GHdokfrUsSEMhz5WbrBSn+24imUXVt4E17pJRBUo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777727; c=relaxed/simple; bh=9aK4jdZmF1ToqNiZetoB/6dP7GUhww2O/JrrrKTukA8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=HDseSk3WDGUXgCyYPWxWEuuaWqp49y9y/u7RdKBdwYGr7j2TjnVzj0cZAXcImAiuNfaJPWcexnJWoJKsH/2M5CCOHrCrWGRUbpFuGP7pvn+Wx1XV1qOAFNtk5NbjhUxEmSROJcWl/vixsSTJLDBMdBRfsm+LbZFs7gHjxqOAR5w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=12fYov7U; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="12fYov7U" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1750777726; x=1782313726; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9aK4jdZmF1ToqNiZetoB/6dP7GUhww2O/JrrrKTukA8=; b=12fYov7UljcZsOG60zJDOXfrcShAf+jLD0a7DnBgjkdtCV6PVeaRyPkE TV9/wd6Vc0oOhIzLuuWZU1t1kWkbjVFVr+VIJgOLCezpwBEIV+Mlzk5EG mUaU87SHCctUIQQc5Tzxb9D3boNGovpapCKsSnMGON0IhcAAE7hwym8Bz SNYsLP0+iCFgV3Bw+HOa8uSoJRvmJ1dbqUOCR6z95gqhqXOjnowzf9qdv gE7whJ4DDcu/wDIlUz6LC04PRSPDA5y+Afr0CM6ZMUgH1x4zRBQxbG4Wt 2jrPN0VxmILKljoR+eLeTpM6O7wkBG7L/Xp1wn0og/gaeVvwfGIiNF03K w==; X-CSE-ConnectionGUID: 4+RzxTN1Qsa6vG3Bpty4nA== X-CSE-MsgGUID: IpZZg6yqQlO1SSuE50+wlA== X-IronPort-AV: E=Sophos;i="6.16,262,1744095600"; d="scan'208";a="42688171" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 24 Jun 2025 08:08:42 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Tue, 24 Jun 2025 08:08:36 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Tue, 24 Jun 2025 08:08:36 -0700 From: To: , , , , CC: , , , , , Ryan Wanner Subject: [PATCH v2 02/32] clk: at91: pmc: Move macro to header file Date: Tue, 24 Jun 2025 08:07:59 -0700 Message-ID: <6776f06473d3be71882ef938a4314947f565e26f.1750182562.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Ryan Wanner Move this macro to the header file as it is used by more than one driver file. Signed-off-by: Ryan Wanner --- drivers/clk/at91/pmc.h | 3 +++ drivers/clk/at91/sama7d65.c | 3 --- drivers/clk/at91/sama7g5.c | 3 --- 3 files changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index 0b721a65b77f..63d4c425bed5 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -21,6 +21,9 @@ =20 #define AT91_CLK_PD_HW(h) ((struct clk_parent_data){ .hw =3D (h) }) =20 +/* Used to create an array entry identifying a PLL by its components. */ +#define PLL_IDS_TO_ARR_ENTRY(_id, _comp) { PLL_ID_##_id, PLL_COMPID_##_com= p} + extern spinlock_t pmc_pcr_lock; =20 struct pmc_data { diff --git a/drivers/clk/at91/sama7d65.c b/drivers/clk/at91/sama7d65.c index a5d40df8b2f2..b74813a288a8 100644 --- a/drivers/clk/at91/sama7d65.c +++ b/drivers/clk/at91/sama7d65.c @@ -428,9 +428,6 @@ static struct sama7d65_pll { }, }; =20 -/* Used to create an array entry identifying a PLL by its components. */ -#define PLL_IDS_TO_ARR_ENTRY(_id, _comp) { PLL_ID_##_id, PLL_COMPID_##_com= p} - /* * Master clock (MCK[0..9]) description * @n: clock name diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index 8385badc1c70..bf6092fea217 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -341,9 +341,6 @@ static struct sama7g5_pll { }, }; =20 -/* Used to create an array entry identifying a PLL by its components. */ -#define PLL_IDS_TO_ARR_ENTRY(_id, _comp) { PLL_ID_##_id, PLL_COMPID_##_com= p} - /* * Master clock (MCK[1..4]) description * @n: clock name --=20 2.43.0 From nobody Wed Oct 8 20:52:50 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 202B32EF2A5; Tue, 24 Jun 2025 15:08:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777728; cv=none; b=CWaiupB05YGZD7/i9QcEwNnprRS0Hj+HNr2xIvFO4beJMr3mAzYUNldl+obg6vZkIhmCnMaX4sfNXH4gEiTnW/K5bar4PcAjL96bYVa8rGcGjLu9zBG4KnJ/9ubJwTr+CFctGlLlkBuCy6pDk8dyud79trWobV41KExLamP754Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777728; c=relaxed/simple; bh=ZBh22/c2+KopszsJUpBiG9YTeWqU4Yw6hxq8LfGhxvE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=MlV3tXGjjrr7tcbl9/QwwLazaqgEAPQlDS8IodLhbMOay17srNV3vZqGYTt/U85uKwGMlbtaOEDayHvPgZ97z8yI/VD3LisMvzHPa7RFxaV5AotWoC4bxbdtrXBLUI0URkua5olsT7IB+rFAwinMSVrSio6jRQ0O38LsNoL3KPY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=WOsh3Ogq; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="WOsh3Ogq" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1750777726; x=1782313726; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ZBh22/c2+KopszsJUpBiG9YTeWqU4Yw6hxq8LfGhxvE=; b=WOsh3OgqWgj7wRQ2sn7OYlgnb3xOFyBf42ePatm4isMOF91zyL7vTFNL 1TVnvxptzm0KzJq9kXOOVi0S3VrL7CFzk4AvU1P2U3DIqkN4anE3UmhvU ufw7X2UdfmDpZ24azuQY+mhpofTh4vugS5rGJXMUuOhTkSv35PdqzzHsi VtNvxiypZBtacBoONuezAW7Lf37wmN1BGbZdbxFRwhrPz4TWWxwo+KE7d LyISxG3uP1LiiHKhhtStM2AKWHjqVQV4R5P3FTsKOqvuKQxct+WnCtyKS Csk9JZG8K2JDx/xpxlcI9gDUChirOABBG6ipLtdhty9guELgkK0I2jOM/ A==; X-CSE-ConnectionGUID: 4+RzxTN1Qsa6vG3Bpty4nA== X-CSE-MsgGUID: NQTeGBggQUS8efeOAU26ow== X-IronPort-AV: E=Sophos;i="6.16,262,1744095600"; d="scan'208";a="42688172" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 24 Jun 2025 08:08:43 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Tue, 24 Jun 2025 08:08:36 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Tue, 24 Jun 2025 08:08:36 -0700 From: To: , , , , CC: , , , , Subject: [PATCH v2 03/32] clk: at91: clk-sam9x60-pll: use clk_parent_data Date: Tue, 24 Jun 2025 08:08:00 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Use struct clk_parent_data instead of struct parent_hw as this leads to less usage of __clk_get_hw() in SoC specific clock drivers and simpler conversion of existing SoC specific clock drivers from parent_names to modern clk_parent_data structures. As clk-sam9x60-pll need to know parent's rate at initialization we pass it now from SoC specific drivers. This will lead in the end at removing __clk_get_hw() in SoC specific drivers (that will be solved by subsequent commits). Signed-off-by: Claudiu Beznea [ryan.wanner@microchip.com: Remove SoC specific driver changes, those will be added in subsequent commits.] Signed-off-by: Ryan Wanner --- drivers/clk/at91/clk-sam9x60-pll.c | 14 +++++--------- drivers/clk/at91/pmc.h | 5 +++-- 2 files changed, 8 insertions(+), 11 deletions(-) diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9= x60-pll.c index cefd9948e103..03a7d00dcc6d 100644 --- a/drivers/clk/at91/clk-sam9x60-pll.c +++ b/drivers/clk/at91/clk-sam9x60-pll.c @@ -630,19 +630,19 @@ static const struct clk_ops sam9x60_fixed_div_pll_ops= =3D { =20 struct clk_hw * __init sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock, - const char *name, const char *parent_name, - struct clk_hw *parent_hw, u8 id, + const char *name, const struct clk_parent_data *parent_data, + unsigned long parent_rate, u8 id, const struct clk_pll_characteristics *characteristics, const struct clk_pll_layout *layout, u32 flags) { struct sam9x60_frac *frac; struct clk_hw *hw; struct clk_init_data init =3D {}; - unsigned long parent_rate, irqflags; + unsigned long irqflags; unsigned int val; int ret; =20 - if (id > PLL_MAX_ID || !lock || !parent_hw) + if (id > PLL_MAX_ID || !lock || !parent_data) return ERR_PTR(-EINVAL); =20 frac =3D kzalloc(sizeof(*frac), GFP_KERNEL); @@ -650,10 +650,7 @@ sam9x60_clk_register_frac_pll(struct regmap *regmap, s= pinlock_t *lock, return ERR_PTR(-ENOMEM); =20 init.name =3D name; - if (parent_name) - init.parent_names =3D &parent_name; - else - init.parent_hws =3D (const struct clk_hw **)&parent_hw; + init.parent_data =3D (const struct clk_parent_data *)parent_data; init.num_parents =3D 1; if (flags & CLK_SET_RATE_GATE) init.ops =3D &sam9x60_frac_pll_ops; @@ -684,7 +681,6 @@ sam9x60_clk_register_frac_pll(struct regmap *regmap, sp= inlock_t *lock, * its rate leading to enabling this PLL with unsupported * rate. This will lead to PLL not being locked at all. */ - parent_rate =3D clk_hw_get_rate(parent_hw); if (!parent_rate) { hw =3D ERR_PTR(-EINVAL); goto free; diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index 63d4c425bed5..b43f6652417f 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -255,8 +255,9 @@ sam9x60_clk_register_div_pll(struct regmap *regmap, spi= nlock_t *lock, =20 struct clk_hw * __init sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock, - const char *name, const char *parent_name, - struct clk_hw *parent_hw, u8 id, + const char *name, + const struct clk_parent_data *parent_data, + unsigned long parent_rate, u8 id, const struct clk_pll_characteristics *characteristics, const struct clk_pll_layout *layout, u32 flags); =20 --=20 2.43.0 From nobody Wed Oct 8 20:52:50 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B98142EF65C; Tue, 24 Jun 2025 15:08:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777728; cv=none; b=HPPB5DYHf9dARDyp3W7IrUJT7teQB7sTxrDCPjkRI/UC8YBWkkt6D6M+a8ULxFb/lBfXph7VslnJJgeffqGK08+OYxuaQ2ytSLNq7CXSL2UWVArCBJJ0kvdcEiR14Kn/5m65cHKABlayZJtaToGV6/oJV5oDuTaqC1mrehSqR24= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777728; c=relaxed/simple; bh=/z69PibqywpVDUupVFU5et9XVf8qDTlwUsinAZCZ8UM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=TZzvnOlYvp8TSTG6I6WQNQ4Gwju3/SDSnlvuBZFXACceIHAUoZZHAyGTabDwgvE1mRyEwj2G2ioyUUVxOFoqF1scP8Z6vJNRF70we38XkuyKf7+fkVZNHpxzw54xag5kODWvf1tj3CW4lpdxPSmHpT57Md9M4cVPiA61xC4ZPDI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=Fm8R0HCu; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="Fm8R0HCu" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1750777726; x=1782313726; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=/z69PibqywpVDUupVFU5et9XVf8qDTlwUsinAZCZ8UM=; b=Fm8R0HCulFPUEIKiIaTdB1QVVhlFV+0/4wYusE/StVgA7pm8cg1fL6bU HzpMfjjp4mE/DOHWDC2XHu0XWO/KpXh/aA8z/1qgZ8jHYktH+hk1RdlFL CI3yeEbGqd4T9dbr35HxSwRL8DmQKuBahRo0EWQKinYJ2hG/UmR+4gYL4 1pwrgaBX2DWDcqLHdRQNiwPzZhgj1+ZbyXKeTss/qqmrsN/SPLaozaj2B 3Ue3ns7/iZI/JWqt9p4gj6w5Jm60M/UO6hObwCpkWzMYIWjBhtjbjGcO0 qmG+EXMbN0Fd/PvxWXj03HxAJ5dwt3J2hl95y+Lugp3myvSV/H9x4amOn g==; X-CSE-ConnectionGUID: 4+RzxTN1Qsa6vG3Bpty4nA== X-CSE-MsgGUID: Q0O/25CwQsu2txuQI1HkOw== X-IronPort-AV: E=Sophos;i="6.16,262,1744095600"; d="scan'208";a="42688174" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 24 Jun 2025 08:08:43 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Tue, 24 Jun 2025 08:08:36 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Tue, 24 Jun 2025 08:08:36 -0700 From: To: , , , , CC: , , , , Subject: [PATCH v2 04/32] clk: at91: clk-peripheral: switch to clk_parent_data Date: Tue, 24 Jun 2025 08:08:01 -0700 Message-ID: <94aa65af65553f4251bcc9ca6420c8feafc27324.1750182562.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Use struct clk_parent_data instead of parent_hw. Signed-off-by: Claudiu Beznea [ryan.wanner@microchip.com: Remove the SoC specific changes those will be added in a later commit. And adjust commit message] Signed-off-by: Ryan Wanner --- drivers/clk/at91/clk-peripheral.c | 16 ++++++++-------- drivers/clk/at91/pmc.h | 4 ++-- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/clk/at91/clk-peripheral.c b/drivers/clk/at91/clk-perip= heral.c index c173a44c800a..ed97b3c0a66b 100644 --- a/drivers/clk/at91/clk-peripheral.c +++ b/drivers/clk/at91/clk-peripheral.c @@ -97,7 +97,7 @@ static const struct clk_ops peripheral_ops =3D { =20 struct clk_hw * __init at91_clk_register_peripheral(struct regmap *regmap, const char *name, - const char *parent_name, struct clk_hw *parent_hw, + const char *parent_name, struct clk_parent_data *parent_data, u32 id) { struct clk_peripheral *periph; @@ -105,7 +105,7 @@ at91_clk_register_peripheral(struct regmap *regmap, con= st char *name, struct clk_hw *hw; int ret; =20 - if (!name || !(parent_name || parent_hw) || id > PERIPHERAL_ID_MAX) + if (!name || !(parent_name || parent_data) || id > PERIPHERAL_ID_MAX) return ERR_PTR(-EINVAL); =20 periph =3D kzalloc(sizeof(*periph), GFP_KERNEL); @@ -114,8 +114,8 @@ at91_clk_register_peripheral(struct regmap *regmap, con= st char *name, =20 init.name =3D name; init.ops =3D &peripheral_ops; - if (parent_hw) - init.parent_hws =3D (const struct clk_hw **)&parent_hw; + if (parent_data) + init.parent_data =3D (const struct clk_parent_data *)parent_data; else init.parent_names =3D &parent_name; init.num_parents =3D 1; @@ -448,7 +448,7 @@ struct clk_hw * __init at91_clk_register_sam9x5_peripheral(struct regmap *regmap, spinlock_t *loc= k, const struct clk_pcr_layout *layout, const char *name, const char *parent_name, - struct clk_hw *parent_hw, + struct clk_parent_data *parent_data, u32 id, const struct clk_range *range, int chg_pid, unsigned long flags) { @@ -457,7 +457,7 @@ at91_clk_register_sam9x5_peripheral(struct regmap *regm= ap, spinlock_t *lock, struct clk_hw *hw; int ret; =20 - if (!name || !(parent_name || parent_hw)) + if (!name || !(parent_name || parent_data)) return ERR_PTR(-EINVAL); =20 periph =3D kzalloc(sizeof(*periph), GFP_KERNEL); @@ -465,8 +465,8 @@ at91_clk_register_sam9x5_peripheral(struct regmap *regm= ap, spinlock_t *lock, return ERR_PTR(-ENOMEM); =20 init.name =3D name; - if (parent_hw) - init.parent_hws =3D (const struct clk_hw **)&parent_hw; + if (parent_data) + init.parent_data =3D (const struct clk_parent_data *)parent_data; else init.parent_names =3D &parent_name; init.num_parents =3D 1; diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index b43f6652417f..b6f2aca1e1fd 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -226,13 +226,13 @@ at91_clk_sama7g5_register_master(struct regmap *regma= p, =20 struct clk_hw * __init at91_clk_register_peripheral(struct regmap *regmap, const char *name, - const char *parent_name, struct clk_hw *parent_hw, + const char *parent_name, struct clk_parent_data *parent_data, u32 id); struct clk_hw * __init at91_clk_register_sam9x5_peripheral(struct regmap *regmap, spinlock_t *loc= k, const struct clk_pcr_layout *layout, const char *name, const char *parent_name, - struct clk_hw *parent_hw, + struct clk_parent_data *parent_data, u32 id, const struct clk_range *range, int chg_pid, unsigned long flags); =20 --=20 2.43.0 From nobody Wed Oct 8 20:52:50 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E31DB2EF9CB; Tue, 24 Jun 2025 15:08:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777729; cv=none; b=IOt7lP18FTCMiE3vSJjH91+qYDjKv4DdXcYzjlYa7DbJdwQ4iOXWVv6YGdryeFlOdjpSXO0gIx7vTAQdBYBqnY+qn3xuiHsOnp6JiL2/QSZIReMggkWaqA/DM4lM3bP4ezkjWhMir2DGY+/euwdTKH5qkaRHrh6dOA4CHTrd+EI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777729; c=relaxed/simple; bh=zo0NpMdOdWIh9B4OagOeYIcPDmAgxC72SvmGefvk/Hw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=L8rfdhQd3W9ccnD1CKGZ7hY82sFhSN5w1oUja/kaCgcez1P6a379cfGvUHxu4EK8RIKOhD4V02zy28zlSxyseSk1SjMwOZ/tXDf4WXQiJi4lsiTJc0E4sbkihzSVohG+QXJpUU7G/G6kePEPfEUIWLUM14dUUdvJbEgulDt6YEI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=pmSqjgvd; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="pmSqjgvd" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1750777727; x=1782313727; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=zo0NpMdOdWIh9B4OagOeYIcPDmAgxC72SvmGefvk/Hw=; b=pmSqjgvdw08lsfrSHKDCBLstUd9X3Ph7gL/IkiyaF7TbU8TUH2gnWgks Q9iEbtMyt5ArZK1OsUkefo1ZWKAGgiKTZ+qggGqM2zuFdoozF04UTVIsj uvYN4AKzc1ZgPWm2YBJtFeHe4zObuyILIVjK/4k0WCBaf/eulCpiHvWUF ZWtv0hMs6LYxrZnOvwgYNkk7lEHsdTb1oMvsjSNbRY6sqOrixu/6WVw8W buVUYw8bua8zll82XW3LAfQunn5Bkb3+36ryfMI2AmZA9LzcD1BYmWxBv hkL816AFB7nSGdY0fDzF4ww7mPYhblERtEcSulU+co7zb9Uwyag21NUNx w==; X-CSE-ConnectionGUID: 4+RzxTN1Qsa6vG3Bpty4nA== X-CSE-MsgGUID: 8gRjwljjR/KZuu12BifyyQ== X-IronPort-AV: E=Sophos;i="6.16,262,1744095600"; d="scan'208";a="42688175" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 24 Jun 2025 08:08:44 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Tue, 24 Jun 2025 08:08:36 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Tue, 24 Jun 2025 08:08:36 -0700 From: To: , , , , CC: , , , , Subject: [PATCH v2 05/32] clk: at91: clk-main: switch to clk parent data Date: Tue, 24 Jun 2025 08:08:02 -0700 Message-ID: <222655275e1e58dbb3cb2f6e4e65fc08cc81b7db.1750182562.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Use struct clk_parent_data instead of parent_hw as this leads to the use of modern clock structures. Signed-off-by: Claudiu Beznea [ryan.wanner@microchip.com: Remove SoC specific changes will be added in a later patch. Adjust commit message.] Signed-off-by: Ryan Wanner --- drivers/clk/at91/clk-main.c | 16 ++++++++-------- drivers/clk/at91/pmc.h | 4 ++-- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/clk/at91/clk-main.c b/drivers/clk/at91/clk-main.c index 9b462becc693..514c5690253f 100644 --- a/drivers/clk/at91/clk-main.c +++ b/drivers/clk/at91/clk-main.c @@ -402,7 +402,7 @@ struct clk_hw * __init at91_clk_register_rm9200_main(struct regmap *regmap, const char *name, const char *parent_name, - struct clk_hw *parent_hw) + struct clk_parent_data *parent_data) { struct clk_rm9200_main *clkmain; struct clk_init_data init =3D {}; @@ -412,7 +412,7 @@ at91_clk_register_rm9200_main(struct regmap *regmap, if (!name) return ERR_PTR(-EINVAL); =20 - if (!(parent_name || parent_hw)) + if (!(parent_name || parent_data)) return ERR_PTR(-EINVAL); =20 clkmain =3D kzalloc(sizeof(*clkmain), GFP_KERNEL); @@ -421,8 +421,8 @@ at91_clk_register_rm9200_main(struct regmap *regmap, =20 init.name =3D name; init.ops =3D &rm9200_main_ops; - if (parent_hw) - init.parent_hws =3D (const struct clk_hw **)&parent_hw; + if (parent_data) + init.parent_data =3D (const struct clk_parent_data *)parent_data; else init.parent_names =3D &parent_name; init.num_parents =3D 1; @@ -552,7 +552,7 @@ struct clk_hw * __init at91_clk_register_sam9x5_main(struct regmap *regmap, const char *name, const char **parent_names, - struct clk_hw **parent_hws, + struct clk_parent_data *parent_data, int num_parents) { struct clk_sam9x5_main *clkmain; @@ -564,7 +564,7 @@ at91_clk_register_sam9x5_main(struct regmap *regmap, if (!name) return ERR_PTR(-EINVAL); =20 - if (!(parent_hws || parent_names) || !num_parents) + if (!(parent_data || parent_names) || !num_parents) return ERR_PTR(-EINVAL); =20 clkmain =3D kzalloc(sizeof(*clkmain), GFP_KERNEL); @@ -573,8 +573,8 @@ at91_clk_register_sam9x5_main(struct regmap *regmap, =20 init.name =3D name; init.ops =3D &sam9x5_main_ops; - if (parent_hws) - init.parent_hws =3D (const struct clk_hw **)parent_hws; + if (parent_data) + init.parent_data =3D (const struct clk_parent_data *)parent_data; else init.parent_names =3D parent_names; init.num_parents =3D num_parents; diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index b6f2aca1e1fd..e32a5e85d08f 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -195,11 +195,11 @@ struct clk_hw * __init at91_clk_register_rm9200_main(struct regmap *regmap, const char *name, const char *parent_name, - struct clk_hw *parent_hw); + struct clk_parent_data *parent_data); struct clk_hw * __init at91_clk_register_sam9x5_main(struct regmap *regmap, const char *name, const char **parent_names, - struct clk_hw **parent_hws, int num_parents); + struct clk_parent_data *parent_data, int num_parents); =20 struct clk_hw * __init at91_clk_register_master_pres(struct regmap *regmap, const char *name, --=20 2.43.0 From nobody Wed Oct 8 20:52:50 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B91ED2EFDAF; Tue, 24 Jun 2025 15:08:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777731; cv=none; b=c+Dby6hGHzLaEnGNsNjZ0mBWkeajUf11etW49hLigeqobX/eyPZLUc4U94wDaH9T2BWT5xKRsZ4cng/s/ndW1poDl918RSaigR3p1Yl6xjDGaIexjEDcx3IJI1umdf4Z2u1fco1PBi19anC45dxi1QxBYUBXgVCnhFb0ywwlsfo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777731; c=relaxed/simple; bh=hp9bs1IqXyCPrYq1/MdaARbYzcOOz47PKwT4z0/XYaw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=B+mPPQJfhDg7WNA4yhc30OGbHMGUhnG9i0LX6S4d3gU9XBg1yJovUgH5bqP8oclnm9ijfKO3u9aHRfrNy2s3Gy1saT78E2zHTfJ36Ns7CBWEXePQj2cxIdaVCHtGCtkDpDq6wnfADL2INLGCf0f4kmzD96QNT9bwPDB27iK1Xzk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=ImXWw9dZ; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="ImXWw9dZ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1750777728; x=1782313728; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hp9bs1IqXyCPrYq1/MdaARbYzcOOz47PKwT4z0/XYaw=; b=ImXWw9dZC+z21Ksl2YOp5x87HwWODMro3mIRZqKz1HvuJmq45UEimKRJ kgoGIBWcYOHGO89GGCCDvij7fz0EYBtQOQUtrFC6gWqp/dKXxm408pifP TPfAsrrHa/pJGR/5m+RiZRH1FCavlMcyxHeGE/YQJHsPhN3qb3ZYyJa4Y /1QeiC06NFJpfLEiZShNInx/olotPMq9FDtK0SzlB1O+gxngUe6rvBZkx dGUKik33cZxd5jvY/g6rSM7tNMOmKmiRtZpv4y9ZWf2ynxlY+H2LmUfq/ EXeabm4GGnNQCXIM3AoaJfV6TGhpudL4qMDxWotZMnV0IQrLBeRViHTGe Q==; X-CSE-ConnectionGUID: 4+RzxTN1Qsa6vG3Bpty4nA== X-CSE-MsgGUID: nIYkURz8Q+ubsa6mo1wPvA== X-IronPort-AV: E=Sophos;i="6.16,262,1744095600"; d="scan'208";a="42688177" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 24 Jun 2025 08:08:44 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Tue, 24 Jun 2025 08:08:36 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Tue, 24 Jun 2025 08:08:36 -0700 From: To: , , , , CC: , , , , Subject: [PATCH v2 06/32] clk: at91: clk-utmi: use clk_parent_data Date: Tue, 24 Jun 2025 08:08:03 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Use struct clk_parent_data instead of struct parent_hw as this leads to less usage of __clk_get_hw() in SoC specific clock drivers and simpler conversion of existing SoC specific clock drivers from parent_names to modern clk_parent_data structures. Signed-off-by: Claudiu Beznea [ryan.wanner@microchip.com: Remove SoC specific changes into a separate commit.] Signed-off-by: Ryan Wanner --- drivers/clk/at91/clk-utmi.c | 16 ++++++++-------- drivers/clk/at91/pmc.h | 4 ++-- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/clk/at91/clk-utmi.c b/drivers/clk/at91/clk-utmi.c index b991180beea1..38ffe4d712a5 100644 --- a/drivers/clk/at91/clk-utmi.c +++ b/drivers/clk/at91/clk-utmi.c @@ -144,7 +144,7 @@ static struct clk_hw * __init at91_clk_register_utmi_internal(struct regmap *regmap_pmc, struct regmap *regmap_sfr, const char *name, const char *parent_name, - struct clk_hw *parent_hw, + struct clk_parent_data *parent_data, const struct clk_ops *ops, unsigned long flags) { struct clk_utmi *utmi; @@ -152,7 +152,7 @@ at91_clk_register_utmi_internal(struct regmap *regmap_p= mc, struct clk_init_data init =3D {}; int ret; =20 - if (!(parent_name || parent_hw)) + if (!(parent_name || parent_data)) return ERR_PTR(-EINVAL); =20 utmi =3D kzalloc(sizeof(*utmi), GFP_KERNEL); @@ -161,8 +161,8 @@ at91_clk_register_utmi_internal(struct regmap *regmap_p= mc, =20 init.name =3D name; init.ops =3D ops; - if (parent_hw) - init.parent_hws =3D (const struct clk_hw **)&parent_hw; + if (parent_data) + init.parent_data =3D (const struct clk_parent_data *)parent_data; else init.parent_names =3D &parent_name; init.num_parents =3D 1; @@ -185,10 +185,10 @@ at91_clk_register_utmi_internal(struct regmap *regmap= _pmc, struct clk_hw * __init at91_clk_register_utmi(struct regmap *regmap_pmc, struct regmap *regmap_sf= r, const char *name, const char *parent_name, - struct clk_hw *parent_hw) + struct clk_parent_data *parent_data) { return at91_clk_register_utmi_internal(regmap_pmc, regmap_sfr, name, - parent_name, parent_hw, &utmi_ops, CLK_SET_RATE_GATE); + parent_name, parent_data, &utmi_ops, CLK_SET_RATE_GATE); } =20 static int clk_utmi_sama7g5_prepare(struct clk_hw *hw) @@ -287,8 +287,8 @@ static const struct clk_ops sama7g5_utmi_ops =3D { =20 struct clk_hw * __init at91_clk_sama7g5_register_utmi(struct regmap *regmap_pmc, const char *name, - const char *parent_name, struct clk_hw *parent_hw) + const char *parent_name, struct clk_parent_data *parent_data) { return at91_clk_register_utmi_internal(regmap_pmc, NULL, name, - parent_name, parent_hw, &sama7g5_utmi_ops, 0); + parent_name, parent_data, &sama7g5_utmi_ops, 0); } diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index e32a5e85d08f..d9a04fddb0b1 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -299,10 +299,10 @@ at91rm9200_clk_register_usb(struct regmap *regmap, co= nst char *name, struct clk_hw * __init at91_clk_register_utmi(struct regmap *regmap_pmc, struct regmap *regmap_sf= r, const char *name, const char *parent_name, - struct clk_hw *parent_hw); + struct clk_parent_data *parent_data); =20 struct clk_hw * __init at91_clk_sama7g5_register_utmi(struct regmap *regmap, const char *name, - const char *parent_name, struct clk_hw *parent_hw); + const char *parent_name, struct clk_parent_data *parent_data); =20 #endif /* __PMC_H_ */ --=20 2.43.0 From nobody Wed Oct 8 20:52:50 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 206C02F0055; Tue, 24 Jun 2025 15:08:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777731; cv=none; b=gSqiLNxjw7NK2hvrp9EMmqETnBKWUybDshSnnXALIYSQmRRQUOmrypfqu4Lqrw8JDmqOgV7h9InMwupEpXqNzbjOBZhjnfgH1YhdFg6526JestrKP/sR9Y+EUl0QPx/ioucxcfCZGp3c+U09+dX9nnu/rxDyRAu2y02rUVZ1Ug4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777731; c=relaxed/simple; bh=ZDB97x4hn7BJDJn8U5FbCjOYcfLmkYwWAj8cLLlw6do=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=vB+cYDUPWFjd6oHQ6jfE/sfII0Vm0JdKUjDL0YebtcygUDbk9GgRB0E/G6ZxVVowFXKRwjQU6Tf6eP1In49sWHb7+fdI1THGoow5ULL7mwj5YzlNADutybeAHb4+VYVHWtzmSWy6OdJHXfZ5zM5OKEp6r82aub8fQ7aXKl2SjV0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=IKScVUy9; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="IKScVUy9" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1750777729; x=1782313729; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ZDB97x4hn7BJDJn8U5FbCjOYcfLmkYwWAj8cLLlw6do=; b=IKScVUy9ua8Zle3HZzypOhLpCtYA4v+K2kUd0uZOngnBnXWmbBRmVFdJ Ifc3beB7+Vmu+3aXxYxjKUpO+4iPwgeqHd2+fCv49lGxulnezfQmJUoj0 6fEoFNM51X0xkre9GDFXWGMOqzjsxPjEG61TOVm0bji+dFxcNSesuFkNz WuVgaIT6o1d/ni/Toe9Ud40rGlHR98QVzFmSS9Tn7guFqEzp1PQYZDQKZ hxJ6nQN9MDubLm5gR05/gWm3r/10AR0KsUm7aHFduRersJ4PU+g7u6aO9 6PNY0G1OPKBXCDoMwT7HdeHDF1+Qjr8xmdUigUZbIFZKTo4wsyP6c2CA1 w==; X-CSE-ConnectionGUID: 4+RzxTN1Qsa6vG3Bpty4nA== X-CSE-MsgGUID: a6+NAS7ZQ2u5sHoJeOp1aw== X-IronPort-AV: E=Sophos;i="6.16,262,1744095600"; d="scan'208";a="42688178" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 24 Jun 2025 08:08:44 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Tue, 24 Jun 2025 08:08:37 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Tue, 24 Jun 2025 08:08:37 -0700 From: To: , , , , CC: , , , , Subject: [PATCH v2 07/32] clk: at91: clk-master: use clk_parent_data Date: Tue, 24 Jun 2025 08:08:04 -0700 Message-ID: <361fa7d7f1f9579a38a27b7623cfa5c8c92f54d5.1750182562.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Use struct clk_parent_data instead of struct parent_hw as this leads to less usage of __clk_get_hw() in SoC specific clock drivers and simpler conversion of existing SoC specific clock drivers from parent_names to modern clk_parent_data structures. Signed-off-by: Claudiu Beznea [ryan.wanner@microchip.com: Remove SoC specific changes as they will be added later. Adjust commit message to reflect the removal of the SoC specific changes.] Signed-off-by: Ryan Wanner --- drivers/clk/at91/clk-master.c | 24 ++++++++++++------------ drivers/clk/at91/pmc.h | 6 +++--- 2 files changed, 15 insertions(+), 15 deletions(-) diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c index 7a544e429d34..cc4f3beb51e5 100644 --- a/drivers/clk/at91/clk-master.c +++ b/drivers/clk/at91/clk-master.c @@ -473,7 +473,7 @@ static struct clk_hw * __init at91_clk_register_master_internal(struct regmap *regmap, const char *name, int num_parents, const char **parent_names, - struct clk_hw **parent_hws, + struct clk_parent_data *parent_data, const struct clk_master_layout *layout, const struct clk_master_characteristics *characteristics, const struct clk_ops *ops, spinlock_t *lock, u32 flags) @@ -485,7 +485,7 @@ at91_clk_register_master_internal(struct regmap *regmap, unsigned long irqflags; int ret; =20 - if (!name || !num_parents || !(parent_names || parent_hws) || !lock) + if (!name || !num_parents || !(parent_names || parent_data) || !lock) return ERR_PTR(-EINVAL); =20 master =3D kzalloc(sizeof(*master), GFP_KERNEL); @@ -494,8 +494,8 @@ at91_clk_register_master_internal(struct regmap *regmap, =20 init.name =3D name; init.ops =3D ops; - if (parent_hws) - init.parent_hws =3D (const struct clk_hw **)parent_hws; + if (parent_data) + init.parent_data =3D (const struct clk_parent_data *)parent_data; else init.parent_names =3D parent_names; init.num_parents =3D num_parents; @@ -531,13 +531,13 @@ struct clk_hw * __init at91_clk_register_master_pres(struct regmap *regmap, const char *name, int num_parents, const char **parent_names, - struct clk_hw **parent_hws, + struct clk_parent_data *parent_data, const struct clk_master_layout *layout, const struct clk_master_characteristics *characteristics, spinlock_t *lock) { return at91_clk_register_master_internal(regmap, name, num_parents, - parent_names, parent_hws, layout, + parent_names, parent_data, layout, characteristics, &master_pres_ops, lock, CLK_SET_RATE_GATE); @@ -546,7 +546,7 @@ at91_clk_register_master_pres(struct regmap *regmap, struct clk_hw * __init at91_clk_register_master_div(struct regmap *regmap, const char *name, const char *parent_name, - struct clk_hw *parent_hw, const struct clk_master_layout *layout, + struct clk_parent_data *parent_data, const struct clk_master_layout *lay= out, const struct clk_master_characteristics *characteristics, spinlock_t *lock, u32 flags, u32 safe_div) { @@ -560,7 +560,7 @@ at91_clk_register_master_div(struct regmap *regmap, =20 hw =3D at91_clk_register_master_internal(regmap, name, 1, parent_name ? &parent_name : NULL, - parent_hw ? &parent_hw : NULL, layout, + parent_data, layout, characteristics, ops, lock, flags); =20 @@ -812,7 +812,7 @@ struct clk_hw * __init at91_clk_sama7g5_register_master(struct regmap *regmap, const char *name, int num_parents, const char **parent_names, - struct clk_hw **parent_hws, + struct clk_parent_data *parent_data, u32 *mux_table, spinlock_t *lock, u8 id, bool critical, int chg_pid) @@ -824,7 +824,7 @@ at91_clk_sama7g5_register_master(struct regmap *regmap, unsigned int val; int ret; =20 - if (!name || !num_parents || !(parent_names || parent_hws) || !mux_table = || + if (!name || !num_parents || !(parent_names || parent_data) || !mux_table= || !lock || id > MASTER_MAX_ID) return ERR_PTR(-EINVAL); =20 @@ -834,8 +834,8 @@ at91_clk_sama7g5_register_master(struct regmap *regmap, =20 init.name =3D name; init.ops =3D &sama7g5_master_ops; - if (parent_hws) - init.parent_hws =3D (const struct clk_hw **)parent_hws; + if (parent_data) + init.parent_data =3D (const struct clk_parent_data *)parent_data; else init.parent_names =3D parent_names; init.num_parents =3D num_parents; diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index d9a04fddb0b1..54d472276fc9 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -204,14 +204,14 @@ at91_clk_register_sam9x5_main(struct regmap *regmap, = const char *name, struct clk_hw * __init at91_clk_register_master_pres(struct regmap *regmap, const char *name, int num_parents, const char **parent_names, - struct clk_hw **parent_hws, + struct clk_parent_data *parent_data, const struct clk_master_layout *layout, const struct clk_master_characteristics *characteristics, spinlock_t *lock); =20 struct clk_hw * __init at91_clk_register_master_div(struct regmap *regmap, const char *name, - const char *parent_names, struct clk_hw *parent_hw, + const char *parent_names, struct clk_parent_data *parent_data, const struct clk_master_layout *layout, const struct clk_master_characteristics *characteristics, spinlock_t *lock, u32 flags, u32 safe_div); @@ -220,7 +220,7 @@ struct clk_hw * __init at91_clk_sama7g5_register_master(struct regmap *regmap, const char *name, int num_parents, const char **parent_names, - struct clk_hw **parent_hws, u32 *mux_table, + struct clk_parent_data *parent_data, u32 *mux_table, spinlock_t *lock, u8 id, bool critical, int chg_pid); =20 --=20 2.43.0 From nobody Wed Oct 8 20:52:50 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E2BAD2F1984; Tue, 24 Jun 2025 15:08:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777731; cv=none; b=U9SUBBcOw8GCxr3PhmXIOaqRKTPbsJEH/K34JJBRVGFWxO0VeBvnu2PSd4NAuiQxbld3TdZHFkiBYl8Lg5f4JstEsdznTdiSCIk6pZ8bVIemfKGh7K9ngFc5chKLzt1R1F/guGbab+/pqwTnCFdimwVxspr6XUTqRp4htO8tSWg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777731; c=relaxed/simple; bh=NFlza7NMXYr7yoaM4juKHHENgegAA1/AX4WT/TjqqEs=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=aOfzl0doZDd7qwZoP4T92Kv0OI4V5CxKGRMzScDaEY/UqUPrCVVgHPYv8QpOaFaZG1Lcbjmp44IcZ2edAgi6Vl5jzbc/hyT4YkwDP3Rs0bBY55tuyQIf9/aCmnAE/Fy7ylZV99XIhOqAt/+GqvyguPrYPOJ4kJVCfIuuTYwaWAU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=mzJwNzZB; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="mzJwNzZB" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1750777729; x=1782313729; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=NFlza7NMXYr7yoaM4juKHHENgegAA1/AX4WT/TjqqEs=; b=mzJwNzZBzcd8CAqxFIyPsTm9EX/Kc/9SR3WlcpaA6Hak8DOloy8Xl0Xo 0StZJeMOyKzi8qnaQ48OPedOy5ZO9AvZXy1Y26147l2fL1JRaaT2Ap2CY Q6tUsyR4lrCgIef/knF5QCTwxMB5dsKOQyvepjKfYjL1C2QN3YOlJW6uc +MgaEXoM8XEcNQUUoMi2Agcdo7v9ejrQ6/hyv/bc7joBy0iZwpLaVfd3f sWfXo0Qw+44fyueZNvYTv0QRRCsIkY+6kGwBdfAGyXwl054eBCO20uj76 CKqb5zGYVEVRaqufSpi5ES93VafFbw5S9qbhzwGrXAljPhA1IUbaXBK58 Q==; X-CSE-ConnectionGUID: 4+RzxTN1Qsa6vG3Bpty4nA== X-CSE-MsgGUID: elByiUfvT9SJiDW4RZv8kg== X-IronPort-AV: E=Sophos;i="6.16,262,1744095600"; d="scan'208";a="42688180" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 24 Jun 2025 08:08:45 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Tue, 24 Jun 2025 08:08:37 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Tue, 24 Jun 2025 08:08:37 -0700 From: To: , , , , CC: , , , , Subject: [PATCH v2 08/32] clk: at91: clk-programmable: use clk_parent_data Date: Tue, 24 Jun 2025 08:08:05 -0700 Message-ID: <44cbeb6ac133a44e0c09da82434cda10c894a66a.1750182562.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Use struct clk_parent_data instead of struct parent_hw as this leads to less usage of __clk_get_hw() in SoC specific clock drivers and simpler conversion of existing SoC specific clock drivers from parent_names to modern clk_parent_data structures. Signed-off-by: Claudiu Beznea [ryan.wanner@microchip.com: Remove SoC specific changes those will be added in a separate commit.] Signed-off-by: Ryan Wanner --- drivers/clk/at91/clk-programmable.c | 8 ++++---- drivers/clk/at91/pmc.h | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/clk/at91/clk-programmable.c b/drivers/clk/at91/clk-pro= grammable.c index 1195fb405503..275ca701f294 100644 --- a/drivers/clk/at91/clk-programmable.c +++ b/drivers/clk/at91/clk-programmable.c @@ -215,7 +215,7 @@ static const struct clk_ops programmable_ops =3D { struct clk_hw * __init at91_clk_register_programmable(struct regmap *regmap, const char *name, const char **parent_names, - struct clk_hw **parent_hws, u8 num_parents, u8 id, + struct clk_parent_data *parent_data, u8 num_parents, u8 id, const struct clk_programmable_layout *layout, u32 *mux_table) { @@ -224,7 +224,7 @@ at91_clk_register_programmable(struct regmap *regmap, struct clk_init_data init =3D {}; int ret; =20 - if (id > PROG_ID_MAX || !(parent_names || parent_hws)) + if (id > PROG_ID_MAX || !(parent_names || parent_data)) return ERR_PTR(-EINVAL); =20 prog =3D kzalloc(sizeof(*prog), GFP_KERNEL); @@ -233,8 +233,8 @@ at91_clk_register_programmable(struct regmap *regmap, =20 init.name =3D name; init.ops =3D &programmable_ops; - if (parent_hws) - init.parent_hws =3D (const struct clk_hw **)parent_hws; + if (parent_data) + init.parent_data =3D (const struct clk_parent_data *)parent_data; else init.parent_names =3D parent_names; init.num_parents =3D num_parents; diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index 54d472276fc9..34036f2d0578 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -263,7 +263,7 @@ sam9x60_clk_register_frac_pll(struct regmap *regmap, sp= inlock_t *lock, =20 struct clk_hw * __init at91_clk_register_programmable(struct regmap *regmap, const char *name, - const char **parent_names, struct clk_hw **parent_hws, + const char **parent_names, struct clk_parent_data *parent_data, u8 num_parents, u8 id, const struct clk_programmable_layout *layout, u32 *mux_table); --=20 2.43.0 From nobody Wed Oct 8 20:52:50 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 372C22F0022; Tue, 24 Jun 2025 15:08:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777733; cv=none; b=E+WYJLsNjM87obpNJg6n0xpcmPRdrxEhNp9mocAJGMJ50+G/RCTv3Zyks7iV7YbUP/6EwQLEEacyPdsM3AulpUOHIAxncO/PLljrSSPPCfWpK8CLdmaunMRo51j3I0s87QQg70tPQXcERaWRE8MoKIgRIAIeN13TCweYDFvJiLo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777733; c=relaxed/simple; bh=mGNBpxLhK/suF8aQRgzePzXG6XsVBcxdF/e78gbuu1M=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=lnag56HsdkFRxau1axieHpeVthHtbudNSkLAFcc7M/3JcEgzG988dT56j6kfz4a+36NUbpW+6p2ZsrUYlAvfAvnJdvnyMsfW8pZIHcIvxaBghTyXeLEPyTsuzWbLlxr6D3VOVNb9a6XjQ5u137zBK98rqo7TcDtDT+q30fHLmGo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=PaF2XQuz; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="PaF2XQuz" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1750777731; x=1782313731; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mGNBpxLhK/suF8aQRgzePzXG6XsVBcxdF/e78gbuu1M=; b=PaF2XQuz2sP6E7EnktdSCKt2XE9pq2HgRXj4xegATYqrlNV22WLZgtkj SyA34bdVhoXIBbVo4D0TLgDvzJdAkSJ0BmVA80IStqoihSHrfEaoJimuF xTWpaUWzNPltn1LYrZhNn5biKi56pYQsmy0VvpkI8q41GQ2f7siKmjKm4 152Kr0oJLczseKHjAxxK5DQlIfGPMKw2iljT7eWHsq0WNDRebGOAorzlz 5W+gQlcpf/X3vJT4kYkztINKsVx4fDP1i2jeGaZOwWHBTskIbi3j7zV85 1uu4PqFe9Avwrljxz33FrahZeQMuYnO74DWog0d8ds73UGr8UNhGPB6Pe Q==; X-CSE-ConnectionGUID: 4+RzxTN1Qsa6vG3Bpty4nA== X-CSE-MsgGUID: rFYi28elRHSiPxGB3goiuw== X-IronPort-AV: E=Sophos;i="6.16,262,1744095600"; d="scan'208";a="42688183" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 24 Jun 2025 08:08:45 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Tue, 24 Jun 2025 08:08:37 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Tue, 24 Jun 2025 08:08:37 -0700 From: To: , , , , CC: , , , , Subject: [PATCH v2 09/32] clk: at91: clk-generated: use clk_parent_data Date: Tue, 24 Jun 2025 08:08:06 -0700 Message-ID: <2ca410a8828aa740266a3d736504b925f3a37c84.1750182562.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Use struct clk_parent_data instead of struct parent_hw as this leads to less usage of __clk_get_hw() in SoC specific clock drivers and simpler conversion of existing SoC specific clock drivers from parent_names to modern clk_parent_data structures. Signed-off-by: Claudiu Beznea [ryan.wanner@microchip.com: Remove SoC specific changes.] Signed-off-by: Ryan Wanner --- drivers/clk/at91/clk-generated.c | 8 ++++---- drivers/clk/at91/pmc.h | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/clk/at91/clk-generated.c b/drivers/clk/at91/clk-genera= ted.c index 4b4edeecc889..d9e00167dbc8 100644 --- a/drivers/clk/at91/clk-generated.c +++ b/drivers/clk/at91/clk-generated.c @@ -319,7 +319,7 @@ struct clk_hw * __init at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock, const struct clk_pcr_layout *layout, const char *name, const char **parent_names, - struct clk_hw **parent_hws, + struct clk_parent_data *parent_data, u32 *mux_table, u8 num_parents, u8 id, const struct clk_range *range, int chg_pid) @@ -329,7 +329,7 @@ at91_clk_register_generated(struct regmap *regmap, spin= lock_t *lock, struct clk_hw *hw; int ret; =20 - if (!(parent_names || parent_hws)) + if (!(parent_names || parent_data)) return ERR_PTR(-ENOMEM); =20 gck =3D kzalloc(sizeof(*gck), GFP_KERNEL); @@ -338,8 +338,8 @@ at91_clk_register_generated(struct regmap *regmap, spin= lock_t *lock, =20 init.name =3D name; init.ops =3D &generated_ops; - if (parent_hws) - init.parent_hws =3D (const struct clk_hw **)parent_hws; + if (parent_data) + init.parent_data =3D (const struct clk_parent_data *)parent_data; else init.parent_names =3D parent_names; init.num_parents =3D num_parents; diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index 34036f2d0578..0646775dfb1d 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -171,7 +171,7 @@ struct clk_hw * __init at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock, const struct clk_pcr_layout *layout, const char *name, const char **parent_names, - struct clk_hw **parent_hws, u32 *mux_table, + struct clk_parent_data *parent_data, u32 *mux_table, u8 num_parents, u8 id, const struct clk_range *range, int chg_pid); =20 --=20 2.43.0 From nobody Wed Oct 8 20:52:50 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A43712F270B; Tue, 24 Jun 2025 15:08:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777734; cv=none; b=NLKr24xrn1oIjrHdHLLDBo+rbUhOFWMHEKWDEqVx1Orf/pecsIrlcw/ldkoEQcjVcyacdqCWZbXIOwT9nXOG3mIx1qCOWT5QM8JSei531jZG12cF9iuS2QGtbvW6EgHBbdjecGyDi0mTdGs21lz8X11BtmJclegXjmTpoVtZ8rs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777734; c=relaxed/simple; bh=OGpUdaWgmzLt78/5e1PIEn4p0QRFG77KwlZ6mGggQxQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=UMcEC6PbWZ8NhFIvh3HxLmfKLG1gEMkjIO564+xZyK/g0uLdFLaxD43eSDVWX8g+VFfCOw0WX7bozT7L9LW9lRkQ8ZxMr/jkjjhkfw2UWOykU+KutKij9vnkDtx2AdsQdGkwnFgLs2+k35hRyAmNlKxF1EgbeVrVfOipJCDUgdg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=qHQVvrYW; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="qHQVvrYW" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1750777731; x=1782313731; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=OGpUdaWgmzLt78/5e1PIEn4p0QRFG77KwlZ6mGggQxQ=; b=qHQVvrYWrWQtSaYCWZFmcl72mJZXJd4raPGV/G0UrLGMI4F1J7cGSzt7 KnuGZOVTF3wGz2HDQ//QueVhYmwKi5+yXz0B/wb7gGW0SO/Mmm+o3PVGs uRBZln4WCJSrn9jKJQFtxZrHSfZYqlK0lAiU7C6Eqmo1MVM52aorNyibS j+sKDmAncgvsU04Zgt4vhYxY9RIUBm5RdrUR2Gvnon9BKoJS+t/wsqI9c HHS4pJTpvh3VmHMJhQDfAR6A8B41nRA5mEYLsU8aozTTZHXoRVV9oS2Qx ID7NHuvsodzjIw4JGRN0bOuMG+Vb/BWGe2Ub2dQ3F2q8uFtK15PRK0iA2 g==; X-CSE-ConnectionGUID: 4+RzxTN1Qsa6vG3Bpty4nA== X-CSE-MsgGUID: 3qyNMxbBR3ehMCe8tC6DDQ== X-IronPort-AV: E=Sophos;i="6.16,262,1744095600"; d="scan'208";a="42688185" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 24 Jun 2025 08:08:46 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Tue, 24 Jun 2025 08:08:37 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Tue, 24 Jun 2025 08:08:37 -0700 From: To: , , , , CC: , , , , Subject: [PATCH v2 10/32] clk: at91: clk-usb: add support for clk_parent_data Date: Tue, 24 Jun 2025 08:08:07 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Add support for clk_parent_data in usb clock driver. All the SoC based drivers that rely on clk-usb were adapted to the new API change. The switch itself for SoCs will be done in subsequent patches. Signed-off-by: Claudiu Beznea Signed-off-by: Ryan Wanner --- drivers/clk/at91/at91rm9200.c | 2 +- drivers/clk/at91/at91sam9260.c | 2 +- drivers/clk/at91/at91sam9g45.c | 2 +- drivers/clk/at91/at91sam9n12.c | 2 +- drivers/clk/at91/at91sam9x5.c | 2 +- drivers/clk/at91/clk-usb.c | 41 ++++++++++++++++++++++------------ drivers/clk/at91/dt-compat.c | 6 ++--- drivers/clk/at91/pmc.h | 11 +++++---- drivers/clk/at91/sam9x60.c | 2 +- drivers/clk/at91/sama5d2.c | 2 +- drivers/clk/at91/sama5d3.c | 2 +- drivers/clk/at91/sama5d4.c | 2 +- 12 files changed, 46 insertions(+), 30 deletions(-) diff --git a/drivers/clk/at91/at91rm9200.c b/drivers/clk/at91/at91rm9200.c index 3f19e737ae4d..e5a034f208d8 100644 --- a/drivers/clk/at91/at91rm9200.c +++ b/drivers/clk/at91/at91rm9200.c @@ -157,7 +157,7 @@ static void __init at91rm9200_pmc_setup(struct device_n= ode *np) =20 at91rm9200_pmc->chws[PMC_MCK] =3D hw; =20 - hw =3D at91rm9200_clk_register_usb(regmap, "usbck", "pllbck", usb_div); + hw =3D at91rm9200_clk_register_usb(regmap, "usbck", "pllbck", NULL, usb_d= iv); if (IS_ERR(hw)) goto err_free; =20 diff --git a/drivers/clk/at91/at91sam9260.c b/drivers/clk/at91/at91sam9260.c index 0799a13060ea..ae6f126f204a 100644 --- a/drivers/clk/at91/at91sam9260.c +++ b/drivers/clk/at91/at91sam9260.c @@ -434,7 +434,7 @@ static void __init at91sam926x_pmc_setup(struct device_= node *np, =20 at91sam9260_pmc->chws[PMC_MCK] =3D hw; =20 - hw =3D at91rm9200_clk_register_usb(regmap, "usbck", "pllbck", usb_div); + hw =3D at91rm9200_clk_register_usb(regmap, "usbck", "pllbck", NULL, usb_d= iv); if (IS_ERR(hw)) goto err_free; =20 diff --git a/drivers/clk/at91/at91sam9g45.c b/drivers/clk/at91/at91sam9g45.c index f45a7b80f7d8..684d2bcb36e8 100644 --- a/drivers/clk/at91/at91sam9g45.c +++ b/drivers/clk/at91/at91sam9g45.c @@ -176,7 +176,7 @@ static void __init at91sam9g45_pmc_setup(struct device_= node *np) =20 parent_names[0] =3D "plladivck"; parent_names[1] =3D "utmick"; - hw =3D at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, 2); + hw =3D at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, NULL, 2= ); if (IS_ERR(hw)) goto err_free; =20 diff --git a/drivers/clk/at91/at91sam9n12.c b/drivers/clk/at91/at91sam9n12.c index 751786184ae2..9fc20b177b13 100644 --- a/drivers/clk/at91/at91sam9n12.c +++ b/drivers/clk/at91/at91sam9n12.c @@ -201,7 +201,7 @@ static void __init at91sam9n12_pmc_setup(struct device_= node *np) =20 at91sam9n12_pmc->chws[PMC_MCK] =3D hw; =20 - hw =3D at91sam9n12_clk_register_usb(regmap, "usbck", "pllbck"); + hw =3D at91sam9n12_clk_register_usb(regmap, "usbck", "pllbck", NULL); if (IS_ERR(hw)) goto err_free; =20 diff --git a/drivers/clk/at91/at91sam9x5.c b/drivers/clk/at91/at91sam9x5.c index 3b801d12fac0..5728cfb9036f 100644 --- a/drivers/clk/at91/at91sam9x5.c +++ b/drivers/clk/at91/at91sam9x5.c @@ -222,7 +222,7 @@ static void __init at91sam9x5_pmc_setup(struct device_n= ode *np, =20 parent_names[0] =3D "plladivck"; parent_names[1] =3D "utmick"; - hw =3D at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, 2); + hw =3D at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, NULL, 2= ); if (IS_ERR(hw)) goto err_free; =20 diff --git a/drivers/clk/at91/clk-usb.c b/drivers/clk/at91/clk-usb.c index b0696a928aa9..b2503fad4543 100644 --- a/drivers/clk/at91/clk-usb.c +++ b/drivers/clk/at91/clk-usb.c @@ -221,12 +221,12 @@ static const struct clk_ops at91sam9n12_usb_ops =3D { =20 static struct clk_hw * __init _at91sam9x5_clk_register_usb(struct regmap *regmap, const char *name, - const char **parent_names, u8 num_parents, - u32 usbs_mask) + const char **parent_names, struct clk_parent_data *parent_data, + u8 num_parents, u32 usbs_mask) { struct at91sam9x5_clk_usb *usb; struct clk_hw *hw; - struct clk_init_data init; + struct clk_init_data init =3D {}; int ret; =20 usb =3D kzalloc(sizeof(*usb), GFP_KERNEL); @@ -235,7 +235,10 @@ _at91sam9x5_clk_register_usb(struct regmap *regmap, co= nst char *name, =20 init.name =3D name; init.ops =3D &at91sam9x5_usb_ops; - init.parent_names =3D parent_names; + if (parent_data) + init.parent_data =3D (const struct clk_parent_data *)parent_data; + else + init.parent_names =3D parent_names; init.num_parents =3D num_parents; init.flags =3D CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | CLK_SET_RATE_PARENT; @@ -257,27 +260,30 @@ _at91sam9x5_clk_register_usb(struct regmap *regmap, c= onst char *name, =20 struct clk_hw * __init at91sam9x5_clk_register_usb(struct regmap *regmap, const char *name, - const char **parent_names, u8 num_parents) + const char **parent_names, struct clk_parent_data *parent_data, + u8 num_parents) { return _at91sam9x5_clk_register_usb(regmap, name, parent_names, - num_parents, SAM9X5_USBS_MASK); + parent_data, num_parents, SAM9X5_USBS_MASK); } =20 struct clk_hw * __init sam9x60_clk_register_usb(struct regmap *regmap, const char *name, - const char **parent_names, u8 num_parents) + const char **parent_names, struct clk_parent_data *parent_data, + u8 num_parents) { return _at91sam9x5_clk_register_usb(regmap, name, parent_names, - num_parents, SAM9X60_USBS_MASK); + parent_data, num_parents, + SAM9X60_USBS_MASK); } =20 struct clk_hw * __init at91sam9n12_clk_register_usb(struct regmap *regmap, const char *name, - const char *parent_name) + const char *parent_name, struct clk_parent_data *parent_data) { struct at91sam9x5_clk_usb *usb; struct clk_hw *hw; - struct clk_init_data init; + struct clk_init_data init =3D {}; int ret; =20 usb =3D kzalloc(sizeof(*usb), GFP_KERNEL); @@ -286,7 +292,10 @@ at91sam9n12_clk_register_usb(struct regmap *regmap, co= nst char *name, =20 init.name =3D name; init.ops =3D &at91sam9n12_usb_ops; - init.parent_names =3D &parent_name; + if (parent_data) + init.parent_data =3D (const struct clk_parent_data *)parent_data; + else + init.parent_names =3D &parent_name; init.num_parents =3D 1; init.flags =3D CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT; =20 @@ -390,11 +399,12 @@ static const struct clk_ops at91rm9200_usb_ops =3D { =20 struct clk_hw * __init at91rm9200_clk_register_usb(struct regmap *regmap, const char *name, - const char *parent_name, const u32 *divisors) + const char *parent_name, struct clk_parent_data *parent_data, + const u32 *divisors) { struct at91rm9200_clk_usb *usb; struct clk_hw *hw; - struct clk_init_data init; + struct clk_init_data init =3D {}; int ret; =20 usb =3D kzalloc(sizeof(*usb), GFP_KERNEL); @@ -403,7 +413,10 @@ at91rm9200_clk_register_usb(struct regmap *regmap, con= st char *name, =20 init.name =3D name; init.ops =3D &at91rm9200_usb_ops; - init.parent_names =3D &parent_name; + if (parent_data) + init.parent_data =3D (const struct clk_parent_data *)parent_data; + else + init.parent_names =3D &parent_name; init.num_parents =3D 1; init.flags =3D CLK_SET_RATE_PARENT; =20 diff --git a/drivers/clk/at91/dt-compat.c b/drivers/clk/at91/dt-compat.c index f5a5f9ba7634..7883198f6a98 100644 --- a/drivers/clk/at91/dt-compat.c +++ b/drivers/clk/at91/dt-compat.c @@ -946,7 +946,7 @@ static void __init of_at91sam9x5_clk_usb_setup(struct d= evice_node *np) if (IS_ERR(regmap)) return; =20 - hw =3D at91sam9x5_clk_register_usb(regmap, name, parent_names, + hw =3D at91sam9x5_clk_register_usb(regmap, name, parent_names, NULL, num_parents); if (IS_ERR(hw)) return; @@ -976,7 +976,7 @@ static void __init of_at91sam9n12_clk_usb_setup(struct = device_node *np) if (IS_ERR(regmap)) return; =20 - hw =3D at91sam9n12_clk_register_usb(regmap, name, parent_name); + hw =3D at91sam9n12_clk_register_usb(regmap, name, parent_name, NULL); if (IS_ERR(hw)) return; =20 @@ -1009,7 +1009,7 @@ static void __init of_at91rm9200_clk_usb_setup(struct= device_node *np) of_node_put(parent_np); if (IS_ERR(regmap)) return; - hw =3D at91rm9200_clk_register_usb(regmap, name, parent_name, divisors); + hw =3D at91rm9200_clk_register_usb(regmap, name, parent_name, NULL, divis= ors); if (IS_ERR(hw)) return; =20 diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index 0646775dfb1d..c66ee44255d7 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -285,16 +285,19 @@ at91_clk_register_system(struct regmap *regmap, const= char *name, =20 struct clk_hw * __init at91sam9x5_clk_register_usb(struct regmap *regmap, const char *name, - const char **parent_names, u8 num_parents); + const char **parent_names, struct clk_parent_data *parent_data, + u8 num_parents); struct clk_hw * __init at91sam9n12_clk_register_usb(struct regmap *regmap, const char *name, - const char *parent_name); + const char *parent_name, struct clk_parent_data *parent_data); struct clk_hw * __init sam9x60_clk_register_usb(struct regmap *regmap, const char *name, - const char **parent_names, u8 num_parents); + const char **parent_names, struct clk_parent_data *parent_data, + u8 num_parents); struct clk_hw * __init at91rm9200_clk_register_usb(struct regmap *regmap, const char *name, - const char *parent_name, const u32 *divisors); + const char *parent_name, struct clk_parent_data *parent_data, + const u32 *divisors); =20 struct clk_hw * __init at91_clk_register_utmi(struct regmap *regmap_pmc, struct regmap *regmap_sf= r, diff --git a/drivers/clk/at91/sam9x60.c b/drivers/clk/at91/sam9x60.c index db6db9e2073e..d959b30e1352 100644 --- a/drivers/clk/at91/sam9x60.c +++ b/drivers/clk/at91/sam9x60.c @@ -304,7 +304,7 @@ static void __init sam9x60_pmc_setup(struct device_node= *np) parent_names[0] =3D "pllack_divck"; parent_names[1] =3D "upllck_divck"; parent_names[2] =3D "main_osc"; - hw =3D sam9x60_clk_register_usb(regmap, "usbck", parent_names, 3); + hw =3D sam9x60_clk_register_usb(regmap, "usbck", parent_names, NULL, 3); if (IS_ERR(hw)) goto err_free; =20 diff --git a/drivers/clk/at91/sama5d2.c b/drivers/clk/at91/sama5d2.c index c16594fce90c..8bbc34e22cda 100644 --- a/drivers/clk/at91/sama5d2.c +++ b/drivers/clk/at91/sama5d2.c @@ -284,7 +284,7 @@ static void __init sama5d2_pmc_setup(struct device_node= *np) =20 parent_names[0] =3D "plladivck"; parent_names[1] =3D "utmick"; - hw =3D at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, 2); + hw =3D at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, NULL, 2= ); if (IS_ERR(hw)) goto err_free; =20 diff --git a/drivers/clk/at91/sama5d3.c b/drivers/clk/at91/sama5d3.c index 522ce6031446..05d0cdd22bc4 100644 --- a/drivers/clk/at91/sama5d3.c +++ b/drivers/clk/at91/sama5d3.c @@ -201,7 +201,7 @@ static void __init sama5d3_pmc_setup(struct device_node= *np) =20 parent_names[0] =3D "plladivck"; parent_names[1] =3D "utmick"; - hw =3D at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, 2); + hw =3D at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, NULL, 2= ); if (IS_ERR(hw)) goto err_free; =20 diff --git a/drivers/clk/at91/sama5d4.c b/drivers/clk/at91/sama5d4.c index 160c0bddb6a3..da84b4cef827 100644 --- a/drivers/clk/at91/sama5d4.c +++ b/drivers/clk/at91/sama5d4.c @@ -222,7 +222,7 @@ static void __init sama5d4_pmc_setup(struct device_node= *np) =20 parent_names[0] =3D "plladivck"; parent_names[1] =3D "utmick"; - hw =3D at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, 2); + hw =3D at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, NULL, 2= ); if (IS_ERR(hw)) goto err_free; =20 --=20 2.43.0 From nobody Wed Oct 8 20:52:50 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1A2852D9EDF; Tue, 24 Jun 2025 15:08:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777734; cv=none; b=WPGj4fe4iNxxlwq1RPYQSu+E+ddTm+LRxgCqWSD5tu+FHsyx+B1iXUGCfRSjcuJ4b9FYGd8u7dlqhqHZXXEPgatPkUZARziMxpAPLHI0I73HKK5a6NylAgI+A3JYgM+gonE0wTC+QkNoUWjgpa+eECzHwGT+6z+YT+dW7bc3tSM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777734; c=relaxed/simple; bh=wcQCCQ4uaXtZbvFd2XYJ6W0tmvuYiFFyHsqGjqUUthA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=M+IatzgnQkZx9o03kfPPm/9lNAl4lgP3BvWuxe/Hf0a8Yje2REeWABd12lr5o1PgSNZ8M8rWpzQWE1hTkhVAFXTHWZs273MYy3dC04bDfW4oqsStU5YU1h3EtlXrZ8yMxhgAhIiA8nV7RmT7swwqlBcWMhEPxwtqtCkbPJIMFeM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=XpHxnWVb; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="XpHxnWVb" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1750777731; x=1782313731; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wcQCCQ4uaXtZbvFd2XYJ6W0tmvuYiFFyHsqGjqUUthA=; b=XpHxnWVb/0aFjgfl70Nl1HQDxAtpYdQIzwhufoCbLv154PA9F2N5qB+Q D9GF0hJPcocF9ujGnIgBMNoDm3yiQg9gvS99DJJAd7zSAnq1O9moU6+ar Jn3FitOdPF57bIEuaYYMchJ2yuH9HXS6kRlxGrNyDujwTx/0osnmJZazD k6bJTwss5bJTv8lBNVvRczXiyu6avbveLssdPZPsy8UGjdu+eUjl1n5MM hT5Q5BI+ES+TBROkon4bKJzoERWxCVgB8Dh82mlGiyjDmRa0OlMqP618C nkTeI0ECTUXvCU5xb6uyAOF6fkgrjXSPGtmZQu39EBh4jEq2WP25juxq4 w==; X-CSE-ConnectionGUID: 4+RzxTN1Qsa6vG3Bpty4nA== X-CSE-MsgGUID: qwvEBGcpT7WaoKH9MHFjVw== X-IronPort-AV: E=Sophos;i="6.16,262,1744095600"; d="scan'208";a="42688186" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 24 Jun 2025 08:08:46 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Tue, 24 Jun 2025 08:08:37 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Tue, 24 Jun 2025 08:08:37 -0700 From: To: , , , , CC: , , , , Subject: [PATCH v2 11/32] clk: at91: clk-system: use clk_parent_data Date: Tue, 24 Jun 2025 08:08:08 -0700 Message-ID: <59b77d6860468d607020741bbd2050fd01730c6f.1750182562.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Use struct clk_parent_data instead of struct parent_hw as this leads to less usage of __clk_get_hw() in SoC specific clock drivers and simpler conversion of existing SoC specific clock drivers from parent_names to modern clk_parent_data structures. Signed-off-by: Claudiu Beznea [ryan.wanner@microchip.com: Remove SoC specific changes.] Signed-off-by: Ryan Wanner --- drivers/clk/at91/clk-system.c | 8 ++++---- drivers/clk/at91/pmc.h | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/clk/at91/clk-system.c b/drivers/clk/at91/clk-system.c index 90eed39d0785..55f8e46fe9c7 100644 --- a/drivers/clk/at91/clk-system.c +++ b/drivers/clk/at91/clk-system.c @@ -105,7 +105,7 @@ static const struct clk_ops system_ops =3D { =20 struct clk_hw * __init at91_clk_register_system(struct regmap *regmap, const char *name, - const char *parent_name, struct clk_hw *parent_hw, u8 id, + const char *parent_name, struct clk_parent_data *parent_data, u8 id, unsigned long flags) { struct clk_system *sys; @@ -113,7 +113,7 @@ at91_clk_register_system(struct regmap *regmap, const c= har *name, struct clk_init_data init =3D {}; int ret; =20 - if (!(parent_name || parent_hw) || id > SYSTEM_MAX_ID) + if (!(parent_name || parent_data) || id > SYSTEM_MAX_ID) return ERR_PTR(-EINVAL); =20 sys =3D kzalloc(sizeof(*sys), GFP_KERNEL); @@ -122,8 +122,8 @@ at91_clk_register_system(struct regmap *regmap, const c= har *name, =20 init.name =3D name; init.ops =3D &system_ops; - if (parent_hw) - init.parent_hws =3D (const struct clk_hw **)&parent_hw; + if (parent_data) + init.parent_data =3D (const struct clk_parent_data *)parent_data; else init.parent_names =3D &parent_name; init.num_parents =3D 1; diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index c66ee44255d7..87ab1211576f 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -280,7 +280,7 @@ at91sam9x5_clk_register_smd(struct regmap *regmap, cons= t char *name, =20 struct clk_hw * __init at91_clk_register_system(struct regmap *regmap, const char *name, - const char *parent_name, struct clk_hw *parent_hw, + const char *parent_name, struct clk_parent_data *parent_data, u8 id, unsigned long flags); =20 struct clk_hw * __init --=20 2.43.0 From nobody Wed Oct 8 20:52:50 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 827F22D9EFF; Tue, 24 Jun 2025 15:08:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777735; cv=none; b=cM3HUmve3i5TNUWxMVcRz7WQaL3RsKRTeiW6HbFCRi/jzLUdLGXpy9BbpUpD/kWapJ3XaISx+lGnjpYYMhg/yp6XkqzZnk//r0SsPagasGaqnty5HGtgfRPkMDu6sQK7GbJKsiech9U1lqjoaBa9oJzq1xH/se2gLo83k01OeiU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777735; c=relaxed/simple; bh=IOmmE+u6QTHG7zImgwkpWUVJQIDMRXSw76pKyrmRpPE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=e18807LD3rUp8FFabovjE4tNhIEvpFoXw03H+sh2xOgQxN/WxIVmHKnJnnbf8LF01HUPmxeFKRctPupwr8zf1kBJBow5xTSXb+Ht0Zbm4oG4HjZWBCTC9k2qfpUIKgYsG+ttCp/V0mAq3BVD9Cozkmp6pE21w42DTJtj4B4KNu8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=Y/Pe3NGj; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="Y/Pe3NGj" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1750777733; x=1782313733; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=IOmmE+u6QTHG7zImgwkpWUVJQIDMRXSw76pKyrmRpPE=; b=Y/Pe3NGjS0wlVMOvomGCdpCrh9nJq32t5J+s5O6eP8UdsQVJq2up/l80 GXr9ZNCNbTgHMX2q5cexFmrTnXfBbuesPiAUO2VcZvMwfdSpEghfflwYo V+YL27B4M66hQGqVpTK2GfwD2HfXTS2gOPrAf1vfZ32oXWGFTLWdSkLM/ qKFEZTMfFnyDrHZnW8nh2XtFPvnXHm48Un9/RnCoqMJl7GqfBKztYdl3M CkkR++z1nRBVd9DGg+bRpnlgcGsW4KteDoztIJlzqJ27CsxzAH+1AQ0KB DGsN7tY6I1wziRa97BVLIyJaGQglFJfuhcf9V3uz1a8uEmXQuddB5oUeR g==; X-CSE-ConnectionGUID: 4+RzxTN1Qsa6vG3Bpty4nA== X-CSE-MsgGUID: sq55A1TYTk+js9keUGKarA== X-IronPort-AV: E=Sophos;i="6.16,262,1744095600"; d="scan'208";a="42688187" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 24 Jun 2025 08:08:47 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Tue, 24 Jun 2025 08:08:37 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Tue, 24 Jun 2025 08:08:37 -0700 From: To: , , , , CC: , , , , Subject: [PATCH v2 12/32] clk: at91: clk-pll: add support for parent_hw Date: Tue, 24 Jun 2025 08:08:09 -0700 Message-ID: <46b968a38e722af2fbe6f2f4219add67323f05b9.1750182562.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Add support for parent_hw in pll clock driver. With this parent-child relation is described with pointers rather than strings making registration a bit faster. All the SoC based drivers that rely on clk-pll were adapted to the new API change. The switch itself for SoCs will be done in subsequent patches. Signed-off-by: Claudiu Beznea [ryan.wanner@microchip.com: Remove SoC specific changes as they are going to be coalesced into one SoC specific commit.] Signed-off-by: Ryan Wanner --- drivers/clk/at91/clk-pll.c | 9 ++++++--- drivers/clk/at91/dt-compat.c | 2 +- drivers/clk/at91/pmc.h | 2 +- 3 files changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/clk/at91/clk-pll.c b/drivers/clk/at91/clk-pll.c index 249d6a53cedf..f973c3b1bbec 100644 --- a/drivers/clk/at91/clk-pll.c +++ b/drivers/clk/at91/clk-pll.c @@ -310,13 +310,13 @@ static const struct clk_ops pll_ops =3D { =20 struct clk_hw * __init at91_clk_register_pll(struct regmap *regmap, const char *name, - const char *parent_name, u8 id, + const char *parent_name, struct clk_parent_data *parent_data, u8 i= d, const struct clk_pll_layout *layout, const struct clk_pll_characteristics *characteristics) { struct clk_pll *pll; struct clk_hw *hw; - struct clk_init_data init; + struct clk_init_data init =3D {}; int offset =3D PLL_REG(id); unsigned int pllr; int ret; @@ -330,7 +330,10 @@ at91_clk_register_pll(struct regmap *regmap, const cha= r *name, =20 init.name =3D name; init.ops =3D &pll_ops; - init.parent_names =3D &parent_name; + if (parent_data) + init.parent_data =3D (const struct clk_parent_data *)parent_data; + else + init.parent_names =3D &parent_name; init.num_parents =3D 1; init.flags =3D CLK_SET_RATE_GATE; =20 diff --git a/drivers/clk/at91/dt-compat.c b/drivers/clk/at91/dt-compat.c index 7883198f6a98..2c5faa3b1cfd 100644 --- a/drivers/clk/at91/dt-compat.c +++ b/drivers/clk/at91/dt-compat.c @@ -665,7 +665,7 @@ of_at91_clk_pll_setup(struct device_node *np, if (!characteristics) return; =20 - hw =3D at91_clk_register_pll(regmap, name, parent_name, id, layout, + hw =3D at91_clk_register_pll(regmap, name, parent_name, NULL, id, layout, characteristics); if (IS_ERR(hw)) goto out_free_characteristics; diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index 87ab1211576f..0feaf8497b60 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -238,7 +238,7 @@ at91_clk_register_sam9x5_peripheral(struct regmap *regm= ap, spinlock_t *lock, =20 struct clk_hw * __init at91_clk_register_pll(struct regmap *regmap, const char *name, - const char *parent_name, u8 id, + const char *parent_name, struct clk_parent_data *parent_data, u8 i= d, const struct clk_pll_layout *layout, const struct clk_pll_characteristics *characteristics); struct clk_hw * __init --=20 2.43.0 From nobody Wed Oct 8 20:52:50 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3CAD62F3C17; Tue, 24 Jun 2025 15:08:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777736; cv=none; b=P6fYpMIUsfP+R4Pr+w7phyhUaNlrby2ibgvD7w5WLFxHSngCscxcJAnlpOfmAP2bWO/PRDlgytcii6a6LcSNtjJqvyREXzUAoW7IKYNm557KIhORQA0vRvJfmKueAqBOa1MUOLalJTS3JzHoBbwM30+KdyxZEIGJtxU9cNDR9CI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777736; c=relaxed/simple; bh=XmdhpYDW+3QqRjHcegC00+obRxvH9zemgREp2uxK+Go=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=BlY93V+6zILs7OvuqG8xyq4bcqI+VF4ZokJt6yKcqy9qrhqPOSl066i8kpCeUudyzpN+L8j9YXB+a1MGVJQhfGlmybz6bP5nRYjHgkPXkAz+eRAbX0fCXbqur67PTdmn+ES9382vvWgmbB5R4F/C4gOsPiVzHUYt30JpNanROc4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=u3OguPGk; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="u3OguPGk" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1750777734; x=1782313734; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=XmdhpYDW+3QqRjHcegC00+obRxvH9zemgREp2uxK+Go=; b=u3OguPGkM21ePbDaRRCzChpIPrccueYz/y6tSRBqL5zO0qcOzjwaH2b7 sJRXc0yTHQ1B6HF7jivbFqWSSOGJhPRorfC1ZxY865cWpMVFu58w7KjHD 2zVyPehJzt72O4WWX52AhFOWS+x3V5+uAUoiojuQzRPP08aXFf8b6ev3a rBtnlzpwI4oDHYLmwgYsFcaJzr0+JXWBvrQhNM9+aZNinwNq2oKXo4MBu RMVXaCIJbMtX0oDSA7+jicz2wl3nkhez880dcYDilgnSBftNhaG3Ciq6y JutoDB0ZVofT6seAKy/dQzshU1UTpL+DyO7ksVejvlT+epA54O1vwvoJr g==; X-CSE-ConnectionGUID: 4+RzxTN1Qsa6vG3Bpty4nA== X-CSE-MsgGUID: NWLryf3aSAOkeiKqt8hB/w== X-IronPort-AV: E=Sophos;i="6.16,262,1744095600"; d="scan'208";a="42688189" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 24 Jun 2025 08:08:47 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Tue, 24 Jun 2025 08:08:38 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Tue, 24 Jun 2025 08:08:38 -0700 From: To: , , , , CC: , , , , Subject: [PATCH v2 13/32] clk: at91: clk-audio-pll: add support for parent_hw Date: Tue, 24 Jun 2025 08:08:10 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Add support for parent_hw in audio pll clock drivers. With this parent-child relation is described with pointers rather than strings making registration a bit faster. All the SoC based drivers that rely on clk-audio-pll were adapted to the new API change. The switch itself for SoCs will be done in subsequent patches. Signed-off-by: Claudiu Beznea [ryan.wanner@microchip.com: Remove SoC specific changes as they are going to be coalesced into one SoC specific commit.] Signed-off-by: Ryan Wanner --- drivers/clk/at91/clk-audio-pll.c | 28 ++++++++++++++++++++-------- drivers/clk/at91/dt-compat.c | 6 +++--- drivers/clk/at91/pmc.h | 6 +++--- 3 files changed, 26 insertions(+), 14 deletions(-) diff --git a/drivers/clk/at91/clk-audio-pll.c b/drivers/clk/at91/clk-audio-= pll.c index a92da64c12e1..da9b2e699dcc 100644 --- a/drivers/clk/at91/clk-audio-pll.c +++ b/drivers/clk/at91/clk-audio-pll.c @@ -450,7 +450,8 @@ static const struct clk_ops audio_pll_pmc_ops =3D { =20 struct clk_hw * __init at91_clk_register_audio_pll_frac(struct regmap *regmap, const char *name, - const char *parent_name) + const char *parent_name, + struct clk_parent_data *parent_data) { struct clk_audio_frac *frac_ck; struct clk_init_data init =3D {}; @@ -462,7 +463,10 @@ at91_clk_register_audio_pll_frac(struct regmap *regmap= , const char *name, =20 init.name =3D name; init.ops =3D &audio_pll_frac_ops; - init.parent_names =3D &parent_name; + if (parent_data) + init.parent_data =3D (const struct clk_parent_data *)parent_data; + else + init.parent_names =3D &parent_name; init.num_parents =3D 1; init.flags =3D CLK_SET_RATE_GATE; =20 @@ -480,10 +484,11 @@ at91_clk_register_audio_pll_frac(struct regmap *regma= p, const char *name, =20 struct clk_hw * __init at91_clk_register_audio_pll_pad(struct regmap *regmap, const char *name, - const char *parent_name) + const char *parent_name, + struct clk_parent_data *parent_data) { struct clk_audio_pad *apad_ck; - struct clk_init_data init; + struct clk_init_data init =3D {}; int ret; =20 apad_ck =3D kzalloc(sizeof(*apad_ck), GFP_KERNEL); @@ -492,7 +497,10 @@ at91_clk_register_audio_pll_pad(struct regmap *regmap,= const char *name, =20 init.name =3D name; init.ops =3D &audio_pll_pad_ops; - init.parent_names =3D &parent_name; + if (parent_data) + init.parent_data =3D (const struct clk_parent_data *)parent_data; + else + init.parent_names =3D &parent_name; init.num_parents =3D 1; init.flags =3D CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | CLK_SET_RATE_PARENT; @@ -511,10 +519,11 @@ at91_clk_register_audio_pll_pad(struct regmap *regmap= , const char *name, =20 struct clk_hw * __init at91_clk_register_audio_pll_pmc(struct regmap *regmap, const char *name, - const char *parent_name) + const char *parent_name, + struct clk_parent_data *parent_data) { struct clk_audio_pmc *apmc_ck; - struct clk_init_data init; + struct clk_init_data init =3D {}; int ret; =20 apmc_ck =3D kzalloc(sizeof(*apmc_ck), GFP_KERNEL); @@ -523,7 +532,10 @@ at91_clk_register_audio_pll_pmc(struct regmap *regmap,= const char *name, =20 init.name =3D name; init.ops =3D &audio_pll_pmc_ops; - init.parent_names =3D &parent_name; + if (parent_data) + init.parent_data =3D (const struct clk_parent_data *)parent_data; + else + init.parent_names =3D &parent_name; init.num_parents =3D 1; init.flags =3D CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | CLK_SET_RATE_PARENT; diff --git a/drivers/clk/at91/dt-compat.c b/drivers/clk/at91/dt-compat.c index 2c5faa3b1cfd..22bcaa3b28dd 100644 --- a/drivers/clk/at91/dt-compat.c +++ b/drivers/clk/at91/dt-compat.c @@ -43,7 +43,7 @@ static void __init of_sama5d2_clk_audio_pll_frac_setup(st= ruct device_node *np) =20 parent_name =3D of_clk_get_parent_name(np, 0); =20 - hw =3D at91_clk_register_audio_pll_frac(regmap, name, parent_name); + hw =3D at91_clk_register_audio_pll_frac(regmap, name, parent_name, NULL); if (IS_ERR(hw)) return; =20 @@ -69,7 +69,7 @@ static void __init of_sama5d2_clk_audio_pll_pad_setup(str= uct device_node *np) =20 parent_name =3D of_clk_get_parent_name(np, 0); =20 - hw =3D at91_clk_register_audio_pll_pad(regmap, name, parent_name); + hw =3D at91_clk_register_audio_pll_pad(regmap, name, parent_name, NULL); if (IS_ERR(hw)) return; =20 @@ -95,7 +95,7 @@ static void __init of_sama5d2_clk_audio_pll_pmc_setup(str= uct device_node *np) =20 parent_name =3D of_clk_get_parent_name(np, 0); =20 - hw =3D at91_clk_register_audio_pll_pmc(regmap, name, parent_name); + hw =3D at91_clk_register_audio_pll_pmc(regmap, name, parent_name, NULL); if (IS_ERR(hw)) return; =20 diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index 0feaf8497b60..519d71652619 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -157,15 +157,15 @@ struct clk_hw *of_clk_hw_pmc_get(struct of_phandle_ar= gs *clkspec, void *data); =20 struct clk_hw * __init at91_clk_register_audio_pll_frac(struct regmap *regmap, const char *name, - const char *parent_name); + const char *parent_name, struct clk_parent_data *parent_data); =20 struct clk_hw * __init at91_clk_register_audio_pll_pad(struct regmap *regmap, const char *name, - const char *parent_name); + const char *parent_name, struct clk_parent_data *parent_data); =20 struct clk_hw * __init at91_clk_register_audio_pll_pmc(struct regmap *regmap, const char *name, - const char *parent_name); + const char *parent_name, struct clk_parent_data *parent_data); =20 struct clk_hw * __init at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock, --=20 2.43.0 From nobody Wed Oct 8 20:52:50 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6129E2F3C26; Tue, 24 Jun 2025 15:08:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777736; cv=none; b=KdYYKYwDQjUP1pApCxw8qJ6CMzIGiht573522tpmSEWty7PZwZN6mfz96AIeXWf/z/u3hFB6VwW/FilTzBbIX6C6NCp4iwPoMbljStGtCwQc0QPp8mDA8VqIfSJBGALkK3aXom0uQQ0AHQ7BYajH8geY8vu/Bvh22lpo0aQ5geM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777736; c=relaxed/simple; bh=ewK93IZBE5AdW/boaGsKbjjZ+eEA2xMxJ1F5syBIWcM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=G7e9lT9ND9BANpyJPjDczeJXIPTr5ozLnWFnDxY3sX5DJLY7T6DbNm4VFDiEvHTKSP4iEOwr2xk9/o879XEElEFbGmhALx1u/wMrBxTrBrp6HLNLldPeEC9gz7HX8nJ8MWuJUCRLi4IUDbwwVXs2SaSMpkp2N2OlT6hKDgeGJI4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=KJ2VTkxP; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="KJ2VTkxP" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1750777734; x=1782313734; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ewK93IZBE5AdW/boaGsKbjjZ+eEA2xMxJ1F5syBIWcM=; b=KJ2VTkxPROhjeUFQh0jpo8dNlY7IILETWrKHSKuL1Sss98P5u5jS2E4F BmJx3K8K2LwUpcpyO1IIPisec/96MWH1uNIMG5HfW+OIEEM7u9RQbNZI9 yfPdh+CQJiTafl63v3yYF1Usa9cCUKSFI79quTizE0Xafy9miO7wYAK/a HkV4T4YeB/kSKiz+TcmPh64+Isj0ZGdvrkP+Z5j6PRdEY97pX95FZEUjy GFdez2QpChlixgO1AT4gBylePWkBK/+xvzQesrIHlUilLLIX5N992VdsT EG3Aj6R5UoR/SxbRP1roxNSQWbMMRkLRh4KGghNr3IO0BaBs0hvNwcuWl Q==; X-CSE-ConnectionGUID: 4+RzxTN1Qsa6vG3Bpty4nA== X-CSE-MsgGUID: JmQSy8bSSGanE8uo8FA/cA== X-IronPort-AV: E=Sophos;i="6.16,262,1744095600"; d="scan'208";a="42688191" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 24 Jun 2025 08:08:47 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Tue, 24 Jun 2025 08:08:38 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Tue, 24 Jun 2025 08:08:38 -0700 From: To: , , , , CC: , , , , Subject: [PATCH v2 14/32] clk: at91: clk-plldiv: add support for parent_hw Date: Tue, 24 Jun 2025 08:08:11 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Add support for parent_hw in plldiv clock driver. With this parent-child relation is described with pointers rather than strings making registration a bit faster. All the SoC based drivers that rely on clk-plldiv were adapted to the new API change. The switch itself for SoCs will be done in subsequent patches. Signed-off-by: Claudiu Beznea [ryan.wanner@microchip.com: Remove SoC specific changes as they are going to be coalesced into one SoC specific commit.] Signed-off-by: Ryan Wanner --- drivers/clk/at91/clk-plldiv.c | 11 +++++++---- drivers/clk/at91/dt-compat.c | 2 +- drivers/clk/at91/pmc.h | 2 +- 3 files changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/clk/at91/clk-plldiv.c b/drivers/clk/at91/clk-plldiv.c index ba3a1839a96d..c5d0c6e27397 100644 --- a/drivers/clk/at91/clk-plldiv.c +++ b/drivers/clk/at91/clk-plldiv.c @@ -72,11 +72,11 @@ static const struct clk_ops plldiv_ops =3D { =20 struct clk_hw * __init at91_clk_register_plldiv(struct regmap *regmap, const char *name, - const char *parent_name) + const char *parent_name, struct clk_parent_data *parent_data) { struct clk_plldiv *plldiv; struct clk_hw *hw; - struct clk_init_data init; + struct clk_init_data init =3D {}; int ret; =20 plldiv =3D kzalloc(sizeof(*plldiv), GFP_KERNEL); @@ -85,8 +85,11 @@ at91_clk_register_plldiv(struct regmap *regmap, const ch= ar *name, =20 init.name =3D name; init.ops =3D &plldiv_ops; - init.parent_names =3D parent_name ? &parent_name : NULL; - init.num_parents =3D parent_name ? 1 : 0; + if (parent_data) + init.parent_data =3D (const struct clk_parent_data *)parent_data; + else + init.parent_names =3D &parent_name; + init.num_parents =3D 1; init.flags =3D CLK_SET_RATE_GATE; =20 plldiv->hw.init =3D &init; diff --git a/drivers/clk/at91/dt-compat.c b/drivers/clk/at91/dt-compat.c index 22bcaa3b28dd..3285e3110b58 100644 --- a/drivers/clk/at91/dt-compat.c +++ b/drivers/clk/at91/dt-compat.c @@ -724,7 +724,7 @@ of_at91sam9x5_clk_plldiv_setup(struct device_node *np) if (IS_ERR(regmap)) return; =20 - hw =3D at91_clk_register_plldiv(regmap, name, parent_name); + hw =3D at91_clk_register_plldiv(regmap, name, parent_name, NULL); if (IS_ERR(hw)) return; =20 diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index 519d71652619..df2deb134a8d 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -243,7 +243,7 @@ at91_clk_register_pll(struct regmap *regmap, const char= *name, const struct clk_pll_characteristics *characteristics); struct clk_hw * __init at91_clk_register_plldiv(struct regmap *regmap, const char *name, - const char *parent_name); + const char *parent_name, struct clk_parent_data *parent_data); =20 struct clk_hw * __init sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock, --=20 2.43.0 From nobody Wed Oct 8 20:52:50 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8FBAA29E112; Tue, 24 Jun 2025 15:09:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777781; cv=none; b=dEYcgcUli/ULrjXYxzFBfw0I4lzsugAHBxLR0Dn4Fshik+S+89oNKP97r73c25zsnBcFquG6md189YJ8DQbLlSIyoeEb5Jpu24ygoexbk9sQWlHXsspb28k2jsqJVcAvIX7uunsizpwoKIksWKX5bmt9WL6fIwxu20ZH5+rW/+w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777781; c=relaxed/simple; bh=4m0mSB0qMTXb2csR88OxbItjA7gFCwW1bRUmBS2WlCg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=n2Evq0hkF51Q0mSF/OEELH1FgpHp5akoqdjed29BvunfwYPjXe8Wk8H93xQ3xKeS7BgxmtLEzqZ1nrZp7PwbeqVzII+DH8nbDajtQieUdDu15rGbsJBjC289gwBYiqPiEGRUF7TaICKE48TT9L5ROFy70RpWf+mdSoodeZuEgoY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=D9Un/pWk; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="D9Un/pWk" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1750777779; x=1782313779; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=4m0mSB0qMTXb2csR88OxbItjA7gFCwW1bRUmBS2WlCg=; b=D9Un/pWkr7C7H1Q6MCQ718Patp9bRxLumbprbR5IoufpvsScExiS/nwn MyEjDKlCCv2RyKhCaPEnxh4BzabRZkiFPwWecYx/URE8WpHk35chl1lQd 8d2KCax98Qbsm74YMoMCkHejbzOblheGyuVa3q7hetLzU8UbZc5JiK+Rs iqgOw1wZsj/Q/YDmVzn8+Lv45pp/li2tFN2Q3gv4dL0PRiHLBtoHPqYTz XCdU5BsThG6jimihXsT5za3uHAfCGMDoijDuF3DflOkQafjhReqQmTEYl P86BmqHFA1iKve1gBB9K9pGnVXpfmRJSaOGhhK88yzHAOZlBEDKXU8Nie g==; X-CSE-ConnectionGUID: aaR+vTR6QzCaLHJjoz8HzA== X-CSE-MsgGUID: KA0Z3Rr4SrCGEgboNrq4RA== X-IronPort-AV: E=Sophos;i="6.16,262,1744095600"; d="scan'208";a="43755112" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 24 Jun 2025 08:09:35 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Tue, 24 Jun 2025 08:08:38 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Tue, 24 Jun 2025 08:08:38 -0700 From: To: , , , , CC: , , , , Subject: [PATCH v2 15/32] clk: at91: clk-h32mx: add support for parent_hw Date: Tue, 24 Jun 2025 08:08:12 -0700 Message-ID: <5e9bfd1ee862b83410cc6579e47cb291ee6aeaf7.1750182562.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Add support for parent_hw in h32mx clock driver. With this parent-child relation is described with pointers rather than strings making registration a bit faster. All the SoC based drivers that rely on clk-h32mx were adapted to the new API change. The switch itself for SoCs will be done in subsequent patches. Signed-off-by: Claudiu Beznea [ryan.wanner@microchip.com: Remove SoC specific changes as they are going to be coalesced into one SoC specific commit.] Signed-off-by: Ryan Wanner --- drivers/clk/at91/clk-h32mx.c | 11 +++++++---- drivers/clk/at91/dt-compat.c | 2 +- drivers/clk/at91/pmc.h | 2 +- 3 files changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/clk/at91/clk-h32mx.c b/drivers/clk/at91/clk-h32mx.c index 1e6c12eeda10..4b709f9bd831 100644 --- a/drivers/clk/at91/clk-h32mx.c +++ b/drivers/clk/at91/clk-h32mx.c @@ -83,10 +83,10 @@ static const struct clk_ops h32mx_ops =3D { =20 struct clk_hw * __init at91_clk_register_h32mx(struct regmap *regmap, const char *name, - const char *parent_name) + const char *parent_name, struct clk_parent_data *parent_data) { struct clk_sama5d4_h32mx *h32mxclk; - struct clk_init_data init; + struct clk_init_data init =3D {}; int ret; =20 h32mxclk =3D kzalloc(sizeof(*h32mxclk), GFP_KERNEL); @@ -95,8 +95,11 @@ at91_clk_register_h32mx(struct regmap *regmap, const cha= r *name, =20 init.name =3D name; init.ops =3D &h32mx_ops; - init.parent_names =3D parent_name ? &parent_name : NULL; - init.num_parents =3D parent_name ? 1 : 0; + if (parent_data) + init.parent_data =3D (const struct clk_parent_data *)parent_data; + else + init.parent_names =3D &parent_name; + init.num_parents =3D 1; init.flags =3D CLK_SET_RATE_GATE; =20 h32mxclk->hw.init =3D &init; diff --git a/drivers/clk/at91/dt-compat.c b/drivers/clk/at91/dt-compat.c index 3285e3110b58..ccdeba3a1130 100644 --- a/drivers/clk/at91/dt-compat.c +++ b/drivers/clk/at91/dt-compat.c @@ -201,7 +201,7 @@ static void __init of_sama5d4_clk_h32mx_setup(struct de= vice_node *np) =20 parent_name =3D of_clk_get_parent_name(np, 0); =20 - hw =3D at91_clk_register_h32mx(regmap, name, parent_name); + hw =3D at91_clk_register_h32mx(regmap, name, parent_name, NULL); if (IS_ERR(hw)) return; =20 diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index df2deb134a8d..fe42700df6db 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -177,7 +177,7 @@ at91_clk_register_generated(struct regmap *regmap, spin= lock_t *lock, =20 struct clk_hw * __init at91_clk_register_h32mx(struct regmap *regmap, const char *name, - const char *parent_name); + const char *parent_name, struct clk_parent_data *parent_data); =20 struct clk_hw * __init at91_clk_i2s_mux_register(struct regmap *regmap, const char *name, --=20 2.43.0 From nobody Wed Oct 8 20:52:50 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B34F2FD870; Tue, 24 Jun 2025 15:09:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777759; cv=none; b=VecUv7Ye3cr5NfopD41BM/QsBcPIDOb8/mMoTRISEKYpuv9GQeTRSrvWZjItlOhYJ97DY9Lv4QHHhOG1jm1wwGE6rvenUN7P8TReQ0YM3zeC8LOAPUrTCQNKq9rchwpAXC69eHAP9LN62zZybdPEpjCdvV2G7kRdBy1w81BkX+o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777759; c=relaxed/simple; bh=p8hKSAxPTGypFQ4ukRy4fkUp3r3iUW8ues0RYFqVcIo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=cr60zO35nAfAQJC44EQBzXO0C8DwfrnD++CDYBRkL6MX124moYbzOrpZpvrHaoe5dgnDeXhiArQj4aRz54nuXbovTS9AUqOPT62P6wWp0VY3wG5GCOuI+NfFo7g43D1UXRvDkDFte+gqP3tb7RmfUChHgy9Q3Xb/F13ltL8yLCY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=vShGESwl; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="vShGESwl" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1750777757; x=1782313757; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=p8hKSAxPTGypFQ4ukRy4fkUp3r3iUW8ues0RYFqVcIo=; b=vShGESwlcbvUp9SHlGkzz2CuHb+0sX8YLRRJz10PPhXDaylOlaaLO2WV gAZTf7v+M6jFm3iKt9YgShMld0lhExDK0u/2tvd5URjkeb7YhtqpyK8m5 eP0n6K9igIj+7QYy2eAPO6Ni8amnxId3pqSurxSevhAUylDQAxU6B76Qn UKsUPY6qAo7hthGNZlFVhFQGJ8b+6wx2ZxShspemwU6qzpnup6JUSHu6S gRQJsEXSja70JM5dKwLl/XrlwdMydIgmbOzGv5s9QG8TVlYFYFCaPT1pK MH9mIPBj7KBO0Tv+bGoU4JnvGVjE4tgQJF5dP7PX6JMJP039+1fbkdxdf A==; X-CSE-ConnectionGUID: ticneE1VRpCt6c5L3blMOw== X-CSE-MsgGUID: o7aRdA0LRuObY6L1IPtmtA== X-IronPort-AV: E=Sophos;i="6.16,262,1744095600"; d="scan'208";a="210641583" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 24 Jun 2025 08:09:15 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Tue, 24 Jun 2025 08:08:38 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Tue, 24 Jun 2025 08:08:38 -0700 From: To: , , , , CC: , , , , Subject: [PATCH v2 16/32] clk: at91: clk-i2s-mux: add support for parent_hw Date: Tue, 24 Jun 2025 08:08:13 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Add support for parent_hw in i2s mux clock driver. With this parent-child relation is described with pointers rather than strings making registration a bit faster. All the SoC based drivers that rely on clk-i2s-mux were adapted to the new API change. The switch itself for SoCs will be done in subsequent patches. Signed-off-by: Claudiu Beznea [ryan.wanner@microchip.com: Remove SoC specific changes as they are going to be coalesced into one SoC specific commit.] Signed-off-by: Ryan Wanner --- drivers/clk/at91/clk-i2s-mux.c | 6 +++++- drivers/clk/at91/dt-compat.c | 2 +- drivers/clk/at91/pmc.h | 1 + 3 files changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/clk/at91/clk-i2s-mux.c b/drivers/clk/at91/clk-i2s-mux.c index fe6ce172b8b0..04d9fcf940fb 100644 --- a/drivers/clk/at91/clk-i2s-mux.c +++ b/drivers/clk/at91/clk-i2s-mux.c @@ -51,6 +51,7 @@ static const struct clk_ops clk_i2s_mux_ops =3D { struct clk_hw * __init at91_clk_i2s_mux_register(struct regmap *regmap, const char *name, const char * const *parent_names, + struct clk_parent_data *parent_data, unsigned int num_parents, u8 bus_id) { struct clk_init_data init =3D {}; @@ -63,7 +64,10 @@ at91_clk_i2s_mux_register(struct regmap *regmap, const c= har *name, =20 init.name =3D name; init.ops =3D &clk_i2s_mux_ops; - init.parent_names =3D parent_names; + if (parent_data) + init.parent_data =3D (const struct clk_parent_data *)parent_data; + else + init.parent_names =3D parent_names; init.num_parents =3D num_parents; =20 i2s_ck->hw.init =3D &init; diff --git a/drivers/clk/at91/dt-compat.c b/drivers/clk/at91/dt-compat.c index ccdeba3a1130..2b1aa834f111 100644 --- a/drivers/clk/at91/dt-compat.c +++ b/drivers/clk/at91/dt-compat.c @@ -239,7 +239,7 @@ static void __init of_sama5d2_clk_i2s_mux_setup(struct = device_node *np) continue; =20 hw =3D at91_clk_i2s_mux_register(regmap_sfr, i2s_mux_np->name, - parent_names, 2, bus_id); + parent_names, NULL, 2, bus_id); if (IS_ERR(hw)) continue; =20 diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index fe42700df6db..a380054d580d 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -182,6 +182,7 @@ at91_clk_register_h32mx(struct regmap *regmap, const ch= ar *name, struct clk_hw * __init at91_clk_i2s_mux_register(struct regmap *regmap, const char *name, const char * const *parent_names, + struct clk_parent_data *parent_data, unsigned int num_parents, u8 bus_id); =20 struct clk_hw * __init --=20 2.43.0 From nobody Wed Oct 8 20:52:50 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B2DB2FD86F; Tue, 24 Jun 2025 15:09:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777759; cv=none; b=dd4dQlOMDyNAOxP70Nagb3FpvbAZ5pdixJ4y2FPc7dIiu1kosXCNHAz6Rvd9cz4wKm3Ji1KFYGMJnN2U6Y7m82n4CmSQx/zed/EqXm3+68Pzofvhazw9tKpYTrKxb2DsZX94u3ipailbUPDsSA5uVc4Vv9QI6fOym5VnmvsLYAo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777759; c=relaxed/simple; bh=Lq3ejPHh/1kZivQehV7HtGomJvKoYkbHzTKnAbhG0IQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=LlqgnvO4fIFwz31qdvqG0nfSBLNVnTn2zpiBe4kHSPpKgm2IA1sc5dPaA2mvX+gCQ+XYSfJbGhy1shLnS457J1haCxn8sXFverQcjF5qKd6TQchnTGtT4b0FStGpJrH3Dc3LzvVF6jBQo82t0CJDa+t43N7BV+jlHj0xNwa9v2g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=x1IwGCBS; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="x1IwGCBS" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1750777757; x=1782313757; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Lq3ejPHh/1kZivQehV7HtGomJvKoYkbHzTKnAbhG0IQ=; b=x1IwGCBS2w17Tst+5GcViTji2thcmFxPY7Nny85pjAtEE3puA+S3ImdI qMAPi1BnfumsvCfq70XN9jn7cKnSsdE4sPRa+GqTjRUkcp4NcE3Zrn0ar 8htLIitWm1CO8Xi2PVKyJ1Dn7V2JTIkpjJHonMvHA+528iL7gP8ohDtp4 9UI6tqAS48p8J0M+9wCJ+BPAsvDYV/jVMEXueXkyAlWjTg/QcDEn38zt4 zFHhDQP4w5/MWr0knN1NpJjpAhHRV3ElRoTL9VuLiHvlmlfNFcmhCfcZy vAZc5Kk+Dws+dW1Dj0DqtSN2okFp8obenEK04hTtmw6GjgR0hb+s9PYmW g==; X-CSE-ConnectionGUID: ticneE1VRpCt6c5L3blMOw== X-CSE-MsgGUID: mCaPvkNXRU+OPC+zyXMjlg== X-IronPort-AV: E=Sophos;i="6.16,262,1744095600"; d="scan'208";a="210641584" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 24 Jun 2025 08:09:15 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Tue, 24 Jun 2025 08:08:38 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Tue, 24 Jun 2025 08:08:38 -0700 From: To: , , , , CC: , , , , Subject: [PATCH v2 17/32] clk: at91: clk-smd: add support for clk_parent_data Date: Tue, 24 Jun 2025 08:08:14 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Add support for parent_hw in smd clock drivers. With this parent-child relation is described with pointers rather than strings making registration a bit faster. All the SoC based drivers that rely on clk-smd were adapted to the new API change. The switch itself for SoCs will be done in subsequent patches. Signed-off-by: Claudiu Beznea [ryan.wanner@microchip.com: Remove SoC specific changes as they are going to be coalesced into one SoC specific commit.] Signed-off-by: Ryan Wanner --- drivers/clk/at91/clk-smd.c | 10 +++++++--- drivers/clk/at91/dt-compat.c | 2 +- drivers/clk/at91/pmc.h | 3 ++- 3 files changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/clk/at91/clk-smd.c b/drivers/clk/at91/clk-smd.c index 09c649c8598e..d53dc32b36be 100644 --- a/drivers/clk/at91/clk-smd.c +++ b/drivers/clk/at91/clk-smd.c @@ -111,11 +111,12 @@ static const struct clk_ops at91sam9x5_smd_ops =3D { =20 struct clk_hw * __init at91sam9x5_clk_register_smd(struct regmap *regmap, const char *name, - const char **parent_names, u8 num_parents) + const char **parent_names, struct clk_parent_data *parent_data, + u8 num_parents) { struct at91sam9x5_clk_smd *smd; struct clk_hw *hw; - struct clk_init_data init; + struct clk_init_data init =3D {}; int ret; =20 smd =3D kzalloc(sizeof(*smd), GFP_KERNEL); @@ -124,7 +125,10 @@ at91sam9x5_clk_register_smd(struct regmap *regmap, con= st char *name, =20 init.name =3D name; init.ops =3D &at91sam9x5_smd_ops; - init.parent_names =3D parent_names; + if (parent_data) + init.parent_data =3D (const struct clk_parent_data *)parent_data; + else + init.parent_names =3D parent_names; init.num_parents =3D num_parents; init.flags =3D CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE; =20 diff --git a/drivers/clk/at91/dt-compat.c b/drivers/clk/at91/dt-compat.c index 2b1aa834f111..5afd7c9f53fd 100644 --- a/drivers/clk/at91/dt-compat.c +++ b/drivers/clk/at91/dt-compat.c @@ -859,7 +859,7 @@ static void __init of_at91sam9x5_clk_smd_setup(struct d= evice_node *np) if (IS_ERR(regmap)) return; =20 - hw =3D at91sam9x5_clk_register_smd(regmap, name, parent_names, + hw =3D at91sam9x5_clk_register_smd(regmap, name, parent_names, NULL, num_parents); if (IS_ERR(hw)) return; diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index a380054d580d..e5ab2fb3bc89 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -277,7 +277,8 @@ at91_clk_register_sam9260_slow(struct regmap *regmap, =20 struct clk_hw * __init at91sam9x5_clk_register_smd(struct regmap *regmap, const char *name, - const char **parent_names, u8 num_parents); + const char **parent_names, struct clk_parent_data *parent_data, + u8 num_parents); =20 struct clk_hw * __init at91_clk_register_system(struct regmap *regmap, const char *name, --=20 2.43.0 From nobody Wed Oct 8 20:52:50 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0C8D72FE303; Tue, 24 Jun 2025 15:09:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777761; cv=none; b=sYqZg+vX4gvJaMYHpTyOLiw3dMHZpo9Zho1EL9bYC7ohRLH+tjHe1rawQclPSvGupoDMqwOlSVLmzADg9OWTTrbxVOPMuzYpuLwB2DxnaQuCq6M9e28VX9Y2hAs4ihDx3erNjfqVJ5K/GPyxV8jxsIsjqKXfQYPhX3nKexGekBM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777761; c=relaxed/simple; bh=ks//bS6BKYns21riYfrNCT4X6p254F5rw7NfuZH7dgU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=RUUkgRA8DPTSqw+bFjRCzSk3utp6PqbN/P+Ef9yuSCAKIXEJlnIP201+E58XGfhDC4WO/IENDrX+wj3SZhbEg1f4JX9BJkbf2NThehcX83mYuvqkSfkLriQxmMZF3+59fvRh+MQLmTgcjFcNtpQAjLC5rE+rk6+IHCPGLCeuvZI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=Y4QgDx8H; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="Y4QgDx8H" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1750777759; x=1782313759; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ks//bS6BKYns21riYfrNCT4X6p254F5rw7NfuZH7dgU=; b=Y4QgDx8HTPY00Pg/dh1S3xb4HR7o+bp6xf702jmyiN32QbA4S40qgGdB lxtzAK5galP23pP47dD/kIzNn+srZCGbr5tCjxT/eDK3RajVnwzQx3xlt aAggQCB3NQP0eO85Kr1YVByTxklP/G0ia6g82zafeg9G4QRb1QSoV2S/h Zvrf/Qnehqv6iY6giN1PnYa8jRJWY3FtoyiaD2/N9gJAdkIvawa6cX4y6 oRtBu6XRhCN/LDNjB1HT73gev9JhRtFEMHRIO6HnN+S6ZCwFMmQuJMQmQ A7LHZI4YxI9ji4XfrZKAkibgW3oW4nfdC84ATc9RaqfYFzoTqEbANfTJX g==; X-CSE-ConnectionGUID: ticneE1VRpCt6c5L3blMOw== X-CSE-MsgGUID: JVVgi/eEQK2Jc2N/P3uw4Q== X-IronPort-AV: E=Sophos;i="6.16,262,1744095600"; d="scan'208";a="210641586" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 24 Jun 2025 08:09:16 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Tue, 24 Jun 2025 08:08:38 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Tue, 24 Jun 2025 08:08:38 -0700 From: To: , , , , CC: , , , , Subject: [PATCH v2 18/32] clk: at91: clk-slow: add support for parent_hw Date: Tue, 24 Jun 2025 08:08:15 -0700 Message-ID: <1890a4cd63daba9288ea29c6a295e86c278cba57.1750182562.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Add support for parent_hw in slow clock drivers. With this parent-child relation is described with pointers rather than strings making registration a bit faster. All the SoC based drivers that rely on clk-slow were adapted to the new API change. The switch itself for SoCs will be done in subsequent patches. Signed-off-by: Claudiu Beznea [ryan.wanner@microchip.com: Remove SoC specific changes as they are going to be coalesced into one SoC specific commit.] Signed-off-by: Ryan Wanner --- drivers/clk/at91/clk-slow.c | 8 ++++++-- drivers/clk/at91/dt-compat.c | 2 +- drivers/clk/at91/pmc.h | 1 + 3 files changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/clk/at91/clk-slow.c b/drivers/clk/at91/clk-slow.c index ac9f7a48b76e..5b7fc6210e09 100644 --- a/drivers/clk/at91/clk-slow.c +++ b/drivers/clk/at91/clk-slow.c @@ -39,11 +39,12 @@ struct clk_hw * __init at91_clk_register_sam9260_slow(struct regmap *regmap, const char *name, const char **parent_names, + struct clk_parent_data *parent_data, int num_parents) { struct clk_sam9260_slow *slowck; struct clk_hw *hw; - struct clk_init_data init; + struct clk_init_data init =3D {}; int ret; =20 if (!name) @@ -58,7 +59,10 @@ at91_clk_register_sam9260_slow(struct regmap *regmap, =20 init.name =3D name; init.ops =3D &sam9260_slow_ops; - init.parent_names =3D parent_names; + if (parent_data) + init.parent_data =3D (const struct clk_parent_data *)&parent_data; + else + init.parent_names =3D parent_names; init.num_parents =3D num_parents; init.flags =3D 0; =20 diff --git a/drivers/clk/at91/dt-compat.c b/drivers/clk/at91/dt-compat.c index 5afd7c9f53fd..fa8658d3be7b 100644 --- a/drivers/clk/at91/dt-compat.c +++ b/drivers/clk/at91/dt-compat.c @@ -823,7 +823,7 @@ static void __init of_at91sam9260_clk_slow_setup(struct= device_node *np) =20 of_property_read_string(np, "clock-output-names", &name); =20 - hw =3D at91_clk_register_sam9260_slow(regmap, name, parent_names, + hw =3D at91_clk_register_sam9260_slow(regmap, name, parent_names, NULL, num_parents); if (IS_ERR(hw)) return; diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index e5ab2fb3bc89..24c32e42f264 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -273,6 +273,7 @@ struct clk_hw * __init at91_clk_register_sam9260_slow(struct regmap *regmap, const char *name, const char **parent_names, + struct clk_parent_data *parent_data, int num_parents); =20 struct clk_hw * __init --=20 2.43.0 From nobody Wed Oct 8 20:52:50 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4CB372FD88B; Tue, 24 Jun 2025 15:09:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777761; cv=none; b=bn+AAC88rA6elmm9a4R/aF2BMSZhk0GK4SrVZ7O1mxPwnivHgdj5pCAoqogKcBTGuPVNvnQ5+o7voVTqKDwitGFkJ7kPCViZuIzl9Re1EJi01obLy4afJzO4TIy3J6/Cc9xlWnF/TTcbW0Y2QJ0Bh4UciZsClO8OP1LyHez7EC0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777761; c=relaxed/simple; bh=ffLCRQIseVGjgdlMeKiALJlGivY7LZoOp7kTEnqo5rQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=rx8vSvPpbHpr11CB/vcACLKFLN4XnLrApV1OmacmeK5eMxhvfxN87MQuamjLSq/BMTJECD1/LstT+jdAKY+sxoCXnrCOLntNlHlzkFM8pqoE6m0pytnxHdWWUGqltNkmX72mFPpRc/zCHyfVwVq/bYZQ3yx0D8F+rS6sVZBIu10= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=KwRDETI+; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="KwRDETI+" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1750777759; x=1782313759; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ffLCRQIseVGjgdlMeKiALJlGivY7LZoOp7kTEnqo5rQ=; b=KwRDETI+IRZLVzoJm33BupXnHJdLBPF3nKur9cTQXFKr7yzGquhCm7PL hVyz7lnmbgAdpQPwD0svLjO+bPoGTY4GjjbZCmrluRy4DN50+o8Yj5mIf JMEhFW+uRNIyWHTivowadso+VpC0MXZeqx9TP5MmQzi+8vPnCT+n424qf hzaEarAfeONt61PMtzc6e51DakY4XSja+Wn2yEfVB8Xl4Hi6sbp+9+PAW JJE7+ORUq4XieZTrO/iuXUGe/rgcussF5BRG5iT0pAvLhSFeQwtB5uLBF qFWgPdPOUk05+sTRvSCSmjB2s54dHb/vCQKslp9EHr7DOgz/p9GvrWc2f A==; X-CSE-ConnectionGUID: ticneE1VRpCt6c5L3blMOw== X-CSE-MsgGUID: VyZhH3hfQKu0ih5KcCCzoA== X-IronPort-AV: E=Sophos;i="6.16,262,1744095600"; d="scan'208";a="210641587" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 24 Jun 2025 08:09:16 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Tue, 24 Jun 2025 08:08:38 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Tue, 24 Jun 2025 08:08:38 -0700 From: To: , , , , CC: , , , , Subject: [PATCH v2 19/32] clk: at91: dt-compat: switch to parent_hw and parent_data Date: Tue, 24 Jun 2025 08:08:16 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Switch old dt-compat clocks to use parent_hw and parent_data. Having parent_hw instead of parent names improves to clock registration speed and re-parenting. Signed-off-by: Claudiu Beznea Signed-off-by: Ryan Wanner --- drivers/clk/at91/dt-compat.c | 80 +++++++++++++++++++++++++----------- 1 file changed, 56 insertions(+), 24 deletions(-) diff --git a/drivers/clk/at91/dt-compat.c b/drivers/clk/at91/dt-compat.c index fa8658d3be7b..15f65a19d991 100644 --- a/drivers/clk/at91/dt-compat.c +++ b/drivers/clk/at91/dt-compat.c @@ -43,7 +43,8 @@ static void __init of_sama5d2_clk_audio_pll_frac_setup(st= ruct device_node *np) =20 parent_name =3D of_clk_get_parent_name(np, 0); =20 - hw =3D at91_clk_register_audio_pll_frac(regmap, name, parent_name, NULL); + hw =3D at91_clk_register_audio_pll_frac(regmap, name, NULL, + &AT91_CLK_PD_NAME(parent_name, 0)); if (IS_ERR(hw)) return; =20 @@ -69,7 +70,8 @@ static void __init of_sama5d2_clk_audio_pll_pad_setup(str= uct device_node *np) =20 parent_name =3D of_clk_get_parent_name(np, 0); =20 - hw =3D at91_clk_register_audio_pll_pad(regmap, name, parent_name, NULL); + hw =3D at91_clk_register_audio_pll_pad(regmap, name, NULL, + &AT91_CLK_PD_NAME(parent_name, 0)); if (IS_ERR(hw)) return; =20 @@ -95,7 +97,7 @@ static void __init of_sama5d2_clk_audio_pll_pmc_setup(str= uct device_node *np) =20 parent_name =3D of_clk_get_parent_name(np, 0); =20 - hw =3D at91_clk_register_audio_pll_pmc(regmap, name, parent_name, NULL); + hw =3D at91_clk_register_audio_pll_pmc(regmap, name, NULL, &AT91_CLK_PD_N= AME(parent_name, 0)); if (IS_ERR(hw)) return; =20 @@ -129,6 +131,7 @@ static void __init of_sama5d2_clk_generated_setup(struc= t device_node *np) struct clk_hw *hw; unsigned int num_parents; const char *parent_names[GENERATED_SOURCE_MAX]; + struct clk_parent_data parent_data[GENERATED_SOURCE_MAX]; struct device_node *gcknp, *parent_np; struct clk_range range =3D CLK_RANGE(0, 0); struct regmap *regmap; @@ -149,6 +152,8 @@ static void __init of_sama5d2_clk_generated_setup(struc= t device_node *np) if (IS_ERR(regmap)) return; =20 + for (unsigned int i =3D 0; i < num_parents; i++) + parent_data[i] =3D AT91_CLK_PD_NAME(parent_names[i], i); for_each_child_of_node(np, gcknp) { int chg_pid =3D INT_MIN; =20 @@ -171,7 +176,7 @@ static void __init of_sama5d2_clk_generated_setup(struc= t device_node *np) =20 hw =3D at91_clk_register_generated(regmap, &pmc_pcr_lock, &dt_pcr_layout, name, - parent_names, NULL, NULL, + NULL, parent_data, NULL, num_parents, id, &range, chg_pid); if (IS_ERR(hw)) @@ -201,7 +206,7 @@ static void __init of_sama5d4_clk_h32mx_setup(struct de= vice_node *np) =20 parent_name =3D of_clk_get_parent_name(np, 0); =20 - hw =3D at91_clk_register_h32mx(regmap, name, parent_name, NULL); + hw =3D at91_clk_register_h32mx(regmap, name, NULL, &AT91_CLK_PD_NAME(pare= nt_name, 0)); if (IS_ERR(hw)) return; =20 @@ -228,6 +233,8 @@ static void __init of_sama5d2_clk_i2s_mux_setup(struct = device_node *np) return; =20 for_each_child_of_node(np, i2s_mux_np) { + struct clk_parent_data parent_data[2]; + if (of_property_read_u8(i2s_mux_np, "reg", &bus_id)) continue; =20 @@ -238,8 +245,10 @@ static void __init of_sama5d2_clk_i2s_mux_setup(struct= device_node *np) if (ret !=3D 2) continue; =20 + parent_data[0] =3D AT91_CLK_PD_NAME(parent_names[0], 0); + parent_data[1] =3D AT91_CLK_PD_NAME(parent_names[1], 1); hw =3D at91_clk_i2s_mux_register(regmap_sfr, i2s_mux_np->name, - parent_names, NULL, 2, bus_id); + NULL, parent_data, 2, bus_id); if (IS_ERR(hw)) continue; =20 @@ -269,7 +278,8 @@ static void __init of_at91rm9200_clk_main_osc_setup(str= uct device_node *np) if (IS_ERR(regmap)) return; =20 - hw =3D at91_clk_register_main_osc(regmap, name, parent_name, NULL, bypass= ); + hw =3D at91_clk_register_main_osc(regmap, name, NULL, + &AT91_CLK_PD_NAME(parent_name, 0), bypass); if (IS_ERR(hw)) return; =20 @@ -323,7 +333,7 @@ static void __init of_at91rm9200_clk_main_setup(struct = device_node *np) if (IS_ERR(regmap)) return; =20 - hw =3D at91_clk_register_rm9200_main(regmap, name, parent_name, NULL); + hw =3D at91_clk_register_rm9200_main(regmap, name, NULL, &AT91_CLK_PD_NAM= E(parent_name, 0)); if (IS_ERR(hw)) return; =20 @@ -336,6 +346,7 @@ static void __init of_at91sam9x5_clk_main_setup(struct = device_node *np) { struct clk_hw *hw; const char *parent_names[2]; + struct clk_parent_data parent_data[2]; unsigned int num_parents; const char *name =3D np->name; struct regmap *regmap; @@ -354,7 +365,9 @@ static void __init of_at91sam9x5_clk_main_setup(struct = device_node *np) =20 of_property_read_string(np, "clock-output-names", &name); =20 - hw =3D at91_clk_register_sam9x5_main(regmap, name, parent_names, NULL, + parent_data[0] =3D AT91_CLK_PD_NAME(parent_names[0], 0); + parent_data[1] =3D AT91_CLK_PD_NAME(parent_names[1], 1); + hw =3D at91_clk_register_sam9x5_main(regmap, name, NULL, parent_data, num_parents); if (IS_ERR(hw)) return; @@ -396,6 +409,7 @@ of_at91_clk_master_setup(struct device_node *np, struct clk_hw *hw; unsigned int num_parents; const char *parent_names[MASTER_SOURCE_MAX]; + struct clk_parent_data parent_data[MASTER_SOURCE_MAX]; const char *name =3D np->name; struct clk_master_characteristics *characteristics; struct regmap *regmap; @@ -419,13 +433,15 @@ of_at91_clk_master_setup(struct device_node *np, if (IS_ERR(regmap)) return; =20 + for (unsigned int i =3D 0; i < MASTER_SOURCE_MAX; i++) + parent_data[i] =3D AT91_CLK_PD_NAME(parent_names[i], i); hw =3D at91_clk_register_master_pres(regmap, "masterck_pres", num_parents, - parent_names, NULL, layout, + NULL, parent_data, layout, characteristics, &mck_lock); if (IS_ERR(hw)) goto out_free_characteristics; =20 - hw =3D at91_clk_register_master_div(regmap, name, "masterck_pres", NULL, + hw =3D at91_clk_register_master_div(regmap, name, NULL, &AT91_CLK_PD_HW(h= w), layout, characteristics, &mck_lock, CLK_SET_RATE_GATE, 0); if (IS_ERR(hw)) @@ -489,8 +505,8 @@ of_at91_clk_periph_setup(struct device_node *np, u8 typ= e) name =3D periphclknp->name; =20 if (type =3D=3D PERIPHERAL_AT91RM9200) { - hw =3D at91_clk_register_peripheral(regmap, name, - parent_name, NULL, id); + hw =3D at91_clk_register_peripheral(regmap, name, NULL, + &AT91_CLK_PD_NAME(parent_name, 0), id); } else { struct clk_range range =3D CLK_RANGE(0, 0); unsigned long flags =3D 0; @@ -511,8 +527,8 @@ of_at91_clk_periph_setup(struct device_node *np, u8 typ= e) &pmc_pcr_lock, &dt_pcr_layout, name, - parent_name, NULL, + &AT91_CLK_PD_NAME(parent_name, 0), id, &range, INT_MIN, flags); @@ -665,7 +681,8 @@ of_at91_clk_pll_setup(struct device_node *np, if (!characteristics) return; =20 - hw =3D at91_clk_register_pll(regmap, name, parent_name, NULL, id, layout, + hw =3D at91_clk_register_pll(regmap, name, NULL, &AT91_CLK_PD_NAME(parent= _name, 0), + id, layout, characteristics); if (IS_ERR(hw)) goto out_free_characteristics; @@ -724,7 +741,7 @@ of_at91sam9x5_clk_plldiv_setup(struct device_node *np) if (IS_ERR(regmap)) return; =20 - hw =3D at91_clk_register_plldiv(regmap, name, parent_name, NULL); + hw =3D at91_clk_register_plldiv(regmap, name, NULL, &AT91_CLK_PD_NAME(par= ent_name, 0)); if (IS_ERR(hw)) return; =20 @@ -743,6 +760,7 @@ of_at91_clk_prog_setup(struct device_node *np, struct clk_hw *hw; unsigned int num_parents; const char *parent_names[PROG_SOURCE_MAX]; + struct clk_parent_data parent_data[PROG_SOURCE_MAX]; const char *name; struct device_node *progclknp, *parent_np; struct regmap *regmap; @@ -763,6 +781,8 @@ of_at91_clk_prog_setup(struct device_node *np, if (IS_ERR(regmap)) return; =20 + for (unsigned int i =3D 0; i < PROG_SOURCE_MAX; i++) + parent_data[i] =3D AT91_CLK_PD_NAME(parent_names[i], i); for_each_child_of_node(np, progclknp) { if (of_property_read_u32(progclknp, "reg", &id)) continue; @@ -771,7 +791,7 @@ of_at91_clk_prog_setup(struct device_node *np, name =3D progclknp->name; =20 hw =3D at91_clk_register_programmable(regmap, name, - parent_names, NULL, num_parents, + NULL, parent_data, num_parents, id, layout, mux_table); if (IS_ERR(hw)) continue; @@ -805,6 +825,7 @@ static void __init of_at91sam9260_clk_slow_setup(struct= device_node *np) { struct clk_hw *hw; const char *parent_names[2]; + struct clk_parent_data parent_data[2]; unsigned int num_parents; const char *name =3D np->name; struct regmap *regmap; @@ -823,7 +844,9 @@ static void __init of_at91sam9260_clk_slow_setup(struct= device_node *np) =20 of_property_read_string(np, "clock-output-names", &name); =20 - hw =3D at91_clk_register_sam9260_slow(regmap, name, parent_names, NULL, + parent_data[0] =3D AT91_CLK_PD_NAME(parent_names[0], 0); + parent_data[1] =3D AT91_CLK_PD_NAME(parent_names[1], 1); + hw =3D at91_clk_register_sam9260_slow(regmap, name, NULL, parent_data, num_parents); if (IS_ERR(hw)) return; @@ -841,6 +864,7 @@ static void __init of_at91sam9x5_clk_smd_setup(struct d= evice_node *np) struct clk_hw *hw; unsigned int num_parents; const char *parent_names[SMD_SOURCE_MAX]; + struct clk_parent_data parent_data[SMD_SOURCE_MAX]; const char *name =3D np->name; struct regmap *regmap; struct device_node *parent_np; @@ -859,7 +883,9 @@ static void __init of_at91sam9x5_clk_smd_setup(struct d= evice_node *np) if (IS_ERR(regmap)) return; =20 - hw =3D at91sam9x5_clk_register_smd(regmap, name, parent_names, NULL, + for (unsigned int i =3D 0; i < SMD_SOURCE_MAX; i++) + parent_data[i] =3D AT91_CLK_PD_NAME(parent_names[i], i); + hw =3D at91sam9x5_clk_register_smd(regmap, name, NULL, parent_data, num_parents); if (IS_ERR(hw)) return; @@ -909,7 +935,8 @@ static void __init of_at91rm9200_clk_sys_setup(struct d= evice_node *np) if (!strcmp(sysclknp->name, "ddrck")) flags =3D CLK_IS_CRITICAL; =20 - hw =3D at91_clk_register_system(regmap, name, parent_name, NULL, + hw =3D at91_clk_register_system(regmap, name, NULL, + &AT91_CLK_PD_NAME(parent_name, 0), id, flags); if (IS_ERR(hw)) continue; @@ -928,6 +955,7 @@ static void __init of_at91sam9x5_clk_usb_setup(struct d= evice_node *np) struct clk_hw *hw; unsigned int num_parents; const char *parent_names[USB_SOURCE_MAX]; + struct clk_parent_data parent_data[USB_SOURCE_MAX]; const char *name =3D np->name; struct regmap *regmap; struct device_node *parent_np; @@ -946,7 +974,9 @@ static void __init of_at91sam9x5_clk_usb_setup(struct d= evice_node *np) if (IS_ERR(regmap)) return; =20 - hw =3D at91sam9x5_clk_register_usb(regmap, name, parent_names, NULL, + for (unsigned int i =3D 0; i < USB_SOURCE_MAX; i++) + parent_data[i] =3D AT91_CLK_PD_NAME(parent_names[i], i); + hw =3D at91sam9x5_clk_register_usb(regmap, name, NULL, parent_data, num_parents); if (IS_ERR(hw)) return; @@ -976,7 +1006,7 @@ static void __init of_at91sam9n12_clk_usb_setup(struct= device_node *np) if (IS_ERR(regmap)) return; =20 - hw =3D at91sam9n12_clk_register_usb(regmap, name, parent_name, NULL); + hw =3D at91sam9n12_clk_register_usb(regmap, name, NULL, &AT91_CLK_PD_NAME= (parent_name, 0)); if (IS_ERR(hw)) return; =20 @@ -1009,7 +1039,8 @@ static void __init of_at91rm9200_clk_usb_setup(struct= device_node *np) of_node_put(parent_np); if (IS_ERR(regmap)) return; - hw =3D at91rm9200_clk_register_usb(regmap, name, parent_name, NULL, divis= ors); + hw =3D at91rm9200_clk_register_usb(regmap, name, NULL, &AT91_CLK_PD_NAME(= parent_name, 0), + divisors); if (IS_ERR(hw)) return; =20 @@ -1056,7 +1087,8 @@ static void __init of_at91sam9x5_clk_utmi_setup(struc= t device_node *np) regmap_sfr =3D NULL; } =20 - hw =3D at91_clk_register_utmi(regmap_pmc, regmap_sfr, name, parent_name, = NULL); + hw =3D at91_clk_register_utmi(regmap_pmc, regmap_sfr, name, NULL, + &AT91_CLK_PD_NAME(parent_name, 0)); if (IS_ERR(hw)) return; =20 --=20 2.43.0 From nobody Wed Oct 8 20:52:50 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5F2C92FD88E; Tue, 24 Jun 2025 15:09:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777761; cv=none; b=p8EPpPBI0XErGW722SoNxEO+pPupy81jV9azFZRFRsPE3cxk/J3bKCzRlE5MXA3P1ra6kJoQKq3gU4BA3sHRRO5SurP3lSNsEDfiEe/uBYVgoWPSGPvnhVPD2/rrcQbx5M6/e2UnJTVd7EDz5kTjyakwV/dCgw2QmmgYWLhYmkI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777761; c=relaxed/simple; bh=Wy1k6qwxcZ9zyVWU7NiKahrw8iO6B4PQen0dkvULY20=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=YSxRjZoj1YVs9lBeFgJfBSBgomjJ6wlz5duwRczVqmOHkhBTmOc91jsUGIEqs/pLhlD4PIO4lpyvgBvYf0eqJ4PqNn61Et4r1q51VwTtwrJoQtNdQlbTHv7p2HW1+gRo3xkZBmgZmtTdYnyq1NS+wWbcYFuqQZ66usjkI061bI0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=D5fdDzLe; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="D5fdDzLe" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1750777759; x=1782313759; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Wy1k6qwxcZ9zyVWU7NiKahrw8iO6B4PQen0dkvULY20=; b=D5fdDzLehmcd+s/ey4+DmfOe+Blcq346P/Le0Fl8DidpRxyco4rKulml DD0vz4jCjgKmxkx7tVlqLpBVjg7K0NKj/lGRgLUFefw4S38Rhb/Ce8j80 OSJ5Y390JD9AcZ1T6s6YrjvOU8VcYZGuREi2/2lPaZqz29G/szyDNt97x n8qeoC5AI0ynp2G95qFaPtHbI7CEwTAzqlpzzDaJNCo2zjK4dAkfw6Gpn 38MKPkrbZIFN3J7N9ojIjPQx1mH8x1FxTZq5P482hDzkSGBJPePHapD43 TnE1U/63UEnILCBpBWQwPPED7eXBBJRAxIszuOozKB5UiLXccsYYuy7f0 A==; X-CSE-ConnectionGUID: ticneE1VRpCt6c5L3blMOw== X-CSE-MsgGUID: t8VN0KghR3u1IUAGV/7HMg== X-IronPort-AV: E=Sophos;i="6.16,262,1744095600"; d="scan'208";a="210641588" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 24 Jun 2025 08:09:17 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Tue, 24 Jun 2025 08:08:39 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Tue, 24 Jun 2025 08:08:39 -0700 From: To: , , , , CC: , , , , Subject: [PATCH v2 20/32] clk: at91: sam9x60: switch to parent_hw and parent_data Date: Tue, 24 Jun 2025 08:08:17 -0700 Message-ID: <7b54ed71ce0cc8134c77b6f5914bf0e95ffa4d77.1750182562.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Switch SAM9X60 clocks to use modern parent_hw and parent_data. Signed-off-by: Claudiu Beznea Signed-off-by: Ryan Wanner --- drivers/clk/at91/sam9x60.c | 117 ++++++++++++++++++------------------- 1 file changed, 56 insertions(+), 61 deletions(-) diff --git a/drivers/clk/at91/sam9x60.c b/drivers/clk/at91/sam9x60.c index d959b30e1352..b2e86e600a9f 100644 --- a/drivers/clk/at91/sam9x60.c +++ b/drivers/clk/at91/sam9x60.c @@ -79,9 +79,9 @@ static const struct clk_pcr_layout sam9x60_pcr_layout =3D= { .pid_mask =3D GENMASK(6, 0), }; =20 -static const struct { +static struct { char *n; - char *p; + struct clk_hw *parent_hw; unsigned long flags; u8 id; } sam9x60_systemck[] =3D { @@ -89,11 +89,11 @@ static const struct { * ddrck feeds DDR controller and is enabled by bootloader thus we need * to keep it enabled in case there is no Linux consumer for it. */ - { .n =3D "ddrck", .p =3D "masterck_div", .id =3D 2, .flags =3D CLK_IS_CR= ITICAL }, - { .n =3D "uhpck", .p =3D "usbck", .id =3D 6 }, - { .n =3D "pck0", .p =3D "prog0", .id =3D 8 }, - { .n =3D "pck1", .p =3D "prog1", .id =3D 9 }, - { .n =3D "qspick", .p =3D "masterck_div", .id =3D 19 }, + { .n =3D "ddrck", .id =3D 2, .flags =3D CLK_IS_CRITICAL }, + { .n =3D "uhpck", .id =3D 6 }, + { .n =3D "pck0", .id =3D 8 }, + { .n =3D "pck1", .id =3D 9 }, + { .n =3D "qspick", .id =3D 19 }, }; =20 static const struct { @@ -184,32 +184,17 @@ static const struct { =20 static void __init sam9x60_pmc_setup(struct device_node *np) { + const char *td_slck_name =3D "td_slck", *md_slck_name =3D "md_slck"; + u8 td_slck_index =3D 0, md_slck_index =3D 1, main_xtal_index =3D 2; + struct clk_hw *hw, *main_rc_hw, *main_osc_hw; + const char *main_xtal_name =3D "main_xtal"; struct clk_range range =3D CLK_RANGE(0, 0); - const char *td_slck_name, *md_slck_name, *mainxtal_name; + struct clk_parent_data parent_data[6]; struct pmc_data *sam9x60_pmc; - const char *parent_names[6]; - struct clk_hw *main_osc_hw; + struct clk_hw *usbck_hw; struct regmap *regmap; - struct clk_hw *hw; int i; =20 - i =3D of_property_match_string(np, "clock-names", "td_slck"); - if (i < 0) - return; - - td_slck_name =3D of_clk_get_parent_name(np, i); - - i =3D of_property_match_string(np, "clock-names", "md_slck"); - if (i < 0) - return; - - md_slck_name =3D of_clk_get_parent_name(np, i); - - i =3D of_property_match_string(np, "clock-names", "main_xtal"); - if (i < 0) - return; - mainxtal_name =3D of_clk_get_parent_name(np, i); - regmap =3D device_node_to_regmap(np); if (IS_ERR(regmap)) return; @@ -221,26 +206,28 @@ static void __init sam9x60_pmc_setup(struct device_no= de *np) if (!sam9x60_pmc) return; =20 - hw =3D at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000, - 50000000); - if (IS_ERR(hw)) + main_rc_hw =3D at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000= 000, + 50000000); + if (IS_ERR(main_rc_hw)) goto err_free; =20 - hw =3D at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL= , 0); + main_osc_hw =3D at91_clk_register_main_osc(regmap, "main_osc", NULL, + &AT91_CLK_PD_NAME(main_xtal_name, main_xtal_index), + 0); if (IS_ERR(hw)) goto err_free; - main_osc_hw =3D hw; =20 - parent_names[0] =3D "main_rc_osc"; - parent_names[1] =3D "main_osc"; - hw =3D at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL= , 2); + parent_data[0] =3D AT91_CLK_PD_HW(main_rc_hw); + parent_data[1] =3D AT91_CLK_PD_HW(main_osc_hw); + hw =3D at91_clk_register_sam9x5_main(regmap, "mainck", NULL, parent_data,= 2); if (IS_ERR(hw)) goto err_free; =20 sam9x60_pmc->chws[PMC_MAIN] =3D hw; =20 hw =3D sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, "pllack_fracc= k", - "mainck", sam9x60_pmc->chws[PMC_MAIN], + &AT91_CLK_PD_HW(sam9x60_pmc->chws[PMC_MAIN]), + clk_hw_get_rate(sam9x60_pmc->chws[PMC_MAIN]), 0, &plla_characteristics, &pll_frac_layout, /* @@ -253,7 +240,7 @@ static void __init sam9x60_pmc_setup(struct device_node= *np) goto err_free; =20 hw =3D sam9x60_clk_register_div_pll(regmap, &pmc_pll_lock, "pllack_divck", - "pllack_fracck", NULL, 0, &plla_characteristics, + NULL, hw, 0, &plla_characteristics, &pll_div_layout, /* * This feeds CPU. It should not @@ -266,14 +253,15 @@ static void __init sam9x60_pmc_setup(struct device_no= de *np) sam9x60_pmc->chws[PMC_PLLACK] =3D hw; =20 hw =3D sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, "upllck_fracc= k", - "main_osc", main_osc_hw, 1, - &upll_characteristics, + &AT91_CLK_PD_HW(main_osc_hw), + clk_hw_get_rate(main_osc_hw), + 1, &upll_characteristics, &pll_frac_layout, CLK_SET_RATE_GATE); if (IS_ERR(hw)) goto err_free; =20 hw =3D sam9x60_clk_register_div_pll(regmap, &pmc_pll_lock, "upllck_divck", - "upllck_fracck", NULL, 1, &upll_characteristics, + NULL, hw, 1, &upll_characteristics, &pll_div_layout, CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | @@ -283,17 +271,17 @@ static void __init sam9x60_pmc_setup(struct device_no= de *np) =20 sam9x60_pmc->chws[PMC_UTMI] =3D hw; =20 - parent_names[0] =3D md_slck_name; - parent_names[1] =3D "mainck"; - parent_names[2] =3D "pllack_divck"; + parent_data[0] =3D AT91_CLK_PD_NAME(md_slck_name, md_slck_index); + parent_data[1] =3D AT91_CLK_PD_HW(sam9x60_pmc->chws[PMC_MAIN]); + parent_data[2] =3D AT91_CLK_PD_HW(sam9x60_pmc->chws[PMC_PLLACK]); hw =3D at91_clk_register_master_pres(regmap, "masterck_pres", 3, - parent_names, NULL, &sam9x60_master_layout, + NULL, parent_data, &sam9x60_master_layout, &mck_characteristics, &mck_lock); if (IS_ERR(hw)) goto err_free; =20 hw =3D at91_clk_register_master_div(regmap, "masterck_div", - "masterck_pres", NULL, &sam9x60_master_layout, + NULL, &AT91_CLK_PD_HW(hw), &sam9x60_master_layout, &mck_characteristics, &mck_lock, CLK_SET_RATE_GATE, 0); if (IS_ERR(hw)) @@ -301,26 +289,26 @@ static void __init sam9x60_pmc_setup(struct device_no= de *np) =20 sam9x60_pmc->chws[PMC_MCK] =3D hw; =20 - parent_names[0] =3D "pllack_divck"; - parent_names[1] =3D "upllck_divck"; - parent_names[2] =3D "main_osc"; - hw =3D sam9x60_clk_register_usb(regmap, "usbck", parent_names, NULL, 3); - if (IS_ERR(hw)) + parent_data[0] =3D AT91_CLK_PD_HW(sam9x60_pmc->chws[PMC_PLLACK]); + parent_data[1] =3D AT91_CLK_PD_HW(sam9x60_pmc->chws[PMC_UTMI]); + parent_data[2] =3D AT91_CLK_PD_HW(main_osc_hw); + usbck_hw =3D sam9x60_clk_register_usb(regmap, "usbck", NULL, parent_data,= 3); + if (IS_ERR(usbck_hw)) goto err_free; =20 - parent_names[0] =3D md_slck_name; - parent_names[1] =3D td_slck_name; - parent_names[2] =3D "mainck"; - parent_names[3] =3D "masterck_div"; - parent_names[4] =3D "pllack_divck"; - parent_names[5] =3D "upllck_divck"; + parent_data[0] =3D AT91_CLK_PD_NAME(md_slck_name, md_slck_index); + parent_data[1] =3D AT91_CLK_PD_NAME(td_slck_name, td_slck_index); + parent_data[2] =3D AT91_CLK_PD_HW(sam9x60_pmc->chws[PMC_MAIN]); + parent_data[3] =3D AT91_CLK_PD_HW(sam9x60_pmc->chws[PMC_MCK]); + parent_data[4] =3D AT91_CLK_PD_HW(sam9x60_pmc->chws[PMC_PLLACK]); + parent_data[5] =3D AT91_CLK_PD_HW(sam9x60_pmc->chws[PMC_UTMI]); for (i =3D 0; i < 2; i++) { char name[6]; =20 snprintf(name, sizeof(name), "prog%d", i); =20 hw =3D at91_clk_register_programmable(regmap, name, - parent_names, NULL, 6, i, + NULL, parent_data, 6, i, &sam9x60_programmable_layout, NULL); if (IS_ERR(hw)) @@ -329,9 +317,15 @@ static void __init sam9x60_pmc_setup(struct device_nod= e *np) sam9x60_pmc->pchws[i] =3D hw; } =20 + /* Set systemck parent hws. */ + sam9x60_systemck[0].parent_hw =3D sam9x60_pmc->chws[PMC_MCK]; + sam9x60_systemck[1].parent_hw =3D usbck_hw; + sam9x60_systemck[2].parent_hw =3D sam9x60_pmc->pchws[0]; + sam9x60_systemck[3].parent_hw =3D sam9x60_pmc->pchws[1]; + sam9x60_systemck[4].parent_hw =3D sam9x60_pmc->chws[PMC_MCK]; for (i =3D 0; i < ARRAY_SIZE(sam9x60_systemck); i++) { hw =3D at91_clk_register_system(regmap, sam9x60_systemck[i].n, - sam9x60_systemck[i].p, NULL, + NULL, &AT91_CLK_PD_HW(sam9x60_systemck[i].parent_hw), sam9x60_systemck[i].id, sam9x60_systemck[i].flags); if (IS_ERR(hw)) @@ -344,7 +338,8 @@ static void __init sam9x60_pmc_setup(struct device_node= *np) hw =3D at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, &sam9x60_pcr_layout, sam9x60_periphck[i].n, - "masterck_div", NULL, + NULL, + &AT91_CLK_PD_HW(sam9x60_pmc->chws[PMC_MCK]), sam9x60_periphck[i].id, &range, INT_MIN, sam9x60_periphck[i].flags); @@ -358,7 +353,7 @@ static void __init sam9x60_pmc_setup(struct device_node= *np) hw =3D at91_clk_register_generated(regmap, &pmc_pcr_lock, &sam9x60_pcr_layout, sam9x60_gck[i].n, - parent_names, NULL, NULL, 6, + NULL, parent_data, NULL, 6, sam9x60_gck[i].id, &sam9x60_gck[i].r, INT_MIN); if (IS_ERR(hw)) --=20 2.43.0 From nobody Wed Oct 8 20:52:50 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 486A62FE327; Tue, 24 Jun 2025 15:09:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777763; cv=none; b=W0vo1I4s86FCCBdWvHpNMsoZjfCaYao4Er6p6iZf+Izhkm6CgI7vgY+9btcuVJRIOUuk86lOGGaAoIM4OpGjrB8ibY4VAh6xYO9YBuNCCyXJycU4sSV68RA0Vrn8D8tZhbQgPwBCFesdsjv58p1Ut/tNLnWxfUBSzKqSx+hhM0c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777763; c=relaxed/simple; bh=p5PDzDnHI8l/OWgkEoxtwDdORlRKrZTTSGrtXa9jSuQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=NIgDGp+qT60Dw7Kd8Xi/aVMsIzJy+A/tVUVhJw677FA1PNfnKkHr78V7Uc50DWq9iWRMhsKgczIlvCKuCsHV+lN9ODIx0QuBCDKiRWT131smCaztmnduWw2wpmx7EBT4H5QhiR8aSQ2o3x0hR1X98M7EYfb7PNe9Mp1pUcEZ/Ek= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=gMs0uu4w; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="gMs0uu4w" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1750777761; x=1782313761; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=p5PDzDnHI8l/OWgkEoxtwDdORlRKrZTTSGrtXa9jSuQ=; b=gMs0uu4w7b2SzgWsmYtIE5oVeEsmmEQsvg/EypSj90P4rQ/U2et5V1vK WwRqDlxsI+P1t0pQJ7TgdVOpvVLw9CkFWl2aQc9jRQkd2CYUIJVYmzQ/Y xOQPpg5iX7p4AOWuX9UK+Uxqs/tpbfgHjWwj2ol0KTFhnR6/zc0sqzPCL QChSlhPua2x+82cn5sZWKY4+ZxaeP/SoztFK7N60hehPEjePBwHwXrDcM Wbl8zJ7d4lI3tT1brFWPCGokzaw4GKuy3js43niAj2wivpOJgr00GbQzg G5k8DBPODwaT533Hqb1vQPO51tiFt0jSa8I7r0WeVeKF/ieFlDp7dCwfv A==; X-CSE-ConnectionGUID: ticneE1VRpCt6c5L3blMOw== X-CSE-MsgGUID: s28c1akGSVyjp9ESLpoNxA== X-IronPort-AV: E=Sophos;i="6.16,262,1744095600"; d="scan'208";a="210641589" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 24 Jun 2025 08:09:17 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Tue, 24 Jun 2025 08:08:39 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Tue, 24 Jun 2025 08:08:39 -0700 From: To: , , , , CC: , , , , Subject: [PATCH v2 21/32] clk: at91: sama5d2: switch to parent_hw and parent_data Date: Tue, 24 Jun 2025 08:08:18 -0700 Message-ID: <6df068977c06a23b503bd9191a2a6cab880c9a1e.1750182562.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Switch SAMA5D2 clocks to use parent_hw and parent_data. Having parent_hw instead of parent names improves to clock registration speed and re-parenting. Extra time saved on registration is ~410us when running at 492MHz. Signed-off-by: Claudiu Beznea Signed-off-by: Ryan Wanner --- drivers/clk/at91/sama5d2.c | 168 +++++++++++++++++++------------------ 1 file changed, 86 insertions(+), 82 deletions(-) diff --git a/drivers/clk/at91/sama5d2.c b/drivers/clk/at91/sama5d2.c index 8bbc34e22cda..538ffb8deedb 100644 --- a/drivers/clk/at91/sama5d2.c +++ b/drivers/clk/at91/sama5d2.c @@ -37,9 +37,9 @@ static const struct clk_pcr_layout sama5d2_pcr_layout =3D= { .pid_mask =3D GENMASK(6, 0), }; =20 -static const struct { +static struct { char *n; - char *p; + struct clk_hw *parent_hw; unsigned long flags; u8 id; } sama5d2_systemck[] =3D { @@ -47,14 +47,14 @@ static const struct { * ddrck feeds DDR controller and is enabled by bootloader thus we need * to keep it enabled in case there is no Linux consumer for it. */ - { .n =3D "ddrck", .p =3D "masterck_div", .id =3D 2, .flags =3D CLK_IS_CRI= TICAL }, - { .n =3D "lcdck", .p =3D "masterck_div", .id =3D 3 }, - { .n =3D "uhpck", .p =3D "usbck", .id =3D 6 }, - { .n =3D "udpck", .p =3D "usbck", .id =3D 7 }, - { .n =3D "pck0", .p =3D "prog0", .id =3D 8 }, - { .n =3D "pck1", .p =3D "prog1", .id =3D 9 }, - { .n =3D "pck2", .p =3D "prog2", .id =3D 10 }, - { .n =3D "iscck", .p =3D "masterck_div", .id =3D 18 }, + { .n =3D "ddrck", .id =3D 2, .flags =3D CLK_IS_CRITICAL }, + { .n =3D "lcdck", .id =3D 3 }, + { .n =3D "uhpck", .id =3D 6 }, + { .n =3D "udpck", .id =3D 7 }, + { .n =3D "pck0", .id =3D 8 }, + { .n =3D "pck1", .id =3D 9 }, + { .n =3D "pck2", .id =3D 10 }, + { .n =3D "iscck", .id =3D 18 }, }; =20 static const struct { @@ -164,25 +164,15 @@ static const struct clk_programmable_layout sama5d2_p= rogrammable_layout =3D { =20 static void __init sama5d2_pmc_setup(struct device_node *np) { + struct clk_hw *hw, *audio_fracck_hw, *usbck_hw, *main_rc_hw, *main_osc_hw; + const char *slow_clk_name =3D "slowck", *main_xtal_name =3D "main_xtal"; + u8 slow_clk_index =3D 0, main_xtal_index =3D 1; struct clk_range range =3D CLK_RANGE(0, 0); - const char *slck_name, *mainxtal_name; - struct pmc_data *sama5d2_pmc; - const char *parent_names[6]; + struct clk_parent_data parent_data[6]; struct regmap *regmap, *regmap_sfr; - struct clk_hw *hw; - int i; + struct pmc_data *sama5d2_pmc; bool bypass; - - i =3D of_property_match_string(np, "clock-names", "slow_clk"); - if (i < 0) - return; - - slck_name =3D of_clk_get_parent_name(np, i); - - i =3D of_property_match_string(np, "clock-names", "main_xtal"); - if (i < 0) - return; - mainxtal_name =3D of_clk_get_parent_name(np, i); + int i; =20 regmap =3D device_node_to_regmap(np); if (IS_ERR(regmap)) @@ -195,51 +185,52 @@ static void __init sama5d2_pmc_setup(struct device_no= de *np) if (!sama5d2_pmc) return; =20 - hw =3D at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000, - 100000000); - if (IS_ERR(hw)) + main_rc_hw =3D at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000= 000, + 100000000); + if (IS_ERR(main_rc_hw)) goto err_free; =20 bypass =3D of_property_read_bool(np, "atmel,osc-bypass"); =20 - hw =3D at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL, - bypass); - if (IS_ERR(hw)) + main_osc_hw =3D at91_clk_register_main_osc(regmap, "main_osc", NULL, + &AT91_CLK_PD_NAME(main_xtal_name, main_xtal_index), + bypass); + if (IS_ERR(main_osc_hw)) goto err_free; =20 - parent_names[0] =3D "main_rc_osc"; - parent_names[1] =3D "main_osc"; - hw =3D at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL= , 2); + parent_data[0] =3D AT91_CLK_PD_HW(main_rc_hw); + parent_data[1] =3D AT91_CLK_PD_HW(main_osc_hw); + hw =3D at91_clk_register_sam9x5_main(regmap, "mainck", NULL, parent_data,= 2); if (IS_ERR(hw)) goto err_free; =20 sama5d2_pmc->chws[PMC_MAIN] =3D hw; - - hw =3D at91_clk_register_pll(regmap, "pllack", "mainck", 0, + hw =3D at91_clk_register_pll(regmap, "pllack", NULL, + &AT91_CLK_PD_HW(sama5d2_pmc->chws[PMC_MAIN]), 0, &sama5d3_pll_layout, &plla_characteristics); if (IS_ERR(hw)) goto err_free; =20 - hw =3D at91_clk_register_plldiv(regmap, "plladivck", "pllack"); + hw =3D at91_clk_register_plldiv(regmap, "plladivck", NULL, &AT91_CLK_PD_H= W(hw)); if (IS_ERR(hw)) goto err_free; =20 sama5d2_pmc->chws[PMC_PLLACK] =3D hw; =20 - hw =3D at91_clk_register_audio_pll_frac(regmap, "audiopll_fracck", - "mainck"); - if (IS_ERR(hw)) + audio_fracck_hw =3D at91_clk_register_audio_pll_frac(regmap, "audiopll_fr= acck", NULL, + &AT91_CLK_PD_HW(sama5d2_pmc->chws[PMC_MAIN])); + if (IS_ERR(audio_fracck_hw)) goto err_free; =20 - hw =3D at91_clk_register_audio_pll_pad(regmap, "audiopll_padck", - "audiopll_fracck"); + hw =3D at91_clk_register_audio_pll_pad(regmap, "audiopll_padck", NULL, + &AT91_CLK_PD_HW(audio_fracck_hw)); if (IS_ERR(hw)) goto err_free; =20 sama5d2_pmc->chws[PMC_AUDIOPINCK] =3D hw; =20 - hw =3D at91_clk_register_audio_pll_pmc(regmap, "audiopll_pmcck", - "audiopll_fracck"); + hw =3D at91_clk_register_audio_pll_pmc(regmap, "audiopll_pmcck", NULL, + &AT91_CLK_PD_HW(audio_fracck_hw)); if (IS_ERR(hw)) goto err_free; =20 @@ -249,25 +240,26 @@ static void __init sama5d2_pmc_setup(struct device_no= de *np) if (IS_ERR(regmap_sfr)) regmap_sfr =3D NULL; =20 - hw =3D at91_clk_register_utmi(regmap, regmap_sfr, "utmick", "mainck", NUL= L); + hw =3D at91_clk_register_utmi(regmap, regmap_sfr, "utmick", NULL, + &AT91_CLK_PD_HW(sama5d2_pmc->chws[PMC_MAIN])); if (IS_ERR(hw)) goto err_free; =20 sama5d2_pmc->chws[PMC_UTMI] =3D hw; =20 - parent_names[0] =3D slck_name; - parent_names[1] =3D "mainck"; - parent_names[2] =3D "plladivck"; - parent_names[3] =3D "utmick"; + parent_data[0] =3D AT91_CLK_PD_NAME(slow_clk_name, slow_clk_index); + parent_data[1] =3D AT91_CLK_PD_HW(sama5d2_pmc->chws[PMC_MAIN]); + parent_data[2] =3D AT91_CLK_PD_HW(sama5d2_pmc->chws[PMC_PLLACK]); + parent_data[3] =3D AT91_CLK_PD_HW(sama5d2_pmc->chws[PMC_UTMI]); hw =3D at91_clk_register_master_pres(regmap, "masterck_pres", 4, - parent_names, NULL, + NULL, parent_data, &at91sam9x5_master_layout, &mck_characteristics, &mck_lock); if (IS_ERR(hw)) goto err_free; =20 - hw =3D at91_clk_register_master_div(regmap, "masterck_div", - "masterck_pres", NULL, + hw =3D at91_clk_register_master_div(regmap, "masterck_div", NULL, + &AT91_CLK_PD_HW(hw), &at91sam9x5_master_layout, &mck_characteristics, &mck_lock, CLK_SET_RATE_GATE, 0); @@ -276,31 +268,32 @@ static void __init sama5d2_pmc_setup(struct device_no= de *np) =20 sama5d2_pmc->chws[PMC_MCK] =3D hw; =20 - hw =3D at91_clk_register_h32mx(regmap, "h32mxck", "masterck_div"); + hw =3D at91_clk_register_h32mx(regmap, "h32mxck", NULL, + &AT91_CLK_PD_HW(sama5d2_pmc->chws[PMC_MCK])); if (IS_ERR(hw)) goto err_free; =20 sama5d2_pmc->chws[PMC_MCK2] =3D hw; =20 - parent_names[0] =3D "plladivck"; - parent_names[1] =3D "utmick"; - hw =3D at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, NULL, 2= ); - if (IS_ERR(hw)) + parent_data[0] =3D AT91_CLK_PD_HW(sama5d2_pmc->chws[PMC_PLLACK]); + parent_data[1] =3D AT91_CLK_PD_HW(sama5d2_pmc->chws[PMC_UTMI]); + usbck_hw =3D at91sam9x5_clk_register_usb(regmap, "usbck", NULL, parent_da= ta, 2); + if (IS_ERR(usbck_hw)) goto err_free; =20 - parent_names[0] =3D slck_name; - parent_names[1] =3D "mainck"; - parent_names[2] =3D "plladivck"; - parent_names[3] =3D "utmick"; - parent_names[4] =3D "masterck_div"; - parent_names[5] =3D "audiopll_pmcck"; + parent_data[0] =3D AT91_CLK_PD_NAME(slow_clk_name, slow_clk_index); + parent_data[1] =3D AT91_CLK_PD_HW(sama5d2_pmc->chws[PMC_MAIN]); + parent_data[2] =3D AT91_CLK_PD_HW(sama5d2_pmc->chws[PMC_PLLACK]); + parent_data[3] =3D AT91_CLK_PD_HW(sama5d2_pmc->chws[PMC_UTMI]); + parent_data[4] =3D AT91_CLK_PD_HW(sama5d2_pmc->chws[PMC_MCK]); + parent_data[5] =3D AT91_CLK_PD_HW(sama5d2_pmc->chws[PMC_AUDIOPLLCK]); for (i =3D 0; i < 3; i++) { char name[6]; =20 snprintf(name, sizeof(name), "prog%d", i); =20 hw =3D at91_clk_register_programmable(regmap, name, - parent_names, NULL, 6, i, + NULL, parent_data, 6, i, &sama5d2_programmable_layout, NULL); if (IS_ERR(hw)) @@ -309,9 +302,18 @@ static void __init sama5d2_pmc_setup(struct device_nod= e *np) sama5d2_pmc->pchws[i] =3D hw; } =20 + /* Set systemck parent hws. */ + sama5d2_systemck[0].parent_hw =3D sama5d2_pmc->chws[PMC_MCK]; + sama5d2_systemck[1].parent_hw =3D sama5d2_pmc->chws[PMC_MCK]; + sama5d2_systemck[2].parent_hw =3D usbck_hw; + sama5d2_systemck[3].parent_hw =3D usbck_hw; + sama5d2_systemck[4].parent_hw =3D sama5d2_pmc->pchws[0]; + sama5d2_systemck[5].parent_hw =3D sama5d2_pmc->pchws[1]; + sama5d2_systemck[6].parent_hw =3D sama5d2_pmc->pchws[2]; + sama5d2_systemck[7].parent_hw =3D sama5d2_pmc->chws[PMC_MCK]; for (i =3D 0; i < ARRAY_SIZE(sama5d2_systemck); i++) { - hw =3D at91_clk_register_system(regmap, sama5d2_systemck[i].n, - sama5d2_systemck[i].p, NULL, + hw =3D at91_clk_register_system(regmap, sama5d2_systemck[i].n, NULL, + &AT91_CLK_PD_HW(sama5d2_systemck[i].parent_hw), sama5d2_systemck[i].id, sama5d2_systemck[i].flags); if (IS_ERR(hw)) @@ -324,7 +326,8 @@ static void __init sama5d2_pmc_setup(struct device_node= *np) hw =3D at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, &sama5d2_pcr_layout, sama5d2_periphck[i].n, - "masterck_div", NULL, + NULL, + &AT91_CLK_PD_HW(sama5d2_pmc->chws[PMC_MCK]), sama5d2_periphck[i].id, &range, INT_MIN, sama5d2_periphck[i].flags); @@ -338,7 +341,8 @@ static void __init sama5d2_pmc_setup(struct device_node= *np) hw =3D at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, &sama5d2_pcr_layout, sama5d2_periph32ck[i].n, - "h32mxck", NULL, + NULL, + &AT91_CLK_PD_HW(sama5d2_pmc->chws[PMC_MCK2]), sama5d2_periph32ck[i].id, &sama5d2_periph32ck[i].r, INT_MIN, 0); @@ -348,17 +352,17 @@ static void __init sama5d2_pmc_setup(struct device_no= de *np) sama5d2_pmc->phws[sama5d2_periph32ck[i].id] =3D hw; } =20 - parent_names[0] =3D slck_name; - parent_names[1] =3D "mainck"; - parent_names[2] =3D "plladivck"; - parent_names[3] =3D "utmick"; - parent_names[4] =3D "masterck_div"; - parent_names[5] =3D "audiopll_pmcck"; + parent_data[0] =3D AT91_CLK_PD_NAME(slow_clk_name, slow_clk_index); + parent_data[1] =3D AT91_CLK_PD_HW(sama5d2_pmc->chws[PMC_MAIN]); + parent_data[2] =3D AT91_CLK_PD_HW(sama5d2_pmc->chws[PMC_PLLACK]); + parent_data[3] =3D AT91_CLK_PD_HW(sama5d2_pmc->chws[PMC_UTMI]); + parent_data[4] =3D AT91_CLK_PD_HW(sama5d2_pmc->chws[PMC_MCK]); + parent_data[5] =3D AT91_CLK_PD_HW(sama5d2_pmc->chws[PMC_AUDIOPLLCK]); for (i =3D 0; i < ARRAY_SIZE(sama5d2_gck); i++) { hw =3D at91_clk_register_generated(regmap, &pmc_pcr_lock, &sama5d2_pcr_layout, sama5d2_gck[i].n, - parent_names, NULL, NULL, 6, + NULL, parent_data, NULL, 6, sama5d2_gck[i].id, &sama5d2_gck[i].r, sama5d2_gck[i].chg_pid); @@ -369,19 +373,19 @@ static void __init sama5d2_pmc_setup(struct device_no= de *np) } =20 if (regmap_sfr) { - parent_names[0] =3D "i2s0_clk"; - parent_names[1] =3D "i2s0_gclk"; + parent_data[0] =3D AT91_CLK_PD_HW(sama5d2_pmc->phws[54]); /* i2s0_clk */ + parent_data[1] =3D AT91_CLK_PD_HW(sama5d2_pmc->ghws[54]); /* i2s0_gclk */ hw =3D at91_clk_i2s_mux_register(regmap_sfr, "i2s0_muxclk", - parent_names, 2, 0); + NULL, parent_data, 2, 0); if (IS_ERR(hw)) goto err_free; =20 sama5d2_pmc->chws[PMC_I2S0_MUX] =3D hw; =20 - parent_names[0] =3D "i2s1_clk"; - parent_names[1] =3D "i2s1_gclk"; + parent_data[0] =3D AT91_CLK_PD_HW(sama5d2_pmc->phws[55]); /* i2s1_clk */ + parent_data[1] =3D AT91_CLK_PD_HW(sama5d2_pmc->ghws[55]); /* i2s1_gclk */ hw =3D at91_clk_i2s_mux_register(regmap_sfr, "i2s1_muxclk", - parent_names, 2, 1); + NULL, parent_data, 2, 1); if (IS_ERR(hw)) goto err_free; =20 --=20 2.43.0 From nobody Wed Oct 8 20:52:50 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 531352FE329; Tue, 24 Jun 2025 15:09:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777763; cv=none; b=j5i2PoQrEaSNSdbLtJr3nS8VR1hQ535IE5Ras1tKMuwXTTgjJi3BsyuIXNYCihAu80FpiBpaHz2Nx0B6yffRSeEGOS4jKrTmfHkmHx5LzHunGfWJ1ltLJd6nb7f+hf9NH1QtedAs3GnqnoGhfz1ahKvpOOGk7egcoD4dgz+//cU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777763; c=relaxed/simple; bh=lUpSHD2GbsWj6zca7ADZCsZWLGRRnF4z4bxVfcHjtYw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=htaa26HHGkn+CQU4p9Jt9FJi5AOUZXNTlmdcTFhdiBxV+MiQ4h2OcAVQwheuyKYAOd6cw0DNyH3WqB9YYn/OxlQIv2v58o0z8GBSHzKUnneL+zMMMP3ZyFmA64xDKX5QAuQg2jMnPqIrRSLf5w0UTxOv56cQWaTD1VhJpv01Lv0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=iurkYYQ9; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="iurkYYQ9" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1750777761; x=1782313761; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lUpSHD2GbsWj6zca7ADZCsZWLGRRnF4z4bxVfcHjtYw=; b=iurkYYQ9GE+Uin2iqzLdDSU6ukUYz3S8aWm4cXzfnZxGvTTkAHyMte+r zIKeX77svP5zuexEuEV4XyUBivxp6XNrQ+vloKwYvrl3W7RQv/T2YiAfV CSAKQGGI2ObJVHhsGMwoHoLQMYZTAkryq8kXwKBJsmYM+U+ST4sJ5rCVr 1vXs2UMKtyRdsRGznitE4eB6hTljOvG6afjPWUN86dMZSvYRmBjxZn2/b BZK3W87935WLFjurkKdAlPpg7t3aYk4mxekEccy9GZZ/RLneycqkwXXtD Y1ve5HedCgkIqzQ9evAGLSKkzQTioMIkaXfDQkCBqui+fMVOU+zOA9jnE w==; X-CSE-ConnectionGUID: ticneE1VRpCt6c5L3blMOw== X-CSE-MsgGUID: fS7TocqsRfKXfgMMDqHqOw== X-IronPort-AV: E=Sophos;i="6.16,262,1744095600"; d="scan'208";a="210641590" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 24 Jun 2025 08:09:18 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Tue, 24 Jun 2025 08:08:39 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Tue, 24 Jun 2025 08:08:39 -0700 From: To: , , , , CC: , , , , Subject: [PATCH v2 22/32] clk: at91: sama5d3: switch to parent_hw and parent_data Date: Tue, 24 Jun 2025 08:08:19 -0700 Message-ID: <61c9978f367ee3dbc3fb45bc5502ca5729f735d0.1750182562.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Switch SAMA5D3 clocks to use parent_hw and parent_data. Having parent_hw instead of parent names improves to clock registration speed and re-parenting. Signed-off-by: Claudiu Beznea Signed-off-by: Ryan Wanner --- drivers/clk/at91/sama5d3.c | 122 +++++++++++++++++++------------------ 1 file changed, 63 insertions(+), 59 deletions(-) diff --git a/drivers/clk/at91/sama5d3.c b/drivers/clk/at91/sama5d3.c index 05d0cdd22bc4..e5b061783b09 100644 --- a/drivers/clk/at91/sama5d3.c +++ b/drivers/clk/at91/sama5d3.c @@ -37,9 +37,9 @@ static const struct clk_pcr_layout sama5d3_pcr_layout =3D= { .div_mask =3D GENMASK(17, 16), }; =20 -static const struct { +static struct { char *n; - char *p; + struct clk_hw *parent_hw; unsigned long flags; u8 id; } sama5d3_systemck[] =3D { @@ -47,14 +47,14 @@ static const struct { * ddrck feeds DDR controller and is enabled by bootloader thus we need * to keep it enabled in case there is no Linux consumer for it. */ - { .n =3D "ddrck", .p =3D "masterck_div", .id =3D 2, .flags =3D CLK_IS_CRI= TICAL }, - { .n =3D "lcdck", .p =3D "masterck_div", .id =3D 3 }, - { .n =3D "smdck", .p =3D "smdclk", .id =3D 4 }, - { .n =3D "uhpck", .p =3D "usbck", .id =3D 6 }, - { .n =3D "udpck", .p =3D "usbck", .id =3D 7 }, - { .n =3D "pck0", .p =3D "prog0", .id =3D 8 }, - { .n =3D "pck1", .p =3D "prog1", .id =3D 9 }, - { .n =3D "pck2", .p =3D "prog2", .id =3D 10 }, + { .n =3D "ddrck", .id =3D 2, .flags =3D CLK_IS_CRITICAL }, + { .n =3D "lcdck", .id =3D 3 }, + { .n =3D "smdck", .id =3D 4 }, + { .n =3D "uhpck", .id =3D 6 }, + { .n =3D "udpck", .id =3D 7 }, + { .n =3D "pck0", .id =3D 8 }, + { .n =3D "pck1", .id =3D 9 }, + { .n =3D "pck2", .id =3D 10 }, }; =20 static const struct { @@ -114,24 +114,15 @@ static const struct { =20 static void __init sama5d3_pmc_setup(struct device_node *np) { - const char *slck_name, *mainxtal_name; + const char *slow_clk_name =3D "slowck", *main_xtal_name =3D "main_xtal"; + struct clk_hw *main_rc_hw, *main_osc_hw, *mainck_hw; + u8 slow_clk_index =3D 0, main_xtal_index =3D 1; + struct clk_hw *smdck_hw, *usbck_hw, *hw; + struct clk_parent_data parent_data[5]; struct pmc_data *sama5d3_pmc; - const char *parent_names[5]; struct regmap *regmap; - struct clk_hw *hw; - int i; bool bypass; - - i =3D of_property_match_string(np, "clock-names", "slow_clk"); - if (i < 0) - return; - - slck_name =3D of_clk_get_parent_name(np, i); - - i =3D of_property_match_string(np, "clock-names", "main_xtal"); - if (i < 0) - return; - mainxtal_name =3D of_clk_get_parent_name(np, i); + int i; =20 regmap =3D device_node_to_regmap(np); if (IS_ERR(regmap)) @@ -143,54 +134,55 @@ static void __init sama5d3_pmc_setup(struct device_no= de *np) if (!sama5d3_pmc) return; =20 - hw =3D at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000, - 50000000); - if (IS_ERR(hw)) + main_rc_hw =3D at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000= 000, + 50000000); + if (IS_ERR(main_rc_hw)) goto err_free; =20 bypass =3D of_property_read_bool(np, "atmel,osc-bypass"); =20 - hw =3D at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL, - bypass); - if (IS_ERR(hw)) + main_osc_hw =3D at91_clk_register_main_osc(regmap, "main_osc", NULL, + &AT91_CLK_PD_NAME(main_xtal_name, main_xtal_index), + bypass); + if (IS_ERR(main_osc_hw)) goto err_free; =20 - parent_names[0] =3D "main_rc_osc"; - parent_names[1] =3D "main_osc"; - hw =3D at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL= , 2); - if (IS_ERR(hw)) + parent_data[0] =3D AT91_CLK_PD_HW(main_rc_hw); + parent_data[1] =3D AT91_CLK_PD_HW(main_osc_hw); + mainck_hw =3D at91_clk_register_sam9x5_main(regmap, "mainck", NULL, paren= t_data, 2); + if (IS_ERR(mainck_hw)) goto err_free; =20 - hw =3D at91_clk_register_pll(regmap, "pllack", "mainck", 0, + hw =3D at91_clk_register_pll(regmap, "pllack", NULL, &AT91_CLK_PD_HW(main= ck_hw), 0, &sama5d3_pll_layout, &plla_characteristics); if (IS_ERR(hw)) goto err_free; =20 - hw =3D at91_clk_register_plldiv(regmap, "plladivck", "pllack"); + hw =3D at91_clk_register_plldiv(regmap, "plladivck", NULL, &AT91_CLK_PD_H= W(hw)); if (IS_ERR(hw)) goto err_free; =20 sama5d3_pmc->chws[PMC_PLLACK] =3D hw; =20 - hw =3D at91_clk_register_utmi(regmap, NULL, "utmick", "mainck", NULL); + hw =3D at91_clk_register_utmi(regmap, NULL, "utmick", NULL, &AT91_CLK_PD_= HW(mainck_hw)); if (IS_ERR(hw)) goto err_free; =20 sama5d3_pmc->chws[PMC_UTMI] =3D hw; =20 - parent_names[0] =3D slck_name; - parent_names[1] =3D "mainck"; - parent_names[2] =3D "plladivck"; - parent_names[3] =3D "utmick"; + parent_data[0] =3D AT91_CLK_PD_NAME(slow_clk_name, slow_clk_index); + parent_data[1] =3D AT91_CLK_PD_HW(mainck_hw); + parent_data[2] =3D AT91_CLK_PD_HW(sama5d3_pmc->chws[PMC_PLLACK]); + parent_data[3] =3D AT91_CLK_PD_HW(sama5d3_pmc->chws[PMC_UTMI]); hw =3D at91_clk_register_master_pres(regmap, "masterck_pres", 4, - parent_names, NULL, + NULL, parent_data, &at91sam9x5_master_layout, &mck_characteristics, &mck_lock); if (IS_ERR(hw)) goto err_free; =20 hw =3D at91_clk_register_master_div(regmap, "masterck_div", - "masterck_pres", NULL, + NULL, &AT91_CLK_PD_HW(hw), &at91sam9x5_master_layout, &mck_characteristics, &mck_lock, CLK_SET_RATE_GATE, 0); @@ -199,28 +191,30 @@ static void __init sama5d3_pmc_setup(struct device_no= de *np) =20 sama5d3_pmc->chws[PMC_MCK] =3D hw; =20 - parent_names[0] =3D "plladivck"; - parent_names[1] =3D "utmick"; - hw =3D at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, NULL, 2= ); - if (IS_ERR(hw)) + parent_data[0] =3D AT91_CLK_PD_HW(sama5d3_pmc->chws[PMC_PLLACK]); + parent_data[1] =3D AT91_CLK_PD_HW(sama5d3_pmc->chws[PMC_UTMI]); + usbck_hw =3D at91sam9x5_clk_register_usb(regmap, "usbck", NULL, parent_da= ta, 2); + if (IS_ERR(usbck_hw)) goto err_free; =20 - hw =3D at91sam9x5_clk_register_smd(regmap, "smdclk", parent_names, 2); - if (IS_ERR(hw)) + parent_data[0] =3D AT91_CLK_PD_HW(sama5d3_pmc->chws[PMC_PLLACK]); + parent_data[1] =3D AT91_CLK_PD_HW(sama5d3_pmc->chws[PMC_UTMI]); + smdck_hw =3D at91sam9x5_clk_register_smd(regmap, "smdclk", NULL, parent_d= ata, 2); + if (IS_ERR(smdck_hw)) goto err_free; =20 - parent_names[0] =3D slck_name; - parent_names[1] =3D "mainck"; - parent_names[2] =3D "plladivck"; - parent_names[3] =3D "utmick"; - parent_names[4] =3D "masterck_div"; + parent_data[0] =3D AT91_CLK_PD_NAME(slow_clk_name, slow_clk_index); + parent_data[1] =3D AT91_CLK_PD_HW(mainck_hw); + parent_data[2] =3D AT91_CLK_PD_HW(sama5d3_pmc->chws[PMC_PLLACK]); + parent_data[3] =3D AT91_CLK_PD_HW(sama5d3_pmc->chws[PMC_UTMI]); + parent_data[4] =3D AT91_CLK_PD_HW(sama5d3_pmc->chws[PMC_MCK]); for (i =3D 0; i < 3; i++) { char name[6]; =20 snprintf(name, sizeof(name), "prog%d", i); =20 hw =3D at91_clk_register_programmable(regmap, name, - parent_names, NULL, 5, i, + NULL, parent_data, 5, i, &at91sam9x5_programmable_layout, NULL); if (IS_ERR(hw)) @@ -229,9 +223,18 @@ static void __init sama5d3_pmc_setup(struct device_nod= e *np) sama5d3_pmc->pchws[i] =3D hw; } =20 + /* Set systemck parent hws. */ + sama5d3_systemck[0].parent_hw =3D sama5d3_pmc->chws[PMC_MCK]; + sama5d3_systemck[1].parent_hw =3D sama5d3_pmc->chws[PMC_MCK]; + sama5d3_systemck[2].parent_hw =3D smdck_hw; + sama5d3_systemck[3].parent_hw =3D usbck_hw; + sama5d3_systemck[4].parent_hw =3D usbck_hw; + sama5d3_systemck[5].parent_hw =3D sama5d3_pmc->pchws[0]; + sama5d3_systemck[6].parent_hw =3D sama5d3_pmc->pchws[1]; + sama5d3_systemck[7].parent_hw =3D sama5d3_pmc->pchws[2]; for (i =3D 0; i < ARRAY_SIZE(sama5d3_systemck); i++) { - hw =3D at91_clk_register_system(regmap, sama5d3_systemck[i].n, - sama5d3_systemck[i].p, NULL, + hw =3D at91_clk_register_system(regmap, sama5d3_systemck[i].n, NULL, + &AT91_CLK_PD_HW(sama5d3_systemck[i].parent_hw), sama5d3_systemck[i].id, sama5d3_systemck[i].flags); if (IS_ERR(hw)) @@ -244,7 +247,8 @@ static void __init sama5d3_pmc_setup(struct device_node= *np) hw =3D at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, &sama5d3_pcr_layout, sama5d3_periphck[i].n, - "masterck_div", NULL, + NULL, + &AT91_CLK_PD_HW(sama5d3_pmc->chws[PMC_MCK]), sama5d3_periphck[i].id, &sama5d3_periphck[i].r, INT_MIN, --=20 2.43.0 From nobody Wed Oct 8 20:52:50 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E8A072FE366; Tue, 24 Jun 2025 15:09:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777764; cv=none; b=jZTiMN0QIlaZT9mfJmpAgt2idIFsI37eYAShEyEfNpOiAMULdtQ8rHl1g1XyyPndI4OUbD5YNTEzqqW65HTYLMKARqkoM6VhQ32hvluYiMraRfMprRmwJx76vT5jHiNEQA9i8UdjSDYLb8olYx+o6CDGzWk/8lv8zOkfZFsuXb8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777764; c=relaxed/simple; bh=Ty7uuZcN3BxqJt4GUDgXg/U7IQq4FA8cfbErKuXtt34=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=DNXrMtFZe96J7AQ4s87bBjJSRpXTngHflZpnkVpBnqYR4NtHz1BXVP0f5TnP+nkAEudEQipMTyPqG4yrx3axu4mC8fshkmc0bgQLceIWv2yeQ4V8Nz3KXyH1aI3CNtR6mz8sAqAD7D+3u4fRuV8Jvfy5w5K7uTa4Y0B9dQ77khs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=X5HDg7UJ; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="X5HDg7UJ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1750777761; x=1782313761; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Ty7uuZcN3BxqJt4GUDgXg/U7IQq4FA8cfbErKuXtt34=; b=X5HDg7UJqPE0bC8mSXWu8IGo1Gpd/u8qQEIPz/iWgRRQCAh+0TuTtaJv tq+BGI2jfZGbZacN9Qp/1KKk8lq+CQ74Ffk2LFQEGHSBp5a2n4a8k6dr+ OhA2jOMNMUtfKO3TdQrWbOXmfLUPKBtHB84OymxtKHso0zi3Y20cuvj96 uPv+DDbscEdTP0jeA0PIBJDti2Bx6p1s74hz1uDCoXksgClZqiK/XFoH3 ypxC4UM1Y9hv4o5cxTvJTw0ZiQMwD/xCITisnqJqTMK0UnMaHGekC9SGL VA/PD/RpXxZBumAY8irE1DkJ4oGsiKDY/AeqpYOU1iahTXUPoGiEPYf+7 Q==; X-CSE-ConnectionGUID: ticneE1VRpCt6c5L3blMOw== X-CSE-MsgGUID: ESz7as65QLSvYK7EFsO9Lg== X-IronPort-AV: E=Sophos;i="6.16,262,1744095600"; d="scan'208";a="210641592" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 24 Jun 2025 08:09:18 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Tue, 24 Jun 2025 08:08:39 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Tue, 24 Jun 2025 08:08:39 -0700 From: To: , , , , CC: , , , , Subject: [PATCH v2 23/32] clk: at91: sama5d4: switch to parent_hw and parent_data Date: Tue, 24 Jun 2025 08:08:20 -0700 Message-ID: <651e598cf41d017832a69e15358a0027733d9944.1750182562.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Switch SAMA5D4 clocks to use parent_hw and parent_data. Having parent_hw instead of parent names improves to clock registration speed and re-parenting. Signed-off-by: Claudiu Beznea Signed-off-by: Ryan Wanner --- drivers/clk/at91/sama5d4.c | 129 +++++++++++++++++++------------------ 1 file changed, 66 insertions(+), 63 deletions(-) diff --git a/drivers/clk/at91/sama5d4.c b/drivers/clk/at91/sama5d4.c index da84b4cef827..a06fea1a7a02 100644 --- a/drivers/clk/at91/sama5d4.c +++ b/drivers/clk/at91/sama5d4.c @@ -36,9 +36,9 @@ static const struct clk_pcr_layout sama5d4_pcr_layout =3D= { .pid_mask =3D GENMASK(6, 0), }; =20 -static const struct { +static struct { char *n; - char *p; + struct clk_hw *parent_hw; unsigned long flags; u8 id; } sama5d4_systemck[] =3D { @@ -46,14 +46,14 @@ static const struct { * ddrck feeds DDR controller and is enabled by bootloader thus we need * to keep it enabled in case there is no Linux consumer for it. */ - { .n =3D "ddrck", .p =3D "masterck_div", .id =3D 2, .flags =3D CLK_IS_CRI= TICAL }, - { .n =3D "lcdck", .p =3D "masterck_div", .id =3D 3 }, - { .n =3D "smdck", .p =3D "smdclk", .id =3D 4 }, - { .n =3D "uhpck", .p =3D "usbck", .id =3D 6 }, - { .n =3D "udpck", .p =3D "usbck", .id =3D 7 }, - { .n =3D "pck0", .p =3D "prog0", .id =3D 8 }, - { .n =3D "pck1", .p =3D "prog1", .id =3D 9 }, - { .n =3D "pck2", .p =3D "prog2", .id =3D 10 }, + { .n =3D "ddrck", .id =3D 2, .flags =3D CLK_IS_CRITICAL }, + { .n =3D "lcdck", .id =3D 3 }, + { .n =3D "smdck", .id =3D 4 }, + { .n =3D "uhpck", .id =3D 6 }, + { .n =3D "udpck", .id =3D 7 }, + { .n =3D "pck0", .id =3D 8 }, + { .n =3D "pck1", .id =3D 9 }, + { .n =3D "pck2", .id =3D 10 }, }; =20 static const struct { @@ -128,25 +128,16 @@ static const struct { =20 static void __init sama5d4_pmc_setup(struct device_node *np) { + const char *slow_clk_name =3D "slowck", *main_xtal_name =3D "main_xtal"; + struct clk_hw *main_rc_hw, *main_osc_hw, *mainck_hw; + u8 slow_clk_index =3D 0, main_xtal_index =3D 1; + struct clk_hw *smdck_hw, *usbck_hw, *hw; struct clk_range range =3D CLK_RANGE(0, 0); - const char *slck_name, *mainxtal_name; + struct clk_parent_data parent_data[5]; struct pmc_data *sama5d4_pmc; - const char *parent_names[5]; struct regmap *regmap; - struct clk_hw *hw; - int i; bool bypass; - - i =3D of_property_match_string(np, "clock-names", "slow_clk"); - if (i < 0) - return; - - slck_name =3D of_clk_get_parent_name(np, i); - - i =3D of_property_match_string(np, "clock-names", "main_xtal"); - if (i < 0) - return; - mainxtal_name =3D of_clk_get_parent_name(np, i); + int i; =20 regmap =3D device_node_to_regmap(np); if (IS_ERR(regmap)) @@ -158,54 +149,54 @@ static void __init sama5d4_pmc_setup(struct device_no= de *np) if (!sama5d4_pmc) return; =20 - hw =3D at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000, - 100000000); - if (IS_ERR(hw)) + main_rc_hw =3D at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000= 000, + 100000000); + if (IS_ERR(main_rc_hw)) goto err_free; =20 bypass =3D of_property_read_bool(np, "atmel,osc-bypass"); =20 - hw =3D at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL, - bypass); - if (IS_ERR(hw)) + main_osc_hw =3D at91_clk_register_main_osc(regmap, "main_osc", NULL, + &AT91_CLK_PD_NAME(main_xtal_name, main_xtal_index), + bypass); + if (IS_ERR(main_osc_hw)) goto err_free; =20 - parent_names[0] =3D "main_rc_osc"; - parent_names[1] =3D "main_osc"; - hw =3D at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL= , 2); + parent_data[0] =3D AT91_CLK_PD_HW(main_rc_hw); + parent_data[1] =3D AT91_CLK_PD_HW(main_osc_hw); + mainck_hw =3D at91_clk_register_sam9x5_main(regmap, "mainck", NULL, paren= t_data, 2); if (IS_ERR(hw)) goto err_free; =20 - hw =3D at91_clk_register_pll(regmap, "pllack", "mainck", 0, + hw =3D at91_clk_register_pll(regmap, "pllack", NULL, &AT91_CLK_PD_HW(main= ck_hw), 0, &sama5d3_pll_layout, &plla_characteristics); if (IS_ERR(hw)) goto err_free; =20 - hw =3D at91_clk_register_plldiv(regmap, "plladivck", "pllack"); + hw =3D at91_clk_register_plldiv(regmap, "plladivck", NULL, &AT91_CLK_PD_H= W(hw)); if (IS_ERR(hw)) goto err_free; =20 sama5d4_pmc->chws[PMC_PLLACK] =3D hw; =20 - hw =3D at91_clk_register_utmi(regmap, NULL, "utmick", "mainck", NULL); + hw =3D at91_clk_register_utmi(regmap, NULL, "utmick", NULL, &AT91_CLK_PD_= HW(mainck_hw)); if (IS_ERR(hw)) goto err_free; =20 sama5d4_pmc->chws[PMC_UTMI] =3D hw; =20 - parent_names[0] =3D slck_name; - parent_names[1] =3D "mainck"; - parent_names[2] =3D "plladivck"; - parent_names[3] =3D "utmick"; + parent_data[0] =3D AT91_CLK_PD_NAME(slow_clk_name, slow_clk_index); + parent_data[1] =3D AT91_CLK_PD_HW(mainck_hw); + parent_data[2] =3D AT91_CLK_PD_HW(sama5d4_pmc->chws[PMC_PLLACK]); + parent_data[3] =3D AT91_CLK_PD_HW(sama5d4_pmc->chws[PMC_UTMI]); hw =3D at91_clk_register_master_pres(regmap, "masterck_pres", 4, - parent_names, NULL, + NULL, parent_data, &at91sam9x5_master_layout, &mck_characteristics, &mck_lock); if (IS_ERR(hw)) goto err_free; =20 - hw =3D at91_clk_register_master_div(regmap, "masterck_div", - "masterck_pres", NULL, + hw =3D at91_clk_register_master_div(regmap, "masterck_div", NULL, &AT91_C= LK_PD_HW(hw), &at91sam9x5_master_layout, &mck_characteristics, &mck_lock, CLK_SET_RATE_GATE, 0); @@ -214,36 +205,37 @@ static void __init sama5d4_pmc_setup(struct device_no= de *np) =20 sama5d4_pmc->chws[PMC_MCK] =3D hw; =20 - hw =3D at91_clk_register_h32mx(regmap, "h32mxck", "masterck_div"); + hw =3D at91_clk_register_h32mx(regmap, "h32mxck", NULL, + &AT91_CLK_PD_HW(sama5d4_pmc->chws[PMC_MCK])); if (IS_ERR(hw)) goto err_free; =20 sama5d4_pmc->chws[PMC_MCK2] =3D hw; =20 - parent_names[0] =3D "plladivck"; - parent_names[1] =3D "utmick"; - hw =3D at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, NULL, 2= ); - if (IS_ERR(hw)) + parent_data[0] =3D AT91_CLK_PD_HW(sama5d4_pmc->chws[PMC_PLLACK]); + parent_data[1] =3D AT91_CLK_PD_HW(sama5d4_pmc->chws[PMC_UTMI]); + usbck_hw =3D at91sam9x5_clk_register_usb(regmap, "usbck", NULL, parent_da= ta, 2); + if (IS_ERR(usbck_hw)) goto err_free; =20 - parent_names[0] =3D "plladivck"; - parent_names[1] =3D "utmick"; - hw =3D at91sam9x5_clk_register_smd(regmap, "smdclk", parent_names, 2); - if (IS_ERR(hw)) + parent_data[0] =3D AT91_CLK_PD_HW(sama5d4_pmc->chws[PMC_PLLACK]); + parent_data[1] =3D AT91_CLK_PD_HW(sama5d4_pmc->chws[PMC_UTMI]); + smdck_hw =3D at91sam9x5_clk_register_smd(regmap, "smdclk", NULL, parent_d= ata, 2); + if (IS_ERR(smdck_hw)) goto err_free; =20 - parent_names[0] =3D slck_name; - parent_names[1] =3D "mainck"; - parent_names[2] =3D "plladivck"; - parent_names[3] =3D "utmick"; - parent_names[4] =3D "masterck_div"; + parent_data[0] =3D AT91_CLK_PD_NAME(slow_clk_name, slow_clk_index); + parent_data[1] =3D AT91_CLK_PD_HW(mainck_hw); + parent_data[2] =3D AT91_CLK_PD_HW(sama5d4_pmc->chws[PMC_PLLACK]); + parent_data[3] =3D AT91_CLK_PD_HW(sama5d4_pmc->chws[PMC_UTMI]); + parent_data[4] =3D AT91_CLK_PD_HW(sama5d4_pmc->chws[PMC_MCK]); for (i =3D 0; i < 3; i++) { char name[6]; =20 snprintf(name, sizeof(name), "prog%d", i); =20 hw =3D at91_clk_register_programmable(regmap, name, - parent_names, NULL, 5, i, + NULL, parent_data, 5, i, &at91sam9x5_programmable_layout, NULL); if (IS_ERR(hw)) @@ -252,9 +244,18 @@ static void __init sama5d4_pmc_setup(struct device_nod= e *np) sama5d4_pmc->pchws[i] =3D hw; } =20 + /* Set systemck parent hws. */ + sama5d4_systemck[0].parent_hw =3D sama5d4_pmc->chws[PMC_MCK]; + sama5d4_systemck[1].parent_hw =3D sama5d4_pmc->chws[PMC_MCK]; + sama5d4_systemck[2].parent_hw =3D smdck_hw; + sama5d4_systemck[3].parent_hw =3D usbck_hw; + sama5d4_systemck[4].parent_hw =3D usbck_hw; + sama5d4_systemck[5].parent_hw =3D sama5d4_pmc->pchws[0]; + sama5d4_systemck[6].parent_hw =3D sama5d4_pmc->pchws[1]; + sama5d4_systemck[7].parent_hw =3D sama5d4_pmc->pchws[2]; for (i =3D 0; i < ARRAY_SIZE(sama5d4_systemck); i++) { - hw =3D at91_clk_register_system(regmap, sama5d4_systemck[i].n, - sama5d4_systemck[i].p, NULL, + hw =3D at91_clk_register_system(regmap, sama5d4_systemck[i].n, NULL, + &AT91_CLK_PD_HW(sama5d4_systemck[i].parent_hw), sama5d4_systemck[i].id, sama5d4_systemck[i].flags); if (IS_ERR(hw)) @@ -267,7 +268,8 @@ static void __init sama5d4_pmc_setup(struct device_node= *np) hw =3D at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, &sama5d4_pcr_layout, sama5d4_periphck[i].n, - "masterck_div", NULL, + NULL, + &AT91_CLK_PD_HW(sama5d4_pmc->chws[PMC_MCK]), sama5d4_periphck[i].id, &range, INT_MIN, sama5d4_periphck[i].flags); @@ -281,7 +283,8 @@ static void __init sama5d4_pmc_setup(struct device_node= *np) hw =3D at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, &sama5d4_pcr_layout, sama5d4_periph32ck[i].n, - "h32mxck", NULL, + NULL, + &AT91_CLK_PD_HW(sama5d4_pmc->chws[PMC_MCK2]), sama5d4_periph32ck[i].id, &range, INT_MIN, 0); if (IS_ERR(hw)) --=20 2.43.0 From nobody Wed Oct 8 20:52:50 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C0F702FE36E; Tue, 24 Jun 2025 15:09:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777766; cv=none; b=kRLQLo2s+aQq4js4ZD4cjVC7B05KAzmFqviKf2F/p7u3iHYmPr8jp+eibyynGwtQWIPYzylkluLSU3jbK1qgsfi3fDYticm5RUhuRKXwvHbrr6cb+Klq7EQW2BXNjAIXJka3xY2O3ubN4gmYCWasYC72O7QR9P0ivaHqZQvV5Ik= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777766; c=relaxed/simple; bh=45HBGPbfcx1yNpsLcAsoMx4UqrF/eK24Fo5weJaY5kE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=MymBjuIu0nTvWHysoSE6SitOmEWlK3er4FNf/bCEK4c2LKj/uh8NSNfIqTbnVU3RuxKwTdIZqZjWK1oTb6enyqv7064iuFwszEXuKPI6ccY6hZBTAb6bMw1BBS0zSksypa8I0RogNLblKye+07y8sBOErv7weaW+Lf3BFn+0sEw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=aBE3VbG0; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="aBE3VbG0" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1750777763; x=1782313763; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=45HBGPbfcx1yNpsLcAsoMx4UqrF/eK24Fo5weJaY5kE=; b=aBE3VbG0NKF/CWrjj/xavUT68Cw05Fvnbfp+U400ZNsqcAdYTDfmOZ8X ADH0lnmdr1IpgJYzCM2Lmtck+MxWC5WMBtSulJNn4goU/7Fe/7KtcwWIv k7VaiQkvlm2hjf91LI9HwqHSRrrrvo0vXeJKkJqIcR2vPurMcFdF/7dPp FgdYYDglMMLP9tMXJWN77hWXqXq4BIhu87p8MMx9+RnpW2Q8MqVzlLPIF kONaTG672cd3m1WxSjznEHPnvf5ylf9FtaZ4fCvCYHk10dJUX1WS6U2Ri +AA9tEO0+wDyn2Z0xM19IN8plsrx7RG87FX8S0ciA60MjtuClagS+lpT2 A==; X-CSE-ConnectionGUID: ticneE1VRpCt6c5L3blMOw== X-CSE-MsgGUID: nfwGsX0pQiiFJlrpXxnqJw== X-IronPort-AV: E=Sophos;i="6.16,262,1744095600"; d="scan'208";a="210641594" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 24 Jun 2025 08:09:18 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Tue, 24 Jun 2025 08:08:39 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Tue, 24 Jun 2025 08:08:39 -0700 From: To: , , , , CC: , , , , Subject: [PATCH v2 24/32] clk: at91: at91sam9x5: switch to parent_hw and parent_data Date: Tue, 24 Jun 2025 08:08:21 -0700 Message-ID: <0e31fdf8ce5bf6740ee6f0d18feafea9283e85da.1750182562.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Switch AT91SAM9X5 clocks to use parent_hw and parent_data. Having parent_hw instead of parent names improves to clock registration speed and re-parenting. Signed-off-by: Claudiu Beznea Signed-off-by: Ryan Wanner --- drivers/clk/at91/at91sam9x5.c | 125 ++++++++++++++++++---------------- 1 file changed, 65 insertions(+), 60 deletions(-) diff --git a/drivers/clk/at91/at91sam9x5.c b/drivers/clk/at91/at91sam9x5.c index 5728cfb9036f..f6138622ab50 100644 --- a/drivers/clk/at91/at91sam9x5.c +++ b/drivers/clk/at91/at91sam9x5.c @@ -38,9 +38,9 @@ static const struct clk_pll_characteristics plla_characte= ristics =3D { .out =3D plla_out, }; =20 -static const struct { +static struct { char *n; - char *p; + struct clk_hw *parent_hw; unsigned long flags; u8 id; } at91sam9x5_systemck[] =3D { @@ -48,12 +48,12 @@ static const struct { * ddrck feeds DDR controller and is enabled by bootloader thus we need * to keep it enabled in case there is no Linux consumer for it. */ - { .n =3D "ddrck", .p =3D "masterck_div", .id =3D 2, .flags =3D CLK_IS_CRI= TICAL }, - { .n =3D "smdck", .p =3D "smdclk", .id =3D 4 }, - { .n =3D "uhpck", .p =3D "usbck", .id =3D 6 }, - { .n =3D "udpck", .p =3D "usbck", .id =3D 7 }, - { .n =3D "pck0", .p =3D "prog0", .id =3D 8 }, - { .n =3D "pck1", .p =3D "prog1", .id =3D 9 }, + { .n =3D "ddrck", .id =3D 2, .flags =3D CLK_IS_CRITICAL }, + { .n =3D "smdck", .id =3D 4 }, + { .n =3D "uhpck", .id =3D 6 }, + { .n =3D "udpck", .id =3D 7 }, + { .n =3D "pck0", .id =3D 8 }, + { .n =3D "pck1", .id =3D 9 }, }; =20 static const struct clk_pcr_layout at91sam9x5_pcr_layout =3D { @@ -133,25 +133,16 @@ static void __init at91sam9x5_pmc_setup(struct device= _node *np, const struct pck *extra_pcks, bool has_lcdck) { + const char *slow_clk_name =3D "slowck", *main_xtal_name =3D "main_xtal"; + struct clk_hw *main_rc_hw, *main_osc_hw, *hw; + u8 slow_clk_index =3D 0, main_xtal_index =3D 0; struct clk_range range =3D CLK_RANGE(0, 0); - const char *slck_name, *mainxtal_name; + struct clk_parent_data parent_data[6]; + struct clk_hw *smdck_hw, *usbck_hw; struct pmc_data *at91sam9x5_pmc; - const char *parent_names[6]; struct regmap *regmap; - struct clk_hw *hw; - int i; bool bypass; - - i =3D of_property_match_string(np, "clock-names", "slow_clk"); - if (i < 0) - return; - - slck_name =3D of_clk_get_parent_name(np, i); - - i =3D of_property_match_string(np, "clock-names", "main_xtal"); - if (i < 0) - return; - mainxtal_name =3D of_clk_get_parent_name(np, i); + int i; =20 regmap =3D device_node_to_regmap(np); if (IS_ERR(regmap)) @@ -162,56 +153,59 @@ static void __init at91sam9x5_pmc_setup(struct device= _node *np, if (!at91sam9x5_pmc) return; =20 - hw =3D at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000, - 50000000); - if (IS_ERR(hw)) + main_rc_hw =3D at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000= 000, + 50000000); + if (IS_ERR(main_rc_hw)) goto err_free; =20 bypass =3D of_property_read_bool(np, "atmel,osc-bypass"); =20 - hw =3D at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL, - bypass); - if (IS_ERR(hw)) + main_osc_hw =3D at91_clk_register_main_osc(regmap, "main_osc", NULL, + &AT91_CLK_PD_NAME(main_xtal_name, main_xtal_index), + bypass); + if (IS_ERR(main_osc_hw)) goto err_free; =20 - parent_names[0] =3D "main_rc_osc"; - parent_names[1] =3D "main_osc"; - hw =3D at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL= , 2); + parent_data[0] =3D AT91_CLK_PD_HW(main_rc_hw); + parent_data[1] =3D AT91_CLK_PD_HW(main_osc_hw); + hw =3D at91_clk_register_sam9x5_main(regmap, "mainck", NULL, parent_data,= 2); if (IS_ERR(hw)) goto err_free; =20 at91sam9x5_pmc->chws[PMC_MAIN] =3D hw; =20 - hw =3D at91_clk_register_pll(regmap, "pllack", "mainck", 0, + hw =3D at91_clk_register_pll(regmap, "pllack", NULL, + &AT91_CLK_PD_HW(at91sam9x5_pmc->chws[PMC_MAIN]), 0, &at91rm9200_pll_layout, &plla_characteristics); if (IS_ERR(hw)) goto err_free; =20 - hw =3D at91_clk_register_plldiv(regmap, "plladivck", "pllack"); + hw =3D at91_clk_register_plldiv(regmap, "plladivck", NULL, &AT91_CLK_PD_H= W(hw)); if (IS_ERR(hw)) goto err_free; =20 at91sam9x5_pmc->chws[PMC_PLLACK] =3D hw; =20 - hw =3D at91_clk_register_utmi(regmap, NULL, "utmick", "mainck", NULL); + hw =3D at91_clk_register_utmi(regmap, NULL, "utmick", NULL, + &AT91_CLK_PD_HW(at91sam9x5_pmc->chws[PMC_MAIN])); if (IS_ERR(hw)) goto err_free; =20 at91sam9x5_pmc->chws[PMC_UTMI] =3D hw; =20 - parent_names[0] =3D slck_name; - parent_names[1] =3D "mainck"; - parent_names[2] =3D "plladivck"; - parent_names[3] =3D "utmick"; + parent_data[0] =3D AT91_CLK_PD_NAME(slow_clk_name, slow_clk_index); + parent_data[1] =3D AT91_CLK_PD_HW(at91sam9x5_pmc->chws[PMC_MAIN]); + parent_data[2] =3D AT91_CLK_PD_HW(at91sam9x5_pmc->chws[PMC_PLLACK]); + parent_data[3] =3D AT91_CLK_PD_HW(at91sam9x5_pmc->chws[PMC_UTMI]); hw =3D at91_clk_register_master_pres(regmap, "masterck_pres", 4, - parent_names, NULL, + NULL, parent_data, &at91sam9x5_master_layout, &mck_characteristics, &mck_lock); if (IS_ERR(hw)) goto err_free; =20 - hw =3D at91_clk_register_master_div(regmap, "masterck_div", - "masterck_pres", NULL, + hw =3D at91_clk_register_master_div(regmap, "masterck_div", NULL, + &AT91_CLK_PD_HW(hw), &at91sam9x5_master_layout, &mck_characteristics, &mck_lock, CLK_SET_RATE_GATE, 0); @@ -220,28 +214,30 @@ static void __init at91sam9x5_pmc_setup(struct device= _node *np, =20 at91sam9x5_pmc->chws[PMC_MCK] =3D hw; =20 - parent_names[0] =3D "plladivck"; - parent_names[1] =3D "utmick"; - hw =3D at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, NULL, 2= ); - if (IS_ERR(hw)) + parent_data[0] =3D AT91_CLK_PD_HW(at91sam9x5_pmc->chws[PMC_PLLACK]); + parent_data[1] =3D AT91_CLK_PD_HW(at91sam9x5_pmc->chws[PMC_UTMI]); + usbck_hw =3D at91sam9x5_clk_register_usb(regmap, "usbck", NULL, parent_da= ta, 2); + if (IS_ERR(usbck_hw)) goto err_free; =20 - hw =3D at91sam9x5_clk_register_smd(regmap, "smdclk", parent_names, 2); - if (IS_ERR(hw)) + parent_data[0] =3D AT91_CLK_PD_HW(at91sam9x5_pmc->chws[PMC_PLLACK]); + parent_data[1] =3D AT91_CLK_PD_HW(at91sam9x5_pmc->chws[PMC_UTMI]); + smdck_hw =3D at91sam9x5_clk_register_smd(regmap, "smdclk", NULL, parent_d= ata, 2); + if (IS_ERR(smdck_hw)) goto err_free; =20 - parent_names[0] =3D slck_name; - parent_names[1] =3D "mainck"; - parent_names[2] =3D "plladivck"; - parent_names[3] =3D "utmick"; - parent_names[4] =3D "masterck_div"; + parent_data[0] =3D AT91_CLK_PD_NAME(slow_clk_name, slow_clk_index); + parent_data[1] =3D AT91_CLK_PD_HW(at91sam9x5_pmc->chws[PMC_MAIN]); + parent_data[2] =3D AT91_CLK_PD_HW(at91sam9x5_pmc->chws[PMC_PLLACK]); + parent_data[3] =3D AT91_CLK_PD_HW(at91sam9x5_pmc->chws[PMC_UTMI]); + parent_data[4] =3D AT91_CLK_PD_HW(at91sam9x5_pmc->chws[PMC_MCK]); for (i =3D 0; i < 2; i++) { char name[6]; =20 snprintf(name, sizeof(name), "prog%d", i); =20 hw =3D at91_clk_register_programmable(regmap, name, - parent_names, NULL, 5, i, + NULL, parent_data, 5, i, &at91sam9x5_programmable_layout, NULL); if (IS_ERR(hw)) @@ -250,9 +246,16 @@ static void __init at91sam9x5_pmc_setup(struct device_= node *np, at91sam9x5_pmc->pchws[i] =3D hw; } =20 + /* Set systemck parent hws. */ + at91sam9x5_systemck[0].parent_hw =3D at91sam9x5_pmc->chws[PMC_MCK]; + at91sam9x5_systemck[1].parent_hw =3D smdck_hw; + at91sam9x5_systemck[2].parent_hw =3D usbck_hw; + at91sam9x5_systemck[3].parent_hw =3D usbck_hw; + at91sam9x5_systemck[4].parent_hw =3D at91sam9x5_pmc->pchws[0]; + at91sam9x5_systemck[5].parent_hw =3D at91sam9x5_pmc->pchws[1]; for (i =3D 0; i < ARRAY_SIZE(at91sam9x5_systemck); i++) { - hw =3D at91_clk_register_system(regmap, at91sam9x5_systemck[i].n, - at91sam9x5_systemck[i].p, NULL, + hw =3D at91_clk_register_system(regmap, at91sam9x5_systemck[i].n, NULL, + &AT91_CLK_PD_HW(at91sam9x5_systemck[i].parent_hw), at91sam9x5_systemck[i].id, at91sam9x5_systemck[i].flags); if (IS_ERR(hw)) @@ -262,8 +265,8 @@ static void __init at91sam9x5_pmc_setup(struct device_n= ode *np, } =20 if (has_lcdck) { - hw =3D at91_clk_register_system(regmap, "lcdck", "masterck_div", - NULL, 3, 0); + hw =3D at91_clk_register_system(regmap, "lcdck", NULL, + &AT91_CLK_PD_HW(at91sam9x5_pmc->chws[PMC_MCK]), 3, 0); if (IS_ERR(hw)) goto err_free; =20 @@ -274,7 +277,8 @@ static void __init at91sam9x5_pmc_setup(struct device_n= ode *np, hw =3D at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, &at91sam9x5_pcr_layout, at91sam9x5_periphck[i].n, - "masterck_div", NULL, + NULL, + &AT91_CLK_PD_HW(at91sam9x5_pmc->chws[PMC_MCK]), at91sam9x5_periphck[i].id, &range, INT_MIN, 0); if (IS_ERR(hw)) @@ -287,7 +291,8 @@ static void __init at91sam9x5_pmc_setup(struct device_n= ode *np, hw =3D at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, &at91sam9x5_pcr_layout, extra_pcks[i].n, - "masterck_div", NULL, + NULL, + &AT91_CLK_PD_HW(at91sam9x5_pmc->chws[PMC_MCK]), extra_pcks[i].id, &range, INT_MIN, 0); if (IS_ERR(hw)) --=20 2.43.0 From nobody Wed Oct 8 20:52:50 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C16B32FD891; Tue, 24 Jun 2025 15:09:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777766; cv=none; b=TiD7AJbqS+zJvY4LXLvUo8dM09NVS2cejUL9HEJzCfyt61YZ+MArD5Qs0D74hXQK1Aqbnhzjus2Kdp3ZAdpxglF6TS83emGl0Z3PLSkTr+iHld4RSW4sepfTCA9a/XwaMtH2qXh1z6lnGU2RTWZtFSYpYWDmdcUPGW3O12MnY4o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777766; c=relaxed/simple; bh=O2Zt1XX0R1JiK19VDiYWzEWiF0EXKDRs0eFCWGMPWCI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=TFUUjdSPQOUSNwcg60JBgz6u1XlKuDDq7+fmSeBVyLsaVFLYBcf4G87tSkO6dWuuARUrWe36s2CzKJS8/8mTC7TPFkcO5riflGiFFgszP6Uxl2mWcKbURMvDnuJDPVUC2wSsIg0V7xT/E/bToKC/qF5bgrh9oWgZorGF2PLCSyA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=vbEZ1S1x; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="vbEZ1S1x" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1750777763; x=1782313763; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=O2Zt1XX0R1JiK19VDiYWzEWiF0EXKDRs0eFCWGMPWCI=; b=vbEZ1S1xm66gyaqWGnvPT3jUjpJ5PjsQoJjLkh0nCJdp4Cl8CIbaoiDX qhv32KECsd6/2ouiOFNvF7MPktM4raWcqILc/c8BBt6w72B07YaGXj/gb IztnM9FfP8MPxCKU7mhclylUK6Rwq25l4ZUWZTNQ+meVHIrir07vSWxvU NOkx71BNjVBz+DfHOYVASltBdF8Ns49N0jFlq33c4a94ViQBSpv3oKdyl EdkPy2yvmwPnqA+txSkXDibfHB15Bom9h87+ClfXmNw0Eta7NO/DOV99Z H66qG5Om0g1RFCZqhdl/wq32zjP9wi6b02+cnzKFUt/Yths72463XfIvN w==; X-CSE-ConnectionGUID: ticneE1VRpCt6c5L3blMOw== X-CSE-MsgGUID: AQ3qOGdpSYiTgkL1gij/Gg== X-IronPort-AV: E=Sophos;i="6.16,262,1744095600"; d="scan'208";a="210641595" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 24 Jun 2025 08:09:19 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Tue, 24 Jun 2025 08:08:39 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Tue, 24 Jun 2025 08:08:39 -0700 From: To: , , , , CC: , , , , Subject: [PATCH v2 25/32] clk: at91: at91rm9200: switch to parent_hw and parent_data Date: Tue, 24 Jun 2025 08:08:22 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Switch AT91RM9200 clocks to use parent_hw and parent_data. Having parent_hw instead of parent names improves to clock registration speed and re-parenting. Signed-off-by: Claudiu Beznea Signed-off-by: Ryan Wanner --- drivers/clk/at91/at91rm9200.c | 95 ++++++++++++++++++----------------- 1 file changed, 49 insertions(+), 46 deletions(-) diff --git a/drivers/clk/at91/at91rm9200.c b/drivers/clk/at91/at91rm9200.c index e5a034f208d8..b834ca5ed092 100644 --- a/drivers/clk/at91/at91rm9200.c +++ b/drivers/clk/at91/at91rm9200.c @@ -11,7 +11,7 @@ static DEFINE_SPINLOCK(rm9200_mck_lock); =20 struct sck { char *n; - char *p; + struct clk_hw *parent_hw; u8 id; }; =20 @@ -39,13 +39,13 @@ static const struct clk_pll_characteristics rm9200_pll_= characteristics =3D { .out =3D rm9200_pll_out, }; =20 -static const struct sck at91rm9200_systemck[] =3D { - { .n =3D "udpck", .p =3D "usbck", .id =3D 1 }, - { .n =3D "uhpck", .p =3D "usbck", .id =3D 4 }, - { .n =3D "pck0", .p =3D "prog0", .id =3D 8 }, - { .n =3D "pck1", .p =3D "prog1", .id =3D 9 }, - { .n =3D "pck2", .p =3D "prog2", .id =3D 10 }, - { .n =3D "pck3", .p =3D "prog3", .id =3D 11 }, +static struct sck at91rm9200_systemck[] =3D { + { .n =3D "udpck", .id =3D 1 }, + { .n =3D "uhpck", .id =3D 4 }, + { .n =3D "pck0", .id =3D 8 }, + { .n =3D "pck1", .id =3D 9 }, + { .n =3D "pck2", .id =3D 10 }, + { .n =3D "pck3", .id =3D 11 }, }; =20 static const struct pck at91rm9200_periphck[] =3D { @@ -76,25 +76,15 @@ static const struct pck at91rm9200_periphck[] =3D { =20 static void __init at91rm9200_pmc_setup(struct device_node *np) { - const char *slowxtal_name, *mainxtal_name; + const char *slow_clk_name =3D "slowck", *main_xtal_name =3D "main_xtal"; + struct clk_hw *usbck_hw, *main_osc_hw, *hw; + u8 slow_clk_index =3D 0, main_xtal_index =3D 1; + struct clk_parent_data parent_data[6]; struct pmc_data *at91rm9200_pmc; u32 usb_div[] =3D { 1, 2, 0, 0 }; - const char *parent_names[6]; struct regmap *regmap; - struct clk_hw *hw; - int i; bool bypass; - - i =3D of_property_match_string(np, "clock-names", "slow_xtal"); - if (i < 0) - return; - - slowxtal_name =3D of_clk_get_parent_name(np, i); - - i =3D of_property_match_string(np, "clock-names", "main_xtal"); - if (i < 0) - return; - mainxtal_name =3D of_clk_get_parent_name(np, i); + int i; =20 regmap =3D device_node_to_regmap(np); if (IS_ERR(regmap)) @@ -108,18 +98,21 @@ static void __init at91rm9200_pmc_setup(struct device_= node *np) =20 bypass =3D of_property_read_bool(np, "atmel,osc-bypass"); =20 - hw =3D at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL, - bypass); - if (IS_ERR(hw)) + main_osc_hw =3D at91_clk_register_main_osc(regmap, "main_osc", NULL, + &AT91_CLK_PD_NAME(main_xtal_name, main_xtal_index), + bypass); + if (IS_ERR(main_osc_hw)) goto err_free; =20 - hw =3D at91_clk_register_rm9200_main(regmap, "mainck", "main_osc", NULL); + hw =3D at91_clk_register_rm9200_main(regmap, "mainck", NULL, + &AT91_CLK_PD_HW(main_osc_hw)); if (IS_ERR(hw)) goto err_free; =20 at91rm9200_pmc->chws[PMC_MAIN] =3D hw; =20 - hw =3D at91_clk_register_pll(regmap, "pllack", "mainck", 0, + hw =3D at91_clk_register_pll(regmap, "pllack", NULL, + &AT91_CLK_PD_HW(at91rm9200_pmc->chws[PMC_MAIN]), 0, &at91rm9200_pll_layout, &rm9200_pll_characteristics); if (IS_ERR(hw)) @@ -127,7 +120,8 @@ static void __init at91rm9200_pmc_setup(struct device_n= ode *np) =20 at91rm9200_pmc->chws[PMC_PLLACK] =3D hw; =20 - hw =3D at91_clk_register_pll(regmap, "pllbck", "mainck", 1, + hw =3D at91_clk_register_pll(regmap, "pllbck", NULL, + &AT91_CLK_PD_HW(at91rm9200_pmc->chws[PMC_MAIN]), 1, &at91rm9200_pll_layout, &rm9200_pll_characteristics); if (IS_ERR(hw)) @@ -135,20 +129,19 @@ static void __init at91rm9200_pmc_setup(struct device= _node *np) =20 at91rm9200_pmc->chws[PMC_PLLBCK] =3D hw; =20 - parent_names[0] =3D slowxtal_name; - parent_names[1] =3D "mainck"; - parent_names[2] =3D "pllack"; - parent_names[3] =3D "pllbck"; + parent_data[0] =3D AT91_CLK_PD_NAME(slow_clk_name, slow_clk_index); + parent_data[1] =3D AT91_CLK_PD_HW(at91rm9200_pmc->chws[PMC_MAIN]); + parent_data[2] =3D AT91_CLK_PD_HW(at91rm9200_pmc->chws[PMC_PLLACK]); + parent_data[3] =3D AT91_CLK_PD_HW(at91rm9200_pmc->chws[PMC_PLLBCK]); hw =3D at91_clk_register_master_pres(regmap, "masterck_pres", 4, - parent_names, NULL, + NULL, parent_data, &at91rm9200_master_layout, &rm9200_mck_characteristics, &rm9200_mck_lock); if (IS_ERR(hw)) goto err_free; =20 - hw =3D at91_clk_register_master_div(regmap, "masterck_div", - "masterck_pres", NULL, + hw =3D at91_clk_register_master_div(regmap, "masterck_div", NULL, &AT91_C= LK_PD_HW(hw), &at91rm9200_master_layout, &rm9200_mck_characteristics, &rm9200_mck_lock, CLK_SET_RATE_GATE, 0); @@ -157,21 +150,23 @@ static void __init at91rm9200_pmc_setup(struct device= _node *np) =20 at91rm9200_pmc->chws[PMC_MCK] =3D hw; =20 - hw =3D at91rm9200_clk_register_usb(regmap, "usbck", "pllbck", NULL, usb_d= iv); - if (IS_ERR(hw)) + usbck_hw =3D at91rm9200_clk_register_usb(regmap, "usbck", NULL, + &AT91_CLK_PD_HW(at91rm9200_pmc->chws[PMC_PLLBCK]), + usb_div); + if (IS_ERR(usbck_hw)) goto err_free; =20 - parent_names[0] =3D slowxtal_name; - parent_names[1] =3D "mainck"; - parent_names[2] =3D "pllack"; - parent_names[3] =3D "pllbck"; + parent_data[0] =3D AT91_CLK_PD_NAME(slow_clk_name, slow_clk_index); + parent_data[1] =3D AT91_CLK_PD_HW(at91rm9200_pmc->chws[PMC_MAIN]); + parent_data[2] =3D AT91_CLK_PD_HW(at91rm9200_pmc->chws[PMC_PLLACK]); + parent_data[3] =3D AT91_CLK_PD_HW(at91rm9200_pmc->chws[PMC_PLLBCK]); for (i =3D 0; i < 4; i++) { char name[6]; =20 snprintf(name, sizeof(name), "prog%d", i); =20 hw =3D at91_clk_register_programmable(regmap, name, - parent_names, NULL, 4, i, + NULL, parent_data, 4, i, &at91rm9200_programmable_layout, NULL); if (IS_ERR(hw)) @@ -180,9 +175,16 @@ static void __init at91rm9200_pmc_setup(struct device_= node *np) at91rm9200_pmc->pchws[i] =3D hw; } =20 + /* Set systemck parent hws. */ + at91rm9200_systemck[0].parent_hw =3D usbck_hw; + at91rm9200_systemck[1].parent_hw =3D usbck_hw; + at91rm9200_systemck[2].parent_hw =3D at91rm9200_pmc->pchws[0]; + at91rm9200_systemck[3].parent_hw =3D at91rm9200_pmc->pchws[1]; + at91rm9200_systemck[4].parent_hw =3D at91rm9200_pmc->pchws[2]; + at91rm9200_systemck[5].parent_hw =3D at91rm9200_pmc->pchws[3]; for (i =3D 0; i < ARRAY_SIZE(at91rm9200_systemck); i++) { - hw =3D at91_clk_register_system(regmap, at91rm9200_systemck[i].n, - at91rm9200_systemck[i].p, NULL, + hw =3D at91_clk_register_system(regmap, at91rm9200_systemck[i].n, NULL, + &AT91_CLK_PD_HW(at91rm9200_systemck[i].parent_hw), at91rm9200_systemck[i].id, 0); if (IS_ERR(hw)) goto err_free; @@ -193,7 +195,8 @@ static void __init at91rm9200_pmc_setup(struct device_n= ode *np) for (i =3D 0; i < ARRAY_SIZE(at91rm9200_periphck); i++) { hw =3D at91_clk_register_peripheral(regmap, at91rm9200_periphck[i].n, - "masterck_div", NULL, + NULL, + &AT91_CLK_PD_HW(at91rm9200_pmc->chws[PMC_MCK]), at91rm9200_periphck[i].id); if (IS_ERR(hw)) goto err_free; --=20 2.43.0 From nobody Wed Oct 8 20:52:50 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 322312FEE1D; Tue, 24 Jun 2025 15:09:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777767; cv=none; b=BWBm9oysXCWHFLIFZbaneSFyGieuCYUF/OlTc4sashlxXM3jxrDd7MWmt8qIRpMewQ12iSoYPib1hNUd/tMKljGoMjYqvI0qr0EF/Yi9JWHLY0twl/gBPmsyI6Gb1q20EWJTCMpIucYREf/yw8GJ/qC552Z5/jNwjdgfTEAYI38= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777767; c=relaxed/simple; bh=wfB5uD6gCAGNdoYI5EDNa7yZo4eCMYHdNNhDsFxYvQo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=dEh15AuCECkaFUD+f+g/yYNkfPvZS+KzmsO5fuZtPKR/A/tElLROD2anKp/VKq7lP8pYl/lingDWKKeRSA9wo2mj3FWoc9yREdORuQg70dGL55x3KbYTl1ZgyOCgg4qfAfK4LkDr00BfOM9VCBCQDJrwx6m3GDqOJYEzENXUGSQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=T/NkOn+1; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="T/NkOn+1" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1750777764; x=1782313764; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wfB5uD6gCAGNdoYI5EDNa7yZo4eCMYHdNNhDsFxYvQo=; b=T/NkOn+1GFLI2AV7k34+1bVnJYW/DDmUYL8yKPtP+opBi+dRU7ekC2dU YDZaGtQTCjckhWuPcthAEquya5Up5PlB1W7Mmlek09r9WDbahmCIeJrrD khQKtbAc21BRvrcFqeO9mIUL6bzyPsc5MmNeZmcRhO/NUQU+CNy5ywWSR 0uiXzM0L1lVv9ziojLQvXJOEwUE/df9lfCwHvwTPBtzA+xP1hF46Wl7F+ 3TIBp7UMI83WDvm5FFWtKncqZgypcBjNliuKWHJeuXu4cksmn2gtP68Vz V/3+UOTQm9z1rAN4IiE3bW519OevLLn8npen0kUg8nh7GwnQsiDqAklxu w==; X-CSE-ConnectionGUID: ticneE1VRpCt6c5L3blMOw== X-CSE-MsgGUID: y5KC2cayRRO9o5jg7WNSvA== X-IronPort-AV: E=Sophos;i="6.16,262,1744095600"; d="scan'208";a="210641596" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 24 Jun 2025 08:09:19 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Tue, 24 Jun 2025 08:08:40 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Tue, 24 Jun 2025 08:08:40 -0700 From: To: , , , , CC: , , , , Subject: [PATCH v2 26/32] clk: at91: at91sam9260: switch to parent_hw and parent_data Date: Tue, 24 Jun 2025 08:08:23 -0700 Message-ID: <9d0506b03b23ce3354b8a956e5da183302ad1f31.1750182562.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Switch AT91SAM92600 clocks to use parent_hw and parent_data. Having parent_hw instead of parent names improves to clock registration speed and re-parenting. Signed-off-by: Claudiu Beznea Signed-off-by: Ryan Wanner --- drivers/clk/at91/at91sam9260.c | 136 +++++++++++++++++---------------- 1 file changed, 70 insertions(+), 66 deletions(-) diff --git a/drivers/clk/at91/at91sam9260.c b/drivers/clk/at91/at91sam9260.c index ae6f126f204a..827ae743b657 100644 --- a/drivers/clk/at91/at91sam9260.c +++ b/drivers/clk/at91/at91sam9260.c @@ -9,7 +9,7 @@ =20 struct sck { char *n; - char *p; + struct clk_hw *parent_hw; u8 id; }; =20 @@ -24,7 +24,7 @@ struct at91sam926x_data { const struct clk_pll_layout *pllb_layout; const struct clk_pll_characteristics *pllb_characteristics; const struct clk_master_characteristics *mck_characteristics; - const struct sck *sck; + struct sck *sck; const struct pck *pck; u8 num_sck; u8 num_pck; @@ -72,11 +72,11 @@ static const struct clk_pll_characteristics sam9260_pll= b_characteristics =3D { .out =3D sam9260_pllb_out, }; =20 -static const struct sck at91sam9260_systemck[] =3D { - { .n =3D "uhpck", .p =3D "usbck", .id =3D 6 }, - { .n =3D "udpck", .p =3D "usbck", .id =3D 7 }, - { .n =3D "pck0", .p =3D "prog0", .id =3D 8 }, - { .n =3D "pck1", .p =3D "prog1", .id =3D 9 }, +static struct sck at91sam9260_systemck[] =3D { + { .n =3D "uhpck", .id =3D 6 }, + { .n =3D "udpck", .id =3D 7 }, + { .n =3D "pck0", .id =3D 8 }, + { .n =3D "pck1", .id =3D 9 }, }; =20 static const struct pck at91sam9260_periphck[] =3D { @@ -213,15 +213,15 @@ static const struct clk_pll_characteristics sam9261_p= llb_characteristics =3D { .out =3D sam9261_pllb_out, }; =20 -static const struct sck at91sam9261_systemck[] =3D { - { .n =3D "uhpck", .p =3D "usbck", .id =3D 6 }, - { .n =3D "udpck", .p =3D "usbck", .id =3D 7 }, - { .n =3D "pck0", .p =3D "prog0", .id =3D 8 }, - { .n =3D "pck1", .p =3D "prog1", .id =3D 9 }, - { .n =3D "pck2", .p =3D "prog2", .id =3D 10 }, - { .n =3D "pck3", .p =3D "prog3", .id =3D 11 }, - { .n =3D "hclk0", .p =3D "masterck_div", .id =3D 16 }, - { .n =3D "hclk1", .p =3D "masterck_div", .id =3D 17 }, +static struct sck at91sam9261_systemck[] =3D { + { .n =3D "uhpck", .id =3D 6 }, + { .n =3D "udpck", .id =3D 7 }, + { .n =3D "pck0", .id =3D 8 }, + { .n =3D "pck1", .id =3D 9 }, + { .n =3D "pck2", .id =3D 10 }, + { .n =3D "pck3", .id =3D 11 }, + { .n =3D "hclk0", .id =3D 16 }, + { .n =3D "hclk1", .id =3D 17 }, }; =20 static const struct pck at91sam9261_periphck[] =3D { @@ -277,13 +277,13 @@ static const struct clk_pll_characteristics sam9263_p= ll_characteristics =3D { .out =3D sam9260_plla_out, }; =20 -static const struct sck at91sam9263_systemck[] =3D { - { .n =3D "uhpck", .p =3D "usbck", .id =3D 6 }, - { .n =3D "udpck", .p =3D "usbck", .id =3D 7 }, - { .n =3D "pck0", .p =3D "prog0", .id =3D 8 }, - { .n =3D "pck1", .p =3D "prog1", .id =3D 9 }, - { .n =3D "pck2", .p =3D "prog2", .id =3D 10 }, - { .n =3D "pck3", .p =3D "prog3", .id =3D 11 }, +static struct sck at91sam9263_systemck[] =3D { + { .n =3D "uhpck", .id =3D 6 }, + { .n =3D "udpck", .id =3D 7 }, + { .n =3D "pck0", .id =3D 8 }, + { .n =3D "pck1", .id =3D 9 }, + { .n =3D "pck2", .id =3D 10 }, + { .n =3D "pck3", .id =3D 11 }, }; =20 static const struct pck at91sam9263_periphck[] =3D { @@ -329,26 +329,15 @@ static struct at91sam926x_data at91sam9263_data =3D { static void __init at91sam926x_pmc_setup(struct device_node *np, struct at91sam926x_data *data) { - const char *slowxtal_name, *mainxtal_name; + const char *slow_clk_name =3D "slowck", *main_xtal_name =3D "main_xtal"; + u8 slow_clk_index =3D 0, main_xtal_index =3D 1; + struct clk_parent_data parent_data[4]; struct pmc_data *at91sam9260_pmc; u32 usb_div[] =3D { 1, 2, 4, 0 }; - const char *parent_names[6]; - const char *slck_name; + struct clk_hw *usbck_hw, *hw; struct regmap *regmap; - struct clk_hw *hw; - int i; bool bypass; - - i =3D of_property_match_string(np, "clock-names", "slow_xtal"); - if (i < 0) - return; - - slowxtal_name =3D of_clk_get_parent_name(np, i); - - i =3D of_property_match_string(np, "clock-names", "main_xtal"); - if (i < 0) - return; - mainxtal_name =3D of_clk_get_parent_name(np, i); + int i; =20 regmap =3D device_node_to_regmap(np); if (IS_ERR(regmap)) @@ -363,12 +352,13 @@ static void __init at91sam926x_pmc_setup(struct devic= e_node *np, =20 bypass =3D of_property_read_bool(np, "atmel,osc-bypass"); =20 - hw =3D at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL, + hw =3D at91_clk_register_main_osc(regmap, "main_osc", NULL, + &AT91_CLK_PD_NAME(main_xtal_name, main_xtal_index), bypass); if (IS_ERR(hw)) goto err_free; =20 - hw =3D at91_clk_register_rm9200_main(regmap, "mainck", "main_osc", NULL); + hw =3D at91_clk_register_rm9200_main(regmap, "mainck", NULL, &AT91_CLK_PD= _HW(hw)); if (IS_ERR(hw)) goto err_free; =20 @@ -382,20 +372,17 @@ static void __init at91sam926x_pmc_setup(struct devic= e_node *np, if (IS_ERR(hw)) goto err_free; =20 - parent_names[0] =3D "slow_rc_osc"; - parent_names[1] =3D "slow_xtal"; - hw =3D at91_clk_register_sam9260_slow(regmap, "slck", - parent_names, 2); + parent_data[0] =3D AT91_CLK_PD_HW(hw); + parent_data[1] =3D AT91_CLK_PD_NAME(slow_clk_name, slow_clk_index); + hw =3D at91_clk_register_sam9260_slow(regmap, "slck", NULL, parent_data,= 2); if (IS_ERR(hw)) goto err_free; =20 at91sam9260_pmc->chws[PMC_SLOW] =3D hw; - slck_name =3D "slck"; - } else { - slck_name =3D slowxtal_name; } =20 - hw =3D at91_clk_register_pll(regmap, "pllack", "mainck", 0, + hw =3D at91_clk_register_pll(regmap, "pllack", NULL, + &AT91_CLK_PD_HW(at91sam9260_pmc->chws[PMC_MAIN]), 0, data->plla_layout, data->plla_characteristics); if (IS_ERR(hw)) @@ -403,7 +390,8 @@ static void __init at91sam926x_pmc_setup(struct device_= node *np, =20 at91sam9260_pmc->chws[PMC_PLLACK] =3D hw; =20 - hw =3D at91_clk_register_pll(regmap, "pllbck", "mainck", 1, + hw =3D at91_clk_register_pll(regmap, "pllbck", NULL, + &AT91_CLK_PD_HW(at91sam9260_pmc->chws[PMC_MAIN]), 1, data->pllb_layout, data->pllb_characteristics); if (IS_ERR(hw)) @@ -411,12 +399,12 @@ static void __init at91sam926x_pmc_setup(struct devic= e_node *np, =20 at91sam9260_pmc->chws[PMC_PLLBCK] =3D hw; =20 - parent_names[0] =3D slck_name; - parent_names[1] =3D "mainck"; - parent_names[2] =3D "pllack"; - parent_names[3] =3D "pllbck"; + parent_data[0] =3D AT91_CLK_PD_NAME(slow_clk_name, slow_clk_index); + parent_data[1] =3D AT91_CLK_PD_HW(at91sam9260_pmc->chws[PMC_MAIN]); + parent_data[2] =3D AT91_CLK_PD_HW(at91sam9260_pmc->chws[PMC_PLLACK]); + parent_data[3] =3D AT91_CLK_PD_HW(at91sam9260_pmc->chws[PMC_PLLACK]); hw =3D at91_clk_register_master_pres(regmap, "masterck_pres", 4, - parent_names, NULL, + NULL, parent_data, &at91rm9200_master_layout, data->mck_characteristics, &at91sam9260_mck_lock); @@ -424,7 +412,7 @@ static void __init at91sam926x_pmc_setup(struct device_= node *np, goto err_free; =20 hw =3D at91_clk_register_master_div(regmap, "masterck_div", - "masterck_pres", NULL, + NULL, &AT91_CLK_PD_HW(hw), &at91rm9200_master_layout, data->mck_characteristics, &at91sam9260_mck_lock, @@ -434,21 +422,23 @@ static void __init at91sam926x_pmc_setup(struct devic= e_node *np, =20 at91sam9260_pmc->chws[PMC_MCK] =3D hw; =20 - hw =3D at91rm9200_clk_register_usb(regmap, "usbck", "pllbck", NULL, usb_d= iv); - if (IS_ERR(hw)) + usbck_hw =3D at91rm9200_clk_register_usb(regmap, "usbck", NULL, + &AT91_CLK_PD_HW(at91sam9260_pmc->chws[PMC_PLLBCK]), + usb_div); + if (IS_ERR(usbck_hw)) goto err_free; =20 - parent_names[0] =3D slck_name; - parent_names[1] =3D "mainck"; - parent_names[2] =3D "pllack"; - parent_names[3] =3D "pllbck"; + parent_data[0] =3D AT91_CLK_PD_NAME(slow_clk_name, slow_clk_index); + parent_data[1] =3D AT91_CLK_PD_HW(at91sam9260_pmc->chws[PMC_MAIN]); + parent_data[2] =3D AT91_CLK_PD_HW(at91sam9260_pmc->chws[PMC_PLLACK]); + parent_data[3] =3D AT91_CLK_PD_HW(at91sam9260_pmc->chws[PMC_PLLBCK]); for (i =3D 0; i < data->num_progck; i++) { char name[6]; =20 snprintf(name, sizeof(name), "prog%d", i); =20 hw =3D at91_clk_register_programmable(regmap, name, - parent_names, NULL, 4, i, + NULL, parent_data, 4, i, &at91rm9200_programmable_layout, NULL); if (IS_ERR(hw)) @@ -457,9 +447,22 @@ static void __init at91sam926x_pmc_setup(struct device= _node *np, at91sam9260_pmc->pchws[i] =3D hw; } =20 + /* Set systemck parent hws. */ + data->sck[0].parent_hw =3D usbck_hw; + data->sck[1].parent_hw =3D usbck_hw; + data->sck[2].parent_hw =3D at91sam9260_pmc->pchws[0]; + data->sck[3].parent_hw =3D at91sam9260_pmc->pchws[1]; + if (data->num_sck =3D=3D 6) { + data->sck[4].parent_hw =3D at91sam9260_pmc->pchws[2]; + data->sck[5].parent_hw =3D at91sam9260_pmc->pchws[3]; + } + if (data->num_sck =3D=3D 8) { + data->sck[6].parent_hw =3D at91sam9260_pmc->chws[PMC_MCK]; + data->sck[7].parent_hw =3D at91sam9260_pmc->chws[PMC_MCK]; + } for (i =3D 0; i < data->num_sck; i++) { - hw =3D at91_clk_register_system(regmap, data->sck[i].n, - data->sck[i].p, NULL, + hw =3D at91_clk_register_system(regmap, data->sck[i].n, NULL, + &AT91_CLK_PD_HW(data->sck[i].parent_hw), data->sck[i].id, 0); if (IS_ERR(hw)) goto err_free; @@ -470,7 +473,8 @@ static void __init at91sam926x_pmc_setup(struct device_= node *np, for (i =3D 0; i < data->num_pck; i++) { hw =3D at91_clk_register_peripheral(regmap, data->pck[i].n, - "masterck_div", NULL, + NULL, + &AT91_CLK_PD_HW(at91sam9260_pmc->chws[PMC_MCK]), data->pck[i].id); if (IS_ERR(hw)) goto err_free; --=20 2.43.0 From nobody Wed Oct 8 20:52:50 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4023F30206F; Tue, 24 Jun 2025 15:09:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777768; cv=none; b=J44Mpaafn6d55n6pO/PczP12wv7cKahgnsJQ2bLN6SfpYvAelrE44+s2LOsfeZXiyvUVq0+8lLZljIUuC9zotz3PHs+18upLzmaIrM3P8Er4UCmOgLu8dC9MNhfL08BW9bAMxZHaUsKlvhaLnh1KjBnsPBmXHEKJlil+9QkwaYA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777768; c=relaxed/simple; bh=JWotn6zOQ5IW0wDa+ISJNrl2eUUzRYVOewzqf7oerG0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=hhaCZOq3SA7dSkrNFG1ONzLsgMUsy0nfzH5ffev4ax+WQWsXgRC8nbm7lAjEesVc9is0oCvZIlygDkQNbPqWuha/egfyIwIbK/baNVWxlaSwmoqBj9IpgY99GhD/8LB5ow0Hs9kGOvJnUn/nRckF6SEKxLYLU6LZQXTs7s6/fbk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=Gigfw06I; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="Gigfw06I" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1750777766; x=1782313766; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=JWotn6zOQ5IW0wDa+ISJNrl2eUUzRYVOewzqf7oerG0=; b=Gigfw06IuWHuFPXiv9tMGf5GJ0RXw+nthTe5mZEKBvfLwz9YgWfq5I3h NIp0ojUd899ROxwlRVUFB9gUBk9n6652UIL6elH0W5yBSmHd08xPB55Sz Jin+rMKPr9PVoQKOhPSotpfYP5uwbvKPDGjIVcp1bSAz5g+hoKUwQ+c1q nSL8USlRJVGs5AkYb7ERzUuflseQ+IADngloKq15CFrmmGm3ILJ5R+NHD +YgxR/Ef8TeJt9Qh0DulptpoIqmAqFpXOwDcRsFPVuT/yE6axkY/EJSin snuwftmdCzrfuSHeV/tC25l6abQGeRNJegoBJMr7nk8zIK5mOt05PF1ln A==; X-CSE-ConnectionGUID: ticneE1VRpCt6c5L3blMOw== X-CSE-MsgGUID: jq4Jq8oeRVyyAiCfQ1wnSg== X-IronPort-AV: E=Sophos;i="6.16,262,1744095600"; d="scan'208";a="210641598" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 24 Jun 2025 08:09:20 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Tue, 24 Jun 2025 08:08:40 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Tue, 24 Jun 2025 08:08:40 -0700 From: To: , , , , CC: , , , , Subject: [PATCH v2 27/32] clk: at91: at91sam9g45: switch to parent_hw and parent_data Date: Tue, 24 Jun 2025 08:08:24 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Switch AT91SAM9G45 clocks to use parent_hw and parent_data. Having parent_hw instead of parent names improves to clock registration speed and re-parenting. Signed-off-by: Claudiu Beznea Signed-off-by: Ryan Wanner --- drivers/clk/at91/at91sam9g45.c | 89 +++++++++++++++++----------------- 1 file changed, 44 insertions(+), 45 deletions(-) diff --git a/drivers/clk/at91/at91sam9g45.c b/drivers/clk/at91/at91sam9g45.c index 684d2bcb36e8..54cc4e1bbdc3 100644 --- a/drivers/clk/at91/at91sam9g45.c +++ b/drivers/clk/at91/at91sam9g45.c @@ -37,9 +37,9 @@ static const struct clk_pll_characteristics plla_characte= ristics =3D { .out =3D plla_out, }; =20 -static const struct { +static struct { char *n; - char *p; + struct clk_hw *parent_hw; unsigned long flags; u8 id; } at91sam9g45_systemck[] =3D { @@ -47,10 +47,10 @@ static const struct { * ddrck feeds DDR controller and is enabled by bootloader thus we need * to keep it enabled in case there is no Linux consumer for it. */ - { .n =3D "ddrck", .p =3D "masterck_div", .id =3D 2, .flags =3D CLK_IS_CRI= TICAL }, - { .n =3D "uhpck", .p =3D "usbck", .id =3D 6 }, - { .n =3D "pck0", .p =3D "prog0", .id =3D 8 }, - { .n =3D "pck1", .p =3D "prog1", .id =3D 9 }, + { .n =3D "ddrck", .id =3D 2, .flags =3D CLK_IS_CRITICAL }, + { .n =3D "uhpck", .id =3D 6 }, + { .n =3D "pck0", .id =3D 8 }, + { .n =3D "pck1", .id =3D 9 }, }; =20 struct pck { @@ -92,24 +92,14 @@ static const struct pck at91sam9g45_periphck[] =3D { =20 static void __init at91sam9g45_pmc_setup(struct device_node *np) { - const char *slck_name, *mainxtal_name; + const char *slow_clk_name =3D "slowck", *main_xtal_name =3D "main_xtal"; + u8 slow_clk_index =3D 0, main_xtal_index =3D 1; + struct clk_parent_data parent_data[5]; struct pmc_data *at91sam9g45_pmc; - const char *parent_names[6]; + struct clk_hw *usbck_hw, *hw; struct regmap *regmap; - struct clk_hw *hw; - int i; bool bypass; - - i =3D of_property_match_string(np, "clock-names", "slow_clk"); - if (i < 0) - return; - - slck_name =3D of_clk_get_parent_name(np, i); - - i =3D of_property_match_string(np, "clock-names", "main_xtal"); - if (i < 0) - return; - mainxtal_name =3D of_clk_get_parent_name(np, i); + int i; =20 regmap =3D device_node_to_regmap(np); if (IS_ERR(regmap)) @@ -123,40 +113,43 @@ static void __init at91sam9g45_pmc_setup(struct devic= e_node *np) =20 bypass =3D of_property_read_bool(np, "atmel,osc-bypass"); =20 - hw =3D at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL, + hw =3D at91_clk_register_main_osc(regmap, "main_osc", NULL, + &AT91_CLK_PD_NAME(main_xtal_name, main_xtal_index), bypass); if (IS_ERR(hw)) goto err_free; =20 - hw =3D at91_clk_register_rm9200_main(regmap, "mainck", "main_osc", NULL); + hw =3D at91_clk_register_rm9200_main(regmap, "mainck", NULL, &AT91_CLK_PD= _HW(hw)); if (IS_ERR(hw)) goto err_free; =20 at91sam9g45_pmc->chws[PMC_MAIN] =3D hw; =20 - hw =3D at91_clk_register_pll(regmap, "pllack", "mainck", 0, + hw =3D at91_clk_register_pll(regmap, "pllack", NULL, + &AT91_CLK_PD_HW(at91sam9g45_pmc->chws[PMC_MAIN]), 0, &at91rm9200_pll_layout, &plla_characteristics); if (IS_ERR(hw)) goto err_free; =20 - hw =3D at91_clk_register_plldiv(regmap, "plladivck", "pllack"); + hw =3D at91_clk_register_plldiv(regmap, "plladivck", NULL, &AT91_CLK_PD_H= W(hw)); if (IS_ERR(hw)) goto err_free; =20 at91sam9g45_pmc->chws[PMC_PLLACK] =3D hw; =20 - hw =3D at91_clk_register_utmi(regmap, NULL, "utmick", "mainck", NULL); + hw =3D at91_clk_register_utmi(regmap, NULL, "utmick", NULL, + &AT91_CLK_PD_HW(at91sam9g45_pmc->chws[PMC_MAIN])); if (IS_ERR(hw)) goto err_free; =20 at91sam9g45_pmc->chws[PMC_UTMI] =3D hw; =20 - parent_names[0] =3D slck_name; - parent_names[1] =3D "mainck"; - parent_names[2] =3D "plladivck"; - parent_names[3] =3D "utmick"; + parent_data[0] =3D AT91_CLK_PD_NAME(slow_clk_name, slow_clk_index); + parent_data[1] =3D AT91_CLK_PD_HW(at91sam9g45_pmc->chws[PMC_MAIN]); + parent_data[2] =3D AT91_CLK_PD_HW(at91sam9g45_pmc->chws[PMC_PLLACK]); + parent_data[3] =3D AT91_CLK_PD_HW(at91sam9g45_pmc->chws[PMC_UTMI]); hw =3D at91_clk_register_master_pres(regmap, "masterck_pres", 4, - parent_names, NULL, + NULL, parent_data, &at91rm9200_master_layout, &mck_characteristics, &at91sam9g45_mck_lock); @@ -164,7 +157,7 @@ static void __init at91sam9g45_pmc_setup(struct device_= node *np) goto err_free; =20 hw =3D at91_clk_register_master_div(regmap, "masterck_div", - "masterck_pres", NULL, + NULL, &AT91_CLK_PD_HW(hw), &at91rm9200_master_layout, &mck_characteristics, &at91sam9g45_mck_lock, @@ -174,24 +167,24 @@ static void __init at91sam9g45_pmc_setup(struct devic= e_node *np) =20 at91sam9g45_pmc->chws[PMC_MCK] =3D hw; =20 - parent_names[0] =3D "plladivck"; - parent_names[1] =3D "utmick"; - hw =3D at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, NULL, 2= ); - if (IS_ERR(hw)) + parent_data[0] =3D AT91_CLK_PD_HW(at91sam9g45_pmc->chws[PMC_PLLACK]); + parent_data[1] =3D AT91_CLK_PD_HW(at91sam9g45_pmc->chws[PMC_UTMI]); + usbck_hw =3D at91sam9x5_clk_register_usb(regmap, "usbck", NULL, parent_da= ta, 2); + if (IS_ERR(usbck_hw)) goto err_free; =20 - parent_names[0] =3D slck_name; - parent_names[1] =3D "mainck"; - parent_names[2] =3D "plladivck"; - parent_names[3] =3D "utmick"; - parent_names[4] =3D "masterck_div"; + parent_data[0] =3D AT91_CLK_PD_NAME(slow_clk_name, slow_clk_index); + parent_data[1] =3D AT91_CLK_PD_HW(at91sam9g45_pmc->chws[PMC_MAIN]); + parent_data[2] =3D AT91_CLK_PD_HW(at91sam9g45_pmc->chws[PMC_PLLACK]); + parent_data[3] =3D AT91_CLK_PD_HW(at91sam9g45_pmc->chws[PMC_UTMI]); + parent_data[4] =3D AT91_CLK_PD_HW(at91sam9g45_pmc->chws[PMC_MCK]); for (i =3D 0; i < 2; i++) { char name[6]; =20 snprintf(name, sizeof(name), "prog%d", i); =20 hw =3D at91_clk_register_programmable(regmap, name, - parent_names, NULL, 5, i, + NULL, parent_data, 5, i, &at91sam9g45_programmable_layout, NULL); if (IS_ERR(hw)) @@ -200,9 +193,14 @@ static void __init at91sam9g45_pmc_setup(struct device= _node *np) at91sam9g45_pmc->pchws[i] =3D hw; } =20 + /* Set systemck parent hws. */ + at91sam9g45_systemck[0].parent_hw =3D at91sam9g45_pmc->chws[PMC_MCK]; + at91sam9g45_systemck[1].parent_hw =3D usbck_hw; + at91sam9g45_systemck[2].parent_hw =3D at91sam9g45_pmc->pchws[0]; + at91sam9g45_systemck[3].parent_hw =3D at91sam9g45_pmc->pchws[1]; for (i =3D 0; i < ARRAY_SIZE(at91sam9g45_systemck); i++) { - hw =3D at91_clk_register_system(regmap, at91sam9g45_systemck[i].n, - at91sam9g45_systemck[i].p, NULL, + hw =3D at91_clk_register_system(regmap, at91sam9g45_systemck[i].n, NULL, + &AT91_CLK_PD_HW(at91sam9g45_systemck[i].parent_hw), at91sam9g45_systemck[i].id, at91sam9g45_systemck[i].flags); if (IS_ERR(hw)) @@ -214,7 +212,8 @@ static void __init at91sam9g45_pmc_setup(struct device_= node *np) for (i =3D 0; i < ARRAY_SIZE(at91sam9g45_periphck); i++) { hw =3D at91_clk_register_peripheral(regmap, at91sam9g45_periphck[i].n, - "masterck_div", NULL, + NULL, + &AT91_CLK_PD_HW(at91sam9g45_pmc->chws[PMC_MCK]), at91sam9g45_periphck[i].id); if (IS_ERR(hw)) goto err_free; --=20 2.43.0 From nobody Wed Oct 8 20:52:50 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8B4C530207F; Tue, 24 Jun 2025 15:09:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777769; cv=none; b=Z0eITQ2R9C/rYysZe5ciMnmSHxvptFeLMnkJQEavHFxC4bnNgbzesahjUbxy32dJA9Enx5226DpqzUe+7B25krnOf1J9dCOdMk18fWLrucuFc6xKjoK2L61t/JRzYud5F+CY5I0dEDEB9qzFnIeGDtrgCrvikpWDYp293AmKCyw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777769; c=relaxed/simple; bh=WC8YPIamCKdl/fhxgb6SfKtVltL3KYPDpIB6iAksfX8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=EVDBroeUhivzfIrLU0QPtbe0Pbl4m+9+B20iINlAZW7FZXvckQUQSDa4vtU0/4uF1Onz3NmZX07JiAcIWbUhhHJdswy4u3OA6Q2Ab4ABg+JrHTeSkU29NT/Q4i67rnqPQZI86CAuY2FcQ542Pd7lOmaPJhs0xuevQ2P4wrYcBpM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=PFTmM1Ve; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="PFTmM1Ve" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1750777766; x=1782313766; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=WC8YPIamCKdl/fhxgb6SfKtVltL3KYPDpIB6iAksfX8=; b=PFTmM1Ver893rtFi3qw2AZLD0O8aBCaeWBOf9Eq7gYedf0i/nc6VQDA1 9tEuq9uLYUU6OM7Ltg+8YFmZMqIfovAEAsh7dPZQmar27jzLnzdTUBpcC laEAITHkkBRpe7ITMgSWufW2Dwh7dCIirAv/Dkx7BIicSRtvyunaDQCky TLPFr4Z1KxkMCobgiCt1FxQE3NNGVwcDDMbbJUg8H9Gbeo3PTkUo7pwN8 5sdu8x8+Z2RZCEzb+JI99xUH0YdBz3kjEI/BsT/pCOXViM6gOx7wfrbNn JqOBDgP+nDEZfdluWBVvVROluDf2YFfp+tPRcYUAtQ68Ifzlufuc5ugiX g==; X-CSE-ConnectionGUID: ticneE1VRpCt6c5L3blMOw== X-CSE-MsgGUID: RF3kVCOAQmCGowdZSpu2uw== X-IronPort-AV: E=Sophos;i="6.16,262,1744095600"; d="scan'208";a="210641599" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 24 Jun 2025 08:09:20 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Tue, 24 Jun 2025 08:08:40 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Tue, 24 Jun 2025 08:08:40 -0700 From: To: , , , , CC: , , , , Subject: [PATCH v2 28/32] clk: at91: at91sam9n12: switch to parent_hw and parent_data Date: Tue, 24 Jun 2025 08:08:25 -0700 Message-ID: <7997f9a84b3dab39023326c8dece968818bf51c6.1750182562.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Switch AT91SAM9N12 clocks to use parent_hw and parent_data. Having parent_hw instead of parent names improves to clock registration speed and re-parenting. Signed-off-by: Claudiu Beznea Signed-off-by: Ryan Wanner --- drivers/clk/at91/at91sam9n12.c | 106 +++++++++++++++++---------------- 1 file changed, 54 insertions(+), 52 deletions(-) diff --git a/drivers/clk/at91/at91sam9n12.c b/drivers/clk/at91/at91sam9n12.c index 9fc20b177b13..88950003a58e 100644 --- a/drivers/clk/at91/at91sam9n12.c +++ b/drivers/clk/at91/at91sam9n12.c @@ -51,9 +51,9 @@ static const struct clk_pll_characteristics pllb_characte= ristics =3D { .out =3D pllb_out, }; =20 -static const struct { +static struct { char *n; - char *p; + struct clk_hw *parent_hw; unsigned long flags; u8 id; } at91sam9n12_systemck[] =3D { @@ -61,12 +61,12 @@ static const struct { * ddrck feeds DDR controller and is enabled by bootloader thus we need * to keep it enabled in case there is no Linux consumer for it. */ - { .n =3D "ddrck", .p =3D "masterck_div", .id =3D 2, .flags =3D CLK_IS_CRI= TICAL }, - { .n =3D "lcdck", .p =3D "masterck_div", .id =3D 3 }, - { .n =3D "uhpck", .p =3D "usbck", .id =3D 6 }, - { .n =3D "udpck", .p =3D "usbck", .id =3D 7 }, - { .n =3D "pck0", .p =3D "prog0", .id =3D 8 }, - { .n =3D "pck1", .p =3D "prog1", .id =3D 9 }, + { .n =3D "ddrck", .id =3D 2, .flags =3D CLK_IS_CRITICAL }, + { .n =3D "lcdck", .id =3D 3 }, + { .n =3D "uhpck", .id =3D 6 }, + { .n =3D "udpck", .id =3D 7 }, + { .n =3D "pck0", .id =3D 8 }, + { .n =3D "pck1", .id =3D 9 }, }; =20 static const struct clk_pcr_layout at91sam9n12_pcr_layout =3D { @@ -111,25 +111,15 @@ static const struct pck at91sam9n12_periphck[] =3D { =20 static void __init at91sam9n12_pmc_setup(struct device_node *np) { + const char *slow_clk_name =3D "slowck", *main_xtal_name =3D "main_xtal"; + struct clk_hw *usbck_hw, *hw, *main_rc_hw, *main_osc_hw; + u8 slow_clk_index =3D 0, main_xtal_index =3D 1; struct clk_range range =3D CLK_RANGE(0, 0); - const char *slck_name, *mainxtal_name; + struct clk_parent_data parent_data[5]; struct pmc_data *at91sam9n12_pmc; - const char *parent_names[6]; struct regmap *regmap; - struct clk_hw *hw; - int i; bool bypass; - - i =3D of_property_match_string(np, "clock-names", "slow_clk"); - if (i < 0) - return; - - slck_name =3D of_clk_get_parent_name(np, i); - - i =3D of_property_match_string(np, "clock-names", "main_xtal"); - if (i < 0) - return; - mainxtal_name =3D of_clk_get_parent_name(np, i); + int i; =20 regmap =3D device_node_to_regmap(np); if (IS_ERR(regmap)) @@ -140,50 +130,53 @@ static void __init at91sam9n12_pmc_setup(struct devic= e_node *np) if (!at91sam9n12_pmc) return; =20 - hw =3D at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000, - 50000000); - if (IS_ERR(hw)) + main_rc_hw =3D at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000= 000, + 50000000); + if (IS_ERR(main_rc_hw)) goto err_free; =20 bypass =3D of_property_read_bool(np, "atmel,osc-bypass"); =20 - hw =3D at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL, - bypass); - if (IS_ERR(hw)) + main_osc_hw =3D at91_clk_register_main_osc(regmap, "main_osc", NULL, + &AT91_CLK_PD_NAME(main_xtal_name, main_xtal_index), + bypass); + if (IS_ERR(main_osc_hw)) goto err_free; =20 - parent_names[0] =3D "main_rc_osc"; - parent_names[1] =3D "main_osc"; - hw =3D at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL= , 2); + parent_data[0] =3D AT91_CLK_PD_HW(main_rc_hw); + parent_data[1] =3D AT91_CLK_PD_HW(main_osc_hw); + hw =3D at91_clk_register_sam9x5_main(regmap, "mainck", NULL, parent_data,= 2); if (IS_ERR(hw)) goto err_free; =20 at91sam9n12_pmc->chws[PMC_MAIN] =3D hw; =20 - hw =3D at91_clk_register_pll(regmap, "pllack", "mainck", 0, + hw =3D at91_clk_register_pll(regmap, "pllack", NULL, + &AT91_CLK_PD_HW(at91sam9n12_pmc->chws[PMC_MAIN]), 0, &at91rm9200_pll_layout, &plla_characteristics); if (IS_ERR(hw)) goto err_free; =20 - hw =3D at91_clk_register_plldiv(regmap, "plladivck", "pllack"); + hw =3D at91_clk_register_plldiv(regmap, "plladivck", NULL, &AT91_CLK_PD_H= W(hw)); if (IS_ERR(hw)) goto err_free; =20 at91sam9n12_pmc->chws[PMC_PLLACK] =3D hw; =20 - hw =3D at91_clk_register_pll(regmap, "pllbck", "mainck", 1, + hw =3D at91_clk_register_pll(regmap, "pllbck", NULL, + &AT91_CLK_PD_HW(at91sam9n12_pmc->chws[PMC_MAIN]), 1, &at91rm9200_pll_layout, &pllb_characteristics); if (IS_ERR(hw)) goto err_free; =20 at91sam9n12_pmc->chws[PMC_PLLBCK] =3D hw; =20 - parent_names[0] =3D slck_name; - parent_names[1] =3D "mainck"; - parent_names[2] =3D "plladivck"; - parent_names[3] =3D "pllbck"; + parent_data[0] =3D AT91_CLK_PD_NAME(slow_clk_name, slow_clk_index); + parent_data[1] =3D AT91_CLK_PD_HW(at91sam9n12_pmc->chws[PMC_MAIN]); + parent_data[2] =3D AT91_CLK_PD_HW(at91sam9n12_pmc->chws[PMC_PLLACK]); + parent_data[3] =3D AT91_CLK_PD_HW(at91sam9n12_pmc->chws[PMC_PLLBCK]); hw =3D at91_clk_register_master_pres(regmap, "masterck_pres", 4, - parent_names, NULL, + NULL, parent_data, &at91sam9x5_master_layout, &mck_characteristics, &at91sam9n12_mck_lock); @@ -191,7 +184,7 @@ static void __init at91sam9n12_pmc_setup(struct device_= node *np) goto err_free; =20 hw =3D at91_clk_register_master_div(regmap, "masterck_div", - "masterck_pres", NULL, + NULL, &AT91_CLK_PD_HW(hw), &at91sam9x5_master_layout, &mck_characteristics, &at91sam9n12_mck_lock, @@ -201,22 +194,23 @@ static void __init at91sam9n12_pmc_setup(struct devic= e_node *np) =20 at91sam9n12_pmc->chws[PMC_MCK] =3D hw; =20 - hw =3D at91sam9n12_clk_register_usb(regmap, "usbck", "pllbck", NULL); - if (IS_ERR(hw)) + usbck_hw =3D at91sam9n12_clk_register_usb(regmap, "usbck", NULL, + &AT91_CLK_PD_HW(at91sam9n12_pmc->chws[PMC_PLLBCK])); + if (IS_ERR(usbck_hw)) goto err_free; =20 - parent_names[0] =3D slck_name; - parent_names[1] =3D "mainck"; - parent_names[2] =3D "plladivck"; - parent_names[3] =3D "pllbck"; - parent_names[4] =3D "masterck_div"; + parent_data[0] =3D AT91_CLK_PD_NAME(slow_clk_name, slow_clk_index); + parent_data[1] =3D AT91_CLK_PD_HW(at91sam9n12_pmc->chws[PMC_MAIN]); + parent_data[2] =3D AT91_CLK_PD_HW(at91sam9n12_pmc->chws[PMC_PLLACK]); + parent_data[3] =3D AT91_CLK_PD_HW(at91sam9n12_pmc->chws[PMC_PLLBCK]); + parent_data[4] =3D AT91_CLK_PD_HW(at91sam9n12_pmc->chws[PMC_MCK]); for (i =3D 0; i < 2; i++) { char name[6]; =20 snprintf(name, sizeof(name), "prog%d", i); =20 hw =3D at91_clk_register_programmable(regmap, name, - parent_names, NULL, 5, i, + NULL, parent_data, 5, i, &at91sam9x5_programmable_layout, NULL); if (IS_ERR(hw)) @@ -225,9 +219,16 @@ static void __init at91sam9n12_pmc_setup(struct device= _node *np) at91sam9n12_pmc->pchws[i] =3D hw; } =20 + /* Set systemck parent hws. */ + at91sam9n12_systemck[0].parent_hw =3D at91sam9n12_pmc->chws[PMC_MCK]; + at91sam9n12_systemck[1].parent_hw =3D at91sam9n12_pmc->chws[PMC_MCK]; + at91sam9n12_systemck[2].parent_hw =3D usbck_hw; + at91sam9n12_systemck[3].parent_hw =3D usbck_hw; + at91sam9n12_systemck[4].parent_hw =3D at91sam9n12_pmc->pchws[0]; + at91sam9n12_systemck[5].parent_hw =3D at91sam9n12_pmc->pchws[1]; for (i =3D 0; i < ARRAY_SIZE(at91sam9n12_systemck); i++) { - hw =3D at91_clk_register_system(regmap, at91sam9n12_systemck[i].n, - at91sam9n12_systemck[i].p, NULL, + hw =3D at91_clk_register_system(regmap, at91sam9n12_systemck[i].n, NULL, + &AT91_CLK_PD_HW(at91sam9n12_systemck[i].parent_hw), at91sam9n12_systemck[i].id, at91sam9n12_systemck[i].flags); if (IS_ERR(hw)) @@ -240,7 +241,8 @@ static void __init at91sam9n12_pmc_setup(struct device_= node *np) hw =3D at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, &at91sam9n12_pcr_layout, at91sam9n12_periphck[i].n, - "masterck_div", NULL, + NULL, + &AT91_CLK_PD_HW(at91sam9n12_pmc->chws[PMC_MCK]), at91sam9n12_periphck[i].id, &range, INT_MIN, 0); if (IS_ERR(hw)) --=20 2.43.0 From nobody Wed Oct 8 20:52:50 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 30BE4302CB3; Tue, 24 Jun 2025 15:09:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777769; cv=none; b=g7vC9F9VO2/t9L2z8GWvB7urqWiHxhds8eQjW5EfkRg5LZeI94Yq1Om4bbspYaAd9yZ72Odf3V+C5KGXXIRIQFuX3tHDt6kRdXLxrHjMg99qq9eyEfx4eLzjGrQn/vATTHZnKpNTjsNF2GFn0pLEWCwyBWBYdXUl5X4XhaWv/ro= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777769; c=relaxed/simple; bh=j4U0G9PmAbm5SXv2TgKAMjj1kvsuGzzoXlg5TgpL514=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=S3taxC+btHtTVc/slxB5WS3t4aQWU9qQhpyiz623vqE5Dax1lJd21e9tSmux2KbfnaV/k+0ezPEeG5dn3qiCJCRgMHww6oIDTUfM+dvA/DE1eRIcjb22W5cWhgtqiM7v2rcwZyzPPkYvVb3X2ta2uFTvyad0VdWpJvWMVo6OIGI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=b4Xlt9bh; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="b4Xlt9bh" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1750777767; x=1782313767; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=j4U0G9PmAbm5SXv2TgKAMjj1kvsuGzzoXlg5TgpL514=; b=b4Xlt9bhrcp4rd74AubAz+3f9oJ0izvQ/xIFiln5KL3d9wQyv+8oN8uF rIV+TVdo+SJnGTbpAvyKfD6Rn8UOrfqnZefdjoc4oOfaSA6doWiCRD5O+ vON7sLSvKpPjQWhhOtJL3Uul3Od0HRLgcVE5zs44/ubju83Q4yUPPQDBr 65CBtLP9T3vi4z8FmJMWF8s6ubg7gKizedU6Z8O4HsISAHTTuhFDsav/c mokQ4xb4RFO62BoCUkVBE+lVFMKa5Q4QllXS78EE66Fa8J/6R27LfkLyw 6XDL4vF6Fq+MrzMv/Zy4NJ6KnUVtvxEuEWMv7wXWfqkpwbMAjYLbkvlTt Q==; X-CSE-ConnectionGUID: ticneE1VRpCt6c5L3blMOw== X-CSE-MsgGUID: 45hWAS1ySROWMxp9r7X/gA== X-IronPort-AV: E=Sophos;i="6.16,262,1744095600"; d="scan'208";a="210641600" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 24 Jun 2025 08:09:21 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Tue, 24 Jun 2025 08:08:40 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Tue, 24 Jun 2025 08:08:40 -0700 From: To: , , , , CC: , , , , Subject: [PATCH v2 29/32] clk: at91: at91sam9rl: switch to clk_parent_data Date: Tue, 24 Jun 2025 08:08:26 -0700 Message-ID: <330369706e18903b56fbc69926013557802439d0.1750182562.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Switch AT91SAM9RL clocks to use parent_hw and parent_data. Having parent_hw instead of parent names improves to clock registration speed and re-parenting. Signed-off-by: Claudiu Beznea Signed-off-by: Ryan Wanner --- drivers/clk/at91/at91sam9rl.c | 63 ++++++++++++++++------------------- 1 file changed, 28 insertions(+), 35 deletions(-) diff --git a/drivers/clk/at91/at91sam9rl.c b/drivers/clk/at91/at91sam9rl.c index 969f809e7d65..5b342b707213 100644 --- a/drivers/clk/at91/at91sam9rl.c +++ b/drivers/clk/at91/at91sam9rl.c @@ -28,13 +28,12 @@ static const struct clk_pll_characteristics sam9rl_plla= _characteristics =3D { .out =3D sam9rl_plla_out, }; =20 -static const struct { +static struct { char *n; - char *p; u8 id; } at91sam9rl_systemck[] =3D { - { .n =3D "pck0", .p =3D "prog0", .id =3D 8 }, - { .n =3D "pck1", .p =3D "prog1", .id =3D 9 }, + { .n =3D "pck0", .id =3D 8 }, + { .n =3D "pck1", .id =3D 9 }, }; =20 static const struct { @@ -67,24 +66,14 @@ static const struct { =20 static void __init at91sam9rl_pmc_setup(struct device_node *np) { - const char *slck_name, *mainxtal_name; + const char *slow_clk_name =3D "slowck", *main_xtal_name =3D "main_xtal"; + u8 slow_clk_index =3D 0, main_xtal_index =3D 1; + struct clk_parent_data parent_data[6]; struct pmc_data *at91sam9rl_pmc; - const char *parent_names[6]; struct regmap *regmap; struct clk_hw *hw; int i; =20 - i =3D of_property_match_string(np, "clock-names", "slow_clk"); - if (i < 0) - return; - - slck_name =3D of_clk_get_parent_name(np, i); - - i =3D of_property_match_string(np, "clock-names", "main_xtal"); - if (i < 0) - return; - mainxtal_name =3D of_clk_get_parent_name(np, i); - regmap =3D device_node_to_regmap(np); if (IS_ERR(regmap)) return; @@ -95,13 +84,15 @@ static void __init at91sam9rl_pmc_setup(struct device_n= ode *np) if (!at91sam9rl_pmc) return; =20 - hw =3D at91_clk_register_rm9200_main(regmap, "mainck", mainxtal_name, NUL= L); + hw =3D at91_clk_register_rm9200_main(regmap, "mainck", NULL, + &AT91_CLK_PD_NAME(main_xtal_name, main_xtal_index)); if (IS_ERR(hw)) goto err_free; =20 at91sam9rl_pmc->chws[PMC_MAIN] =3D hw; =20 - hw =3D at91_clk_register_pll(regmap, "pllack", "mainck", 0, + hw =3D at91_clk_register_pll(regmap, "pllack", NULL, + &AT91_CLK_PD_HW(at91sam9rl_pmc->chws[PMC_MAIN]), 0, &at91rm9200_pll_layout, &sam9rl_plla_characteristics); if (IS_ERR(hw)) @@ -109,18 +100,19 @@ static void __init at91sam9rl_pmc_setup(struct device= _node *np) =20 at91sam9rl_pmc->chws[PMC_PLLACK] =3D hw; =20 - hw =3D at91_clk_register_utmi(regmap, NULL, "utmick", "mainck", NULL); + hw =3D at91_clk_register_utmi(regmap, NULL, "utmick", NULL, + &AT91_CLK_PD_HW(at91sam9rl_pmc->chws[PMC_MAIN])); if (IS_ERR(hw)) goto err_free; =20 at91sam9rl_pmc->chws[PMC_UTMI] =3D hw; =20 - parent_names[0] =3D slck_name; - parent_names[1] =3D "mainck"; - parent_names[2] =3D "pllack"; - parent_names[3] =3D "utmick"; + parent_data[0] =3D AT91_CLK_PD_NAME(slow_clk_name, slow_clk_index); + parent_data[1] =3D AT91_CLK_PD_HW(at91sam9rl_pmc->chws[PMC_MAIN]); + parent_data[2] =3D AT91_CLK_PD_HW(at91sam9rl_pmc->chws[PMC_PLLACK]); + parent_data[3] =3D AT91_CLK_PD_HW(at91sam9rl_pmc->chws[PMC_UTMI]); hw =3D at91_clk_register_master_pres(regmap, "masterck_pres", 4, - parent_names, NULL, + NULL, parent_data, &at91rm9200_master_layout, &sam9rl_mck_characteristics, &sam9rl_mck_lock); @@ -128,7 +120,7 @@ static void __init at91sam9rl_pmc_setup(struct device_n= ode *np) goto err_free; =20 hw =3D at91_clk_register_master_div(regmap, "masterck_div", - "masterck_pres", NULL, + NULL, &AT91_CLK_PD_HW(hw), &at91rm9200_master_layout, &sam9rl_mck_characteristics, &sam9rl_mck_lock, CLK_SET_RATE_GATE, 0); @@ -137,18 +129,18 @@ static void __init at91sam9rl_pmc_setup(struct device= _node *np) =20 at91sam9rl_pmc->chws[PMC_MCK] =3D hw; =20 - parent_names[0] =3D slck_name; - parent_names[1] =3D "mainck"; - parent_names[2] =3D "pllack"; - parent_names[3] =3D "utmick"; - parent_names[4] =3D "masterck_div"; + parent_data[0] =3D AT91_CLK_PD_NAME(slow_clk_name, slow_clk_index); + parent_data[1] =3D AT91_CLK_PD_HW(at91sam9rl_pmc->chws[PMC_MAIN]); + parent_data[2] =3D AT91_CLK_PD_HW(at91sam9rl_pmc->chws[PMC_PLLACK]); + parent_data[3] =3D AT91_CLK_PD_HW(at91sam9rl_pmc->chws[PMC_UTMI]); + parent_data[4] =3D AT91_CLK_PD_HW(at91sam9rl_pmc->chws[PMC_MCK]); for (i =3D 0; i < 2; i++) { char name[6]; =20 snprintf(name, sizeof(name), "prog%d", i); =20 hw =3D at91_clk_register_programmable(regmap, name, - parent_names, NULL, 5, i, + NULL, parent_data, 5, i, &at91rm9200_programmable_layout, NULL); if (IS_ERR(hw)) @@ -158,8 +150,8 @@ static void __init at91sam9rl_pmc_setup(struct device_n= ode *np) } =20 for (i =3D 0; i < ARRAY_SIZE(at91sam9rl_systemck); i++) { - hw =3D at91_clk_register_system(regmap, at91sam9rl_systemck[i].n, - at91sam9rl_systemck[i].p, NULL, + hw =3D at91_clk_register_system(regmap, at91sam9rl_systemck[i].n, NULL, + &AT91_CLK_PD_HW(at91sam9rl_pmc->pchws[0]), at91sam9rl_systemck[i].id, 0); if (IS_ERR(hw)) goto err_free; @@ -170,7 +162,8 @@ static void __init at91sam9rl_pmc_setup(struct device_n= ode *np) for (i =3D 0; i < ARRAY_SIZE(at91sam9rl_periphck); i++) { hw =3D at91_clk_register_peripheral(regmap, at91sam9rl_periphck[i].n, - "masterck_div", NULL, + NULL, + &AT91_CLK_PD_HW(at91sam9rl_pmc->chws[PMC_MCK]), at91sam9rl_periphck[i].id); if (IS_ERR(hw)) goto err_free; --=20 2.43.0 From nobody Wed Oct 8 20:52:50 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 130B7307ADC; Tue, 24 Jun 2025 15:09:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777772; cv=none; b=Wm3Q0rixxzvHpH3Gc1wFB/MIAQqrK8Xljfztx1r9X1/7etv8AO+L92yiG9qUJsRZPsm2AFXhvBC+tIQAt/QjDuCyQVYMictu3dsVxeoYpr7tBbmfm8fr3ZTTVlZlf5SqgajMoebv+AHlOS1soqvQkJxz7Yb5Frnc0GjvdruxY7s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777772; c=relaxed/simple; bh=01WDjAazIBZnlebGBhQ6OfYUO1K+0yu13s6SYyGN+Jc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=hinqPdV7h+Ca/nVso2/qRV3MvWe34aLLX66ahOjNsL4chjTAHj3oBvnoUqVDk2PKZPGLMLK36PJF8Ns/3Lk8Pq71lpQEzgpEHoJSvAGP4W0KGbm37Mml47FE5eSYIcXxGHk3RXMdS7lcxRkgEYgGBSEg2iVfgRX6q3QxQ2zFDNo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=wChyaTtd; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="wChyaTtd" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1750777768; x=1782313768; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=01WDjAazIBZnlebGBhQ6OfYUO1K+0yu13s6SYyGN+Jc=; b=wChyaTtdgS5STANoSicKPmtokx9wvCX18j2M0XvTIk79YkHfBeAoSgBR mWIPeXMqM+kGAyGzmXVy3GFr6ydTPfQFXW8qQ6mhpxNGdEwhcYzfJVbZa TJkm7ttmD9u2oQil+JwrFq0SUusmG1FR+a6FhIh0jSERarynIFpCvn0Wz sybWr83WbM6pIFQx/bFamNSU2Y3Qji9moXMUoM2tr85VOVV8C4lzfkfvk BItHJ/rqJ8LGYHrM18J+e2ByYq4te7gYp/7m7F4raIHhjItCAx0o0lrvl hvrDDDAprv0OfsmfaPhjGFbmr8O5LlKJOtyaLfaTZnMUXc8eNst8LFrxK w==; X-CSE-ConnectionGUID: ticneE1VRpCt6c5L3blMOw== X-CSE-MsgGUID: vvewy80oT5Wy/lIL5hoydg== X-IronPort-AV: E=Sophos;i="6.16,262,1744095600"; d="scan'208";a="210641601" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 24 Jun 2025 08:09:21 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Tue, 24 Jun 2025 08:08:40 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Tue, 24 Jun 2025 08:08:40 -0700 From: To: , , , , CC: , , , , , Ryan Wanner Subject: [PATCH v2 30/32] clk: at91: sam9x75: switch to parent_hw and parent_data Date: Tue, 24 Jun 2025 08:08:27 -0700 Message-ID: <5f7063f4905184ee3bf0eea48f09b79df4518b81.1750182562.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Ryan Wanner Switch SAM9X75 clocks to use modern parent_hw and parent_data. Signed-off-by: Ryan Wanner --- drivers/clk/at91/sam9x7.c | 330 +++++++++++++++++++++----------------- 1 file changed, 186 insertions(+), 144 deletions(-) diff --git a/drivers/clk/at91/sam9x7.c b/drivers/clk/at91/sam9x7.c index cbb8b220f16b..cd0d5a0884b2 100644 --- a/drivers/clk/at91/sam9x7.c +++ b/drivers/clk/at91/sam9x7.c @@ -33,10 +33,22 @@ enum pll_ids { PLL_ID_UPLL, PLL_ID_AUDIO, PLL_ID_LVDS, - PLL_ID_PLLA_DIV2, PLL_ID_MAX, }; =20 +/* + * PLL component identifier + * @PLL_COMPID_FRAC: Fractional PLL component identifier + * @PLL_COMPID_DIV0: 1st PLL divider component identifier + * @PLL_COMPID_DIV1: 2nd PLL divider component identifier + */ +enum pll_component_id { + PLL_COMPID_FRAC, + PLL_COMPID_DIV0, + PLL_COMPID_DIV1, + PLL_COMPID_MAX, +}; + /** * enum pll_type - PLL type identifiers * @PLL_TYPE_FRAC: fractional PLL identifier @@ -180,6 +192,18 @@ static const struct clk_pll_layout pll_divio_layout = =3D { .endiv_shift =3D 30, }; =20 +/* + * SAM9X7 PLL possible parents + * @SAM9X7_PLL_PARENT_MAINCK: MAINCK is PLL a parent + * @SAM9X7_PLL_PARENT_MAIN_XTAL: MAIN XTAL is a PLL parent + * @SAM9X7_PLL_PARENT_FRACCK: Frac PLL is a PLL parent (for PLL dividers) + */ +enum sam9x7_pll_parent { + SAM9X7_PLL_PARENT_MAINCK, + SAM9X7_PLL_PARENT_MAIN_XTAL, + SAM9X7_PLL_PARENT_FRACCK +}; + /* * PLL clocks description * @n: clock name @@ -187,22 +211,24 @@ static const struct clk_pll_layout pll_divio_layout = =3D { * @l: clock layout * @t: clock type * @c: pll characteristics + * @hw: pointer to clk_hw * @f: clock flags * @eid: export index in sam9x7->chws[] array */ -static const struct { +static struct { const char *n; - const char *p; const struct clk_pll_layout *l; u8 t; const struct clk_pll_characteristics *c; + struct clk_hw *hw; unsigned long f; + enum sam9x7_pll_parent p; u8 eid; -} sam9x7_plls[][3] =3D { +} sam9x7_plls[][PLL_COMPID_MAX] =3D { [PLL_ID_PLLA] =3D { - { + [PLL_COMPID_FRAC] =3D { .n =3D "plla_fracck", - .p =3D "mainck", + .p =3D SAM9X7_PLL_PARENT_MAINCK, .l =3D &plla_frac_layout, .t =3D PLL_TYPE_FRAC, /* @@ -213,9 +239,9 @@ static const struct { .c =3D &plla_characteristics, }, =20 - { + [PLL_COMPID_DIV0] =3D { .n =3D "plla_divpmcck", - .p =3D "plla_fracck", + .p =3D SAM9X7_PLL_PARENT_FRACCK, .l =3D &pll_divpmc_layout, .t =3D PLL_TYPE_DIV, /* This feeds CPU. It should not be disabled */ @@ -223,21 +249,35 @@ static const struct { .eid =3D PMC_PLLACK, .c =3D &plla_characteristics, }, + + [PLL_COMPID_DIV1] =3D { + .n =3D "plla_div2pmcck", + .p =3D SAM9X7_PLL_PARENT_FRACCK, + .l =3D &plladiv2_divpmc_layout, + /* + * This may feed critical parts of the system like timers. + * It should not be disabled. + */ + .f =3D CLK_IS_CRITICAL | CLK_SET_RATE_GATE, + .c =3D &plladiv2_characteristics, + .eid =3D PMC_PLLADIV2, + .t =3D PLL_TYPE_DIV, + }, }, =20 [PLL_ID_UPLL] =3D { - { + [PLL_COMPID_FRAC] =3D { .n =3D "upll_fracck", - .p =3D "main_osc", + .p =3D SAM9X7_PLL_PARENT_MAIN_XTAL, .l =3D &pll_frac_layout, .t =3D PLL_TYPE_FRAC, .f =3D CLK_SET_RATE_GATE, .c =3D &upll_characteristics, }, =20 - { + [PLL_COMPID_DIV0] =3D { .n =3D "upll_divpmcck", - .p =3D "upll_fracck", + .p =3D SAM9X7_PLL_PARENT_FRACCK, .l =3D &pll_divpmc_layout, .t =3D PLL_TYPE_DIV, .f =3D CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | @@ -248,18 +288,18 @@ static const struct { }, =20 [PLL_ID_AUDIO] =3D { - { + [PLL_COMPID_FRAC] =3D { .n =3D "audiopll_fracck", - .p =3D "main_osc", + .p =3D SAM9X7_PLL_PARENT_MAIN_XTAL, .l =3D &pll_frac_layout, .f =3D CLK_SET_RATE_GATE, .c =3D &audiopll_characteristics, .t =3D PLL_TYPE_FRAC, }, =20 - { + [PLL_COMPID_DIV0] =3D { .n =3D "audiopll_divpmcck", - .p =3D "audiopll_fracck", + .p =3D SAM9X7_PLL_PARENT_FRACCK, .l =3D &pll_divpmc_layout, .f =3D CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | CLK_SET_RATE_PARENT, @@ -268,9 +308,9 @@ static const struct { .t =3D PLL_TYPE_DIV, }, =20 - { + [PLL_COMPID_DIV1] =3D { .n =3D "audiopll_diviock", - .p =3D "audiopll_fracck", + .p =3D SAM9X7_PLL_PARENT_FRACCK, .l =3D &pll_divio_layout, .f =3D CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | CLK_SET_RATE_PARENT, @@ -281,18 +321,18 @@ static const struct { }, =20 [PLL_ID_LVDS] =3D { - { + [PLL_COMPID_FRAC] =3D { .n =3D "lvdspll_fracck", - .p =3D "main_osc", + .p =3D SAM9X7_PLL_PARENT_MAIN_XTAL, .l =3D &pll_frac_layout, .f =3D CLK_SET_RATE_GATE, .c =3D &lvdspll_characteristics, .t =3D PLL_TYPE_FRAC, }, =20 - { + [PLL_COMPID_DIV0] =3D { .n =3D "lvdspll_divpmcck", - .p =3D "lvdspll_fracck", + .p =3D SAM9X7_PLL_PARENT_FRACCK, .l =3D &pll_divpmc_layout, .f =3D CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | CLK_SET_RATE_PARENT, @@ -301,22 +341,6 @@ static const struct { .t =3D PLL_TYPE_DIV, }, }, - - [PLL_ID_PLLA_DIV2] =3D { - { - .n =3D "plla_div2pmcck", - .p =3D "plla_fracck", - .l =3D &plladiv2_divpmc_layout, - /* - * This may feed critical parts of the system like timers. - * It should not be disabled. - */ - .f =3D CLK_IS_CRITICAL | CLK_SET_RATE_GATE, - .c =3D &plladiv2_characteristics, - .eid =3D PMC_PLLADIV2, - .t =3D PLL_TYPE_DIV, - }, - }, }; =20 static const struct clk_programmable_layout sam9x7_programmable_layout =3D= { @@ -334,9 +358,9 @@ static const struct clk_pcr_layout sam9x7_pcr_layout = =3D { .pid_mask =3D GENMASK(6, 0), }; =20 -static const struct { +static struct { char *n; - char *p; + struct clk_hw *parent_hw; u8 id; unsigned long flags; } sam9x7_systemck[] =3D { @@ -344,10 +368,10 @@ static const struct { * ddrck feeds DDR controller and is enabled by bootloader thus we need * to keep it enabled in case there is no Linux consumer for it. */ - { .n =3D "ddrck", .p =3D "masterck_div", .id =3D 2, .flags =3D CLK_IS_CR= ITICAL }, - { .n =3D "uhpck", .p =3D "usbck", .id =3D 6 }, - { .n =3D "pck0", .p =3D "prog0", .id =3D 8 }, - { .n =3D "pck1", .p =3D "prog1", .id =3D 9 }, + { .n =3D "ddrck", .id =3D 2, .flags =3D CLK_IS_CRITICAL }, + { .n =3D "uhpck", .id =3D 6 }, + { .n =3D "pck0", .id =3D 8 }, + { .n =3D "pck1", .id =3D 9 }, }; =20 /* @@ -420,16 +444,21 @@ static const struct { /* * Generic clock description * @n: clock name - * @pp: PLL parents + * @pp: PLL parents (entry formed by PLL components identifiers + * (see enum pll_component_id)) * @pp_mux_table: PLL parents mux table * @r: clock output range * @pp_chg_id: id in parent array of changeable PLL parent * @pp_count: PLL parents count * @id: clock id */ + static const struct { const char *n; - const char *pp[8]; + struct { + int pll_id; + int pll_compid; + } pp[8]; const char pp_mux_table[8]; struct clk_range r; int pp_chg_id; @@ -439,7 +468,7 @@ static const struct { { .n =3D "flex0_gclk", .id =3D 5, - .pp =3D { "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table =3D { 8, }, .pp_count =3D 1, .pp_chg_id =3D INT_MIN, @@ -448,7 +477,7 @@ static const struct { { .n =3D "flex1_gclk", .id =3D 6, - .pp =3D { "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table =3D { 8, }, .pp_count =3D 1, .pp_chg_id =3D INT_MIN, @@ -457,7 +486,7 @@ static const struct { { .n =3D "flex2_gclk", .id =3D 7, - .pp =3D { "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table =3D { 8, }, .pp_count =3D 1, .pp_chg_id =3D INT_MIN, @@ -466,7 +495,7 @@ static const struct { { .n =3D "flex3_gclk", .id =3D 8, - .pp =3D { "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table =3D { 8, }, .pp_count =3D 1, .pp_chg_id =3D INT_MIN, @@ -475,7 +504,7 @@ static const struct { { .n =3D "flex6_gclk", .id =3D 9, - .pp =3D { "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table =3D { 8, }, .pp_count =3D 1, .pp_chg_id =3D INT_MIN, @@ -484,7 +513,7 @@ static const struct { { .n =3D "flex7_gclk", .id =3D 10, - .pp =3D { "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table =3D { 8, }, .pp_count =3D 1, .pp_chg_id =3D INT_MIN, @@ -493,7 +522,7 @@ static const struct { { .n =3D "flex8_gclk", .id =3D 11, - .pp =3D { "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table =3D { 8, }, .pp_count =3D 1, .pp_chg_id =3D INT_MIN, @@ -503,7 +532,7 @@ static const struct { .n =3D "sdmmc0_gclk", .id =3D 12, .r =3D { .max =3D 105000000 }, - .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), PLL_IDS_TO_ARR_ENTRY(PLLA, = DIV1), }, .pp_mux_table =3D { 6, 8, }, .pp_count =3D 2, .pp_chg_id =3D INT_MIN, @@ -512,7 +541,7 @@ static const struct { { .n =3D "flex4_gclk", .id =3D 13, - .pp =3D { "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table =3D { 8, }, .pp_count =3D 1, .pp_chg_id =3D INT_MIN, @@ -521,7 +550,7 @@ static const struct { { .n =3D "flex5_gclk", .id =3D 14, - .pp =3D { "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table =3D { 8, }, .pp_count =3D 1, .pp_chg_id =3D INT_MIN, @@ -530,7 +559,7 @@ static const struct { { .n =3D "flex9_gclk", .id =3D 15, - .pp =3D { "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table =3D { 8, }, .pp_count =3D 1, .pp_chg_id =3D INT_MIN, @@ -539,7 +568,7 @@ static const struct { { .n =3D "flex10_gclk", .id =3D 16, - .pp =3D { "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table =3D { 8, }, .pp_count =3D 1, .pp_chg_id =3D INT_MIN, @@ -548,7 +577,7 @@ static const struct { { .n =3D "tcb0_gclk", .id =3D 17, - .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), PLL_IDS_TO_ARR_ENTRY(PLLA, = DIV1), }, .pp_mux_table =3D { 6, 8, }, .pp_count =3D 2, .pp_chg_id =3D INT_MIN, @@ -557,7 +586,7 @@ static const struct { { .n =3D "adc_gclk", .id =3D 19, - .pp =3D { "upll_divpmcck", "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(UPLL, DIV0), PLL_IDS_TO_ARR_ENTRY(PLLA, D= IV1), }, .pp_mux_table =3D { 5, 8, }, .pp_count =3D 2, .pp_chg_id =3D INT_MIN, @@ -567,7 +596,7 @@ static const struct { .n =3D "lcd_gclk", .id =3D 25, .r =3D { .max =3D 75000000 }, - .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), PLL_IDS_TO_ARR_ENTRY(PLLA, = DIV1), }, .pp_mux_table =3D { 6, 8, }, .pp_count =3D 2, .pp_chg_id =3D INT_MIN, @@ -577,7 +606,7 @@ static const struct { .n =3D "sdmmc1_gclk", .id =3D 26, .r =3D { .max =3D 105000000 }, - .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), PLL_IDS_TO_ARR_ENTRY(PLLA, = DIV1), }, .pp_mux_table =3D { 6, 8, }, .pp_count =3D 2, .pp_chg_id =3D INT_MIN, @@ -587,7 +616,7 @@ static const struct { .n =3D "mcan0_gclk", .id =3D 29, .r =3D { .max =3D 80000000 }, - .pp =3D { "upll_divpmcck", "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(UPLL, DIV0), PLL_IDS_TO_ARR_ENTRY(PLLA, D= IV1), }, .pp_mux_table =3D { 5, 8, }, .pp_count =3D 2, .pp_chg_id =3D INT_MIN, @@ -597,7 +626,7 @@ static const struct { .n =3D "mcan1_gclk", .id =3D 30, .r =3D { .max =3D 80000000 }, - .pp =3D { "upll_divpmcck", "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(UPLL, DIV0), PLL_IDS_TO_ARR_ENTRY(PLLA, D= IV1), }, .pp_mux_table =3D { 5, 8, }, .pp_count =3D 2, .pp_chg_id =3D INT_MIN, @@ -606,7 +635,7 @@ static const struct { { .n =3D "flex11_gclk", .id =3D 32, - .pp =3D { "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table =3D { 8, }, .pp_count =3D 1, .pp_chg_id =3D INT_MIN, @@ -615,7 +644,7 @@ static const struct { { .n =3D "flex12_gclk", .id =3D 33, - .pp =3D { "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table =3D { 8, }, .pp_count =3D 1, .pp_chg_id =3D INT_MIN, @@ -625,7 +654,7 @@ static const struct { .n =3D "i2s_gclk", .id =3D 34, .r =3D { .max =3D 100000000 }, - .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), PLL_IDS_TO_ARR_ENTRY(PLLA, = DIV1), }, .pp_mux_table =3D { 6, 8, }, .pp_count =3D 2, .pp_chg_id =3D INT_MIN, @@ -635,7 +664,7 @@ static const struct { .n =3D "qspi_gclk", .id =3D 35, .r =3D { .max =3D 200000000 }, - .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), PLL_IDS_TO_ARR_ENTRY(PLLA, = DIV1), }, .pp_mux_table =3D { 6, 8, }, .pp_count =3D 2, .pp_chg_id =3D INT_MIN, @@ -644,7 +673,7 @@ static const struct { { .n =3D "pit64b0_gclk", .id =3D 37, - .pp =3D { "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table =3D { 8, }, .pp_count =3D 1, .pp_chg_id =3D INT_MIN, @@ -654,7 +683,7 @@ static const struct { .n =3D "classd_gclk", .id =3D 42, .r =3D { .max =3D 100000000 }, - .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), PLL_IDS_TO_ARR_ENTRY(PLLA, = DIV1), }, .pp_mux_table =3D { 6, 8, }, .pp_count =3D 2, .pp_chg_id =3D INT_MIN, @@ -663,7 +692,7 @@ static const struct { { .n =3D "tcb1_gclk", .id =3D 45, - .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), PLL_IDS_TO_ARR_ENTRY(PLLA, = DIV1), }, .pp_mux_table =3D { 6, 8, }, .pp_count =3D 2, .pp_chg_id =3D INT_MIN, @@ -672,7 +701,7 @@ static const struct { { .n =3D "dbgu_gclk", .id =3D 47, - .pp =3D { "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table =3D { 8, }, .pp_count =3D 1, .pp_chg_id =3D INT_MIN, @@ -682,7 +711,7 @@ static const struct { .n =3D "mipiphy_gclk", .id =3D 55, .r =3D { .max =3D 27000000 }, - .pp =3D { "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table =3D { 8, }, .pp_count =3D 1, .pp_chg_id =3D INT_MIN, @@ -691,7 +720,7 @@ static const struct { { .n =3D "pit64b1_gclk", .id =3D 58, - .pp =3D { "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table =3D { 8, }, .pp_count =3D 1, .pp_chg_id =3D INT_MIN, @@ -700,7 +729,7 @@ static const struct { { .n =3D "gmac_gclk", .id =3D 67, - .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), PLL_IDS_TO_ARR_ENTRY(PLLA, = DIV1), }, .pp_mux_table =3D { 6, 8, }, .pp_count =3D 2, .pp_chg_id =3D INT_MIN, @@ -709,34 +738,25 @@ static const struct { =20 static void __init sam9x7_pmc_setup(struct device_node *np) { + u8 td_slck_index =3D 0, md_slck_index =3D 1, main_xtal_index =3D 2; + const char * const main_xtal_name =3D "main_xtal"; + const char * const td_slck_name =3D "td_slck"; + const char * const md_slck_name =3D "md_slck"; + struct clk_hw *hw, *main_rc_hw, *main_osc_hw; + struct clk_parent_data parent_data[9]; struct clk_range range =3D CLK_RANGE(0, 0); - const char *td_slck_name, *md_slck_name, *mainxtal_name; struct pmc_data *sam9x7_pmc; - const char *parent_names[9]; void **clk_mux_buffer =3D NULL; int clk_mux_buffer_size =3D 0; - struct clk_hw *main_osc_hw; + struct clk *main_xtal; struct regmap *regmap; - struct clk_hw *hw; + struct clk_hw *usbck_hw; int i, j; =20 - i =3D of_property_match_string(np, "clock-names", "td_slck"); - if (i < 0) + main_xtal =3D of_clk_get(np, main_xtal_index); + if (IS_ERR(main_xtal)) return; =20 - td_slck_name =3D of_clk_get_parent_name(np, i); - - i =3D of_property_match_string(np, "clock-names", "md_slck"); - if (i < 0) - return; - - md_slck_name =3D of_clk_get_parent_name(np, i); - - i =3D of_property_match_string(np, "clock-names", "main_xtal"); - if (i < 0) - return; - mainxtal_name =3D of_clk_get_parent_name(np, i); - regmap =3D device_node_to_regmap(np); if (IS_ERR(regmap)) return; @@ -754,46 +774,55 @@ static void __init sam9x7_pmc_setup(struct device_nod= e *np) if (!clk_mux_buffer) goto err_free; =20 - hw =3D at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000, - 50000000); - if (IS_ERR(hw)) + main_rc_hw =3D at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000= 000, + 50000000); + if (IS_ERR(main_rc_hw)) goto err_free; =20 - hw =3D at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL= , 0); - if (IS_ERR(hw)) + main_osc_hw =3D at91_clk_register_main_osc(regmap, "main_osc", NULL, + &AT91_CLK_PD_NAME(main_xtal_name, main_xtal_index), 0); + if (IS_ERR(main_osc_hw)) goto err_free; - main_osc_hw =3D hw; =20 - parent_names[0] =3D "main_rc_osc"; - parent_names[1] =3D "main_osc"; - hw =3D at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL= , 2); + parent_data[0] =3D AT91_CLK_PD_HW(main_rc_hw); + parent_data[1] =3D AT91_CLK_PD_HW(main_osc_hw); + hw =3D at91_clk_register_sam9x5_main(regmap, "mainck", NULL, parent_data,= 2); if (IS_ERR(hw)) goto err_free; =20 sam9x7_pmc->chws[PMC_MAIN] =3D hw; =20 for (i =3D 0; i < PLL_ID_MAX; i++) { - for (j =3D 0; j < 3; j++) { - struct clk_hw *parent_hw; + for (j =3D 0; j < PLL_COMPID_MAX; j++) { + unsigned long parent_rate =3D 0; =20 if (!sam9x7_plls[i][j].n) continue; =20 switch (sam9x7_plls[i][j].t) { case PLL_TYPE_FRAC: - if (!strcmp(sam9x7_plls[i][j].p, "mainck")) - parent_hw =3D sam9x7_pmc->chws[PMC_MAIN]; - else if (!strcmp(sam9x7_plls[i][j].p, "main_osc")) - parent_hw =3D main_osc_hw; - else - parent_hw =3D __clk_get_hw(of_clk_get_by_name - (np, sam9x7_plls[i][j].p)); - + switch (sam9x7_plls[i][j].p) { + case SAM9X7_PLL_PARENT_MAINCK: + parent_data[0] =3D AT91_CLK_PD_NAME("mainck", -1); + parent_rate =3D clk_hw_get_rate(sam9x7_pmc->chws[PMC_MAIN]); + break; + case SAM9X7_PLL_PARENT_MAIN_XTAL: + parent_data[0] =3D AT91_CLK_PD_NAME(main_xtal_name, + main_xtal_index); + parent_rate =3D clk_get_rate(main_xtal); + break; + default: + /* Should not happen. */ + break; + } + + if (!parent_rate) + return; hw =3D sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, sam9x7_plls[i][j].n, - sam9x7_plls[i][j].p, - parent_hw, i, + parent_data, + parent_rate, i, sam9x7_plls[i][j].c, sam9x7_plls[i][j].l, sam9x7_plls[i][j].f); @@ -803,7 +832,7 @@ static void __init sam9x7_pmc_setup(struct device_node = *np) hw =3D sam9x60_clk_register_div_pll(regmap, &pmc_pll_lock, sam9x7_plls[i][j].n, - sam9x7_plls[i][j].p, NULL, i, + NULL, sam9x7_plls[i][0].hw, i, sam9x7_plls[i][j].c, sam9x7_plls[i][j].l, sam9x7_plls[i][j].f, 0); @@ -816,23 +845,24 @@ static void __init sam9x7_pmc_setup(struct device_nod= e *np) if (IS_ERR(hw)) goto err_free; =20 + sam9x7_plls[i][j].hw =3D hw; if (sam9x7_plls[i][j].eid) sam9x7_pmc->chws[sam9x7_plls[i][j].eid] =3D hw; } } =20 - parent_names[0] =3D md_slck_name; - parent_names[1] =3D "mainck"; - parent_names[2] =3D "plla_divpmcck"; - parent_names[3] =3D "upll_divpmcck"; + parent_data[0] =3D AT91_CLK_PD_NAME(md_slck_name, md_slck_index); + parent_data[1] =3D AT91_CLK_PD_HW(sam9x7_pmc->chws[PMC_MAIN]); + parent_data[2] =3D AT91_CLK_PD_HW(sam9x7_plls[PLL_ID_PLLA][PLL_COMPID_DIV= 0].hw); + parent_data[3] =3D AT91_CLK_PD_HW(sam9x7_plls[PLL_ID_UPLL][PLL_COMPID_DIV= 0].hw); hw =3D at91_clk_register_master_pres(regmap, "masterck_pres", 4, - parent_names, NULL, &sam9x7_master_layout, + NULL, parent_data, &sam9x7_master_layout, &mck_characteristics, &mck_lock); if (IS_ERR(hw)) goto err_free; =20 hw =3D at91_clk_register_master_div(regmap, "masterck_div", - "masterck_pres", NULL, &sam9x7_master_layout, + NULL, &AT91_CLK_PD_HW(hw), &sam9x7_master_layout, &mck_characteristics, &mck_lock, CLK_SET_RATE_GATE, 0); if (IS_ERR(hw)) @@ -840,27 +870,27 @@ static void __init sam9x7_pmc_setup(struct device_nod= e *np) =20 sam9x7_pmc->chws[PMC_MCK] =3D hw; =20 - parent_names[0] =3D "plla_divpmcck"; - parent_names[1] =3D "upll_divpmcck"; - parent_names[2] =3D "main_osc"; - hw =3D sam9x60_clk_register_usb(regmap, "usbck", parent_names, 3); + parent_data[0] =3D AT91_CLK_PD_HW(sam9x7_plls[PLL_ID_PLLA][PLL_COMPID_DIV= 0].hw); + parent_data[1] =3D AT91_CLK_PD_HW(sam9x7_plls[PLL_ID_UPLL][PLL_COMPID_DIV= 0].hw); + parent_data[2] =3D AT91_CLK_PD_HW(main_osc_hw); + usbck_hw =3D sam9x60_clk_register_usb(regmap, "usbck", NULL, parent_data,= 3); if (IS_ERR(hw)) goto err_free; =20 - parent_names[0] =3D md_slck_name; - parent_names[1] =3D td_slck_name; - parent_names[2] =3D "mainck"; - parent_names[3] =3D "masterck_div"; - parent_names[4] =3D "plla_divpmcck"; - parent_names[5] =3D "upll_divpmcck"; - parent_names[6] =3D "audiopll_divpmcck"; + parent_data[0] =3D AT91_CLK_PD_NAME(md_slck_name, md_slck_index); + parent_data[1] =3D AT91_CLK_PD_NAME(td_slck_name, td_slck_index); + parent_data[2] =3D AT91_CLK_PD_HW(sam9x7_pmc->chws[PMC_MAIN]); + parent_data[3] =3D AT91_CLK_PD_HW(sam9x7_pmc->chws[PMC_MCK]); + parent_data[4] =3D AT91_CLK_PD_HW(sam9x7_plls[PLL_ID_PLLA][PLL_COMPID_DIV= 0].hw); + parent_data[5] =3D AT91_CLK_PD_HW(sam9x7_plls[PLL_ID_UPLL][PLL_COMPID_DIV= 0].hw); + parent_data[6] =3D AT91_CLK_PD_HW(sam9x7_plls[PLL_ID_AUDIO][PLL_COMPID_DI= V0].hw); for (i =3D 0; i < 2; i++) { char name[6]; =20 snprintf(name, sizeof(name), "prog%d", i); =20 hw =3D at91_clk_register_programmable(regmap, name, - parent_names, NULL, 7, i, + NULL, parent_data, 7, i, &sam9x7_programmable_layout, NULL); if (IS_ERR(hw)) @@ -869,9 +899,14 @@ static void __init sam9x7_pmc_setup(struct device_node= *np) sam9x7_pmc->pchws[i] =3D hw; } =20 + /* Set systemck parent hws. */ + sam9x7_systemck[0].parent_hw =3D sam9x7_pmc->chws[PMC_MCK]; + sam9x7_systemck[1].parent_hw =3D usbck_hw; + sam9x7_systemck[2].parent_hw =3D sam9x7_pmc->pchws[0]; + sam9x7_systemck[3].parent_hw =3D sam9x7_pmc->pchws[1]; for (i =3D 0; i < ARRAY_SIZE(sam9x7_systemck); i++) { hw =3D at91_clk_register_system(regmap, sam9x7_systemck[i].n, - sam9x7_systemck[i].p, NULL, + NULL, &AT91_CLK_PD_HW(sam9x7_systemck[i].parent_hw), sam9x7_systemck[i].id, sam9x7_systemck[i].flags); if (IS_ERR(hw)) @@ -884,7 +919,7 @@ static void __init sam9x7_pmc_setup(struct device_node = *np) hw =3D at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, &sam9x7_pcr_layout, sam9x7_periphck[i].n, - "masterck_div", NULL, + NULL, &AT91_CLK_PD_HW(sam9x7_pmc->chws[PMC_MCK]), sam9x7_periphck[i].id, &range, INT_MIN, sam9x7_periphck[i].f); @@ -894,10 +929,10 @@ static void __init sam9x7_pmc_setup(struct device_nod= e *np) sam9x7_pmc->phws[sam9x7_periphck[i].id] =3D hw; } =20 - parent_names[0] =3D md_slck_name; - parent_names[1] =3D td_slck_name; - parent_names[2] =3D "mainck"; - parent_names[3] =3D "masterck_div"; + parent_data[0] =3D AT91_CLK_PD_NAME(md_slck_name, md_slck_index); + parent_data[1] =3D AT91_CLK_PD_NAME(td_slck_name, td_slck_index); + parent_data[2] =3D AT91_CLK_PD_HW(sam9x7_pmc->chws[PMC_MAIN]); + parent_data[3] =3D AT91_CLK_PD_HW(sam9x7_pmc->chws[PMC_MCK]); for (i =3D 0; i < ARRAY_SIZE(sam9x7_gck); i++) { u8 num_parents =3D 4 + sam9x7_gck[i].pp_count; u32 *mux_table; @@ -910,13 +945,18 @@ static void __init sam9x7_pmc_setup(struct device_nod= e *np) PMC_INIT_TABLE(mux_table, 4); PMC_FILL_TABLE(&mux_table[4], sam9x7_gck[i].pp_mux_table, sam9x7_gck[i].pp_count); - PMC_FILL_TABLE(&parent_names[4], sam9x7_gck[i].pp, - sam9x7_gck[i].pp_count); + + for (j =3D 0; j < sam9x7_gck[i].pp_count; j++) { + u8 pll_id =3D sam9x7_gck[i].pp[j].pll_id; + u8 pll_compid =3D sam9x7_gck[i].pp[j].pll_compid; + + parent_data[4 + j] =3D AT91_CLK_PD_HW(sam9x7_plls[pll_id][pll_compid].h= w); + } =20 hw =3D at91_clk_register_generated(regmap, &pmc_pcr_lock, &sam9x7_pcr_layout, sam9x7_gck[i].n, - parent_names, NULL, mux_table, + NULL, parent_data, mux_table, num_parents, sam9x7_gck[i].id, &sam9x7_gck[i].r, @@ -931,7 +971,7 @@ static void __init sam9x7_pmc_setup(struct device_node = *np) of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sam9x7_pmc); kfree(clk_mux_buffer); =20 - return; + goto put_main_xtal; =20 err_free: if (clk_mux_buffer) { @@ -940,6 +980,8 @@ static void __init sam9x7_pmc_setup(struct device_node = *np) kfree(clk_mux_buffer); } kfree(sam9x7_pmc); +put_main_xtal: + clk_put(main_xtal); } =20 /* Some clks are used for a clocksource */ --=20 2.43.0 From nobody Wed Oct 8 20:52:50 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 61C59307AEB; Tue, 24 Jun 2025 15:09:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777771; cv=none; b=CNQ7/jTvO/1oJp0Fcd2GrchB96ajmyMf6GnGGh52XGM13KWrXO2c/zKl+AOQVZagdBEdyifxKcxpwi4vFemxpKGFeyr1rxFevsHk9X3XRwIu0czxYDFFO58H3dO3xF2ylfjYDpyAiftX5CEPceIK61M5AEV63aIpGwPCjBSmSUw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777771; c=relaxed/simple; bh=Q36se3Fv5wrz4xwPyMEyT8KGoXdptrkCfrP0P7CE8os=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=OLCeoH40vymjBf/m0jCCqmm6ouGwmVhl3kmylpiOtGfb1kfzx1KvpWsYtYVn8obOZPCBbN2JASciVnANTfk3taOYfMXEkS0Q6rLNd1had0onA572rIp06al0kbkfqn+BrQ5V5DrqHpgbBRJmOjLkumJmcynbGCu8mRvmOD5I0+0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=MYgENOY9; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="MYgENOY9" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1750777769; x=1782313769; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Q36se3Fv5wrz4xwPyMEyT8KGoXdptrkCfrP0P7CE8os=; b=MYgENOY9Ib8WYrteZBFONdEAbAmOPMipASCc3fgLE+K6kOVrROgV+Nug umnEaqDxrvr8xA3X8A8dHMeyCT+RrpdDItyFji2gdRfmcKprNVawX7Vec 81hCsBaDVIWGnq4oQgmONL6QuBy5cVh5U1iml/3niptOxA/gPLFtYwn0R i/56zJJyvkb5TDLro5YyXlG+ED8UW4c7jwCpP1hDgNvp8sZygAM7LQWcs NzIeioE7aSoi2ZfrM0eExRLSjm/gtob1y8THBaDccFonvvk4YwoaWhXtg 068w7w7aND+ryP0MLMpxOgAU/AlAu/o/i2MrGHFB1qvMU1GoH6VLApTtK A==; X-CSE-ConnectionGUID: ticneE1VRpCt6c5L3blMOw== X-CSE-MsgGUID: nCSw0OAMR0Gbr53mq+OqRA== X-IronPort-AV: E=Sophos;i="6.16,262,1744095600"; d="scan'208";a="210641602" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 24 Jun 2025 08:09:21 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Tue, 24 Jun 2025 08:08:40 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Tue, 24 Jun 2025 08:08:40 -0700 From: To: , , , , CC: , , , , Subject: [PATCH v2 31/32] clk: at91: sama7g5: switch to clk_parent_data Date: Tue, 24 Jun 2025 08:08:28 -0700 Message-ID: <5bec7266f92f426c061e4452b4a6b67f33911f2c.1750182562.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Switch SAMA7G5 clocks to use parent_hw and parent_data. Having parent_hw instead of parent names improves to clock registration speed and re-parenting. Signed-off-by: Claudiu Beznea [ryan.wanner@microchip.com: Took all the small changes for this SoC from the clock core commits and put them into this patch as one full commit.] Signed-off-by: Ryan Wanner --- drivers/clk/at91/sama7g5.c | 108 ++++++++++++++++++------------------- 1 file changed, 54 insertions(+), 54 deletions(-) diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index bf6092fea217..954202e0e8f9 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -969,35 +969,34 @@ static const struct clk_pcr_layout sama7g5_pcr_layout= =3D { =20 static void __init sama7g5_pmc_setup(struct device_node *np) { - const char *main_xtal_name =3D "main_xtal"; + u8 td_slck_index =3D 0, md_slck_index =3D 1, main_xtal_index =3D 2; + const char * const main_xtal_name =3D "main_xtal"; + const char * const td_slck_name =3D "td_slck"; + const char * const md_slck_name =3D "md_slck"; + struct clk_hw *hw, *main_rc_hw, *main_osc_hw; + struct clk_parent_data parent_data[10]; struct pmc_data *sama7g5_pmc; void **alloc_mem =3D NULL; int alloc_mem_size =3D 0; + struct clk *main_xtal; struct regmap *regmap; - struct clk_hw *hw, *main_rc_hw, *main_osc_hw, *main_xtal_hw; - struct clk_hw *td_slck_hw, *md_slck_hw; - static struct clk_parent_data parent_data; - struct clk_hw *parent_hws[10]; bool bypass; int i, j; =20 - td_slck_hw =3D __clk_get_hw(of_clk_get_by_name(np, "td_slck")); - md_slck_hw =3D __clk_get_hw(of_clk_get_by_name(np, "md_slck")); - main_xtal_hw =3D __clk_get_hw(of_clk_get_by_name(np, main_xtal_name)); - - if (!td_slck_hw || !md_slck_hw || !main_xtal_hw) + main_xtal =3D of_clk_get(np, main_xtal_index); + if (IS_ERR(main_xtal)) return; =20 regmap =3D device_node_to_regmap(np); if (IS_ERR(regmap)) - return; + goto put_main_xtal; =20 sama7g5_pmc =3D pmc_data_allocate(PMC_MCK1 + 1, nck(sama7g5_systemck), nck(sama7g5_periphck), nck(sama7g5_gck), 8); if (!sama7g5_pmc) - return; + goto put_main_xtal; =20 alloc_mem =3D kmalloc(sizeof(void *) * (ARRAY_SIZE(sama7g5_mckx) + ARRAY_SIZE(sama7g5_gck)), @@ -1012,16 +1011,15 @@ static void __init sama7g5_pmc_setup(struct device_= node *np) =20 bypass =3D of_property_read_bool(np, "atmel,osc-bypass"); =20 - parent_data.name =3D main_xtal_name; - parent_data.fw_name =3D main_xtal_name; main_osc_hw =3D at91_clk_register_main_osc(regmap, "main_osc", NULL, - &parent_data, bypass); + &AT91_CLK_PD_NAME(main_xtal_name, main_xtal_index), + bypass); if (IS_ERR(main_osc_hw)) goto err_free; =20 - parent_hws[0] =3D main_rc_hw; - parent_hws[1] =3D main_osc_hw; - hw =3D at91_clk_register_sam9x5_main(regmap, "mainck", NULL, parent_hws, = 2); + parent_data[0] =3D AT91_CLK_PD_HW(main_rc_hw); + parent_data[1] =3D AT91_CLK_PD_HW(main_osc_hw); + hw =3D at91_clk_register_sam9x5_main(regmap, "mainck", NULL, parent_data,= 2); if (IS_ERR(hw)) goto err_free; =20 @@ -1029,7 +1027,7 @@ static void __init sama7g5_pmc_setup(struct device_no= de *np) =20 for (i =3D 0; i < PLL_ID_MAX; i++) { for (j =3D 0; j < PLL_COMPID_MAX; j++) { - struct clk_hw *parent_hw; + unsigned long parent_rate =3D 0; =20 if (!sama7g5_plls[i][j].n) continue; @@ -1038,20 +1036,25 @@ static void __init sama7g5_pmc_setup(struct device_= node *np) case PLL_TYPE_FRAC: switch (sama7g5_plls[i][j].p) { case SAMA7G5_PLL_PARENT_MAINCK: - parent_hw =3D sama7g5_pmc->chws[PMC_MAIN]; + parent_data[0] =3D AT91_CLK_PD_NAME("mainck", -1); + parent_rate =3D clk_hw_get_rate(sama7g5_pmc->chws[PMC_MAIN]); break; case SAMA7G5_PLL_PARENT_MAIN_XTAL: - parent_hw =3D main_xtal_hw; + parent_data[0] =3D AT91_CLK_PD_NAME(main_xtal_name, + main_xtal_index); + parent_rate =3D clk_get_rate(main_xtal); break; default: /* Should not happen. */ - parent_hw =3D NULL; break; } =20 + if (!parent_rate) + return; + hw =3D sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, sama7g5_plls[i][j].n, - NULL, parent_hw, i, + parent_data, parent_rate, i, sama7g5_plls[i][j].c, sama7g5_plls[i][j].l, sama7g5_plls[i][j].f); @@ -1081,7 +1084,7 @@ static void __init sama7g5_pmc_setup(struct device_no= de *np) } =20 hw =3D at91_clk_register_master_div(regmap, "mck0", NULL, - sama7g5_plls[PLL_ID_CPU][1].hw, + &AT91_CLK_PD_HW(sama7g5_plls[PLL_ID_CPU][1].hw), &mck0_layout, &mck0_characteristics, &pmc_mck0_lock, CLK_GET_RATE_NOCACHE, 5); if (IS_ERR(hw)) @@ -1089,12 +1092,11 @@ static void __init sama7g5_pmc_setup(struct device_= node *np) =20 sama7g5_mckx[PCK_PARENT_HW_MCK0].hw =3D sama7g5_pmc->chws[PMC_MCK] =3D hw; =20 - parent_hws[0] =3D md_slck_hw; - parent_hws[1] =3D td_slck_hw; - parent_hws[2] =3D sama7g5_pmc->chws[PMC_MAIN]; + parent_data[0] =3D AT91_CLK_PD_NAME(md_slck_name, md_slck_index); + parent_data[1] =3D AT91_CLK_PD_NAME(td_slck_name, td_slck_index); + parent_data[2] =3D AT91_CLK_PD_HW(sama7g5_pmc->chws[PMC_MAIN]); for (i =3D PCK_PARENT_HW_MCK1; i < ARRAY_SIZE(sama7g5_mckx); i++) { u8 num_parents =3D 3 + sama7g5_mckx[i].ep_count; - struct clk_hw *tmp_parent_hws[8]; u32 *mux_table; =20 mux_table =3D kmalloc_array(num_parents, sizeof(*mux_table), @@ -1109,13 +1111,11 @@ static void __init sama7g5_pmc_setup(struct device_= node *np) u8 pll_id =3D sama7g5_mckx[i].ep[j].pll_id; u8 pll_compid =3D sama7g5_mckx[i].ep[j].pll_compid; =20 - tmp_parent_hws[j] =3D sama7g5_plls[pll_id][pll_compid].hw; + parent_data[3 + j] =3D AT91_CLK_PD_HW(sama7g5_plls[pll_id][pll_compid].= hw); } - PMC_FILL_TABLE(&parent_hws[3], tmp_parent_hws, - sama7g5_mckx[i].ep_count); =20 hw =3D at91_clk_sama7g5_register_master(regmap, sama7g5_mckx[i].n, - num_parents, NULL, parent_hws, mux_table, + num_parents, NULL, parent_data, mux_table, &pmc_mckX_lock, sama7g5_mckx[i].id, sama7g5_mckx[i].c, sama7g5_mckx[i].ep_chg_id); @@ -1129,27 +1129,28 @@ static void __init sama7g5_pmc_setup(struct device_= node *np) sama7g5_pmc->chws[sama7g5_mckx[i].eid] =3D hw; } =20 - hw =3D at91_clk_sama7g5_register_utmi(regmap, "utmick", NULL, main_xtal_h= w); + hw =3D at91_clk_sama7g5_register_utmi(regmap, "utmick", NULL, + &AT91_CLK_PD_NAME(main_xtal_name, main_xtal_index)); if (IS_ERR(hw)) goto err_free; =20 sama7g5_pmc->chws[PMC_UTMI] =3D hw; =20 - parent_hws[0] =3D md_slck_hw; - parent_hws[1] =3D td_slck_hw; - parent_hws[2] =3D sama7g5_pmc->chws[PMC_MAIN]; - parent_hws[3] =3D sama7g5_plls[PLL_ID_SYS][PLL_COMPID_DIV0].hw; - parent_hws[4] =3D sama7g5_plls[PLL_ID_DDR][PLL_COMPID_DIV0].hw; - parent_hws[5] =3D sama7g5_plls[PLL_ID_IMG][PLL_COMPID_DIV0].hw; - parent_hws[6] =3D sama7g5_plls[PLL_ID_BAUD][PLL_COMPID_DIV0].hw; - parent_hws[7] =3D sama7g5_plls[PLL_ID_AUDIO][PLL_COMPID_DIV0].hw; - parent_hws[8] =3D sama7g5_plls[PLL_ID_ETH][PLL_COMPID_DIV0].hw; + parent_data[0] =3D AT91_CLK_PD_NAME(md_slck_name, md_slck_index); + parent_data[1] =3D AT91_CLK_PD_NAME(td_slck_name, td_slck_index); + parent_data[2] =3D AT91_CLK_PD_HW(sama7g5_pmc->chws[PMC_MAIN]); + parent_data[3] =3D AT91_CLK_PD_HW(sama7g5_plls[PLL_ID_SYS][PLL_COMPID_DIV= 0].hw); + parent_data[4] =3D AT91_CLK_PD_HW(sama7g5_plls[PLL_ID_DDR][PLL_COMPID_DIV= 0].hw); + parent_data[5] =3D AT91_CLK_PD_HW(sama7g5_plls[PLL_ID_IMG][PLL_COMPID_DIV= 0].hw); + parent_data[6] =3D AT91_CLK_PD_HW(sama7g5_plls[PLL_ID_BAUD][PLL_COMPID_DI= V0].hw); + parent_data[7] =3D AT91_CLK_PD_HW(sama7g5_plls[PLL_ID_AUDIO][PLL_COMPID_D= IV0].hw); + parent_data[8] =3D AT91_CLK_PD_HW(sama7g5_plls[PLL_ID_ETH][PLL_COMPID_DIV= 0].hw); for (i =3D 0; i < 8; i++) { char name[6]; =20 snprintf(name, sizeof(name), "prog%d", i); =20 - hw =3D at91_clk_register_programmable(regmap, name, NULL, parent_hws, + hw =3D at91_clk_register_programmable(regmap, name, NULL, parent_data, 9, i, &programmable_layout, sama7g5_prog_mux_table); @@ -1161,7 +1162,7 @@ static void __init sama7g5_pmc_setup(struct device_no= de *np) =20 for (i =3D 0; i < ARRAY_SIZE(sama7g5_systemck); i++) { hw =3D at91_clk_register_system(regmap, sama7g5_systemck[i].n, - NULL, sama7g5_pmc->pchws[i], + NULL, &AT91_CLK_PD_HW(sama7g5_pmc->pchws[i]), sama7g5_systemck[i].id, 0); if (IS_ERR(hw)) goto err_free; @@ -1174,7 +1175,7 @@ static void __init sama7g5_pmc_setup(struct device_no= de *np) &sama7g5_pcr_layout, sama7g5_periphck[i].n, NULL, - sama7g5_mckx[sama7g5_periphck[i].p].hw, + &AT91_CLK_PD_HW(sama7g5_mckx[sama7g5_periphck[i].p].hw), sama7g5_periphck[i].id, &sama7g5_periphck[i].r, sama7g5_periphck[i].chgp ? 0 : @@ -1185,12 +1186,11 @@ static void __init sama7g5_pmc_setup(struct device_= node *np) sama7g5_pmc->phws[sama7g5_periphck[i].id] =3D hw; } =20 - parent_hws[0] =3D md_slck_hw; - parent_hws[1] =3D td_slck_hw; - parent_hws[2] =3D sama7g5_pmc->chws[PMC_MAIN]; + parent_data[0] =3D AT91_CLK_PD_NAME(md_slck_name, md_slck_index); + parent_data[1] =3D AT91_CLK_PD_NAME(td_slck_name, td_slck_index); + parent_data[2] =3D AT91_CLK_PD_HW(sama7g5_pmc->chws[PMC_MAIN]); for (i =3D 0; i < ARRAY_SIZE(sama7g5_gck); i++) { u8 num_parents =3D 3 + sama7g5_gck[i].pp_count; - struct clk_hw *tmp_parent_hws[8]; u32 *mux_table; =20 mux_table =3D kmalloc_array(num_parents, sizeof(*mux_table), @@ -1205,15 +1205,13 @@ static void __init sama7g5_pmc_setup(struct device_= node *np) u8 pll_id =3D sama7g5_gck[i].pp[j].pll_id; u8 pll_compid =3D sama7g5_gck[i].pp[j].pll_compid; =20 - tmp_parent_hws[j] =3D sama7g5_plls[pll_id][pll_compid].hw; + parent_data[3 + j] =3D AT91_CLK_PD_HW(sama7g5_plls[pll_id][pll_compid].= hw); } - PMC_FILL_TABLE(&parent_hws[3], tmp_parent_hws, - sama7g5_gck[i].pp_count); =20 hw =3D at91_clk_register_generated(regmap, &pmc_pcr_lock, &sama7g5_pcr_layout, sama7g5_gck[i].n, NULL, - parent_hws, mux_table, + parent_data, mux_table, num_parents, sama7g5_gck[i].id, &sama7g5_gck[i].r, @@ -1227,7 +1225,7 @@ static void __init sama7g5_pmc_setup(struct device_no= de *np) =20 of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sama7g5_pmc); =20 - return; + goto put_main_xtal; =20 err_free: if (alloc_mem) { @@ -1237,6 +1235,8 @@ static void __init sama7g5_pmc_setup(struct device_no= de *np) } =20 kfree(sama7g5_pmc); +put_main_xtal: + clk_put(main_xtal); } =20 /* Some clks are used for a clocksource */ --=20 2.43.0 From nobody Wed Oct 8 20:52:50 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BE971307AFD; Tue, 24 Jun 2025 15:09:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777773; cv=none; b=Yk7vzcXo2S0QjPQwXeFQVo8uu+Omtc1t7fP/6BhuswexDdhM4ti2gWzIwyisW0YKAy1IDawa/nyZWNcJJtlQ/MKmAsW8MdPNWMsGtH1JYQbsw7F057LdTCRxaUMs0BTdVShShFYfZIPU92qgCPzGW/bO+hgBFwUEm8p1TF2R92w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777773; c=relaxed/simple; bh=L7YqKuTIwCYHtrw/RUpnVI94eOPAPR+812suCuUne80=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=copj252Li4tGlqMbyRjGuOEl9cJJkj51kyZgd43y6/4txW1y+8LgAlkZdoUxaUrkhpboE/WoTwrk/uBtJobvmsJJYhmxherncZyrka77h3iDfardG75ocYGcBbru569r6KUsFb/KglwE8Rx9BNGZBn6JraEcCYSY2Lbj6IpkWFc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=n8QA8Bss; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="n8QA8Bss" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1750777769; x=1782313769; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=L7YqKuTIwCYHtrw/RUpnVI94eOPAPR+812suCuUne80=; b=n8QA8BssdDmqOm5jSg3RhOAfuei0/P1QRzKczNyQvSeu0yvBBfPBAIlS 4buJai5ZDPmtXxvfNpA7En+5xmLc7KMfXnJb6jo+Hv3PAAhNqPQW0Ciqs 1z29AqTIwODuFfJNu5PstujXc00c9jh9HUaSvmdHX2vg2GoVY+50ANdGr WVucxqKqAbdC2yCH4uJNwQIfx7Z9cGEM8msFaYR4iXvbJYOev7MZuDAHr TkEisFs/cg05rhQfjrosN9HmTkv/ZDU0o2Jc9btxtsS0YyalGSaq/ZScn 5dqvdLWEeBivBoKBxL0H4JTR8c8MJrnMQscHrIwq+Uptvhx9vReGNlhV/ g==; X-CSE-ConnectionGUID: ticneE1VRpCt6c5L3blMOw== X-CSE-MsgGUID: USWrQUkhRoyvEBRirVuBUQ== X-IronPort-AV: E=Sophos;i="6.16,262,1744095600"; d="scan'208";a="210641603" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 24 Jun 2025 08:09:22 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Tue, 24 Jun 2025 08:08:41 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Tue, 24 Jun 2025 08:08:40 -0700 From: To: , , , , CC: , , , , , Ryan Wanner Subject: [PATCH v2 32/32] clk: at91: sama7d65: switch to clk_parent_data Date: Tue, 24 Jun 2025 08:08:29 -0700 Message-ID: <79fe811a4282bafeb9e30fbf42ae5cf584788eac.1750182562.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Ryan Wanner Switch SAMA7D65 clocks to use parent_hw and parent_data. Having parent_hw instead of parent names improves to clock registration speed and re-parenting. Signed-off-by: Ryan Wanner --- drivers/clk/at91/sama7d65.c | 113 +++++++++++++++++------------------- 1 file changed, 54 insertions(+), 59 deletions(-) diff --git a/drivers/clk/at91/sama7d65.c b/drivers/clk/at91/sama7d65.c index b74813a288a8..23723587cf9a 100644 --- a/drivers/clk/at91/sama7d65.c +++ b/drivers/clk/at91/sama7d65.c @@ -1089,36 +1089,34 @@ static const struct clk_pcr_layout sama7d65_pcr_lay= out =3D { =20 static void __init sama7d65_pmc_setup(struct device_node *np) { - const char *main_xtal_name =3D "main_xtal"; + u8 td_slck_index =3D 0, md_slck_index =3D 1, main_xtal_index =3D 2; + const char * const main_xtal_name =3D "main_xtal"; + const char * const td_slck_name =3D "td_slck"; + const char * const md_slck_name =3D "md_slck"; + struct clk_hw *hw, *main_rc_hw, *main_osc_hw; + struct clk_parent_data parent_data[10]; struct pmc_data *sama7d65_pmc; - const char *parent_names[11]; void **alloc_mem =3D NULL; int alloc_mem_size =3D 0; + struct clk *main_xtal; struct regmap *regmap; - struct clk_hw *hw, *main_rc_hw, *main_osc_hw, *main_xtal_hw; - struct clk_hw *td_slck_hw, *md_slck_hw; - static struct clk_parent_data parent_data; - struct clk_hw *parent_hws[10]; bool bypass; int i, j; =20 - td_slck_hw =3D __clk_get_hw(of_clk_get_by_name(np, "td_slck")); - md_slck_hw =3D __clk_get_hw(of_clk_get_by_name(np, "md_slck")); - main_xtal_hw =3D __clk_get_hw(of_clk_get_by_name(np, main_xtal_name)); - - if (!td_slck_hw || !md_slck_hw || !main_xtal_hw) + main_xtal =3D of_clk_get(np, main_xtal_index); + if (IS_ERR(main_xtal)) return; =20 regmap =3D device_node_to_regmap(np); if (IS_ERR(regmap)) - return; + goto put_main_xtal; =20 sama7d65_pmc =3D pmc_data_allocate(PMC_INDEX_MAX, nck(sama7d65_systemck), nck(sama7d65_periphck), nck(sama7d65_gck), 8); if (!sama7d65_pmc) - return; + goto put_main_xtal; =20 alloc_mem =3D kmalloc(sizeof(void *) * (ARRAY_SIZE(sama7d65_mckx) + ARRAY_SIZE(sama7d65_gck)), @@ -1133,16 +1131,15 @@ static void __init sama7d65_pmc_setup(struct device= _node *np) =20 bypass =3D of_property_read_bool(np, "atmel,osc-bypass"); =20 - parent_data.name =3D main_xtal_name; - parent_data.fw_name =3D main_xtal_name; main_osc_hw =3D at91_clk_register_main_osc(regmap, "main_osc", NULL, - &parent_data, bypass); + &AT91_CLK_PD_NAME(main_xtal_name, main_xtal_index), + bypass); if (IS_ERR(main_osc_hw)) goto err_free; =20 - parent_hws[0] =3D main_rc_hw; - parent_hws[1] =3D main_osc_hw; - hw =3D at91_clk_register_sam9x5_main(regmap, "mainck", NULL, parent_hws, = 2); + parent_data[0] =3D AT91_CLK_PD_HW(main_rc_hw); + parent_data[1] =3D AT91_CLK_PD_HW(main_osc_hw); + hw =3D at91_clk_register_sam9x5_main(regmap, "mainck", NULL, parent_data,= 2); if (IS_ERR(hw)) goto err_free; =20 @@ -1150,7 +1147,7 @@ static void __init sama7d65_pmc_setup(struct device_n= ode *np) =20 for (i =3D 0; i < PLL_ID_MAX; i++) { for (j =3D 0; j < PLL_COMPID_MAX; j++) { - struct clk_hw *parent_hw; + unsigned long parent_rate =3D 0; =20 if (!sama7d65_plls[i][j].n) continue; @@ -1159,20 +1156,22 @@ static void __init sama7d65_pmc_setup(struct device= _node *np) case PLL_TYPE_FRAC: switch (sama7d65_plls[i][j].p) { case SAMA7D65_PLL_PARENT_MAINCK: - parent_hw =3D sama7d65_pmc->chws[PMC_MAIN]; + parent_data[0] =3D AT91_CLK_PD_NAME("mainck", -1); + parent_rate =3D clk_hw_get_rate(sama7d65_pmc->chws[PMC_MAIN]); break; case SAMA7D65_PLL_PARENT_MAIN_XTAL: - parent_hw =3D main_xtal_hw; + parent_data[0] =3D AT91_CLK_PD_NAME(main_xtal_name, + main_xtal_index); + parent_rate =3D clk_get_rate(main_xtal); break; default: /* Should not happen. */ - parent_hw =3D NULL; break; } =20 hw =3D sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, sama7d65_plls[i][j].n, - NULL, parent_hw, i, + parent_data, parent_rate, i, sama7d65_plls[i][j].c, sama7d65_plls[i][j].l, sama7d65_plls[i][j].f); @@ -1202,7 +1201,7 @@ static void __init sama7d65_pmc_setup(struct device_n= ode *np) } =20 hw =3D at91_clk_register_master_div(regmap, "mck0", NULL, - sama7d65_plls[PLL_ID_CPU][1].hw, + &AT91_CLK_PD_HW(sama7d65_plls[PLL_ID_CPU][1].hw), &mck0_layout, &mck0_characteristics, &pmc_mck0_lock, CLK_GET_RATE_NOCACHE, 5); if (IS_ERR(hw)) @@ -1211,12 +1210,11 @@ static void __init sama7d65_pmc_setup(struct device= _node *np) sama7d65_pmc->chws[PMC_MCK] =3D hw; sama7d65_mckx[PCK_PARENT_HW_MCK0].hw =3D hw; =20 - parent_hws[0] =3D md_slck_hw; - parent_hws[1] =3D td_slck_hw; - parent_hws[2] =3D sama7d65_pmc->chws[PMC_MAIN]; + parent_data[0] =3D AT91_CLK_PD_NAME(md_slck_name, md_slck_index); + parent_data[1] =3D AT91_CLK_PD_NAME(td_slck_name, td_slck_index); + parent_data[2] =3D AT91_CLK_PD_HW(sama7d65_pmc->chws[PMC_MAIN]); for (i =3D PCK_PARENT_HW_MCK1; i < ARRAY_SIZE(sama7d65_mckx); i++) { u8 num_parents =3D 3 + sama7d65_mckx[i].ep_count; - struct clk_hw *tmp_parent_hws[8]; u32 *mux_table; =20 mux_table =3D kmalloc_array(num_parents, sizeof(*mux_table), @@ -1233,13 +1231,11 @@ static void __init sama7d65_pmc_setup(struct device= _node *np) u8 pll_id =3D sama7d65_mckx[i].ep[j].pll_id; u8 pll_compid =3D sama7d65_mckx[i].ep[j].pll_compid; =20 - tmp_parent_hws[j] =3D sama7d65_plls[pll_id][pll_compid].hw; + parent_data[3 + j] =3D AT91_CLK_PD_HW(sama7d65_plls[pll_id][pll_compid]= .hw); } - PMC_FILL_TABLE(&parent_hws[3], tmp_parent_hws, - sama7d65_mckx[i].ep_count); =20 hw =3D at91_clk_sama7g5_register_master(regmap, sama7d65_mckx[i].n, - num_parents, NULL, parent_hws, + num_parents, NULL, parent_data, mux_table, &pmc_mckX_lock, sama7d65_mckx[i].id, sama7d65_mckx[i].c, @@ -1253,29 +1249,29 @@ static void __init sama7d65_pmc_setup(struct device= _node *np) sama7d65_pmc->chws[sama7d65_mckx[i].eid] =3D hw; } =20 - parent_names[0] =3D "syspll_divpmcck"; - parent_names[1] =3D "usbpll_divpmcck"; - parent_names[2] =3D "main_osc"; - hw =3D sam9x60_clk_register_usb(regmap, "usbck", parent_names, 3); + parent_data[0] =3D AT91_CLK_PD_HW(sama7d65_plls[PLL_ID_SYS][PLL_COMPID_DI= V0].hw); + parent_data[1] =3D AT91_CLK_PD_HW(sama7d65_plls[PLL_ID_USB][PLL_COMPID_DI= V0].hw); + parent_data[2] =3D AT91_CLK_PD_HW(main_osc_hw); + hw =3D sam9x60_clk_register_usb(regmap, "usbck", NULL, parent_data, 3); if (IS_ERR(hw)) goto err_free; =20 - parent_hws[0] =3D md_slck_hw; - parent_hws[1] =3D td_slck_hw; - parent_hws[2] =3D sama7d65_pmc->chws[PMC_MAIN]; - parent_hws[3] =3D sama7d65_plls[PLL_ID_SYS][PLL_COMPID_DIV0].hw; - parent_hws[4] =3D sama7d65_plls[PLL_ID_DDR][PLL_COMPID_DIV0].hw; - parent_hws[5] =3D sama7d65_plls[PLL_ID_GPU][PLL_COMPID_DIV0].hw; - parent_hws[6] =3D sama7d65_plls[PLL_ID_BAUD][PLL_COMPID_DIV0].hw; - parent_hws[7] =3D sama7d65_plls[PLL_ID_AUDIO][PLL_COMPID_DIV0].hw; - parent_hws[8] =3D sama7d65_plls[PLL_ID_ETH][PLL_COMPID_DIV0].hw; + parent_data[0] =3D AT91_CLK_PD_NAME(md_slck_name, md_slck_index); + parent_data[1] =3D AT91_CLK_PD_NAME(td_slck_name, td_slck_index); + parent_data[2] =3D AT91_CLK_PD_HW(sama7d65_pmc->chws[PMC_MAIN]); + parent_data[3] =3D AT91_CLK_PD_HW(sama7d65_plls[PLL_ID_SYS][PLL_COMPID_DI= V0].hw); + parent_data[4] =3D AT91_CLK_PD_HW(sama7d65_plls[PLL_ID_DDR][PLL_COMPID_DI= V0].hw); + parent_data[5] =3D AT91_CLK_PD_HW(sama7d65_plls[PLL_ID_GPU][PLL_COMPID_DI= V0].hw); + parent_data[6] =3D AT91_CLK_PD_HW(sama7d65_plls[PLL_ID_BAUD][PLL_COMPID_D= IV0].hw); + parent_data[7] =3D AT91_CLK_PD_HW(sama7d65_plls[PLL_ID_AUDIO][PLL_COMPID_= DIV0].hw); + parent_data[8] =3D AT91_CLK_PD_HW(sama7d65_plls[PLL_ID_ETH][PLL_COMPID_DI= V0].hw); =20 for (i =3D 0; i < 8; i++) { char name[6]; =20 snprintf(name, sizeof(name), "prog%d", i); =20 - hw =3D at91_clk_register_programmable(regmap, name, NULL, parent_hws, + hw =3D at91_clk_register_programmable(regmap, name, NULL, parent_data, 9, i, &programmable_layout, sama7d65_prog_mux_table); @@ -1287,7 +1283,7 @@ static void __init sama7d65_pmc_setup(struct device_n= ode *np) =20 for (i =3D 0; i < ARRAY_SIZE(sama7d65_systemck); i++) { hw =3D at91_clk_register_system(regmap, sama7d65_systemck[i].n, - sama7d65_systemck[i].p, NULL, + NULL, &AT91_CLK_PD_HW(sama7d65_pmc->pchws[i]), sama7d65_systemck[i].id, 0); if (IS_ERR(hw)) goto err_free; @@ -1300,7 +1296,7 @@ static void __init sama7d65_pmc_setup(struct device_n= ode *np) &sama7d65_pcr_layout, sama7d65_periphck[i].n, NULL, - sama7d65_mckx[sama7d65_periphck[i].p].hw, + &AT91_CLK_PD_HW(sama7d65_mckx[sama7d65_periphck[i].p].hw), sama7d65_periphck[i].id, &sama7d65_periphck[i].r, sama7d65_periphck[i].chgp ? 0 : @@ -1311,13 +1307,12 @@ static void __init sama7d65_pmc_setup(struct device= _node *np) sama7d65_pmc->phws[sama7d65_periphck[i].id] =3D hw; } =20 - parent_hws[0] =3D md_slck_hw; - parent_hws[1] =3D td_slck_hw; - parent_hws[2] =3D sama7d65_pmc->chws[PMC_MAIN]; - parent_hws[3] =3D sama7d65_pmc->chws[PMC_MCK1]; + parent_data[0] =3D AT91_CLK_PD_NAME(md_slck_name, md_slck_index); + parent_data[1] =3D AT91_CLK_PD_NAME(td_slck_name, td_slck_index); + parent_data[2] =3D AT91_CLK_PD_HW(sama7d65_pmc->chws[PMC_MAIN]); + parent_data[3] =3D AT91_CLK_PD_HW(sama7d65_pmc->chws[PMC_MCK1]); for (i =3D 0; i < ARRAY_SIZE(sama7d65_gck); i++) { u8 num_parents =3D 4 + sama7d65_gck[i].pp_count; - struct clk_hw *tmp_parent_hws[8]; u32 *mux_table; =20 mux_table =3D kmalloc_array(num_parents, sizeof(*mux_table), @@ -1334,15 +1329,13 @@ static void __init sama7d65_pmc_setup(struct device= _node *np) u8 pll_id =3D sama7d65_gck[i].pp[j].pll_id; u8 pll_compid =3D sama7d65_gck[i].pp[j].pll_compid; =20 - tmp_parent_hws[j] =3D sama7d65_plls[pll_id][pll_compid].hw; + parent_data[4 + j] =3D AT91_CLK_PD_HW(sama7d65_plls[pll_id][pll_compid]= .hw); } - PMC_FILL_TABLE(&parent_hws[4], tmp_parent_hws, - sama7d65_gck[i].pp_count); =20 hw =3D at91_clk_register_generated(regmap, &pmc_pcr_lock, &sama7d65_pcr_layout, sama7d65_gck[i].n, NULL, - parent_hws, mux_table, + parent_data, mux_table, num_parents, sama7d65_gck[i].id, &sama7d65_gck[i].r, @@ -1356,7 +1349,7 @@ static void __init sama7d65_pmc_setup(struct device_n= ode *np) of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sama7d65_pmc); kfree(alloc_mem); =20 - return; + goto put_main_xtal; =20 err_free: if (alloc_mem) { @@ -1366,6 +1359,8 @@ static void __init sama7d65_pmc_setup(struct device_n= ode *np) } =20 kfree(sama7d65_pmc); +put_main_xtal: + clk_put(main_xtal); } =20 /* Some clks are used for a clocksource */ --=20 2.43.0