From nobody Thu Oct 9 13:18:04 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B87EC2EB5CE; Tue, 17 Jun 2025 16:08:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750176532; cv=none; b=XW4+jlQvrROW16cW2EFIQ53vfKJKBapHbwibwEe9LHrw/IviL/LSc68GZRVAs/+z/YNflb+23KtY984Astz5c3OF+I2d89iOd6/XLgAGQNZmNlHEYcNcTXO2HnQrHhBTogtQE1D2vVdiq8/3M98LWsUYLtrzVcJ5DxEEClN/OMA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750176532; c=relaxed/simple; bh=4i2WXR/m+DKZimuqrflK/Htmu3/SzQoc8EbGnqOF56c=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=jqYZpPWy6FZGA7+kiqk/ZMdA9mV8CQxbymlZDHaZqx0X3MjlN8ZY4Ccp1+v/JDwRRkKpEJ7sqpNsucp6cGozemIIsIEPRqYi9nr2uNov672KI13FFbt0jwW9M/ULOqU+hzRwtwWFO5S4d1C5UpcHCsISI+3Q10bFJgj0uTFfVLc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=R+tG/LRY; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="R+tG/LRY" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1750176530; x=1781712530; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=4i2WXR/m+DKZimuqrflK/Htmu3/SzQoc8EbGnqOF56c=; b=R+tG/LRYz0Mz3UOR7KOsDnRDo7pQkZdnZai9zOmJqLQnqvWjmtumN68Y KiCmPCgktlfXcuu2Dk4GlnbS5ugFvTGKG4t4b5qk1R2Ag6laTFj4SNwbS oLxQQ4NMB5792O9OcGsKktsSvSkWmPmfURcTVbO74zIhIUgSiM3qVAlRP Q/NUXCM0Wfjd0EfY6QHHCnQ+K23m8vzILYcDWSdyOaReimmFIF1PgeNH+ kSQaScUmEQOd8RCmZQZZ/qZPXhNMrB8pVx+G9h8tEBoQyVte1vSOxVWRl 25qLFw3tHgP2wWd1x16v9w3MH+V/kntH8F4mZv1uVKBzzurF8+H9nzg3K g==; X-CSE-ConnectionGUID: nTbCTdliQ7eOQ0UC/OTqRA== X-CSE-MsgGUID: B0b4be4rQZaj37P5HU+uOw== X-IronPort-AV: E=Sophos;i="6.16,243,1744095600"; d="scan'208";a="210388666" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 17 Jun 2025 09:08:47 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Tue, 17 Jun 2025 09:08:24 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Tue, 17 Jun 2025 09:08:24 -0700 From: To: , , , , , CC: , , , Ryan Wanner Subject: [PATCH v5 1/3] ARM: dts: microchip: sama7g5: Adjust clock xtal phandle Date: Tue, 17 Jun 2025 09:08:40 -0700 Message-ID: <8a9ece664958d07b1be73b4b6676a2a2ee397a94.1750175453.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Ryan Wanner Adjust clock xtal phandles to match the new xtal phandle formatting. Signed-off-by: Ryan Wanner --- arch/arm/boot/dts/microchip/at91-sama7g5ek.dts | 18 ++++++++---------- arch/arm/boot/dts/microchip/sama7g5.dtsi | 9 ++++++--- 2 files changed, 14 insertions(+), 13 deletions(-) diff --git a/arch/arm/boot/dts/microchip/at91-sama7g5ek.dts b/arch/arm/boot= /dts/microchip/at91-sama7g5ek.dts index 2543599013b1..3924f62ff0fb 100644 --- a/arch/arm/boot/dts/microchip/at91-sama7g5ek.dts +++ b/arch/arm/boot/dts/microchip/at91-sama7g5ek.dts @@ -35,16 +35,6 @@ aliases { i2c2 =3D &i2c9; }; =20 - clocks { - slow_xtal { - clock-frequency =3D <32768>; - }; - - main_xtal { - clock-frequency =3D <24000000>; - }; - }; - gpio-keys { compatible =3D "gpio-keys"; =20 @@ -556,6 +546,10 @@ &i2s0 { pinctrl-0 =3D <&pinctrl_i2s0_default>; }; =20 +&main_xtal { + clock-frequency =3D <24000000>; +}; + &pdmc0 { #sound-dai-cells =3D <0>; microchip,mic-pos =3D , /* MIC 1 */ @@ -885,6 +879,10 @@ input@0 { }; }; =20 +&slow_xtal { + clock-frequency =3D <32768>; +}; + &spdifrx { pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_spdifrx_default>; diff --git a/arch/arm/boot/dts/microchip/sama7g5.dtsi b/arch/arm/boot/dts/m= icrochip/sama7g5.dtsi index 17bcdcf0cf4a..e128074137e0 100644 --- a/arch/arm/boot/dts/microchip/sama7g5.dtsi +++ b/arch/arm/boot/dts/microchip/sama7g5.dtsi @@ -117,19 +117,22 @@ map1 { }; =20 clocks { - slow_xtal: slow_xtal { + slow_xtal: clock-slowxtal { compatible =3D "fixed-clock"; + clock-output-names =3D "slow_xtal"; #clock-cells =3D <0>; }; =20 - main_xtal: main_xtal { + main_xtal: clock-mainxtal { compatible =3D "fixed-clock"; + clock-output-names =3D "main_xtal"; #clock-cells =3D <0>; }; =20 - usb_clk: usb_clk { + usb_clk: clock-usbclk { compatible =3D "fixed-clock"; #clock-cells =3D <0>; + clock-output-names =3D "usb_clk"; clock-frequency =3D <48000000>; }; }; --=20 2.43.0 From nobody Thu Oct 9 13:18:04 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 77CE82ED153; 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charset="utf-8" From: Ryan Wanner Add clock-output-names to the xtal nodes, so the driver can correctly register the main and slow xtal. This fixes the issue of the SoC clock driver not being able to find the main xtal and slow xtal correctly causing a bad clock tree. Fixes: 261dcfad1b59 ("ARM: dts: microchip: add sama7d65 SoC DT") Signed-off-by: Ryan Wanner --- arch/arm/boot/dts/microchip/sama7d65.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/= microchip/sama7d65.dtsi index d08d773b1cc5..f96b073a7db5 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -38,11 +38,13 @@ cpu0: cpu@0 { clocks { main_xtal: clock-mainxtal { compatible =3D "fixed-clock"; + clock-output-names =3D "main_xtal"; #clock-cells =3D <0>; }; =20 slow_xtal: clock-slowxtal { compatible =3D "fixed-clock"; + clock-output-names =3D "slow_xtal"; #clock-cells =3D <0>; }; }; --=20 2.43.0 From nobody Thu Oct 9 13:18:04 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A3F92EF2B1; Tue, 17 Jun 2025 16:08:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750176534; cv=none; b=sR4PZMXt+Af22Rgtbuno8cRt5DZ5FEMEuJSzzq4V+UMGcWyowluciRscPuuj8Sq4MMgle37CO0GE93iWeDzdQcHU1DehdasB4zBHbDo5AiXC8Ebs41xbftCRK96fugZPGNgihm+acd472DWi8iBm8dB3vnrSAkN4H/PL3M++46s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750176534; c=relaxed/simple; bh=nqsSXzEVo7LciP/E9QCITo+geSD6uCnlbwEd+v/NZZw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=V7T9QQRv1SzJuH50BSVwuN2CohFCbniKFDfhy+QmE3ykesyK1xUd49ogmesrfx5oj4+tInGMWrx0s1/ZQ/hdT/Xw3cs0kj0RAgbMnXgV9aIXyfx8QOADSNvbs9D2J5jiCtDDILhtTNegiHqaKkH3pFumL7SVn6XXp6DaMWE6biM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=h9Y1DMTJ; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="h9Y1DMTJ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1750176532; x=1781712532; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=nqsSXzEVo7LciP/E9QCITo+geSD6uCnlbwEd+v/NZZw=; b=h9Y1DMTJV3YGvV9JKcOs19EvydySD7kFDzi7z2eIDe4BfDbbLC0+kheW KttpA2HB6JRqEA1z2FC/6VuzA3UzRnmcu5KIVMyWMwnvFx08c6VkCX4kg eQnVCKsZT6ZetAToEUAciEerJd4wNhPZtdGgI3zQunRcR96CLl5fm8fbo EPnso+pGKlQVXrZFP4IPM1/ZExOj2gMnD0GqFLKozEY4t/ikpmYI3+CCO cSOmzq5AWdT2UWyZsqICIL4hw1lu5Hx+54/m85GPA1MA8ABO9v8ZCEl/M 4YD7kzd17/J9oTKdUFddWhHNqKLvMWAP6V4cpCRl5CwiOTPWUHRQysJ+a Q==; X-CSE-ConnectionGUID: nTbCTdliQ7eOQ0UC/OTqRA== X-CSE-MsgGUID: FFAlFapsSs2WBQXKChchzw== X-IronPort-AV: E=Sophos;i="6.16,243,1744095600"; d="scan'208";a="210388675" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 17 Jun 2025 09:08:49 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Tue, 17 Jun 2025 09:08:25 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Tue, 17 Jun 2025 09:08:25 -0700 From: To: , , , , , CC: , , , Ryan Wanner Subject: [PATCH v5 3/3] ARM: dts: microchip: sam9x7: Add clock name property Date: Tue, 17 Jun 2025 09:08:42 -0700 Message-ID: <036518968ac657b93e315bb550b822b59ae6f17c.1750175453.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Ryan Wanner Add clock-output-names to the xtal nodes, so the driver can correctly register the main and slow xtal. This fixes the issue of the SoC clock driver not being able to find the main xtal and slow xtal correctly causing a bad clock tree. Fixes: 41af45af8bc3 ("ARM: dts: at91: sam9x7: add device tree for SoC") Signed-off-by: Ryan Wanner --- arch/arm/boot/dts/microchip/sam9x7.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sam9x7.dtsi b/arch/arm/boot/dts/mi= crochip/sam9x7.dtsi index b217a908f525..114449e90720 100644 --- a/arch/arm/boot/dts/microchip/sam9x7.dtsi +++ b/arch/arm/boot/dts/microchip/sam9x7.dtsi @@ -45,11 +45,13 @@ cpu@0 { clocks { slow_xtal: clock-slowxtal { compatible =3D "fixed-clock"; + clock-output-names =3D "slow_xtal"; #clock-cells =3D <0>; }; =20 main_xtal: clock-mainxtal { compatible =3D "fixed-clock"; + clock-output-names =3D "main_xtal"; #clock-cells =3D <0>; }; }; --=20 2.43.0