From nobody Fri Oct 10 21:06:50 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E853729898D; Thu, 12 Jun 2025 15:17:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749741469; cv=none; b=i3dd2MHxqiGUX6u60G1zRmHmi8ADRBe+0YaHUk2mlUtXABh0GdxsEp86tAj2q3/E2ijOSNU9N2WE82+0n0hxwCcunWbHDYmTVbvUgbx+3gYKKNiAMQ7Atz5kX6Yq0an7NGWWsCRNbUPQkTpBF0uLbigmgFOXIwRINsrXZkPN+Lo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749741469; c=relaxed/simple; bh=12fECthY6pkGs+Y6n/4fbZ5eWnjF1raHBzKHenr6KjA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=uRZ2IBnZ1mzZ2AiuTdsKvP8+bGN6AefNyxjcAyezIImUCdkJpw7/NlcFy9FJJmby01cPUI3kU8p6Kk2FV+dzv9Rse5eRMQiBdGEu6d43wVEFVjIGE0CxMoYqps1MeqcTcphGCWYIHfhIzZ7YtncXBeRq5nYfDjs1i8fUvvCMrGY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ceGV069n; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ceGV069n" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8EC39C4CEF1; Thu, 12 Jun 2025 15:17:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1749741468; bh=12fECthY6pkGs+Y6n/4fbZ5eWnjF1raHBzKHenr6KjA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ceGV069nAXMj1R0JWOfcBYhLfetJ70/gc2BV93shds6zrYH3RjhHJqNQuLMbnQ7QM qBHeyKbV8uNuVPaw1ylPJZKO0+pLriYQ+4ivviAZbWH5aRMjT+F7I0KW4pNpxdKoMB N8i+SjrqmBgUSXMXFjR7cnMhx+ApM6T3FeMJlG7Pnsi1B0hnayNuNE+YN9R4xFTS6J lxFhMDJ624LQL40N9gdZ7yXXM2QxghSTGEYpwATOtu2s5m9EovbiRq5IB4G7mgPcw0 6INeKdtele5OQVrzkuJnSbkOV7MiBWaNj/bGAWjPvkdbKL2AZwUO1HFHufshdkbqk+ MdCg5tZLJeHhQ== Received: from mchehab by mail.kernel.org with local (Exim 4.98.2) (envelope-from ) id 1uPjgY-00000005EvC-2rrM; Thu, 12 Jun 2025 17:17:46 +0200 From: Mauro Carvalho Chehab To: Igor Mammedov , "Michael S . Tsirkin" Cc: Jonathan Cameron , Shiju Jose , qemu-arm@nongnu.org, qemu-devel@nongnu.org, Mauro Carvalho Chehab , "Ani Sinha" , "Dongjiu Geng" , "Paolo Bonzini" , "Peter Maydell" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Shannon Zhao" , "Yanan Wang" , "Zhao Liu" , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v10 (RESEND) 01/20] tests/acpi: virt: add an empty HEST file Date: Thu, 12 Jun 2025 17:17:25 +0200 Message-ID: X-Mailer: git-send-email 2.49.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: Mauro Carvalho Chehab Content-Type: text/plain; charset="utf-8" Such file will be used to track HEST table changes. For now, disallow HEST table check until we update it to the current data. Signed-off-by: Mauro Carvalho Chehab Acked-by: Igor Mammedov Reviewed-by: Jonathan Cameron --- tests/data/acpi/aarch64/virt/HEST | 0 tests/qtest/bios-tables-test-allowed-diff.h | 1 + 2 files changed, 1 insertion(+) create mode 100644 tests/data/acpi/aarch64/virt/HEST diff --git a/tests/data/acpi/aarch64/virt/HEST b/tests/data/acpi/aarch64/vi= rt/HEST new file mode 100644 index 000000000000..e69de29bb2d1 diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index dfb8523c8bf4..39901c58d647 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,2 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/aarch64/virt/HEST", --=20 2.49.0 From nobody Fri Oct 10 21:06:50 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AD17B2F433B; Thu, 12 Jun 2025 15:17:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749741468; cv=none; b=NBcuUHyQXKRaCkkRKdIzsqmZT467FuW8TwHAyZ+O+ELDm7WoVAwx0uDZCKaMFppHNArXwV/QbrMWBgmC7Psmo9h2aLkRR9dADPN/3Yf2SzuyTwgCToc7KHJTmloB50WN5++Eq0QMHOtECFnSfAAUIkJ9Xz+i9bIcUWXV4gILSNI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749741468; c=relaxed/simple; bh=aK27Gkfn9OFGufJJSptOJpvTy7cfsAOawnwDMBApJqU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bjMcNugAtf5rZvSKmZ+cbZV1OSzoRCuvV8hKBXnhydHesCX99FSPKsuY3pj7CrkRzhvcoG7b4upFPIm3lWbFhafsR34dlPIqp4wrbY0kUc0WqF8PMyLyl7Pc6svpAS8BGWG18ZFk4RbHFUhHold5PtStG0rn92NxXHc0VipkVp0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Gs1Hwq5N; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Gs1Hwq5N" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 89846C4CEEA; Thu, 12 Jun 2025 15:17:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1749741468; bh=aK27Gkfn9OFGufJJSptOJpvTy7cfsAOawnwDMBApJqU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Gs1Hwq5NSDfoLIYcEa245EJoIE9CRxRryCKssZbbBk9FMO6AF55JdHxnzEL2coZTd bAAxu2xlm3WeF5A7yyvT3t0CaCTzsTthrfR7dH2AiPThXLG8JGjFX4hZzbH4I0gL7r df8+bDPrsPB6WcSdvTROHogi1ZmV7iZkgHXYjDaM7bgMP/mSbSMkdhSy0rNbI6VAhV mckL4Kfl9lJxLh9/2I8PHi/PJX2yXsrPQ8atWGYMr7Kkp0JNUE66Fpx5DeoqeNEaDC mLUf5ZMy+Ms9e0CUDanc6dWVFlvN9j2N4iRPBagcCUatr/7nUfGWqjiQabPB0ZbA3o 5CzGwiuadzkhA== Received: from mchehab by mail.kernel.org with local (Exim 4.98.2) (envelope-from ) id 1uPjgY-00000005EvG-36qt; Thu, 12 Jun 2025 17:17:46 +0200 From: Mauro Carvalho Chehab To: Igor Mammedov , "Michael S . Tsirkin" Cc: Jonathan Cameron , Shiju Jose , qemu-arm@nongnu.org, qemu-devel@nongnu.org, Mauro Carvalho Chehab , "Ani Sinha" , "Dongjiu Geng" , "Paolo Bonzini" , "Peter Maydell" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Shannon Zhao" , "Yanan Wang" , "Zhao Liu" , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v10 (RESEND) 02/20] tests/qtest/bios-tables-test: extend to also check HEST table Date: Thu, 12 Jun 2025 17:17:26 +0200 Message-ID: <9ce77140500ef68cc939d63952c25579f711ea52.1749741085.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.49.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: Mauro Carvalho Chehab Content-Type: text/plain; charset="utf-8" Currently, aarch64 can generate a HEST table when loaded with -machine ras=3Don. Add support for it. Signed-off-by: Mauro Carvalho Chehab Reviewed-by: Igor Mammedov Reviewed-by: Jonathan Cameron --- tests/qtest/bios-tables-test.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c index 0b2bdf9d0d4c..61cddfa837b2 100644 --- a/tests/qtest/bios-tables-test.c +++ b/tests/qtest/bios-tables-test.c @@ -2122,7 +2122,7 @@ static void test_acpi_aarch64_virt_tcg(void) =20 data.smbios_cpu_max_speed =3D 2900; data.smbios_cpu_curr_speed =3D 2700; - test_acpi_one("-cpu cortex-a57 " + test_acpi_one("-cpu cortex-a57 -machine ras=3Don " "-smbios type=3D4,max-speed=3D2900,current-speed=3D2700"= , &data); free_test_data(&data); } --=20 2.49.0 From nobody Fri Oct 10 21:06:50 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E85A329898E; Thu, 12 Jun 2025 15:17:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749741469; cv=none; b=WeNG/O25xOU6ACzHwNTuMeDVX22jS0L2aLE6lfm0flrut0i9gSGIv0wr3Hfb2p6z4VqxGFGodWBUCOjJSUgaucTodXPQf2CFTNIqvn+l6Rthe12QjN+eG8wCUFzjrjbBkIvZULC7HaUBq/eugo9xeTYORo2Jl3Ylxnv1ngkbZ4Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749741469; c=relaxed/simple; bh=IADrYFANwdNZ1rY1HT52KolBlScr6ckE6a5syaX5oVY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=liIMYXyF9WOBueRO+/TYERVfqd5uV5Hx22Yzs5FSSmNo1Og3wVEurxeUABlZXVDRo98liwH/tNNw9QHj7TOJvICdPpsZtL85QZpCeD/BxA4exWXOR6qoqjwnA8Fq4kBxz2OfGSDADNlIVnL111J0x/wkBJdw1UI65NRsGvFOJA4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=FwRtQafi; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="FwRtQafi" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 89AFCC4CEEB; Thu, 12 Jun 2025 15:17:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1749741468; bh=IADrYFANwdNZ1rY1HT52KolBlScr6ckE6a5syaX5oVY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FwRtQafizvhHBnRTdXWuDuyqnQ2vrkcSLc894V2TYhXqOxNIHRNilE1HCfiiP0JbP kUbFcmO3sN2DLEZdPJSj4C4qWGOdLNj7BkHkYwIEIkLZa5FZ7ZE8+nDyUtuAiD0aiD wnp2z1Bw3GPQhWF16A35Tz0N0SyLCE38z7ijUFkAaEiaCxYah9gQXgEIwl36PXlQV8 92P9JeEWzQpvuYfvYBSULQx9L65zWGobJC5VPr+nUG84fNIahQPilL0uhCVq8B4XGR 3r5rGL+7VCodzj4vFEfL2P2nUEqNq5RiUDa+OSg+v/bf+8MrQoEyW1SHMnR7lh9S5+ diqiHdZJGq2mg== Received: from mchehab by mail.kernel.org with local (Exim 4.98.2) (envelope-from ) id 1uPjgY-00000005EvK-3Kwo; Thu, 12 Jun 2025 17:17:46 +0200 From: Mauro Carvalho Chehab To: Igor Mammedov , "Michael S . Tsirkin" Cc: Jonathan Cameron , Shiju Jose , qemu-arm@nongnu.org, qemu-devel@nongnu.org, Mauro Carvalho Chehab , "Ani Sinha" , "Dongjiu Geng" , "Paolo Bonzini" , "Peter Maydell" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Shannon Zhao" , "Yanan Wang" , "Zhao Liu" , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v10 (RESEND) 03/20] tests/acpi: virt: update HEST file with its current data Date: Thu, 12 Jun 2025 17:17:27 +0200 Message-ID: X-Mailer: git-send-email 2.49.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: Mauro Carvalho Chehab Content-Type: text/plain; charset="utf-8" Now that HEST table is checked for aarch64, add the current firmware file. Signed-off-by: Mauro Carvalho Chehab Acked-by: Igor Mammedov Reviewed-by: Jonathan Cameron --- tests/data/acpi/aarch64/virt/HEST | Bin 0 -> 132 bytes tests/qtest/bios-tables-test-allowed-diff.h | 1 - 2 files changed, 1 deletion(-) diff --git a/tests/data/acpi/aarch64/virt/HEST b/tests/data/acpi/aarch64/vi= rt/HEST index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..4c5d8c5b5da5b3241f93cd0839e= 94272bf6b1486 100644 GIT binary patch literal 132 zcmeZp4Gw8xU|?W;66afGL literal 0 HcmV?d00001 diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index 39901c58d647..dfb8523c8bf4 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,2 +1 @@ /* List of comma-separated changed AML files to ignore */ -"tests/data/acpi/aarch64/virt/HEST", --=20 2.49.0 From nobody Fri Oct 10 21:06:50 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2399D298CAE; Thu, 12 Jun 2025 15:17:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749741469; cv=none; b=A0DL6AA1lMMqbFV2uFviW+WowUwmsFkRSa0rRHXkw7cLDsjCszKlCe2eO35YmuErExamotOynDvC+sYtbQ6PtYKWesc84RPU0NIZ5za5IgFK04YIzUex8bsHV5aLQC39U3W5piwR5I9JqRtd8z4CBD4fKXtzYBU5j6TweILBcrQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749741469; c=relaxed/simple; bh=qT0ATk/szMufp7pLg3EjSMU6UchGJC4t7yLc86gnlkI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=h3/oSXvL0s1KxcX+x5DitVdGoYDiY5kAe+iq6EQhgRHIEPyW6CH/t7B0X2F9/5ZOl9KxpspUHO0irYhUYfOHEEeN0xTMVd7v9qCSLANdxHZ0jrELJAkhXbYUW6RyurvByrn72kKrfBembDdDnZ+5MEUW9G3goK5n9dbE1ElZN8E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=BMm5ZGn/; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="BMm5ZGn/" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A7DB8C4AF0B; Thu, 12 Jun 2025 15:17:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1749741468; bh=qT0ATk/szMufp7pLg3EjSMU6UchGJC4t7yLc86gnlkI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BMm5ZGn/AmZQBiV1AtepxMTZ+psNJkv/PIYHRK2NhVn+nruCRVyJUkG4X1iTGUz6s ZVBCuaCY1NPB9kX/z98uWcBl/q2pEUEQRTizAlwMpKdFS+FFrpj9fjDRIKxJc2A3ZL 6qQgGNd8dhbdMJuLbPmhjxMBeo7G+ws191ROkOUy25ZP3T1KmHU32dACYs10PLRv26 e1GTzOQQBVnCx25rb6nW7yxKpkpF/la8mZAMA27G6j/gjR12qMs7FcSFfUDtdYCWhW +WmuYvzkPtcHb7MOWwBppA92i6DbyZcD4Nwp4YWz9/TfF+qkVwTMP8VT+UqnMWJfDM NpM7QPgavwzPA== Received: from mchehab by mail.kernel.org with local (Exim 4.98.2) (envelope-from ) id 1uPjgY-00000005EvO-3ZDo; Thu, 12 Jun 2025 17:17:46 +0200 From: Mauro Carvalho Chehab To: Igor Mammedov , "Michael S . Tsirkin" Cc: Jonathan Cameron , Shiju Jose , qemu-arm@nongnu.org, qemu-devel@nongnu.org, Mauro Carvalho Chehab , "Ani Sinha" , "Dongjiu Geng" , "Paolo Bonzini" , "Peter Maydell" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Shannon Zhao" , "Yanan Wang" , "Zhao Liu" , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v10 (RESEND) 04/20] Revert "hw/acpi/ghes: Make ghes_record_cper_errors() static" Date: Thu, 12 Jun 2025 17:17:28 +0200 Message-ID: X-Mailer: git-send-email 2.49.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: Mauro Carvalho Chehab Content-Type: text/plain; charset="utf-8" The ghes_record_cper_errors() function was introduced to be used by other types of errors, as part of the error injection patch series. That's why it is not static. Make it non-static again to allow its usage outside ghes.c This reverts commit 611f3bdb20f7828b0813aa90d47d1275ef18329b. Signed-off-by: Mauro Carvalho Chehab Reviewed-by: Jonathan Cameron --- hw/acpi/ghes.c | 6 ++++-- include/hw/acpi/ghes.h | 2 ++ 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/hw/acpi/ghes.c b/hw/acpi/ghes.c index b85bb48195a0..b709c177cdea 100644 --- a/hw/acpi/ghes.c +++ b/hw/acpi/ghes.c @@ -390,8 +390,8 @@ static void get_hw_error_offsets(uint64_t ghes_addr, *read_ack_register_addr =3D ghes_addr + sizeof(uint64_t); } =20 -static void ghes_record_cper_errors(const void *cper, size_t len, - uint16_t source_id, Error **errp) +void ghes_record_cper_errors(const void *cper, size_t len, + uint16_t source_id, Error **errp) { uint64_t cper_addr =3D 0, read_ack_register_addr =3D 0, read_ack_regis= ter; AcpiGedState *acpi_ged_state; @@ -440,6 +440,8 @@ static void ghes_record_cper_errors(const void *cper, s= ize_t len, =20 /* Write the generic error data entry into guest memory */ cpu_physical_memory_write(cper_addr, cper, len); + + return; } =20 int acpi_ghes_memory_errors(uint16_t source_id, uint64_t physical_address) diff --git a/include/hw/acpi/ghes.h b/include/hw/acpi/ghes.h index 578a582203ce..39619a2457cb 100644 --- a/include/hw/acpi/ghes.h +++ b/include/hw/acpi/ghes.h @@ -75,6 +75,8 @@ void acpi_build_hest(GArray *table_data, GArray *hardware= _errors, void acpi_ghes_add_fw_cfg(AcpiGhesState *vms, FWCfgState *s, GArray *hardware_errors); int acpi_ghes_memory_errors(uint16_t source_id, uint64_t error_physical_ad= dr); +void ghes_record_cper_errors(const void *cper, size_t len, + uint16_t source_id, Error **errp); =20 /** * acpi_ghes_present: Report whether ACPI GHES table is present --=20 2.49.0 From nobody Fri Oct 10 21:06:50 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 26C70298CBC; Thu, 12 Jun 2025 15:17:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749741469; cv=none; b=CKYhNk868NYngzZypRLBgd825g4DwR8RVKhqHF4u550/eLYKpygmaCWTxyugmCs8RcTPxKe6VQwysPmq3GlJB561nF0p2nRVWadzqwBpZqAA50P2x/0FNMmvLQDfG1qcHuHHZ2IQftG+/Gcn4xWYUbKqB4miVUPtMKvbQ3QlXzY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749741469; c=relaxed/simple; bh=v7HJmkHLf698NY/CQGtVaWuW+ikOqSPuNvh4HPkC8Hk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=NmgiZHfu4BSLMMVwg8aAYKgkzehKgRR8LJ7yqptr538YZGvcLQ1MZXQffmCDoT41N3b592Cgrl1ZD7UOIzu9/2reRLyeLTjBhWNDhqD+7f9g+lkJiOhVjUCeZl/YqRyJfns91075/pdhSUfQ044R1BInbL1Z+MEpLVVs1lk+ygU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=stzj6yck; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="stzj6yck" Received: by smtp.kernel.org (Postfix) with ESMTPSA id BADB7C4CEF6; Thu, 12 Jun 2025 15:17:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1749741468; bh=v7HJmkHLf698NY/CQGtVaWuW+ikOqSPuNvh4HPkC8Hk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=stzj6yckrFgj0CqpIp2/6UdwvhQJ1bkl8HKsQz6xXRzf9dxTCSqULCmaRp7HC0bls QOEm3uYbUevlT8Kdg+pv3a1csem5rl3FTS0Zj987f+F2lVxzO832N9iTPVTqkM6wlN xCxhTrqQALm6QfpY2XwbSEL4n8XlupD8l7DDAYWB0wTPSZXVBd6uYe0RMwQJGVPzD1 rzdES+/XvkIIicK01AwVONacYisXO1pcoovwPxSeLZJ+6CSCvCpqS9PPtUGLG7tX0Q pYYYinV3lKe+pIAmyZtvGaIH9HjViTjKy6hPG/x646yyHRQLLWVnY4XuOmQFecrnNy ythBJ+gF9VRvg== Received: from mchehab by mail.kernel.org with local (Exim 4.98.2) (envelope-from ) id 1uPjgY-00000005EvS-3p2U; Thu, 12 Jun 2025 17:17:46 +0200 From: Mauro Carvalho Chehab To: Igor Mammedov , "Michael S . Tsirkin" Cc: Jonathan Cameron , Shiju Jose , qemu-arm@nongnu.org, qemu-devel@nongnu.org, Mauro Carvalho Chehab , "Ani Sinha" , "Dongjiu Geng" , "Paolo Bonzini" , "Peter Maydell" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Shannon Zhao" , "Yanan Wang" , "Zhao Liu" , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v10 (RESEND) 05/20] acpi/ghes: Cleanup the code which gets ghes ged state Date: Thu, 12 Jun 2025 17:17:29 +0200 Message-ID: <7e439f17eda73a534d15584d3ec0de11e717734c.1749741085.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.49.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: Mauro Carvalho Chehab Content-Type: text/plain; charset="utf-8" Move the check logic into a common function and simplify the code which checks if GHES is enabled and was properly setup. Signed-off-by: Mauro Carvalho Chehab Reviewed-by: Jonathan Cameron Reviewed-by: Igor Mammedov --- hw/acpi/ghes-stub.c | 7 ++++--- hw/acpi/ghes.c | 38 +++++++++++--------------------------- include/hw/acpi/ghes.h | 14 +++++++------- target/arm/kvm.c | 7 +++++-- 4 files changed, 27 insertions(+), 39 deletions(-) diff --git a/hw/acpi/ghes-stub.c b/hw/acpi/ghes-stub.c index 7cec1812dad9..40f660c246fe 100644 --- a/hw/acpi/ghes-stub.c +++ b/hw/acpi/ghes-stub.c @@ -11,12 +11,13 @@ #include "qemu/osdep.h" #include "hw/acpi/ghes.h" =20 -int acpi_ghes_memory_errors(uint16_t source_id, uint64_t physical_address) +int acpi_ghes_memory_errors(AcpiGhesState *ags, uint16_t source_id, + uint64_t physical_address) { return -1; } =20 -bool acpi_ghes_present(void) +AcpiGhesState *acpi_ghes_get_state(void) { - return false; + return NULL; } diff --git a/hw/acpi/ghes.c b/hw/acpi/ghes.c index b709c177cdea..84b891fd3dcf 100644 --- a/hw/acpi/ghes.c +++ b/hw/acpi/ghes.c @@ -360,18 +360,12 @@ void acpi_ghes_add_fw_cfg(AcpiGhesState *ags, FWCfgSt= ate *s, /* Create a read-write fw_cfg file for Address */ fw_cfg_add_file_callback(s, ACPI_HW_ERROR_ADDR_FW_CFG_FILE, NULL, NULL, NULL, &(ags->hw_error_le), sizeof(ags->hw_error_le), false); - - ags->present =3D true; } =20 static void get_hw_error_offsets(uint64_t ghes_addr, uint64_t *cper_addr, uint64_t *read_ack_register_addr) { - if (!ghes_addr) { - return; - } - /* * non-HEST version supports only one source, so no need to change * the start offset based on the source ID. Also, we can't validate @@ -390,35 +384,20 @@ static void get_hw_error_offsets(uint64_t ghes_addr, *read_ack_register_addr =3D ghes_addr + sizeof(uint64_t); } =20 -void ghes_record_cper_errors(const void *cper, size_t len, +void ghes_record_cper_errors(AcpiGhesState *ags, const void *cper, size_t = len, uint16_t source_id, Error **errp) { uint64_t cper_addr =3D 0, read_ack_register_addr =3D 0, read_ack_regis= ter; - AcpiGedState *acpi_ged_state; - AcpiGhesState *ags; =20 if (len > ACPI_GHES_MAX_RAW_DATA_LENGTH) { error_setg(errp, "GHES CPER record is too big: %zd", len); return; } =20 - acpi_ged_state =3D ACPI_GED(object_resolve_path_type("", TYPE_ACPI_GED, - NULL)); - if (!acpi_ged_state) { - error_setg(errp, "Can't find ACPI_GED object"); - return; - } - ags =3D &acpi_ged_state->ghes_state; - assert(ACPI_GHES_ERROR_SOURCE_COUNT =3D=3D 1); get_hw_error_offsets(le64_to_cpu(ags->hw_error_le), &cper_addr, &read_ack_register_addr); =20 - if (!cper_addr) { - error_setg(errp, "can not find Generic Error Status Block"); - return; - } - cpu_physical_memory_read(read_ack_register_addr, &read_ack_register, sizeof(read_ack_register)= ); =20 @@ -444,7 +423,8 @@ void ghes_record_cper_errors(const void *cper, size_t l= en, return; } =20 -int acpi_ghes_memory_errors(uint16_t source_id, uint64_t physical_address) +int acpi_ghes_memory_errors(AcpiGhesState *ags, uint16_t source_id, + uint64_t physical_address) { /* Memory Error Section Type */ const uint8_t guid[] =3D @@ -470,7 +450,7 @@ int acpi_ghes_memory_errors(uint16_t source_id, uint64_= t physical_address) acpi_ghes_build_append_mem_cper(block, physical_address); =20 /* Report the error */ - ghes_record_cper_errors(block->data, block->len, source_id, &errp); + ghes_record_cper_errors(ags, block->data, block->len, source_id, &errp= ); =20 g_array_free(block, true); =20 @@ -482,7 +462,7 @@ int acpi_ghes_memory_errors(uint16_t source_id, uint64_= t physical_address) return 0; } =20 -bool acpi_ghes_present(void) +AcpiGhesState *acpi_ghes_get_state(void) { AcpiGedState *acpi_ged_state; AcpiGhesState *ags; @@ -491,8 +471,12 @@ bool acpi_ghes_present(void) NULL)); =20 if (!acpi_ged_state) { - return false; + return NULL; } ags =3D &acpi_ged_state->ghes_state; - return ags->present; + + if (!ags->hw_error_le) { + return NULL; + } + return ags; } diff --git a/include/hw/acpi/ghes.h b/include/hw/acpi/ghes.h index 39619a2457cb..f96ac3e85ca2 100644 --- a/include/hw/acpi/ghes.h +++ b/include/hw/acpi/ghes.h @@ -66,7 +66,6 @@ enum { =20 typedef struct AcpiGhesState { uint64_t hw_error_le; - bool present; /* True if GHES is present at all on this board */ } AcpiGhesState; =20 void acpi_build_hest(GArray *table_data, GArray *hardware_errors, @@ -74,15 +73,16 @@ void acpi_build_hest(GArray *table_data, GArray *hardwa= re_errors, const char *oem_id, const char *oem_table_id); void acpi_ghes_add_fw_cfg(AcpiGhesState *vms, FWCfgState *s, GArray *hardware_errors); -int acpi_ghes_memory_errors(uint16_t source_id, uint64_t error_physical_ad= dr); -void ghes_record_cper_errors(const void *cper, size_t len, +int acpi_ghes_memory_errors(AcpiGhesState *ags, uint16_t source_id, + uint64_t error_physical_addr); +void ghes_record_cper_errors(AcpiGhesState *ags, const void *cper, size_t = len, uint16_t source_id, Error **errp); =20 /** - * acpi_ghes_present: Report whether ACPI GHES table is present + * acpi_ghes_get_state: Get a pointer for ACPI ghes state * - * Returns: true if the system has an ACPI GHES table and it is - * safe to call acpi_ghes_memory_errors() to record a memory error. + * Returns: a pointer to ghes state if the system has an ACPI GHES table, + * NULL, otherwise. */ -bool acpi_ghes_present(void); +AcpiGhesState *acpi_ghes_get_state(void); #endif diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 74fda8b80903..c2a7abb66433 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -2342,10 +2342,12 @@ void kvm_arch_on_sigbus_vcpu(CPUState *c, int code,= void *addr) { ram_addr_t ram_addr; hwaddr paddr; + AcpiGhesState *ags; =20 assert(code =3D=3D BUS_MCEERR_AR || code =3D=3D BUS_MCEERR_AO); =20 - if (acpi_ghes_present() && addr) { + ags =3D acpi_ghes_get_state(); + if (ags && addr) { ram_addr =3D qemu_ram_addr_from_host(addr); if (ram_addr !=3D RAM_ADDR_INVALID && kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)= ) { @@ -2363,7 +2365,8 @@ void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, v= oid *addr) */ if (code =3D=3D BUS_MCEERR_AR) { kvm_cpu_synchronize_state(c); - if (!acpi_ghes_memory_errors(ACPI_HEST_SRC_ID_SEA, paddr))= { + if (!acpi_ghes_memory_errors(ags, ACPI_HEST_SRC_ID_SEA, + paddr)) { kvm_inject_arm_sea(c); } else { error_report("failed to record the error"); --=20 2.49.0 From nobody Fri Oct 10 21:06:50 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 23B60298CB7; Thu, 12 Jun 2025 15:17:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749741469; cv=none; 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a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1749741468; bh=cXx1YyBaEjwhA/0QVa4jAY/Yzuttz0iQzax//jLHWBY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=qyr72F4Xjr+nds/dFrtVErZ83+qEKvLnn4b1p3e78UigoX+6mY3JKpMISMDEHWXUu 7Wfc3Nfx1qSGPTLdenlkEUSExCxP3JfeUpojptYu8zalLhvOPbQxD8HbBN2FLaWVFt JnkKKTaYEMhu/hOCzdreiZEPFRWrSjum1PU3QVkvB7B91IsrNjNcyzRk82N4au0Cu9 wJza8n69ThPNEsKbO/L+G7ilBnLDp10EmqazeKkfNdcgYMLqojoKR8s92t7MQnwRVN llH/GVKzVLB3iK+lwNwaFc6w74+CUrKFoQ5EWapbifCG2g0pt/DfWSK6RIgzs4dxcJ RWVYF/Q1Vy48A== Received: from mchehab by mail.kernel.org with local (Exim 4.98.2) (envelope-from ) id 1uPjgY-00000005EvW-44uS; Thu, 12 Jun 2025 17:17:46 +0200 From: Mauro Carvalho Chehab To: Igor Mammedov , "Michael S . Tsirkin" Cc: Jonathan Cameron , Shiju Jose , qemu-arm@nongnu.org, qemu-devel@nongnu.org, Mauro Carvalho Chehab , "Ani Sinha" , "Dongjiu Geng" , "Paolo Bonzini" , "Peter Maydell" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Shannon Zhao" , "Yanan Wang" , "Zhao Liu" , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v10 (RESEND) 06/20] acpi/ghes: prepare to change the way HEST offsets are calculated Date: Thu, 12 Jun 2025 17:17:30 +0200 Message-ID: <395335a058dac3cc2851af34cb0d795a47467dd1.1749741085.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.49.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: Mauro Carvalho Chehab Content-Type: text/plain; charset="utf-8" Add a new ags flag to change the way HEST offsets are calculated. Currently, offsets needed to store ACPI HEST offsets and read ack are calculated based on a previous knowledge from the logic which creates the HEST table. Such logic is not generic, not allowing to easily add more HEST entries nor replicates what OSPM does. As the next patches will be adding a more generic logic, add a new use_hest_addr, set to false, in preparation for such changes. Signed-off-by: Mauro Carvalho Chehab Reviewed-by: Jonathan Cameron Reviewed-by: Igor Mammedov --- hw/acpi/ghes.c | 39 ++++++++++++++++++++++++--------------- hw/arm/virt-acpi-build.c | 13 ++++++++++--- include/hw/acpi/ghes.h | 12 +++++++++++- 3 files changed, 45 insertions(+), 19 deletions(-) diff --git a/hw/acpi/ghes.c b/hw/acpi/ghes.c index 84b891fd3dcf..9243b5ad4acb 100644 --- a/hw/acpi/ghes.c +++ b/hw/acpi/ghes.c @@ -206,7 +206,8 @@ ghes_gen_err_data_uncorrectable_recoverable(GArray *blo= ck, * Initialize "etc/hardware_errors" and "etc/hardware_errors_addr" fw_cfg = blobs. * See docs/specs/acpi_hest_ghes.rst for blobs format. */ -static void build_ghes_error_table(GArray *hardware_errors, BIOSLinker *li= nker) +static void build_ghes_error_table(AcpiGhesState *ags, GArray *hardware_er= rors, + BIOSLinker *linker) { int i, error_status_block_offset; =20 @@ -251,13 +252,15 @@ static void build_ghes_error_table(GArray *hardware_e= rrors, BIOSLinker *linker) i * ACPI_GHES_MAX_RAW_DATA_LENGTH); } =20 - /* - * tell firmware to write hardware_errors GPA into - * hardware_errors_addr fw_cfg, once the former has been initialized. - */ - bios_linker_loader_write_pointer(linker, ACPI_HW_ERROR_ADDR_FW_CFG_FIL= E, 0, - sizeof(uint64_t), - ACPI_HW_ERROR_FW_CFG_FILE, 0); + if (!ags->use_hest_addr) { + /* + * Tell firmware to write hardware_errors GPA into + * hardware_errors_addr fw_cfg, once the former has been initializ= ed. + */ + bios_linker_loader_write_pointer(linker, ACPI_HW_ERROR_ADDR_FW_CFG= _FILE, + 0, sizeof(uint64_t), + ACPI_HW_ERROR_FW_CFG_FILE, 0); + } } =20 /* Build Generic Hardware Error Source version 2 (GHESv2) */ @@ -331,14 +334,15 @@ static void build_ghes_v2(GArray *table_data, } =20 /* Build Hardware Error Source Table */ -void acpi_build_hest(GArray *table_data, GArray *hardware_errors, +void acpi_build_hest(AcpiGhesState *ags, GArray *table_data, + GArray *hardware_errors, BIOSLinker *linker, const char *oem_id, const char *oem_table_id) { AcpiTable table =3D { .sig =3D "HEST", .rev =3D 1, .oem_id =3D oem_id, .oem_table_id =3D oem_table_id= }; =20 - build_ghes_error_table(hardware_errors, linker); + build_ghes_error_table(ags, hardware_errors, linker); =20 acpi_table_begin(&table, table_data); =20 @@ -357,9 +361,11 @@ void acpi_ghes_add_fw_cfg(AcpiGhesState *ags, FWCfgSta= te *s, fw_cfg_add_file(s, ACPI_HW_ERROR_FW_CFG_FILE, hardware_error->data, hardware_error->len); =20 - /* Create a read-write fw_cfg file for Address */ - fw_cfg_add_file_callback(s, ACPI_HW_ERROR_ADDR_FW_CFG_FILE, NULL, NULL, - NULL, &(ags->hw_error_le), sizeof(ags->hw_error_le), false); + if (!ags->use_hest_addr) { + /* Create a read-write fw_cfg file for Address */ + fw_cfg_add_file_callback(s, ACPI_HW_ERROR_ADDR_FW_CFG_FILE, NULL, = NULL, + NULL, &(ags->hw_error_le), sizeof(ags->hw_error_le), false); + } } =20 static void get_hw_error_offsets(uint64_t ghes_addr, @@ -395,8 +401,11 @@ void ghes_record_cper_errors(AcpiGhesState *ags, const= void *cper, size_t len, } =20 assert(ACPI_GHES_ERROR_SOURCE_COUNT =3D=3D 1); - get_hw_error_offsets(le64_to_cpu(ags->hw_error_le), - &cper_addr, &read_ack_register_addr); + + if (!ags->use_hest_addr) { + get_hw_error_offsets(le64_to_cpu(ags->hw_error_le), + &cper_addr, &read_ack_register_addr); + } =20 cpu_physical_memory_read(read_ack_register_addr, &read_ack_register, sizeof(read_ack_register)= ); diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 7e8e0f0298df..b57f1256c30f 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -942,9 +942,16 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildT= ables *tables) build_dbg2(tables_blob, tables->linker, vms); =20 if (vms->ras) { - acpi_add_table(table_offsets, tables_blob); - acpi_build_hest(tables_blob, tables->hardware_errors, tables->link= er, - vms->oem_id, vms->oem_table_id); + AcpiGedState *acpi_ged_state; + AcpiGhesState *ags; + + acpi_ged_state =3D ACPI_GED(vms->acpi_dev); + ags =3D &acpi_ged_state->ghes_state; + if (ags) { + acpi_add_table(table_offsets, tables_blob); + acpi_build_hest(ags, tables_blob, tables->hardware_errors, + tables->linker, vms->oem_id, vms->oem_table_id= ); + } } =20 if (ms->numa_state->num_nodes > 0) { diff --git a/include/hw/acpi/ghes.h b/include/hw/acpi/ghes.h index f96ac3e85ca2..411f592662af 100644 --- a/include/hw/acpi/ghes.h +++ b/include/hw/acpi/ghes.h @@ -64,11 +64,21 @@ enum { ACPI_GHES_ERROR_SOURCE_COUNT }; =20 +/* + * AcpiGhesState stores GPA values that will be used to fill HEST entries. + * + * When use_hest_addr is false, the GPA of the etc/hardware_errors firmware + * is stored at hw_error_le. This is the default on QEMU 9.x. + * + * An GPA value equal to zero means that GHES is not present. + */ typedef struct AcpiGhesState { uint64_t hw_error_le; + bool use_hest_addr; /* Currently, always false */ } AcpiGhesState; =20 -void acpi_build_hest(GArray *table_data, GArray *hardware_errors, +void acpi_build_hest(AcpiGhesState *ags, GArray *table_data, + GArray *hardware_errors, BIOSLinker *linker, const char *oem_id, const char *oem_table_id); void acpi_ghes_add_fw_cfg(AcpiGhesState *vms, FWCfgState *s, --=20 2.49.0 From nobody Fri Oct 10 21:06:50 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EACFA298990; Thu, 12 Jun 2025 15:17:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749741469; cv=none; b=JCSSg7hwJFwgIlG3lbYBA4yf/K3iuqjT06UX82pM8cosBeMX2HLDt4v2sqQzut3SIUW8K2b4rjzP8I4Vfolxgv7CCxbkaCyuoici1l7UwF4mkVgnvDs01EEvHDBKOxNNoHv/ynG0USJH/5nJ6tssruP4qMKlBDQnQdP1su+kN3c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749741469; c=relaxed/simple; bh=1N6hea/7ukAd+5GaVGFyPu+VhER4xnCVrmTaiBTUYb0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=cVSWcng+XnM+msm0rhStyVpmBfca9Yc6L1hLckin/NgTQPbxMXaVjz0Kltf6/l7QTK9eHeVlgccNIfrJFX0urcRbGOxGrMIbbmiztDe0SOOJrLmxVfqEIqomaAiOqjBlL1N38YHaKKWa+FyEcFONCOIdsxwlnsfsfHSykOvdgiA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=q1SxZrup; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="q1SxZrup" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C4755C4CEF7; Thu, 12 Jun 2025 15:17:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1749741468; bh=1N6hea/7ukAd+5GaVGFyPu+VhER4xnCVrmTaiBTUYb0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=q1SxZruptAuOs12qvd0H6OJYiEgDdo1o9oOAmryeNL7p3uIJqa0mmYenyB3220wBq /HguqattQkj3gDxcd5lMFZ2mpZ6RcHP2tdK2vxbdqDinzO3csUKXz8qmVSRhj/rjhS PSv5CJVD/zN5vL3Tbjpw2Y8/lbjUnxocLgE0JDCNwR19z1D58hmc6lghZng5Kox2yU abEN+wEH5KYessJpqAI08GU7/Ff2RCMWIvY91DaH4U/1FFOriSbBB5x028O0TOR+zG F9rEgcO6gt9PSspNnYk0QfjvyA+pUESYYeGNiYEbbpeB2rxtxw4uTFnAiILVmFnYCa urGfR7oRvAl7w== Received: from mchehab by mail.kernel.org with local (Exim 4.98.2) (envelope-from ) id 1uPjgZ-00000005Eva-08Z2; Thu, 12 Jun 2025 17:17:47 +0200 From: Mauro Carvalho Chehab To: Igor Mammedov , "Michael S . Tsirkin" Cc: Jonathan Cameron , Shiju Jose , qemu-arm@nongnu.org, qemu-devel@nongnu.org, Mauro Carvalho Chehab , "Ani Sinha" , "Dongjiu Geng" , "Paolo Bonzini" , "Peter Maydell" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Shannon Zhao" , "Yanan Wang" , "Zhao Liu" , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v10 (RESEND) 07/20] acpi/ghes: add a firmware file with HEST address Date: Thu, 12 Jun 2025 17:17:31 +0200 Message-ID: <31b533ac65fa4746ff3f21e74acf2ab1a78d8b7d.1749741085.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.49.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: Mauro Carvalho Chehab Content-Type: text/plain; charset="utf-8" Store HEST table address at GPA, placing its the start of the table at hest_addr_le variable. Signed-off-by: Mauro Carvalho Chehab Reviewed-by: Jonathan Cameron Reviewed-by: Igor Mammedov --- hw/acpi/ghes.c | 22 ++++++++++++++++++++-- include/hw/acpi/ghes.h | 6 +++++- 2 files changed, 25 insertions(+), 3 deletions(-) diff --git a/hw/acpi/ghes.c b/hw/acpi/ghes.c index 9243b5ad4acb..cbc96c1909f0 100644 --- a/hw/acpi/ghes.c +++ b/hw/acpi/ghes.c @@ -30,6 +30,7 @@ =20 #define ACPI_HW_ERROR_FW_CFG_FILE "etc/hardware_errors" #define ACPI_HW_ERROR_ADDR_FW_CFG_FILE "etc/hardware_errors_addr" +#define ACPI_HEST_ADDR_FW_CFG_FILE "etc/acpi_table_hest_addr" =20 /* The max size in bytes for one error block */ #define ACPI_GHES_MAX_RAW_DATA_LENGTH (1 * KiB) @@ -341,6 +342,9 @@ void acpi_build_hest(AcpiGhesState *ags, GArray *table_= data, { AcpiTable table =3D { .sig =3D "HEST", .rev =3D 1, .oem_id =3D oem_id, .oem_table_id =3D oem_table_id= }; + uint32_t hest_offset; + + hest_offset =3D table_data->len; =20 build_ghes_error_table(ags, hardware_errors, linker); =20 @@ -352,6 +356,17 @@ void acpi_build_hest(AcpiGhesState *ags, GArray *table= _data, ACPI_GHES_NOTIFY_SEA, ACPI_HEST_SRC_ID_SEA); =20 acpi_table_end(linker, &table); + + if (ags->use_hest_addr) { + /* + * Tell firmware to write into GPA the address of HEST via fw_cfg, + * once initialized. + */ + bios_linker_loader_write_pointer(linker, + ACPI_HEST_ADDR_FW_CFG_FILE, 0, + sizeof(uint64_t), + ACPI_BUILD_TABLE_FILE, hest_offse= t); + } } =20 void acpi_ghes_add_fw_cfg(AcpiGhesState *ags, FWCfgState *s, @@ -361,7 +376,10 @@ void acpi_ghes_add_fw_cfg(AcpiGhesState *ags, FWCfgSta= te *s, fw_cfg_add_file(s, ACPI_HW_ERROR_FW_CFG_FILE, hardware_error->data, hardware_error->len); =20 - if (!ags->use_hest_addr) { + if (ags->use_hest_addr) { + fw_cfg_add_file_callback(s, ACPI_HEST_ADDR_FW_CFG_FILE, NULL, NULL, + NULL, &(ags->hest_addr_le), sizeof(ags->hest_addr_le), false); + } else { /* Create a read-write fw_cfg file for Address */ fw_cfg_add_file_callback(s, ACPI_HW_ERROR_ADDR_FW_CFG_FILE, NULL, = NULL, NULL, &(ags->hw_error_le), sizeof(ags->hw_error_le), false); @@ -484,7 +502,7 @@ AcpiGhesState *acpi_ghes_get_state(void) } ags =3D &acpi_ged_state->ghes_state; =20 - if (!ags->hw_error_le) { + if (!ags->hw_error_le && !ags->hest_addr_le) { return NULL; } return ags; diff --git a/include/hw/acpi/ghes.h b/include/hw/acpi/ghes.h index 411f592662af..ea9baab764e2 100644 --- a/include/hw/acpi/ghes.h +++ b/include/hw/acpi/ghes.h @@ -70,9 +70,13 @@ enum { * When use_hest_addr is false, the GPA of the etc/hardware_errors firmware * is stored at hw_error_le. This is the default on QEMU 9.x. * - * An GPA value equal to zero means that GHES is not present. + * When use_hest_addr is true, the GPA of the HEST table is stored at + * hest_addr_le. This is the default for QEMU 10.x and above. + * + * Whe both GPA values are equal to zero means that GHES is not present. */ typedef struct AcpiGhesState { + uint64_t hest_addr_le; uint64_t hw_error_le; bool use_hest_addr; /* Currently, always false */ } AcpiGhesState; --=20 2.49.0 From nobody Fri Oct 10 21:06:50 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 52D30298CD9; Thu, 12 Jun 2025 15:17:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749741469; cv=none; b=WReJ/g4WgBS6pCU0GikRK6dwpZJ4GW2CGPn80jbd9+OwqKVzEuW70dWfj+1rwYJPY2MgwhH681H4/Arm4KahPob+keIHXLUm9LRrbIO8Rwmpt2G9sPXZMKf6VWsrNwx7YzH+VTsaAzT/r8TZr6TWVB6MOcYjh56xvM5GEU1Ko3k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749741469; c=relaxed/simple; bh=En1XCw7CQ7wHukGUv83xjyaNgB5I0qGNc6E86W7ACQ8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=g87zmFCGtGMx89Tx5U6StX0vviGsn3XyDxuI1+Zh6GcP2gC8S7xbSJDyA34HsgSDXErU+g+obR7wJBMjcp5u41JZ/ACZa2sWivV3dlD0gfqgUUtXBnj/Z6x/ixjD+c8VdxhGryx+/BA1XPdqFVePpWeWvuKVHmf9nAkjOANCJV0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=J1UwO7Oe; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="J1UwO7Oe" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 12FFEC4CEF2; Thu, 12 Jun 2025 15:17:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1749741469; bh=En1XCw7CQ7wHukGUv83xjyaNgB5I0qGNc6E86W7ACQ8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=J1UwO7OeZI5WxDWTP02yyeTZmYwekv0+P823TiLZxQAhbg9TDCl8CfabVWn9eDOnm ik1lTFga1c42kZmV2C1z3Ji6tAOmb6PZoBGsVxF5eCEyHs11Xe9gd30tdf7/pADWAn v0C6ka0NrkzY+tQ+MSFwzv0thqLxG8pBfj+uoedOrC8URMWW/LuCSYeVFn2Wq6KSA3 dxCtxKd4NcOBRFZ0m9Cav7Lr7sPDNhgoi4Aks0l8XEu8zG6nIuqqyUap4j6NSi7WGJ SxOdd384pCVBHyVNYVxnZRHBKlgVsk0ZK4sDp50zv99dIsvDnjaFjEvCsMvV59bH7+ ij/leH5qDygyQ== Received: from mchehab by mail.kernel.org with local (Exim 4.98.2) (envelope-from ) id 1uPjgZ-00000005Eve-0Ntg; Thu, 12 Jun 2025 17:17:47 +0200 From: Mauro Carvalho Chehab To: Igor Mammedov , "Michael S . Tsirkin" Cc: Jonathan Cameron , Shiju Jose , qemu-arm@nongnu.org, qemu-devel@nongnu.org, Mauro Carvalho Chehab , "Ani Sinha" , "Dongjiu Geng" , "Paolo Bonzini" , "Peter Maydell" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Shannon Zhao" , "Yanan Wang" , "Zhao Liu" , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v10 (RESEND) 08/20] acpi/ghes: Use HEST table offsets when preparing GHES records Date: Thu, 12 Jun 2025 17:17:32 +0200 Message-ID: X-Mailer: git-send-email 2.49.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: Mauro Carvalho Chehab Content-Type: text/plain; charset="utf-8" There are two pointers that are needed during error injection: 1. The start address of the CPER block to be stored; 2. The address of the read ack. It is preferable to calculate them from the HEST table. This allows checking the source ID, the size of the table and the type of the HEST error block structures. Yet, keep the old code, as this is needed for migration purposes from older QEMU versions. Signed-off-by: Mauro Carvalho Chehab Reviewed-by: Jonathan Cameron Reviewed-by: Igor Mammedov --- hw/acpi/ghes.c | 100 +++++++++++++++++++++++++++++++++++++++++ include/hw/acpi/ghes.h | 2 +- 2 files changed, 101 insertions(+), 1 deletion(-) diff --git a/hw/acpi/ghes.c b/hw/acpi/ghes.c index cbc96c1909f0..668ca72587c7 100644 --- a/hw/acpi/ghes.c +++ b/hw/acpi/ghes.c @@ -41,6 +41,12 @@ /* Address offset in Generic Address Structure(GAS) */ #define GAS_ADDR_OFFSET 4 =20 +/* + * ACPI spec 1.0b + * 5.2.3 System Description Table Header + */ +#define ACPI_DESC_HEADER_OFFSET 36 + /* * The total size of Generic Error Data Entry * ACPI 6.1/6.2: 18.3.2.7.1 Generic Error Data, @@ -61,6 +67,30 @@ */ #define ACPI_GHES_GESB_SIZE 20 =20 +/* + * See the memory layout map at docs/specs/acpi_hest_ghes.rst. + */ + +/* + * ACPI 6.1: 18.3.2.8 Generic Hardware Error Source version 2 + * Table 18-344 Generic Hardware Error Source version 2 (GHESv2) Structure + */ +#define HEST_GHES_V2_ENTRY_SIZE 92 + +/* + * ACPI 6.1: 18.3.2.8 Generic Hardware Error Source version 2 + * Table 18-344 Generic Hardware Error Source version 2 (GHESv2) Structure + * Read Ack Register + */ +#define GHES_READ_ACK_ADDR_OFF 64 + +/* + * ACPI 6.1: 18.3.2.7: Generic Hardware Error Source + * Table 18-341 Generic Hardware Error Source Structure + * Error Status Address + */ +#define GHES_ERR_STATUS_ADDR_OFF 20 + /* * Values for error_severity field */ @@ -408,6 +438,73 @@ static void get_hw_error_offsets(uint64_t ghes_addr, *read_ack_register_addr =3D ghes_addr + sizeof(uint64_t); } =20 +static void get_ghes_source_offsets(uint16_t source_id, + uint64_t hest_addr, + uint64_t *cper_addr, + uint64_t *read_ack_start_addr, + Error **errp) +{ + uint64_t hest_err_block_addr, hest_read_ack_addr; + uint64_t err_source_entry, error_block_addr; + uint32_t num_sources, i; + + hest_addr +=3D ACPI_DESC_HEADER_OFFSET; + + cpu_physical_memory_read(hest_addr, &num_sources, + sizeof(num_sources)); + num_sources =3D le32_to_cpu(num_sources); + + err_source_entry =3D hest_addr + sizeof(num_sources); + + /* + * Currently, HEST Error source navigates only for GHESv2 tables + */ + for (i =3D 0; i < num_sources; i++) { + uint64_t addr =3D err_source_entry; + uint16_t type, src_id; + + cpu_physical_memory_read(addr, &type, sizeof(type)); + type =3D le16_to_cpu(type); + + /* For now, we only know the size of GHESv2 table */ + if (type !=3D ACPI_GHES_SOURCE_GENERIC_ERROR_V2) { + error_setg(errp, "HEST: type %d not supported.", type); + return; + } + + /* Compare CPER source ID at the GHESv2 structure */ + addr +=3D sizeof(type); + cpu_physical_memory_read(addr, &src_id, sizeof(src_id)); + if (le16_to_cpu(src_id) =3D=3D source_id) { + break; + } + + err_source_entry +=3D HEST_GHES_V2_ENTRY_SIZE; + } + if (i =3D=3D num_sources) { + error_setg(errp, "HEST: Source %d not found.", source_id); + return; + } + + /* Navigate through table address pointers */ + hest_err_block_addr =3D err_source_entry + GHES_ERR_STATUS_ADDR_OFF + + GAS_ADDR_OFFSET; + + cpu_physical_memory_read(hest_err_block_addr, &error_block_addr, + sizeof(error_block_addr)); + error_block_addr =3D le64_to_cpu(error_block_addr); + + cpu_physical_memory_read(error_block_addr, cper_addr, + sizeof(*cper_addr)); + *cper_addr =3D le64_to_cpu(*cper_addr); + + hest_read_ack_addr =3D err_source_entry + GHES_READ_ACK_ADDR_OFF + + GAS_ADDR_OFFSET; + cpu_physical_memory_read(hest_read_ack_addr, read_ack_start_addr, + sizeof(*read_ack_start_addr)); + *read_ack_start_addr =3D le64_to_cpu(*read_ack_start_addr); +} + void ghes_record_cper_errors(AcpiGhesState *ags, const void *cper, size_t = len, uint16_t source_id, Error **errp) { @@ -423,6 +520,9 @@ void ghes_record_cper_errors(AcpiGhesState *ags, const = void *cper, size_t len, if (!ags->use_hest_addr) { get_hw_error_offsets(le64_to_cpu(ags->hw_error_le), &cper_addr, &read_ack_register_addr); + } else { + get_ghes_source_offsets(source_id, le64_to_cpu(ags->hest_addr_le), + &cper_addr, &read_ack_register_addr, errp); } =20 cpu_physical_memory_read(read_ack_register_addr, diff --git a/include/hw/acpi/ghes.h b/include/hw/acpi/ghes.h index ea9baab764e2..5265102ba51f 100644 --- a/include/hw/acpi/ghes.h +++ b/include/hw/acpi/ghes.h @@ -78,7 +78,7 @@ enum { typedef struct AcpiGhesState { uint64_t hest_addr_le; uint64_t hw_error_le; - bool use_hest_addr; /* Currently, always false */ + bool use_hest_addr; /* True if HEST address is present */ } AcpiGhesState; =20 void acpi_build_hest(AcpiGhesState *ags, GArray *table_data, --=20 2.49.0 From nobody Fri Oct 10 21:06:50 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D042299952; Thu, 12 Jun 2025 15:17:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Thu, 12 Jun 2025 15:17:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1749741469; bh=fslt9Hp7rK/OAg+jQImQC6ZBKgHxeGpygTcaXz3ySXo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=EetqQmg54h86GClC0MWyGvOFu0zJwwgkLnq2nhvT2j2mv5KZertOh+rdHenvjDpo5 qf3O3L5e+dozND4O2vNwyn4YRTZITYOqG64DMyvvyuPRkCguKt7DUS684RhyUu4C6q nqdSrVDxHRGRP5clJIEFJM/s+leKxqD5w1EcNc0AQiUEsjWBkFbHkHLie5eOIsi04u vyoJ5A6vZSZBf5WJSf2GIxea5maUh25lzz30JOUC/ct0hi9sHv3DwU4T1DlvZvcWgA oXGWfFhWh7YDWSV1nPefxrE3mPoHkxD1eAhIG4AfqEeW/6slLNJkqeF7fp/fn8Q9jR u0+CIm8DoigXw== Received: from mchehab by mail.kernel.org with local (Exim 4.98.2) (envelope-from ) id 1uPjgZ-00000005Evi-0ceP; Thu, 12 Jun 2025 17:17:47 +0200 From: Mauro Carvalho Chehab To: Igor Mammedov , "Michael S . Tsirkin" Cc: Jonathan Cameron , Shiju Jose , qemu-arm@nongnu.org, qemu-devel@nongnu.org, Mauro Carvalho Chehab , "Ani Sinha" , "Dongjiu Geng" , "Paolo Bonzini" , "Peter Maydell" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Shannon Zhao" , "Yanan Wang" , "Zhao Liu" , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v10 (RESEND) 09/20] acpi/ghes: don't hard-code the number of sources for HEST table Date: Thu, 12 Jun 2025 17:17:33 +0200 Message-ID: <65e5f85ed1bc7617ce9a655d2b1b906182e83d53.1749741085.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.49.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: Mauro Carvalho Chehab Content-Type: text/plain; charset="utf-8" The current code is actually dependent on having just one error structure with a single source, as any change there would cause migration issues. As the number of sources should be arch-dependent, as it will depend on what kind of notifications will exist, and how many errors can be reported at the same time, change the logic to be more flexible, allowing the number of sources to be defined when building the HEST table by the caller. Signed-off-by: Mauro Carvalho Chehab Reviewed-by: Jonathan Cameron Reviewed-by: Igor Mammedov --- hw/acpi/ghes.c | 39 +++++++++++++++++++++------------------ hw/arm/virt-acpi-build.c | 8 +++++++- include/hw/acpi/ghes.h | 17 ++++++++++++----- target/arm/kvm.c | 2 +- 4 files changed, 41 insertions(+), 25 deletions(-) diff --git a/hw/acpi/ghes.c b/hw/acpi/ghes.c index 668ca72587c7..f49d0d628fc4 100644 --- a/hw/acpi/ghes.c +++ b/hw/acpi/ghes.c @@ -238,17 +238,17 @@ ghes_gen_err_data_uncorrectable_recoverable(GArray *b= lock, * See docs/specs/acpi_hest_ghes.rst for blobs format. */ static void build_ghes_error_table(AcpiGhesState *ags, GArray *hardware_er= rors, - BIOSLinker *linker) + BIOSLinker *linker, int num_sources) { int i, error_status_block_offset; =20 /* Build error_block_address */ - for (i =3D 0; i < ACPI_GHES_ERROR_SOURCE_COUNT; i++) { + for (i =3D 0; i < num_sources; i++) { build_append_int_noprefix(hardware_errors, 0, sizeof(uint64_t)); } =20 /* Build read_ack_register */ - for (i =3D 0; i < ACPI_GHES_ERROR_SOURCE_COUNT; i++) { + for (i =3D 0; i < num_sources; i++) { /* * Initialize the value of read_ack_register to 1, so GHES can be * writable after (re)boot. @@ -263,13 +263,13 @@ static void build_ghes_error_table(AcpiGhesState *ags= , GArray *hardware_errors, =20 /* Reserve space for Error Status Data Block */ acpi_data_push(hardware_errors, - ACPI_GHES_MAX_RAW_DATA_LENGTH * ACPI_GHES_ERROR_SOURCE_COUNT); + ACPI_GHES_MAX_RAW_DATA_LENGTH * num_sources); =20 /* Tell guest firmware to place hardware_errors blob into RAM */ bios_linker_loader_alloc(linker, ACPI_HW_ERROR_FW_CFG_FILE, hardware_errors, sizeof(uint64_t), false); =20 - for (i =3D 0; i < ACPI_GHES_ERROR_SOURCE_COUNT; i++) { + for (i =3D 0; i < num_sources; i++) { /* * Tell firmware to patch error_block_address entries to point to * corresponding "Generic Error Status Block" @@ -295,12 +295,14 @@ static void build_ghes_error_table(AcpiGhesState *ags= , GArray *hardware_errors, } =20 /* Build Generic Hardware Error Source version 2 (GHESv2) */ -static void build_ghes_v2(GArray *table_data, - BIOSLinker *linker, - enum AcpiGhesNotifyType notify, - uint16_t source_id) +static void build_ghes_v2_entry(GArray *table_data, + BIOSLinker *linker, + const AcpiNotificationSourceId *notif_src, + uint16_t index, int num_sources) { uint64_t address_offset; + const uint16_t notify =3D notif_src->notify; + const uint16_t source_id =3D notif_src->source_id; =20 /* * Type: @@ -331,7 +333,7 @@ static void build_ghes_v2(GArray *table_data, address_offset + GAS_ADDR_OFFSET, sizeof(uint64_t), ACPI_HW_ERROR_FW_CFG_FILE, - source_id * sizeof(uint64_t)); + index * sizeof(uint64_t)); =20 /* Notification Structure */ build_ghes_hw_error_notification(table_data, notify); @@ -351,8 +353,7 @@ static void build_ghes_v2(GArray *table_data, address_offset + GAS_ADDR_OFFSET, sizeof(uint64_t), ACPI_HW_ERROR_FW_CFG_FILE, - (ACPI_GHES_ERROR_SOURCE_COUNT + source_= id) - * sizeof(uint64_t)); + (num_sources + index) * sizeof(uint64_t= )); =20 /* * Read Ack Preserve field @@ -368,22 +369,26 @@ static void build_ghes_v2(GArray *table_data, void acpi_build_hest(AcpiGhesState *ags, GArray *table_data, GArray *hardware_errors, BIOSLinker *linker, + const AcpiNotificationSourceId *notif_source, + int num_sources, const char *oem_id, const char *oem_table_id) { AcpiTable table =3D { .sig =3D "HEST", .rev =3D 1, .oem_id =3D oem_id, .oem_table_id =3D oem_table_id= }; uint32_t hest_offset; + int i; =20 hest_offset =3D table_data->len; =20 - build_ghes_error_table(ags, hardware_errors, linker); + build_ghes_error_table(ags, hardware_errors, linker, num_sources); =20 acpi_table_begin(&table, table_data); =20 /* Error Source Count */ - build_append_int_noprefix(table_data, ACPI_GHES_ERROR_SOURCE_COUNT, 4); - build_ghes_v2(table_data, linker, - ACPI_GHES_NOTIFY_SEA, ACPI_HEST_SRC_ID_SEA); + build_append_int_noprefix(table_data, num_sources, 4); + for (i =3D 0; i < num_sources; i++) { + build_ghes_v2_entry(table_data, linker, ¬if_source[i], i, num_s= ources); + } =20 acpi_table_end(linker, &table); =20 @@ -515,8 +520,6 @@ void ghes_record_cper_errors(AcpiGhesState *ags, const = void *cper, size_t len, return; } =20 - assert(ACPI_GHES_ERROR_SOURCE_COUNT =3D=3D 1); - if (!ags->use_hest_addr) { get_hw_error_offsets(le64_to_cpu(ags->hw_error_le), &cper_addr, &read_ack_register_addr); diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index b57f1256c30f..da3ebf403ef9 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -889,6 +889,10 @@ static void acpi_align_size(GArray *blob, unsigned ali= gn) g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); } =20 +static const AcpiNotificationSourceId hest_ghes_notify[] =3D { + { ACPI_HEST_SRC_ID_SYNC, ACPI_GHES_NOTIFY_SEA }, +}; + static void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) { @@ -950,7 +954,9 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTa= bles *tables) if (ags) { acpi_add_table(table_offsets, tables_blob); acpi_build_hest(ags, tables_blob, tables->hardware_errors, - tables->linker, vms->oem_id, vms->oem_table_id= ); + tables->linker, hest_ghes_notify, + ARRAY_SIZE(hest_ghes_notify), + vms->oem_id, vms->oem_table_id); } } =20 diff --git a/include/hw/acpi/ghes.h b/include/hw/acpi/ghes.h index 5265102ba51f..8c4b08433760 100644 --- a/include/hw/acpi/ghes.h +++ b/include/hw/acpi/ghes.h @@ -57,13 +57,18 @@ enum AcpiGhesNotifyType { ACPI_GHES_NOTIFY_RESERVED =3D 12 }; =20 -enum { - ACPI_HEST_SRC_ID_SEA =3D 0, - /* future ids go here */ - - ACPI_GHES_ERROR_SOURCE_COUNT +/* + * ID numbers used to fill HEST source ID field + */ +enum AcpiGhesSourceID { + ACPI_HEST_SRC_ID_SYNC, }; =20 +typedef struct AcpiNotificationSourceId { + enum AcpiGhesSourceID source_id; + enum AcpiGhesNotifyType notify; +} AcpiNotificationSourceId; + /* * AcpiGhesState stores GPA values that will be used to fill HEST entries. * @@ -84,6 +89,8 @@ typedef struct AcpiGhesState { void acpi_build_hest(AcpiGhesState *ags, GArray *table_data, GArray *hardware_errors, BIOSLinker *linker, + const AcpiNotificationSourceId * const notif_source, + int num_sources, const char *oem_id, const char *oem_table_id); void acpi_ghes_add_fw_cfg(AcpiGhesState *vms, FWCfgState *s, GArray *hardware_errors); diff --git a/target/arm/kvm.c b/target/arm/kvm.c index c2a7abb66433..2191db8af1ab 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -2365,7 +2365,7 @@ void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, v= oid *addr) */ if (code =3D=3D BUS_MCEERR_AR) { kvm_cpu_synchronize_state(c); - if (!acpi_ghes_memory_errors(ags, ACPI_HEST_SRC_ID_SEA, + if (!acpi_ghes_memory_errors(ags, ACPI_HEST_SRC_ID_SYNC, paddr)) { kvm_inject_arm_sea(c); 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Thu, 12 Jun 2025 17:17:47 +0200 From: Mauro Carvalho Chehab To: Igor Mammedov , "Michael S . Tsirkin" Cc: Jonathan Cameron , Shiju Jose , qemu-arm@nongnu.org, qemu-devel@nongnu.org, Mauro Carvalho Chehab , "Ani Sinha" , "Dongjiu Geng" , "Paolo Bonzini" , "Peter Maydell" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Shannon Zhao" , "Yanan Wang" , "Zhao Liu" , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v10 (RESEND) 10/20] acpi/ghes: add a notifier to notify when error data is ready Date: Thu, 12 Jun 2025 17:17:34 +0200 Message-ID: <93416a3f6804f8f4c42b55d379b8efd22e45bc26.1749741085.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.49.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: Mauro Carvalho Chehab Content-Type: text/plain; charset="utf-8" Some error injection notify methods are async, like GPIO notify. Add a notifier to be used when the error record is ready to be sent to the guest OS. Signed-off-by: Mauro Carvalho Chehab Reviewed-by: Jonathan Cameron Acked-by: Igor Mammedov --- hw/acpi/ghes.c | 5 ++++- include/hw/acpi/ghes.h | 3 +++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/hw/acpi/ghes.c b/hw/acpi/ghes.c index f49d0d628fc4..0135ac844bcf 100644 --- a/hw/acpi/ghes.c +++ b/hw/acpi/ghes.c @@ -510,6 +510,9 @@ static void get_ghes_source_offsets(uint16_t source_id, *read_ack_start_addr =3D le64_to_cpu(*read_ack_start_addr); } =20 +NotifierList acpi_generic_error_notifiers =3D + NOTIFIER_LIST_INITIALIZER(error_device_notifiers); + void ghes_record_cper_errors(AcpiGhesState *ags, const void *cper, size_t = len, uint16_t source_id, Error **errp) { @@ -550,7 +553,7 @@ void ghes_record_cper_errors(AcpiGhesState *ags, const = void *cper, size_t len, /* Write the generic error data entry into guest memory */ cpu_physical_memory_write(cper_addr, cper, len); =20 - return; + notifier_list_notify(&acpi_generic_error_notifiers, NULL); } =20 int acpi_ghes_memory_errors(AcpiGhesState *ags, uint16_t source_id, diff --git a/include/hw/acpi/ghes.h b/include/hw/acpi/ghes.h index 8c4b08433760..390943e46d99 100644 --- a/include/hw/acpi/ghes.h +++ b/include/hw/acpi/ghes.h @@ -24,6 +24,9 @@ =20 #include "hw/acpi/bios-linker-loader.h" #include "qapi/error.h" +#include "qemu/notify.h" + +extern NotifierList acpi_generic_error_notifiers; =20 /* * Values for Hardware Error Notification Type field --=20 2.49.0 From nobody Fri Oct 10 21:06:50 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4BC80298CD7; Thu, 12 Jun 2025 15:17:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749741469; cv=none; b=XvJdAxfO91mAAT0x6MVZ7PV8/4repTb9SRw9k+HlHtHbgTUqsRSiGFVhP+9+xkvDzMmBtSr8dmfTAelMf3EtdCJzW/nXqvb1LUxVla/R0i0HxsoCXrgVYFDN5bLMYn5gfWWiZQ88ddh29ANR+vXX8KWDOJGvwMqtWCJ1gddnp7E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749741469; c=relaxed/simple; bh=Ru70Z0gfk7r/ztNDvEUpiGKGD5w8V2rasl2zsjCvPA0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=B7ii/Q9p+qyQ7kLZqiuj7rAidSBdjvD86hl5kKNuI1JiDM4zTehmCE7GS9Pm0+dxALHIfljvmjRweJ4Guh5mSWR8MsbmLGqEU4WWt4VcFq6ThedB/UjYFYsjj8FdRZWSBECyOTTB/m4bs02duItdzvfpQMsjnKwio5KeQ/zzUT0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=gnwk1gdh; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="gnwk1gdh" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0A065C4AF09; Thu, 12 Jun 2025 15:17:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1749741469; bh=Ru70Z0gfk7r/ztNDvEUpiGKGD5w8V2rasl2zsjCvPA0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=gnwk1gdhM/3kbf8HHrU5zzhlH6cnS2A81Xtk2CK4MJethML2GjTybiMCalB6rD6J1 NNZulKG0y3Vc58Ul9XTmHOipZe6b9aw6+q1IHaQPWVgei06/q6JQuJWXlDIrS2xWel UDORctuaOCujSkInB0xcF56QjYvaLsG114CiNSW1/Lk0RtNnk+I7u61WD4Ke6uJd5Z a4POzcQTr28dT7PBgD++1WxFEg2O+mnns/9NzDYDo8ZBDADHT/whBDf93RUEb3wx0Y rWmCqjPyqY4a1lgf+LpTQl1dLyael+8vEWfniXfjpHJ8fSCVU+ZKjqupXayB5MXPt0 XimEFSiXxnBrw== Received: from mchehab by mail.kernel.org with local (Exim 4.98.2) (envelope-from ) id 1uPjgZ-00000005Evq-17RR; Thu, 12 Jun 2025 17:17:47 +0200 From: Mauro Carvalho Chehab To: Igor Mammedov , "Michael S . Tsirkin" Cc: Jonathan Cameron , Shiju Jose , qemu-arm@nongnu.org, qemu-devel@nongnu.org, Mauro Carvalho Chehab , "Ani Sinha" , "Dongjiu Geng" , "Paolo Bonzini" , "Peter Maydell" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Shannon Zhao" , "Yanan Wang" , "Zhao Liu" , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v10 (RESEND) 11/20] acpi/generic_event_device: Update GHES migration to cover hest addr Date: Thu, 12 Jun 2025 17:17:35 +0200 Message-ID: <8f07e0535b4b1d4ae11e643c1885b85f4bcdda6a.1749741085.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.49.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: Mauro Carvalho Chehab Content-Type: text/plain; charset="utf-8" The GHES migration logic should now support HEST table location too. Signed-off-by: Mauro Carvalho Chehab Reviewed-by: Jonathan Cameron Reviewed-by: Igor Mammedov --- hw/acpi/generic_event_device.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/hw/acpi/generic_event_device.c b/hw/acpi/generic_event_device.c index 7a62f8d5bca1..d292f61b4e41 100644 --- a/hw/acpi/generic_event_device.c +++ b/hw/acpi/generic_event_device.c @@ -386,6 +386,34 @@ static const VMStateDescription vmstate_ghes_state =3D= { } }; =20 +static const VMStateDescription vmstate_hest =3D { + .name =3D "acpi-hest", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT64(hest_addr_le, AcpiGhesState), + VMSTATE_END_OF_LIST() + }, +}; + +static bool hest_needed(void *opaque) +{ + AcpiGedState *s =3D opaque; + return s->ghes_state.hest_addr_le; +} + +static const VMStateDescription vmstate_hest_state =3D { + .name =3D "acpi-ged/hest", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D hest_needed, + .fields =3D (const VMStateField[]) { + VMSTATE_STRUCT(ghes_state, AcpiGedState, 1, + vmstate_hest, AcpiGhesState), + VMSTATE_END_OF_LIST() + } +}; + static const VMStateDescription vmstate_acpi_ged =3D { .name =3D "acpi-ged", .version_id =3D 1, @@ -398,6 +426,7 @@ static const VMStateDescription vmstate_acpi_ged =3D { &vmstate_memhp_state, &vmstate_cpuhp_state, &vmstate_ghes_state, + &vmstate_hest_state, NULL } }; --=20 2.49.0 From nobody Fri Oct 10 21:06:50 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5612C298CDC; Thu, 12 Jun 2025 15:17:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749741469; cv=none; b=tJhYvlCY6eZjC/QXL0sC+cEeCG8h9hwE7lKJL85L1Z6Px1oRvfWYYRhNxhQVPAPka3zy1Me0gXfhAuLW+Pr4gpZy/Rk9aiiJjb0LN6BHPtbwIbMOeZnYbdaBKiuigXncUywxYCQxSoR/EKNdmVOyDuGiU/zUrQ2d4S8RjEe6EYg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749741469; c=relaxed/simple; bh=ZtEXcjWPD0aNOQAtqxHuKiNURx4bS3DXUBi6+1xEqLw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Sj5ejJLt/Fxr2+mjfvNg87Yktk2mNC76CKTYivG+N5aQOITlliO3ujZ+RTzcCZ3QZqlI+PLDxueZwFXUKK/xcCDPcZe+mBSL6drYdQdjDgJPLkTweiY27ZAhdDy0cjfSJat9W7omGs95iWIBmRafDb+P6PzcThx78C07K2Iayho= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=DcfJxqRV; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="DcfJxqRV" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2A67EC116B1; Thu, 12 Jun 2025 15:17:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1749741469; bh=ZtEXcjWPD0aNOQAtqxHuKiNURx4bS3DXUBi6+1xEqLw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=DcfJxqRVTP1FSUs5WGe8WteUr3299GtHgegGRvZzoGupecSzejQc+VM2brNKjngvo h5g7oEys1HqnbbPmQ9WrQsJ3g+lAfCeN9dW06h/TQykeTZkPCu9zRKNjqpaO08HYmM 9FJ30b0SSWrFZ4SNeIHE32o3uG0XMytKJkkn4OibEk2EjyTxDYMT/onSJb15oEzHJu UEYUw/fqpFdL7qs5cHpn40MDNbXrOxu9v/byrccyvsmJW3nZ+/T0rMoFuVZiHbf4SG zk13YO4XbikQmzm7r3OLmrNM5l5tVlHoo4E5zRqKmkgcDxfR6JPsigE0/gkZq3ONNA rjlEmf5ny78tw== Received: from mchehab by mail.kernel.org with local (Exim 4.98.2) (envelope-from ) id 1uPjgZ-00000005Evu-1NGm; Thu, 12 Jun 2025 17:17:47 +0200 From: Mauro Carvalho Chehab To: Igor Mammedov , "Michael S . Tsirkin" Cc: Jonathan Cameron , Shiju Jose , qemu-arm@nongnu.org, qemu-devel@nongnu.org, Mauro Carvalho Chehab , "Ani Sinha" , "Dongjiu Geng" , "Paolo Bonzini" , "Peter Maydell" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Shannon Zhao" , "Yanan Wang" , "Zhao Liu" , Eduardo Habkost , Marcel Apfelbaum , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v10 (RESEND) 12/20] acpi/generic_event_device: add logic to detect if HEST addr is available Date: Thu, 12 Jun 2025 17:17:36 +0200 Message-ID: X-Mailer: git-send-email 2.49.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: Mauro Carvalho Chehab Content-Type: text/plain; charset="utf-8" Create a new property (x-has-hest-addr) and use it to detect if the GHES table offsets can be calculated from the HEST address (qemu 10.0 and upper) or via the legacy way via an offset obtained from the hardware_errors firmware file. Signed-off-by: Mauro Carvalho Chehab Reviewed-by: Jonathan Cameron Reviewed-by: Igor Mammedov --- hw/acpi/generic_event_device.c | 2 ++ hw/arm/virt-acpi-build.c | 18 ++++++++++++++++-- hw/core/machine.c | 2 ++ 3 files changed, 20 insertions(+), 2 deletions(-) diff --git a/hw/acpi/generic_event_device.c b/hw/acpi/generic_event_device.c index d292f61b4e41..3cf9dab0d01a 100644 --- a/hw/acpi/generic_event_device.c +++ b/hw/acpi/generic_event_device.c @@ -318,6 +318,8 @@ static void acpi_ged_send_event(AcpiDeviceIf *adev, Acp= iEventStatusBits ev) =20 static const Property acpi_ged_properties[] =3D { DEFINE_PROP_UINT32("ged-event", AcpiGedState, ged_event_bitmap, 0), + DEFINE_PROP_BOOL("x-has-hest-addr", AcpiGedState, + ghes_state.use_hest_addr, false), }; =20 static const VMStateDescription vmstate_memhp_state =3D { diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index da3ebf403ef9..3126234e657d 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -893,6 +893,10 @@ static const AcpiNotificationSourceId hest_ghes_notify= [] =3D { { ACPI_HEST_SRC_ID_SYNC, ACPI_GHES_NOTIFY_SEA }, }; =20 +static const AcpiNotificationSourceId hest_ghes_notify_10_0[] =3D { + { ACPI_HEST_SRC_ID_SYNC, ACPI_GHES_NOTIFY_SEA }, +}; + static void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) { @@ -947,15 +951,25 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuild= Tables *tables) =20 if (vms->ras) { AcpiGedState *acpi_ged_state; + static const AcpiNotificationSourceId *notify; + unsigned int notify_sz; AcpiGhesState *ags; =20 acpi_ged_state =3D ACPI_GED(vms->acpi_dev); ags =3D &acpi_ged_state->ghes_state; if (ags) { acpi_add_table(table_offsets, tables_blob); + + if (!ags->use_hest_addr) { + notify =3D hest_ghes_notify_10_0; + notify_sz =3D ARRAY_SIZE(hest_ghes_notify_10_0); + } else { + notify =3D hest_ghes_notify; + notify_sz =3D ARRAY_SIZE(hest_ghes_notify); + } + acpi_build_hest(ags, tables_blob, tables->hardware_errors, - tables->linker, hest_ghes_notify, - ARRAY_SIZE(hest_ghes_notify), + tables->linker, notify, notify_sz, vms->oem_id, vms->oem_table_id); } } diff --git a/hw/core/machine.c b/hw/core/machine.c index e869821b2246..6c5cf9781181 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -35,10 +35,12 @@ #include "hw/virtio/virtio-pci.h" #include "hw/virtio/virtio-net.h" #include "hw/virtio/virtio-iommu.h" +#include "hw/acpi/generic_event_device.h" #include "audio/audio.h" =20 GlobalProperty hw_compat_10_0[] =3D { { "scsi-hd", "dpofua", "off" }, + { TYPE_ACPI_GED, "x-has-hest-addr", "false" }, }; const size_t hw_compat_10_0_len =3D G_N_ELEMENTS(hw_compat_10_0); =20 --=20 2.49.0 From nobody Fri Oct 10 21:06:50 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 60F7D299929; Thu, 12 Jun 2025 15:17:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749741469; cv=none; b=BC7TA13rhHoI0TFeldFkyB3t5rBmdF5yYB4c/TcZ+c0lLz6wWeFTroKdutNU6tTQXQF9mAVx9g6+xnzbgiu7+uC400ASBHFvoHvlt2JljJvemxOFJRC4uCNH5ljGuTSnlgPU46iccOd5zGsE1CrzMZ5MwfezB7lhtuBGwfVzvfM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749741469; c=relaxed/simple; bh=kaCIzeErmY4eufPDExw2g8MBUSN3U8gwnatWi++NEFE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=OS8AasPtox7LYkahGESUt9blhxMadklkghQ2enw9XMPvOBABAgy+iRJsNiiA678TLsNZ4sO092qmuO879AyAVf6elQHB7sxEOAFPkqCn7xjhBpbhP5/RLKsVFlnHxWhRTViDZiBr3aeQ1sBJznWavQY9S/d3zCYpoV6b6tLgLUg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=cOMNOAR9; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="cOMNOAR9" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2902FC4CEFB; Thu, 12 Jun 2025 15:17:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1749741469; bh=kaCIzeErmY4eufPDExw2g8MBUSN3U8gwnatWi++NEFE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cOMNOAR9bW+gt7URBzVHdN/+Et3Vxs5TSnrFo3y6RxVVqKMe510ICrUbXrsyDKVFT EEs7RshggQzyT3FEZ+tasF5a+Fd1EBVREhH+0gZLfacEOKOwgTRKXQliYfDHujFp4y E+13iqyk72Ajskfjpbh9/HVzm4JWZ775GQ1z/jGYCVIUn2g6NhSDbWWFBMlj/gvPER XOkixfJTJnLcRsslNDvI9zBZ+avE0tZR0HNiu14nbTJyx+RwliROrtZpO6/ttWqtHz no/MzlZtfkDBuN5h421NCqqPlCqUkuafTvjQpcJfGGlwWq5k8wO2t6+2qQ5lS9pcxN UuVr9fxNQjscg== Received: from mchehab by mail.kernel.org with local (Exim 4.98.2) (envelope-from ) id 1uPjgZ-00000005Evy-1cws; Thu, 12 Jun 2025 17:17:47 +0200 From: Mauro Carvalho Chehab To: Igor Mammedov , "Michael S . Tsirkin" Cc: Jonathan Cameron , Shiju Jose , qemu-arm@nongnu.org, qemu-devel@nongnu.org, Mauro Carvalho Chehab , "Ani Sinha" , "Dongjiu Geng" , "Paolo Bonzini" , "Peter Maydell" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Shannon Zhao" , "Yanan Wang" , "Zhao Liu" , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v10 (RESEND) 13/20] acpi/generic_event_device: add an APEI error device Date: Thu, 12 Jun 2025 17:17:37 +0200 Message-ID: <7d0641ef01c6e9803ecb6b087d4c0a22f084155b.1749741085.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.49.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: Mauro Carvalho Chehab Content-Type: text/plain; charset="utf-8" Adds a generic error device to handle generic hardware error events as specified at ACPI 6.5 specification at 18.3.2.7.2: https://uefi.org/specs/ACPI/6.5/18_Platform_Error_Interfaces.html#event-not= ification-for-generic-error-sources using HID PNP0C33. The PNP0C33 device is used to report hardware errors to the guest via ACPI APEI Generic Hardware Error Source (GHES). Co-authored-by: Mauro Carvalho Chehab Co-authored-by: Jonathan Cameron Signed-off-by: Jonathan Cameron Signed-off-by: Mauro Carvalho Chehab Reviewed-by: Igor Mammedov --- hw/acpi/aml-build.c | 10 ++++++++++ hw/acpi/generic_event_device.c | 13 +++++++++++++ include/hw/acpi/acpi_dev_interface.h | 1 + include/hw/acpi/aml-build.h | 2 ++ include/hw/acpi/generic_event_device.h | 1 + 5 files changed, 27 insertions(+) diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c index f8f93a9f66c8..e4bd7b611372 100644 --- a/hw/acpi/aml-build.c +++ b/hw/acpi/aml-build.c @@ -2614,3 +2614,13 @@ Aml *aml_i2c_serial_bus_device(uint16_t address, con= st char *resource_source) =20 return var; } + +/* ACPI 5.0b: 18.3.2.6.2 Event Notification For Generic Error Sources */ +Aml *aml_error_device(void) +{ + Aml *dev =3D aml_device(ACPI_APEI_ERROR_DEVICE); + aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C33"))); + aml_append(dev, aml_name_decl("_UID", aml_int(0))); + + return dev; +} diff --git a/hw/acpi/generic_event_device.c b/hw/acpi/generic_event_device.c index 3cf9dab0d01a..620a1e0d6b01 100644 --- a/hw/acpi/generic_event_device.c +++ b/hw/acpi/generic_event_device.c @@ -26,6 +26,7 @@ static const uint32_t ged_supported_events[] =3D { ACPI_GED_PWR_DOWN_EVT, ACPI_GED_NVDIMM_HOTPLUG_EVT, ACPI_GED_CPU_HOTPLUG_EVT, + ACPI_GED_ERROR_EVT, }; =20 /* @@ -116,6 +117,16 @@ void build_ged_aml(Aml *table, const char *name, Hotpl= ugHandler *hotplug_dev, aml_notify(aml_name(ACPI_POWER_BUTTON_DEVICE), aml_int(0x80))); break; + case ACPI_GED_ERROR_EVT: + /* + * ACPI 5.0b: 5.6.6 Device Object Notifications + * Table 5-135 Error Device Notification Values + * Defines 0x80 as the value to be used on notifications + */ + aml_append(if_ctx, + aml_notify(aml_name(ACPI_APEI_ERROR_DEVICE), + aml_int(0x80))); + break; case ACPI_GED_NVDIMM_HOTPLUG_EVT: aml_append(if_ctx, aml_notify(aml_name("\\_SB.NVDR"), @@ -295,6 +306,8 @@ static void acpi_ged_send_event(AcpiDeviceIf *adev, Acp= iEventStatusBits ev) sel =3D ACPI_GED_MEM_HOTPLUG_EVT; } else if (ev & ACPI_POWER_DOWN_STATUS) { sel =3D ACPI_GED_PWR_DOWN_EVT; + } else if (ev & ACPI_GENERIC_ERROR) { + sel =3D ACPI_GED_ERROR_EVT; } else if (ev & ACPI_NVDIMM_HOTPLUG_STATUS) { sel =3D ACPI_GED_NVDIMM_HOTPLUG_EVT; } else if (ev & ACPI_CPU_HOTPLUG_STATUS) { diff --git a/include/hw/acpi/acpi_dev_interface.h b/include/hw/acpi/acpi_de= v_interface.h index 68d9d15f50aa..8294f8f0ccca 100644 --- a/include/hw/acpi/acpi_dev_interface.h +++ b/include/hw/acpi/acpi_dev_interface.h @@ -13,6 +13,7 @@ typedef enum { ACPI_NVDIMM_HOTPLUG_STATUS =3D 16, ACPI_VMGENID_CHANGE_STATUS =3D 32, ACPI_POWER_DOWN_STATUS =3D 64, + ACPI_GENERIC_ERROR =3D 128, } AcpiEventStatusBits; =20 #define TYPE_ACPI_DEVICE_IF "acpi-device-interface" diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h index c18f68134246..f38e12971932 100644 --- a/include/hw/acpi/aml-build.h +++ b/include/hw/acpi/aml-build.h @@ -252,6 +252,7 @@ struct CrsRangeSet { /* Consumer/Producer */ #define AML_SERIAL_BUS_FLAG_CONSUME_ONLY (1 << 1) =20 +#define ACPI_APEI_ERROR_DEVICE "GEDD" /** * init_aml_allocator: * @@ -382,6 +383,7 @@ Aml *aml_dma(AmlDmaType typ, AmlDmaBusMaster bm, AmlTra= nsferSize sz, uint8_t channel); Aml *aml_sleep(uint64_t msec); Aml *aml_i2c_serial_bus_device(uint16_t address, const char *resource_sour= ce); +Aml *aml_error_device(void); =20 /* Block AML object primitives */ Aml *aml_scope(const char *name_format, ...) G_GNUC_PRINTF(1, 2); diff --git a/include/hw/acpi/generic_event_device.h b/include/hw/acpi/gener= ic_event_device.h index d2dac87b4a9f..1c18ac296fcb 100644 --- a/include/hw/acpi/generic_event_device.h +++ b/include/hw/acpi/generic_event_device.h @@ -101,6 +101,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(AcpiGedState, ACPI_GED) #define ACPI_GED_PWR_DOWN_EVT 0x2 #define ACPI_GED_NVDIMM_HOTPLUG_EVT 0x4 #define ACPI_GED_CPU_HOTPLUG_EVT 0x8 +#define ACPI_GED_ERROR_EVT 0x10 =20 typedef struct GEDState { MemoryRegion evt; --=20 2.49.0 From nobody Fri Oct 10 21:06:50 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A378E299A8A; Thu, 12 Jun 2025 15:17:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749741469; cv=none; b=EUbv141SJGsSoLhQbHxAUuaxI2jN701e1v2zgozuO+qBvhhxUdMr5NJrsyrwpiYieK7U8rs/b1wWo72EnDPe7bpKyUQxX61A0kSnbC/uhRDgn7+a1/vGlpiGi2j5/pUcBj5zlGUSWu83wD3sj4pVpM/HxdCzbI5c6IvMe/o9B3U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749741469; c=relaxed/simple; bh=5800+9pcKbpwq9CBW/e+YLPVT84qYs9jAiAX5nQsi/M=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=d/zBdMtxf6xQcuzSW+F3Tl0Vva+F5C2XBj2dnr8gM+SEZ+D4jtZUAZ9LaNnCuG6byXkrCnIdaZ9oytBX2jc1eicYXwGDXm0+0wEhAqLn1Y/BRiFb2lapwGAgYcG83ZigQttzvzdedE3qeSt611zLTQXT5ZF8IAhh2l1QVRIcFOs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=HqkhG5J4; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="HqkhG5J4" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 38507C116D0; Thu, 12 Jun 2025 15:17:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1749741469; bh=5800+9pcKbpwq9CBW/e+YLPVT84qYs9jAiAX5nQsi/M=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HqkhG5J41imjPv1R5ZtN4zLsGMd+SJAwp0efcggHaslrKnhroV7BfEfNm3q56lo4j cizltsctWOzDiCKJ1h8ilyTVdeLebnqHebKBOb50a7MO80nVJKPiGf35HBDxxxuJ63 nGSoGoFwAqXYfzAilMQalDmYibTW/GJ9cVeLeEr46s3nfBonaNI/3YHlMTZG1c1+lD H0U1SAuLWp+Uc06m7u1/t1R1rk6V2LXEZf5AW/ELS7zh1CnZSWwWLpNSw2gjWe7rrG DtXra/v2IuqDFB8pwhac8I2lrTtKagU8IWe5P+5LMXwi5iRXsyAh187Ezbo4hImRbt wryGJdo+gN31Q== Received: from mchehab by mail.kernel.org with local (Exim 4.98.2) (envelope-from ) id 1uPjgZ-00000005Ew2-1rj9; Thu, 12 Jun 2025 17:17:47 +0200 From: Mauro Carvalho Chehab To: Igor Mammedov , "Michael S . Tsirkin" Cc: Jonathan Cameron , Shiju Jose , qemu-arm@nongnu.org, qemu-devel@nongnu.org, Mauro Carvalho Chehab , "Ani Sinha" , "Dongjiu Geng" , "Paolo Bonzini" , "Peter Maydell" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Shannon Zhao" , "Yanan Wang" , "Zhao Liu" , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v10 (RESEND) 14/20] tests/acpi: virt: allow acpi table changes at DSDT and HEST tables Date: Thu, 12 Jun 2025 17:17:38 +0200 Message-ID: X-Mailer: git-send-email 2.49.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: Mauro Carvalho Chehab Content-Type: text/plain; charset="utf-8" We'll be adding a new GED device for HEST GPIO notification and increasing the number of entries at the HEST table. Blocklist testing HEST and DSDT tables until such changes are completed. Signed-off-by: Mauro Carvalho Chehab Acked-by: Igor Mammedov Reviewed-by: Jonathan Cameron --- tests/qtest/bios-tables-test-allowed-diff.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index dfb8523c8bf4..0a1a26543ba2 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,7 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/aarch64/virt/HEST", +"tests/data/acpi/aarch64/virt/DSDT", +"tests/data/acpi/aarch64/virt/DSDT.acpihmatvirt", +"tests/data/acpi/aarch64/virt/DSDT.memhp", +"tests/data/acpi/aarch64/virt/DSDT.pxb", +"tests/data/acpi/aarch64/virt/DSDT.topology", --=20 2.49.0 From nobody Fri Oct 10 21:06:50 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7B70529994E; Thu, 12 Jun 2025 15:17:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749741469; cv=none; b=heZjxhH+oumX6HEpXkgOWiNM5RRMvChPpj+c3gaLdWuoSSwdeqabpSP/DPmx5vtXAOZChuxTzOFU7zdTjFeM/Swe1qtgDO4TsYdxj7ipFrK/pyn6IlyJ7PaJHOxC0UfERg56Wg4VSqS+H0dTsIm8Ngctz3ybOrxt6G268p2pO9I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749741469; c=relaxed/simple; bh=iqKzCLpBXkIFI6v1NlURAzof90ZSGexhmC5aANXLHhQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GLSrHnlba8j2JQLGrAXv3Wg+HttbIYOrSDWEXjzMsc16EKoPEKMe3gt9OdYHn0iP464K+FUemtiZYHSODZlUHU5ZUXaCwgh1ajKWPFyoPWA4d+WOu1StTsIfyfdQUM4JQ3a6hU5uuo1cd347mNioimx98w4R5seJqeiQRaxdtcI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ivbqrX2e; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ivbqrX2e" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4C021C113CF; Thu, 12 Jun 2025 15:17:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1749741469; bh=iqKzCLpBXkIFI6v1NlURAzof90ZSGexhmC5aANXLHhQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ivbqrX2eZ+mDL59O9crTVCtBzYStZpFK/IEHD4xeuUIp3dNxX3mfVZSGod2taY/ed dr7NOy15766W4oSRMCkOFH8kk3sl4sXXrwHBWo7kBQcyHhmQy6HDXvzkts8mSC8DPz mSU5gwsZUt9fF1k0V7VslvGj6oLV/qp0SO95gTw8Xaj8PWB3tMiAFC3l4jaQ2X988N Re6SuOn5OFTEbY1fGa4VMD1+Ta5KUuK/1eNAXqz69pcU1JBrH3bEUDy/6L4UqENa+a a/d8sIU3OOAzmsZs42VAkhvp+VaFTGbaF/VQUoF0Ko4+fy2AFpMpmj+tP3+pTe2ppG Lc6+MrMRlFW/g== Received: from mchehab by mail.kernel.org with local (Exim 4.98.2) (envelope-from ) id 1uPjgZ-00000005Ew6-27CH; Thu, 12 Jun 2025 17:17:47 +0200 From: Mauro Carvalho Chehab To: Igor Mammedov , "Michael S . Tsirkin" Cc: Jonathan Cameron , Shiju Jose , qemu-arm@nongnu.org, qemu-devel@nongnu.org, Mauro Carvalho Chehab , "Ani Sinha" , "Dongjiu Geng" , "Paolo Bonzini" , "Peter Maydell" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Shannon Zhao" , "Yanan Wang" , "Zhao Liu" , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v10 (RESEND) 15/20] arm/virt: Wire up a GED error device for ACPI / GHES Date: Thu, 12 Jun 2025 17:17:39 +0200 Message-ID: <8e8abaaea1d6058b0f9147dda355238f06704784.1749741085.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.49.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: Mauro Carvalho Chehab Content-Type: text/plain; charset="utf-8" Adds support to ARM virtualization to allow handling generic error ACPI Event via GED & error source device. It is aligned with Linux Kernel patch: https://lore.kernel.org/lkml/1272350481-27951-8-git-send-email-ying.huang@i= ntel.com/ Co-authored-by: Mauro Carvalho Chehab Co-authored-by: Jonathan Cameron Signed-off-by: Jonathan Cameron Signed-off-by: Mauro Carvalho Chehab Acked-by: Igor Mammedov Reviewed-by: Jonathan Cameron --- hw/arm/virt-acpi-build.c | 1 + hw/arm/virt.c | 12 +++++++++++- include/hw/arm/virt.h | 1 + 3 files changed, 13 insertions(+), 1 deletion(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 3126234e657d..33a701d6ad19 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -857,6 +857,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) } =20 acpi_dsdt_add_power_button(scope); + aml_append(scope, aml_error_device()); #ifdef CONFIG_TPM acpi_dsdt_add_tpm(scope, vms); #endif diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 9a6cd085a37a..e994809512f3 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -682,7 +682,7 @@ static inline DeviceState *create_acpi_ged(VirtMachineS= tate *vms) DeviceState *dev; MachineState *ms =3D MACHINE(vms); int irq =3D vms->irqmap[VIRT_ACPI_GED]; - uint32_t event =3D ACPI_GED_PWR_DOWN_EVT; + uint32_t event =3D ACPI_GED_PWR_DOWN_EVT | ACPI_GED_ERROR_EVT; =20 if (ms->ram_slots) { event |=3D ACPI_GED_MEM_HOTPLUG_EVT; @@ -1016,6 +1016,13 @@ static void virt_powerdown_req(Notifier *n, void *op= aque) } } =20 +static void virt_generic_error_req(Notifier *n, void *opaque) +{ + VirtMachineState *s =3D container_of(n, VirtMachineState, generic_erro= r_notifier); + + acpi_send_event(s->acpi_dev, ACPI_GENERIC_ERROR); +} + static void create_gpio_keys(char *fdt, DeviceState *pl061_dev, uint32_t phandle) { @@ -2398,6 +2405,9 @@ static void machvirt_init(MachineState *machine) =20 if (has_ged && aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)= ) { vms->acpi_dev =3D create_acpi_ged(vms); + vms->generic_error_notifier.notify =3D virt_generic_error_req; + notifier_list_add(&acpi_generic_error_notifiers, + &vms->generic_error_notifier); } else { create_gpio_devices(vms, VIRT_GPIO, sysmem); } diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 9a1b0f53d218..16b505604b2c 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -170,6 +170,7 @@ struct VirtMachineState { DeviceState *gic; DeviceState *acpi_dev; Notifier powerdown_notifier; + Notifier generic_error_notifier; PCIBus *bus; char *oem_id; char *oem_table_id; --=20 2.49.0 From nobody Fri Oct 10 21:06:50 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A5B15299A8C; Thu, 12 Jun 2025 15:17:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749741469; cv=none; b=pNih8XR53r3hehW7KSeJZuaUXOqgtvRGcKZsrC2enck8TBKY1HBj64Lv70JmYP3AOx4JAlzrrsn1x17xNFSCrQ5jZWyIgRRrtqcXyxCL/6Snb+6xd+uv8fj9zG4gTlyvFGWyZSr7VSJrVBOSwH3Y9voXkW2H8HIeDCnUTr4eDmc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749741469; c=relaxed/simple; bh=7JEVOBfsQwEv4HPCwN4F/mgrue19H6YVQqVRVcb1WGM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ZCl3OKEHH9boRSoWVvz8RcT3XGkE9uZEhx/RrZhNcF9/PwxKtNYMiPcjdxGxV3vs03GXNgSLHj0HKZY4Sux10joT8yEASm4r5Tuim12EyLtu6Zs2uod2hLP63FFQUDcI/+141AKDmlwCfjZ6XmXKe5THSAjU2peKwF/5ALy4dAQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=DUTb2ktd; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="DUTb2ktd" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5C711C116C6; Thu, 12 Jun 2025 15:17:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1749741469; bh=7JEVOBfsQwEv4HPCwN4F/mgrue19H6YVQqVRVcb1WGM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=DUTb2ktdeXtUc4gaDcaaM7qr7j9dK28V0tVnBscWAuSQ3+ZXsHrzkpkdInpAO4/fE zl8zkOJmcYACLB8yAaYAqKUPFY9mUw+qMpYnwyXU21vw2jLxnq+Al3eDULDS/Z6JJs VyN9MUj1rZhBNw5HYHs12Gusp6jkJk7QcRYFUEkHb1xiXKjsb9Kdt1KZs92Da2whfd 6YB1M828BftqsEuR6gVKKbK1IJpUzJyKm0g5zicA3WKZdauyixPMuhJFRTkc2UVN7C 9S9hT2YjOtsb4YPwcBJ5MORPlMXe2R5bYbGSZ7eQ4GmEPPv5Es6lfVgd9q/VHXido0 kAvCq5BJJcT5g== Received: from mchehab by mail.kernel.org with local (Exim 4.98.2) (envelope-from ) id 1uPjgZ-00000005EwA-2Nlt; Thu, 12 Jun 2025 17:17:47 +0200 From: Mauro Carvalho Chehab To: Igor Mammedov , "Michael S . Tsirkin" Cc: Jonathan Cameron , Shiju Jose , qemu-arm@nongnu.org, qemu-devel@nongnu.org, Mauro Carvalho Chehab , "Ani Sinha" , "Dongjiu Geng" , "Paolo Bonzini" , "Peter Maydell" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Shannon Zhao" , "Yanan Wang" , "Zhao Liu" , Eric Blake , Markus Armbruster , Michael Roth , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v10 (RESEND) 16/20] qapi/acpi-hest: add an interface to do generic CPER error injection Date: Thu, 12 Jun 2025 17:17:40 +0200 Message-ID: <5035b90e853b72e26842e1bc81ec8c08b00202d1.1749741085.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.49.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: Mauro Carvalho Chehab Content-Type: text/plain; charset="utf-8" Creates a QMP command to be used for generic ACPI APEI hardware error injection (HEST) via GHESv2, and add support for it for ARM guests. Error injection uses ACPI_HEST_SRC_ID_QMP source ID to be platform independent. This is mapped at arch virt bindings, depending on the types supported by QEMU and by the BIOS. So, on ARM, this is supported via ACPI_GHES_NOTIFY_GPIO notification type. This patch is co-authored: - original ghes logic to inject a simple ARM record by Shiju Jose; - generic logic to handle block addresses by Jonathan Cameron; - generic GHESv2 error inject by Mauro Carvalho Chehab; Co-authored-by: Jonathan Cameron Co-authored-by: Shiju Jose Co-authored-by: Mauro Carvalho Chehab Signed-off-by: Jonathan Cameron Signed-off-by: Shiju Jose Signed-off-by: Mauro Carvalho Chehab Acked-by: Igor Mammedov Acked-by: Markus Armbruster --- MAINTAINERS | 7 +++++++ hw/acpi/Kconfig | 5 +++++ hw/acpi/ghes.c | 2 +- hw/acpi/ghes_cper.c | 39 +++++++++++++++++++++++++++++++++++++++ hw/acpi/ghes_cper_stub.c | 20 ++++++++++++++++++++ hw/acpi/meson.build | 2 ++ hw/arm/virt-acpi-build.c | 1 + hw/arm/virt.c | 7 +++++++ include/hw/acpi/ghes.h | 1 + include/hw/arm/virt.h | 1 + qapi/acpi-hest.json | 35 +++++++++++++++++++++++++++++++++++ qapi/meson.build | 1 + qapi/qapi-schema.json | 1 + 13 files changed, 121 insertions(+), 1 deletion(-) create mode 100644 hw/acpi/ghes_cper.c create mode 100644 hw/acpi/ghes_cper_stub.c create mode 100644 qapi/acpi-hest.json diff --git a/MAINTAINERS b/MAINTAINERS index 28b3dd2684b4..30acbe89f5cc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2136,6 +2136,13 @@ F: hw/acpi/ghes.c F: include/hw/acpi/ghes.h F: docs/specs/acpi_hest_ghes.rst =20 +ACPI/HEST/GHES/ARM processor CPER +R: Mauro Carvalho Chehab +S: Maintained +F: hw/arm/ghes_cper.c +F: hw/acpi/ghes_cper_stub.c +F: qapi/acpi-hest.json + ppc4xx L: qemu-ppc@nongnu.org S: Orphan diff --git a/hw/acpi/Kconfig b/hw/acpi/Kconfig index 1d4e9f0845c0..daabbe6cd11e 100644 --- a/hw/acpi/Kconfig +++ b/hw/acpi/Kconfig @@ -51,6 +51,11 @@ config ACPI_APEI bool depends on ACPI =20 +config GHES_CPER + bool + depends on ACPI_APEI + default y + config ACPI_PCI bool depends on ACPI && PCI diff --git a/hw/acpi/ghes.c b/hw/acpi/ghes.c index 0135ac844bcf..1d02ef6dcb70 100644 --- a/hw/acpi/ghes.c +++ b/hw/acpi/ghes.c @@ -553,7 +553,7 @@ void ghes_record_cper_errors(AcpiGhesState *ags, const = void *cper, size_t len, /* Write the generic error data entry into guest memory */ cpu_physical_memory_write(cper_addr, cper, len); =20 - notifier_list_notify(&acpi_generic_error_notifiers, NULL); + notifier_list_notify(&acpi_generic_error_notifiers, &source_id); } =20 int acpi_ghes_memory_errors(AcpiGhesState *ags, uint16_t source_id, diff --git a/hw/acpi/ghes_cper.c b/hw/acpi/ghes_cper.c new file mode 100644 index 000000000000..1a391d85fc61 --- /dev/null +++ b/hw/acpi/ghes_cper.c @@ -0,0 +1,39 @@ +/* + * CPER payload parser for error injection + * + * Copyright(C) 2024-2025 Huawei LTD. + * + * This code is licensed under the GPL version 2 or later. See the + * COPYING file in the top-level directory. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" + +#include "qemu/base64.h" +#include "qemu/error-report.h" +#include "qemu/uuid.h" +#include "qapi/qapi-commands-acpi-hest.h" +#include "hw/acpi/ghes.h" + +void qmp_inject_ghes_v2_error(const char *qmp_cper, Error **errp) +{ + AcpiGhesState *ags; + + ags =3D acpi_ghes_get_state(); + if (!ags) { + return; + } + + uint8_t *cper; + size_t len; + + cper =3D qbase64_decode(qmp_cper, -1, &len, errp); + if (!cper) { + error_setg(errp, "missing GHES CPER payload"); + return; + } + + ghes_record_cper_errors(ags, cper, len, ACPI_HEST_SRC_ID_QMP, errp); +} diff --git a/hw/acpi/ghes_cper_stub.c b/hw/acpi/ghes_cper_stub.c new file mode 100644 index 000000000000..b16be73502db --- /dev/null +++ b/hw/acpi/ghes_cper_stub.c @@ -0,0 +1,20 @@ +/* + * Stub interface for CPER payload parser for error injection + * + * Copyright(C) 2024-2025 Huawei LTD. + * + * This code is licensed under the GPL version 2 or later. See the + * COPYING file in the top-level directory. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qapi/qapi-commands-acpi-hest.h" +#include "hw/acpi/ghes.h" + +void qmp_inject_ghes_v2_error(const char *cper, Error **errp) +{ + error_setg(errp, "GHES QMP error inject is not compiled in"); +} diff --git a/hw/acpi/meson.build b/hw/acpi/meson.build index 73f02b96912b..56b5d1ec9691 100644 --- a/hw/acpi/meson.build +++ b/hw/acpi/meson.build @@ -34,4 +34,6 @@ endif system_ss.add(when: 'CONFIG_ACPI', if_false: files('acpi-stub.c', 'aml-bui= ld-stub.c', 'ghes-stub.c', 'acpi_interface.c')) system_ss.add(when: 'CONFIG_ACPI_PCI_BRIDGE', if_false: files('pci-bridge-= stub.c')) system_ss.add_all(when: 'CONFIG_ACPI', if_true: acpi_ss) +system_ss.add(when: 'CONFIG_GHES_CPER', if_true: files('ghes_cper.c')) +system_ss.add(when: 'CONFIG_GHES_CPER', if_false: files('ghes_cper_stub.c'= )) system_ss.add(files('acpi-qmp-cmds.c')) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 33a701d6ad19..8a604b0b038b 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -892,6 +892,7 @@ static void acpi_align_size(GArray *blob, unsigned alig= n) =20 static const AcpiNotificationSourceId hest_ghes_notify[] =3D { { ACPI_HEST_SRC_ID_SYNC, ACPI_GHES_NOTIFY_SEA }, + { ACPI_HEST_SRC_ID_QMP, ACPI_GHES_NOTIFY_GPIO }, }; =20 static const AcpiNotificationSourceId hest_ghes_notify_10_0[] =3D { diff --git a/hw/arm/virt.c b/hw/arm/virt.c index e994809512f3..5832737b3827 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1018,6 +1018,13 @@ static void virt_powerdown_req(Notifier *n, void *op= aque) =20 static void virt_generic_error_req(Notifier *n, void *opaque) { + uint16_t *source_id =3D opaque; + + /* Currently, only QMP source ID is async */ + if (*source_id !=3D ACPI_HEST_SRC_ID_QMP) { + return; + } + VirtMachineState *s =3D container_of(n, VirtMachineState, generic_erro= r_notifier); =20 acpi_send_event(s->acpi_dev, ACPI_GENERIC_ERROR); diff --git a/include/hw/acpi/ghes.h b/include/hw/acpi/ghes.h index 390943e46d99..df2ecbf6e4a9 100644 --- a/include/hw/acpi/ghes.h +++ b/include/hw/acpi/ghes.h @@ -65,6 +65,7 @@ enum AcpiGhesNotifyType { */ enum AcpiGhesSourceID { ACPI_HEST_SRC_ID_SYNC, + ACPI_HEST_SRC_ID_QMP, /* Use it only for QMP injected errors */ }; =20 typedef struct AcpiNotificationSourceId { diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 16b505604b2c..1b70f7750ce9 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -33,6 +33,7 @@ #include "exec/hwaddr.h" #include "qemu/notify.h" #include "hw/boards.h" +#include "hw/acpi/ghes.h" #include "hw/arm/boot.h" #include "hw/arm/bsa.h" #include "hw/block/flash.h" diff --git a/qapi/acpi-hest.json b/qapi/acpi-hest.json new file mode 100644 index 000000000000..fff5018c7ec1 --- /dev/null +++ b/qapi/acpi-hest.json @@ -0,0 +1,35 @@ +# -*- Mode: Python -*- +# vim: filetype=3Dpython + +## +# =3D=3D GHESv2 CPER Error Injection +# +# Defined since ACPI Specification 6.1, +# section 18.3.2.8 Generic Hardware Error Source version 2. See: +# +# https://uefi.org/sites/default/files/resources/ACPI_6_1.pdf +## + + +## +# @inject-ghes-v2-error: +# +# Inject an error with additional ACPI 6.1 GHESv2 error information +# +# @cper: contains a base64 encoded string with raw data for a single +# CPER record with Generic Error Status Block, Generic Error Data +# Entry and generic error data payload, as described at +# https://uefi.org/specs/UEFI/2.10/Apx_N_Common_Platform_Error_Record.= html#format +# +# Features: +# +# @unstable: This command is experimental. +# +# Since: 10.0 +## +{ 'command': 'inject-ghes-v2-error', + 'data': { + 'cper': 'str' + }, + 'features': [ 'unstable' ] +} diff --git a/qapi/meson.build b/qapi/meson.build index 3b035aea339f..59be7e831133 100644 --- a/qapi/meson.build +++ b/qapi/meson.build @@ -58,6 +58,7 @@ qapi_all_modules =3D [ if have_system qapi_all_modules +=3D [ 'acpi', + 'acpi-hest', 'audio', 'cryptodev', 'qdev', diff --git a/qapi/qapi-schema.json b/qapi/qapi-schema.json index a8f66163cb70..05171d5a83c7 100644 --- a/qapi/qapi-schema.json +++ b/qapi/qapi-schema.json @@ -65,6 +65,7 @@ { 'include': 'misc-i386.json' } { 'include': 'audio.json' } { 'include': 'acpi.json' } +{ 'include': 'acpi-hest.json' } { 'include': 'pci.json' } { 'include': 'stats.json' } { 'include': 'virtio.json' } --=20 2.49.0 From nobody Fri Oct 10 21:06:50 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9545D299A81; Thu, 12 Jun 2025 15:17:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749741469; cv=none; b=MXdBFpNvtlsfvGeaOGvrDA7nuomBygU5mQYkrnBdbRxEY8nl2nJect0aQPgKq2ldtbx/k2bzHSQf/e9IpZAaWMephdUIKjoGEI3N+hN+NNVG2rNHxjCGtrXRD5w8MgvknkDgBwMfRHh9DykvQDlx28rsZ+K87nljEba6A4INfL8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749741469; c=relaxed/simple; bh=XDJZhmjHPDXPg7og3rQDpluO+ZElZEtkFB7TOHBZ6B8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=tZNOyYE6EiXiXns4NXSVvap6Xh0ZPTewnglbwN2wtHnyxzNaVEfATUgVjtoiCC0ZBBPzoXdXX8NDKN7mdd1L3y2wB/0bJTQuhVjgvAcNkKQy6mM0JT/OGaMLduxDHQ3Zqbsqsxbol2cVm/t9Spl3cS7cl7tfKeOZuiHR646+ALc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=O0XzS4Ss; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="O0XzS4Ss" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 693B1C19421; Thu, 12 Jun 2025 15:17:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1749741469; bh=XDJZhmjHPDXPg7og3rQDpluO+ZElZEtkFB7TOHBZ6B8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=O0XzS4Ss2eW7Ykyf+R9NN1+Wd7takcs7fLioxh5YnuBURZSy6NpMjPzMXIevf/s7E 82WxLzAtxGHbm0Vq5p0e7J7hGOUZipnFUVE4m+zaeVVhjTBVPhXV2I5bLkM3pfUUSe bt9LP4dUmbc0fUT9Blqf1Cz5VOakW427iRs5wgGo0rlvaxeyjBkK0rwzHNqB0TWqi2 5TCa0/EsoaiKs2cgcQgBDAhBxSuinKqL3DmkREcfrsJLxk16X2VhptFzBWO+keFnGD VtWLv0uRpZA2QCF7AdlAaPldounV3XuvUncXSsBjW5Zs/hkuLLTmydIjMppuINM1jQ j7MuiSjP5BvxQ== Received: from mchehab by mail.kernel.org with local (Exim 4.98.2) (envelope-from ) id 1uPjgZ-00000005EwE-2cjy; Thu, 12 Jun 2025 17:17:47 +0200 From: Mauro Carvalho Chehab To: Igor Mammedov , "Michael S . Tsirkin" Cc: Jonathan Cameron , Shiju Jose , qemu-arm@nongnu.org, qemu-devel@nongnu.org, Mauro Carvalho Chehab , "Ani Sinha" , "Dongjiu Geng" , "Paolo Bonzini" , "Peter Maydell" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Shannon Zhao" , "Yanan Wang" , "Zhao Liu" , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v10 (RESEND) 17/20] acpi/generic_event_device.c: enable use_hest_addr for QEMU 10.x Date: Thu, 12 Jun 2025 17:17:41 +0200 Message-ID: <9431b499f5902343652fea59c8612740eb41884c.1749741085.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.49.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: Mauro Carvalho Chehab Content-Type: text/plain; charset="utf-8" Now that we have everything in place, enable using HEST GPA instead of etc/hardware_errors GPA. Signed-off-by: Mauro Carvalho Chehab Reviewed-by: Jonathan Cameron Reviewed-by: Igor Mammedov --- hw/acpi/generic_event_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/acpi/generic_event_device.c b/hw/acpi/generic_event_device.c index 620a1e0d6b01..e9b344ef3e15 100644 --- a/hw/acpi/generic_event_device.c +++ b/hw/acpi/generic_event_device.c @@ -332,7 +332,7 @@ static void acpi_ged_send_event(AcpiDeviceIf *adev, Acp= iEventStatusBits ev) static const Property acpi_ged_properties[] =3D { DEFINE_PROP_UINT32("ged-event", AcpiGedState, ged_event_bitmap, 0), DEFINE_PROP_BOOL("x-has-hest-addr", AcpiGedState, - ghes_state.use_hest_addr, false), + ghes_state.use_hest_addr, true), }; =20 static const VMStateDescription vmstate_memhp_state =3D { --=20 2.49.0 From nobody Fri Oct 10 21:06:50 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C5B98299AAF; Thu, 12 Jun 2025 15:17:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749741469; cv=none; b=l8miqRys3Z3Jyll+OgbXPpWl+xWrqD1fE+4hjRyx+W0HL/wRkOQHf1Yhjws+LKmhGiiXqPDjh4KOp4oVdpXZtGMr85t3EAHma428oK067CwGxfrX0LNH45EgbOH3h7QUca+BtuZwbEd0wHcjimgtWWc+RSJsI5DoP1CE76oDhqI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749741469; c=relaxed/simple; bh=QSQ8I+MJuHnMxD/IL7FRa/YTRRnQ0jt7QVJt7qURdjg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=XcBpo6D5Q8C5Pa4rpAwd5/yNMYglVP5ZAlr7vsaIf6duPOqKm6y9poGSMmaE3ro56ngFOrfXcr5FVDrFgRjxrFiXbkeSelE0i94THSXRi4ep9w4jtmY2DHni4Rhq7dJJvNMztkcxYfRJLsbELnVQvRplJdH3B4+Lk9LRA/Zp46U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=aObe6YwS; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="aObe6YwS" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7D00CC4CEF6; Thu, 12 Jun 2025 15:17:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1749741469; bh=QSQ8I+MJuHnMxD/IL7FRa/YTRRnQ0jt7QVJt7qURdjg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=aObe6YwSVi6u6MGIxvokv3GroCc1JMpGIZw/QUAkLZ6YnEI0YGZe7KyV887TgxYlr GPkupsJG5AZxl15Ixj06SSObA/ZU6qMi9RFoI0Zo5tV5hdxgLmE2Jx8tV+RUmMYWYO p3GxpeBqIMqKwLfXrwhr+phVIIQgBQspnZtDZwSKIo8llisssDTLw9CXr7RV9Ou0/0 HbLV8m5yLkqlCtg5iBf2xQzjXkzVWF9agYq0TuhvWF7XPFWNf+9AZ6np3GLtikTmOw WUp6P0mUAmDifQJN05yzZTtk9yQrEhyqBL4HlRDYh+qDUWmdTg5zjkdZopIoG+CHA/ WA/CKTvvglipw== Received: from mchehab by mail.kernel.org with local (Exim 4.98.2) (envelope-from ) id 1uPjgZ-00000005EwI-2sMM; Thu, 12 Jun 2025 17:17:47 +0200 From: Mauro Carvalho Chehab To: Igor Mammedov , "Michael S . Tsirkin" Cc: Jonathan Cameron , Shiju Jose , qemu-arm@nongnu.org, qemu-devel@nongnu.org, Mauro Carvalho Chehab , "Ani Sinha" , "Dongjiu Geng" , "Paolo Bonzini" , "Peter Maydell" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Shannon Zhao" , "Yanan Wang" , "Zhao Liu" , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v10 (RESEND) 18/20] tests/acpi: virt: update HEST and DSDT tables Date: Thu, 12 Jun 2025 17:17:42 +0200 Message-ID: <2d4a162ef43ffa49ec43f75679cb112bec6f8f33.1749741085.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.49.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: Mauro Carvalho Chehab Content-Type: text/plain; charset="utf-8" @@ -1,39 +1,39 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20240322 (64-bit version) * Copyright (c) 2000 - 2023 Intel Corporation * - * Disassembly of tests/data/acpi/aarch64/virt/HEST + * Disassembly of /tmp/aml-DMPE22 * * ACPI Data Table [HEST] * * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue (i= n hex) */ [000h 0000 004h] Signature : "HEST" [Hardware Error S= ource Table] -[004h 0004 004h] Table Length : 00000084 +[004h 0004 004h] Table Length : 000000E0 [008h 0008 001h] Revision : 01 -[009h 0009 001h] Checksum : E2 +[009h 0009 001h] Checksum : 6C [00Ah 0010 006h] Oem ID : "BOCHS " [010h 0016 008h] Oem Table ID : "BXPC " [018h 0024 004h] Oem Revision : 00000001 [01Ch 0028 004h] Asl Compiler ID : "BXPC" [020h 0032 004h] Asl Compiler Revision : 00000001 -[024h 0036 004h] Error Source Count : 00000001 +[024h 0036 004h] Error Source Count : 00000002 [028h 0040 002h] Subtable Type : 000A [Generic Hardware Erro= r Source V2] [02Ah 0042 002h] Source Id : 0000 [02Ch 0044 002h] Related Source Id : FFFF [02Eh 0046 001h] Reserved : 00 [02Fh 0047 001h] Enabled : 01 [030h 0048 004h] Records To Preallocate : 00000001 [034h 0052 004h] Max Sections Per Record : 00000001 [038h 0056 004h] Max Raw Data Length : 00000400 [03Ch 0060 00Ch] Error Status Address : [Generic Address Structure] [03Ch 0060 001h] Space ID : 00 [SystemMemory] [03Dh 0061 001h] Bit Width : 40 [03Eh 0062 001h] Bit Offset : 00 [03Fh 0063 001h] Encoded Access Width : 04 [QWord Access:64] [040h 0064 008h] Address : 0000000043DA0000 @@ -42,32 +42,75 @@ [048h 0072 001h] Notify Type : 08 [SEA] [049h 0073 001h] Notify Length : 1C [04Ah 0074 002h] Configuration Write Enable : 0000 [04Ch 0076 004h] PollInterval : 00000000 [050h 0080 004h] Vector : 00000000 [054h 0084 004h] Polling Threshold Value : 00000000 [058h 0088 004h] Polling Threshold Window : 00000000 [05Ch 0092 004h] Error Threshold Value : 00000000 [060h 0096 004h] Error Threshold Window : 00000000 [064h 0100 004h] Error Status Block Length : 00000400 [068h 0104 00Ch] Read Ack Register : [Generic Address Structure] [068h 0104 001h] Space ID : 00 [SystemMemory] [069h 0105 001h] Bit Width : 40 [06Ah 0106 001h] Bit Offset : 00 [06Bh 0107 001h] Encoded Access Width : 04 [QWord Access:64] -[06Ch 0108 008h] Address : 0000000043DA0008 +[06Ch 0108 008h] Address : 0000000043DA0010 [074h 0116 008h] Read Ack Preserve : FFFFFFFFFFFFFFFE [07Ch 0124 008h] Read Ack Write : 0000000000000001 -Raw Table Data: Length 132 (0x84) +[084h 0132 002h] Subtable Type : 000A [Generic Hardware Erro= r Source V2] +[086h 0134 002h] Source Id : 0001 +[088h 0136 002h] Related Source Id : FFFF +[08Ah 0138 001h] Reserved : 00 +[08Bh 0139 001h] Enabled : 01 +[08Ch 0140 004h] Records To Preallocate : 00000001 +[090h 0144 004h] Max Sections Per Record : 00000001 +[094h 0148 004h] Max Raw Data Length : 00000400 + +[098h 0152 00Ch] Error Status Address : [Generic Address Structure] +[098h 0152 001h] Space ID : 00 [SystemMemory] +[099h 0153 001h] Bit Width : 40 +[09Ah 0154 001h] Bit Offset : 00 +[09Bh 0155 001h] Encoded Access Width : 04 [QWord Access:64] +[09Ch 0156 008h] Address : 0000000043DA0008 + +[0A4h 0164 01Ch] Notify : [Hardware Error Notificatio= n Structure] +[0A4h 0164 001h] Notify Type : 07 [GPIO] +[0A5h 0165 001h] Notify Length : 1C +[0A6h 0166 002h] Configuration Write Enable : 0000 +[0A8h 0168 004h] PollInterval : 00000000 +[0ACh 0172 004h] Vector : 00000000 +[0B0h 0176 004h] Polling Threshold Value : 00000000 +[0B4h 0180 004h] Polling Threshold Window : 00000000 +[0B8h 0184 004h] Error Threshold Value : 00000000 +[0BCh 0188 004h] Error Threshold Window : 00000000 + +[0C0h 0192 004h] Error Status Block Length : 00000400 +[0C4h 0196 00Ch] Read Ack Register : [Generic Address Structure] +[0C4h 0196 001h] Space ID : 00 [SystemMemory] +[0C5h 0197 001h] Bit Width : 40 +[0C6h 0198 001h] Bit Offset : 00 +[0C7h 0199 001h] Encoded Access Width : 04 [QWord Access:64] +[0C8h 0200 008h] Address : 0000000043DA0018 - 0000: 48 45 53 54 84 00 00 00 01 E2 42 4F 43 48 53 20 // HEST......BO= CHS +[0D0h 0208 008h] Read Ack Preserve : FFFFFFFFFFFFFFFE +[0D8h 0216 008h] Read Ack Write : 0000000000000001 + +Raw Table Data: Length 224 (0xE0) + @@ -1,30 +1,30 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20240322 (64-bit version) * Copyright (c) 2000 - 2023 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/aarch64/virt/DSDT + * Disassembly of /tmp/aml-TNQ912 * * Original Table Header: * Signature "DSDT" - * Length 0x0000144C (5196) + * Length 0x00001478 (5240) * Revision 0x02 - * Checksum 0x1B + * Checksum 0x04 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPC ", 0x00000001) { Scope (\_SB) { Device (C000) { Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID Name (_UID, Zero) // _UID: Unique ID } @@ -1876,27 +1876,38 @@ 0x00000029, } }) OperationRegion (EREG, SystemMemory, 0x09080000, 0x04) Field (EREG, DWordAcc, NoLock, WriteAsZeros) { ESEL, 32 } Method (_EVT, 1, Serialized) // _EVT: Event { Local0 =3D ESEL /* \_SB_.GED_.ESEL */ If (((Local0 & 0x02) =3D=3D 0x02)) { Notify (PWRB, 0x80) // Status Change } + + If (((Local0 & 0x10) =3D=3D 0x10)) + { + Notify (GEDD, 0x80) // Status Change + } } } Device (PWRB) { Name (_HID, "PNP0C0C" /* Power Button Device */) // _HID: Har= dware ID Name (_UID, Zero) // _UID: Unique ID } + + Device (GEDD) + { + Name (_HID, "PNP0C33" /* Error Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + } } } Signed-off-by: Mauro Carvalho Chehab Reviewed-by: Jonathan Cameron Acked-by: Igor Mammedov --- tests/data/acpi/aarch64/virt/DSDT | Bin 5196 -> 5240 bytes .../data/acpi/aarch64/virt/DSDT.acpihmatvirt | Bin 5282 -> 5326 bytes tests/data/acpi/aarch64/virt/DSDT.memhp | Bin 6557 -> 6601 bytes tests/data/acpi/aarch64/virt/DSDT.pxb | Bin 7679 -> 7723 bytes tests/data/acpi/aarch64/virt/DSDT.topology | Bin 5398 -> 5442 bytes tests/data/acpi/aarch64/virt/HEST | Bin 132 -> 224 bytes tests/qtest/bios-tables-test-allowed-diff.h | 6 ------ 7 files changed, 6 deletions(-) diff --git a/tests/data/acpi/aarch64/virt/DSDT b/tests/data/acpi/aarch64/vi= rt/DSDT index 36d3e5d5a5e47359b6dcb3706f98b4f225677591..a182bd9d7182dccdf63c650d048= c58f18505d001 100644 GIT binary patch delta 109 zcmX@3@k4{lCD}G*h$dM)euOOwJsW4+;nC=3D*7E+g>V+Q2D|zsED)Gn zoxsJ!z{S)S5FX^j)c_F?VBivHb9Z%dnXE4&D;?b=3D31V}^dw9C=3D2KWUSI2#)?aKwjt Hx-b9$X;vI^ delta 64 zcmeyNaYlp7CDV+Q2D|zsED)Gn UoxsJ!z{S)S5FX?-*+E1W06%jPR{#J2 diff --git a/tests/data/acpi/aarch64/virt/DSDT.acpihmatvirt b/tests/data/ac= pi/aarch64/virt/DSDT.acpihmatvirt index e6154d0355f84fdcc51387b4db8f9ee63acae4e9..af1f2b0eb0b77a80c5bd74f201d= 24f71e486627f 100644 GIT binary patch delta 110 zcmZ3ac}|ndCDc(oCIR8`a+lGdXii78eO-)SH|wBICY5U~+W=3DmjDBo yK%2X(iwjpnbdzL2c#soEyoaX?Z-8HbfwO@#14n$Qrwc=3DLlO#wDl9aJAR0;r(tsHj% delta 66 zcmX@7xk!`CCDE%Q&X{O%5jp|7vOwJsWyG4Q-^(NmJk>Ot;Fu6K`OMrn( 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Mauro Carvalho Chehab To: Igor Mammedov , "Michael S . Tsirkin" Cc: Jonathan Cameron , Shiju Jose , qemu-arm@nongnu.org, qemu-devel@nongnu.org, Mauro Carvalho Chehab , "Ani Sinha" , "Dongjiu Geng" , "Paolo Bonzini" , "Peter Maydell" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Shannon Zhao" , "Yanan Wang" , "Zhao Liu" , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v10 (RESEND) 19/20] docs: hest: add new "etc/acpi_table_hest_addr" and update workflow Date: Thu, 12 Jun 2025 17:17:43 +0200 Message-ID: X-Mailer: git-send-email 2.49.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: Mauro Carvalho Chehab Content-Type: text/plain; charset="utf-8" While the HEST layout didn't change, there are some internal changes related to how offsets are calculated and how memory error events are triggered. Update specs to reflect such changes. Signed-off-by: Mauro Carvalho Chehab Reviewed-by: Jonathan Cameron Reviewed-by: Igor Mammedov --- docs/specs/acpi_hest_ghes.rst | 28 +++++++++++++++++----------- 1 file changed, 17 insertions(+), 11 deletions(-) diff --git a/docs/specs/acpi_hest_ghes.rst b/docs/specs/acpi_hest_ghes.rst index c3e9f8d9a702..3d1b85d74b70 100644 --- a/docs/specs/acpi_hest_ghes.rst +++ b/docs/specs/acpi_hest_ghes.rst @@ -89,12 +89,21 @@ Design Details addresses in the "error_block_address" fields with a pointer to the respective "Error Status Data Block" in the "etc/hardware_errors" blob. =20 -(8) QEMU defines a third and write-only fw_cfg blob which is called - "etc/hardware_errors_addr". Through that blob, the firmware can send b= ack - the guest-side allocation addresses to QEMU. The "etc/hardware_errors_= addr" - blob contains a 8-byte entry. QEMU generates a single WRITE_POINTER co= mmand - for the firmware. The firmware will write back the start address of - "etc/hardware_errors" blob to the fw_cfg file "etc/hardware_errors_add= r". +(8) QEMU defines a third and write-only fw_cfg blob to store the location + where the error block offsets, read ack registers and CPER records are + stored. + + Up to QEMU 9.2, the location was at "etc/hardware_errors_addr", and + contains a GPA for the beginning of "etc/hardware_errors". + + Newer versions place the location at "etc/acpi_table_hest_addr", + pointing to the GPA of the HEST table. + + Using above mentioned 'fw_cfg' files, the firmware can send back the + guest-side allocation addresses to QEMU. They contain a 8-byte entry. + QEMU generates a single WRITE_POINTER command for the firmware. The + firmware will write back the start address of either "etc/hardware_err= ors" + or HEST table at the corresponding fw_cfg file. =20 (9) When QEMU gets a SIGBUS from the kernel, QEMU writes CPER into corresp= onding "Error Status Data Block", guest memory, and then injects platform spe= cific @@ -105,8 +114,5 @@ Design Details kernel, on receiving notification, guest APEI driver could read the C= PER error and take appropriate action. =20 -(11) kvm_arch_on_sigbus_vcpu() uses source_id as index in "etc/hardware_er= rors" to - find out "Error Status Data Block" entry corresponding to error sourc= e. So supported - source_id values should be assigned here and not be changed afterward= s to make sure - that guest will write error into expected "Error Status Data Block" e= ven if guest was - migrated to a newer QEMU. +(11) kvm_arch_on_sigbus_vcpu() report RAS errors via a SEA notifications, + when a SIGBUS event is triggered. --=20 2.49.0 From nobody Fri Oct 10 21:06:50 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E4BBB2BEC28; Thu, 12 Jun 2025 15:17:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749741473; cv=none; b=j+EsXeJCnQY8Zut7gk8t0bj9BXdolr2dSzRWINnlahucJ9WptJZsFaNPwvlb9rekQ8IgrguHwfzOsMZ605pF65I/Yi6SxMGdfHVyRhKY5dO41A+DW/XiUZTp7XosmgYZ24tBgg6Eje8eruHHdhXxwdjeIpsjx6u+Hyvl/gzJ+zI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749741473; c=relaxed/simple; bh=aMXdc8zVOp/1YkCFDVtL0XoKwSDR/Bai53NssJz8Zao=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=h1pUbYOgBoobmzW29hXxMuBVpuDAILk0SdSRACwtFP/IUw4DCK36s5vBA7XGtH0/ea+n+QNPVLVdePEKVNGe3LF37nddltEbwjoFu7DfPQJmRlkf2nXf6Pb2OMpLOFXwYBXuX2HYsAfgL1ethrB6B64VFgpxtFmwLhcDheryyFs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=utpS9S62; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="utpS9S62" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E6C44C4CEEA; Thu, 12 Jun 2025 15:17:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1749741472; bh=aMXdc8zVOp/1YkCFDVtL0XoKwSDR/Bai53NssJz8Zao=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=utpS9S629m+AvtQNcN+U4t3FZZ9ByluaaehuxthiWMwwxVhsU+i1o5SaHTnT8WNXn 86kneYXgK8pnU0C7y8WOi457A18x3g349GGOlBaWcea0uHkpuhxKIAW6skXeTyFESv lVMmcA8+O5JmxX1ST5UfMy/VM/q481FClrDF2b3KbtmOU9Xz7n1uH5jpg3hVoXRwZS +0AySDgu/vxHYA95vNGKSCeOPGxbOpGgP76+F7jUamW8m31MjUIXGSForI6q+d8Il/ 2XdlxbJduo82MMugD3TStmPp3rto9oasLpvFPuwn97mDLWb/HjVS5SD0Lkk5WH+np6 HhhX1KXnYth4Q== Received: from mchehab by mail.kernel.org with local (Exim 4.98.2) (envelope-from ) id 1uPjgZ-00000005EwQ-3M8O; Thu, 12 Jun 2025 17:17:47 +0200 From: Mauro Carvalho Chehab To: Igor Mammedov , "Michael S . Tsirkin" Cc: Jonathan Cameron , Shiju Jose , qemu-arm@nongnu.org, qemu-devel@nongnu.org, Mauro Carvalho Chehab , "Ani Sinha" , "Dongjiu Geng" , "Paolo Bonzini" , "Peter Maydell" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Shannon Zhao" , "Yanan Wang" , "Zhao Liu" , Cleber Rosa , John Snow , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v10 (RESEND) 20/20] scripts/ghes_inject: add a script to generate GHES error inject Date: Thu, 12 Jun 2025 17:17:44 +0200 Message-ID: <3a13c03e5a3e32e52f4c857607c233145da6c44d.1749741085.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.49.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: Mauro Carvalho Chehab Content-Type: text/plain; charset="utf-8" Using the QMP GHESv2 API requires preparing a raw data array containing a CPER record. Add a helper script with subcommands to prepare such data. Currently, only ARM Processor error CPER record is supported, by using: $ ghes_inject.py arm which produces those warnings on Linux: [ 705.032426] [Firmware Warn]: GHES: Unhandled processor error type 0x02: = cache error [ 774.866308] {4}[Hardware Error]: Hardware error from APEI Generic Hardwa= re Error Source: 1 [ 774.866583] {4}[Hardware Error]: event severity: recoverable [ 774.866738] {4}[Hardware Error]: Error 0, type: recoverable [ 774.866889] {4}[Hardware Error]: section_type: ARM processor error [ 774.867048] {4}[Hardware Error]: MIDR: 0x00000000000f0510 [ 774.867189] {4}[Hardware Error]: running state: 0x0 [ 774.867321] {4}[Hardware Error]: Power State Coordination Interface st= ate: 0 [ 774.867511] {4}[Hardware Error]: Error info structure 0: [ 774.867679] {4}[Hardware Error]: num errors: 2 [ 774.867801] {4}[Hardware Error]: error_type: 0x02: cache error [ 774.867962] {4}[Hardware Error]: error_info: 0x000000000091000f [ 774.868124] {4}[Hardware Error]: transaction type: Data Access [ 774.868280] {4}[Hardware Error]: cache error, operation type: Data w= rite [ 774.868465] {4}[Hardware Error]: cache level: 2 [ 774.868592] {4}[Hardware Error]: processor context not corrupted [ 774.868774] [Firmware Warn]: GHES: Unhandled processor error type 0x02: = cache error Such script allows customizing the error data, allowing to change all fields at the record. Please use: $ ghes_inject.py arm -h For more details about its usage. Signed-off-by: Mauro Carvalho Chehab Reviewed-by: Jonathan Cameron --- MAINTAINERS | 3 + scripts/arm_processor_error.py | 476 ++++++++++++++++++++++ scripts/ghes_inject.py | 51 +++ scripts/qmp_helper.py | 703 +++++++++++++++++++++++++++++++++ 4 files changed, 1233 insertions(+) create mode 100644 scripts/arm_processor_error.py create mode 100755 scripts/ghes_inject.py create mode 100755 scripts/qmp_helper.py diff --git a/MAINTAINERS b/MAINTAINERS index 30acbe89f5cc..6a9ec7d11d8a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2142,6 +2142,9 @@ S: Maintained F: hw/arm/ghes_cper.c F: hw/acpi/ghes_cper_stub.c F: qapi/acpi-hest.json +F: scripts/ghes_inject.py +F: scripts/arm_processor_error.py +F: scripts/qmp_helper.py =20 ppc4xx L: qemu-ppc@nongnu.org diff --git a/scripts/arm_processor_error.py b/scripts/arm_processor_error.py new file mode 100644 index 000000000000..1dd42e42a877 --- /dev/null +++ b/scripts/arm_processor_error.py @@ -0,0 +1,476 @@ +#!/usr/bin/env python3 +# +# pylint: disable=3DC0301,C0114,R0903,R0912,R0913,R0914,R0915,W0511 +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright (C) 2024-2025 Mauro Carvalho Chehab + +# TODO: current implementation has dummy defaults. +# +# For a better implementation, a QMP addition/call is needed to +# retrieve some data for ARM Processor Error injection: +# +# - ARM registers: power_state, mpidr. + +""" +Generates an ARM processor error CPER, compatible with +UEFI 2.9A Errata. + +Injecting such errors can be done using: + + $ ./scripts/ghes_inject.py arm + Error injected. + +Produces a simple CPER register, as detected on a Linux guest: + +[Hardware Error]: Hardware error from APEI Generic Hardware Error Source: 1 +[Hardware Error]: event severity: recoverable +[Hardware Error]: Error 0, type: recoverable +[Hardware Error]: section_type: ARM processor error +[Hardware Error]: MIDR: 0x0000000000000000 +[Hardware Error]: running state: 0x0 +[Hardware Error]: Power State Coordination Interface state: 0 +[Hardware Error]: Error info structure 0: +[Hardware Error]: num errors: 2 +[Hardware Error]: error_type: 0x02: cache error +[Hardware Error]: error_info: 0x000000000091000f +[Hardware Error]: transaction type: Data Access +[Hardware Error]: cache error, operation type: Data write +[Hardware Error]: cache level: 2 +[Hardware Error]: processor context not corrupted +[Firmware Warn]: GHES: Unhandled processor error type 0x02: cache error + +The ARM Processor Error message can be customized via command line +parameters. For instance: + + $ ./scripts/ghes_inject.py arm --mpidr 0x444 --running --affinity 1 \ + --error-info 12345678 --vendor 0x13,123,4,5,1 --ctx-array 0,1,2,3,= 4,5 \ + -t cache tlb bus micro-arch tlb,micro-arch + Error injected. + +Injects this error, as detected on a Linux guest: + +[Hardware Error]: Hardware error from APEI Generic Hardware Error Source: 1 +[Hardware Error]: event severity: recoverable +[Hardware Error]: Error 0, type: recoverable +[Hardware Error]: section_type: ARM processor error +[Hardware Error]: MIDR: 0x0000000000000000 +[Hardware Error]: Multiprocessor Affinity Register (MPIDR): 0x0000000000= 000000 +[Hardware Error]: error affinity level: 0 +[Hardware Error]: running state: 0x1 +[Hardware Error]: Power State Coordination Interface state: 0 +[Hardware Error]: Error info structure 0: +[Hardware Error]: num errors: 2 +[Hardware Error]: error_type: 0x02: cache error +[Hardware Error]: error_info: 0x0000000000bc614e +[Hardware Error]: cache level: 2 +[Hardware Error]: processor context not corrupted +[Hardware Error]: Error info structure 1: +[Hardware Error]: num errors: 2 +[Hardware Error]: error_type: 0x04: TLB error +[Hardware Error]: error_info: 0x000000000054007f +[Hardware Error]: transaction type: Instruction +[Hardware Error]: TLB error, operation type: Instruction fetch +[Hardware Error]: TLB level: 1 +[Hardware Error]: processor context not corrupted +[Hardware Error]: the error has not been corrected +[Hardware Error]: PC is imprecise +[Hardware Error]: Error info structure 2: +[Hardware Error]: num errors: 2 +[Hardware Error]: error_type: 0x08: bus error +[Hardware Error]: error_info: 0x00000080d6460fff +[Hardware Error]: transaction type: Generic +[Hardware Error]: bus error, operation type: Generic read (type of ins= truction or data request cannot be determined) +[Hardware Error]: affinity level at which the bus error occurred: 1 +[Hardware Error]: processor context corrupted +[Hardware Error]: the error has been corrected +[Hardware Error]: PC is imprecise +[Hardware Error]: Program execution can be restarted reliably at the P= C associated with the error. +[Hardware Error]: participation type: Local processor observed +[Hardware Error]: request timed out +[Hardware Error]: address space: External Memory Access +[Hardware Error]: memory access attributes:0x20 +[Hardware Error]: access mode: secure +[Hardware Error]: Error info structure 3: +[Hardware Error]: num errors: 2 +[Hardware Error]: error_type: 0x10: micro-architectural error +[Hardware Error]: error_info: 0x0000000078da03ff +[Hardware Error]: Error info structure 4: +[Hardware Error]: num errors: 2 +[Hardware Error]: error_type: 0x14: TLB error|micro-architectural error +[Hardware Error]: Context info structure 0: +[Hardware Error]: register context type: AArch64 EL1 context registers +[Hardware Error]: 00000000: 00000000 00000000 +[Hardware Error]: Vendor specific error info has 5 bytes: +[Hardware Error]: 00000000: 13 7b 04 05 01 = .{... +[Firmware Warn]: GHES: Unhandled processor error type 0x02: cache error +[Firmware Warn]: GHES: Unhandled processor error type 0x04: TLB error +[Firmware Warn]: GHES: Unhandled processor error type 0x08: bus error +[Firmware Warn]: GHES: Unhandled processor error type 0x10: micro-architec= tural error +[Firmware Warn]: GHES: Unhandled processor error type 0x14: TLB error|micr= o-architectural error +""" + +import argparse +import re + +from qmp_helper import qmp, util, cper_guid + + +class ArmProcessorEinj: + """ + Implements ARM Processor Error injection via GHES + """ + + DESC =3D """ + Generates an ARM processor error CPER, compatible with + UEFI 2.9A Errata. + """ + + ACPI_GHES_ARM_CPER_LENGTH =3D 40 + ACPI_GHES_ARM_CPER_PEI_LENGTH =3D 32 + + # Context types + CONTEXT_AARCH32_EL1 =3D 1 + CONTEXT_AARCH64_EL1 =3D 5 + CONTEXT_MISC_REG =3D 8 + + def __init__(self, subparsers): + """Initialize the error injection class and add subparser""" + + # Valid choice values + self.arm_valid_bits =3D { + "mpidr": util.bit(0), + "affinity": util.bit(1), + "running": util.bit(2), + "vendor": util.bit(3), + } + + self.pei_flags =3D { + "first": util.bit(0), + "last": util.bit(1), + "propagated": util.bit(2), + "overflow": util.bit(3), + } + + self.pei_error_types =3D { + "cache": util.bit(1), + "tlb": util.bit(2), + "bus": util.bit(3), + "micro-arch": util.bit(4), + } + + self.pei_valid_bits =3D { + "multiple-error": util.bit(0), + "flags": util.bit(1), + "error-info": util.bit(2), + "virt-addr": util.bit(3), + "phy-addr": util.bit(4), + } + + self.data =3D bytearray() + + parser =3D subparsers.add_parser("arm", description=3Dself.DESC) + + arm_valid_bits =3D ",".join(self.arm_valid_bits.keys()) + flags =3D ",".join(self.pei_flags.keys()) + error_types =3D ",".join(self.pei_error_types.keys()) + pei_valid_bits =3D ",".join(self.pei_valid_bits.keys()) + + # UEFI N.16 ARM Validation bits + g_arm =3D parser.add_argument_group("ARM processor") + g_arm.add_argument("--arm", "--arm-valid", + help=3Df"ARM valid bits: {arm_valid_bits}") + g_arm.add_argument("-a", "--affinity", "--level", "--affinity-lev= el", + type=3Dlambda x: int(x, 0), + help=3D"Affinity level (when multiple levels ap= ply)") + g_arm.add_argument("-l", "--mpidr", type=3Dlambda x: int(x, 0), + help=3D"Multiprocessor Affinity Register") + g_arm.add_argument("-i", "--midr", type=3Dlambda x: int(x, 0), + help=3D"Main ID Register") + g_arm.add_argument("-r", "--running", + action=3Dargparse.BooleanOptionalAction, + default=3DNone, + help=3D"Indicates if the processor is running o= r not") + g_arm.add_argument("--psci", "--psci-state", + type=3Dlambda x: int(x, 0), + help=3D"Power State Coordination Interface - PS= CI state") + + # TODO: Add vendor-specific support + + # UEFI N.17 bitmaps (type and flags) + g_pei =3D parser.add_argument_group("ARM Processor Error Info (PEI= )") + g_pei.add_argument("-t", "--type", nargs=3D"+", + help=3Df"one or more error types: {error_types}") + g_pei.add_argument("-f", "--flags", nargs=3D"*", + help=3Df"zero or more error flags: {flags}") + g_pei.add_argument("-V", "--pei-valid", "--error-valid", nargs=3D"= *", + help=3Df"zero or more PEI valid bits: {pei_valid_b= its}") + + # UEFI N.17 Integer values + g_pei.add_argument("-m", "--multiple-error", nargs=3D"+", + help=3D"Number of errors: 0: Single error, 1: Mult= iple errors, 2-65535: Error count if known") + g_pei.add_argument("-e", "--error-info", nargs=3D"+", + help=3D"Error information (UEFI 2.10 tables N.18 t= o N.20)") + g_pei.add_argument("-p", "--physical-address", nargs=3D"+", + help=3D"Physical address") + g_pei.add_argument("-v", "--virtual-address", nargs=3D"+", + help=3D"Virtual address") + + # UEFI N.21 Context + g_ctx =3D parser.add_argument_group("Processor Context") + g_ctx.add_argument("--ctx-type", "--context-type", nargs=3D"*", + help=3D"Type of the context (0=3DARM32 GPR, 5=3DAR= M64 EL1, other values supported)") + g_ctx.add_argument("--ctx-size", "--context-size", nargs=3D"*", + help=3D"Minimal size of the context") + g_ctx.add_argument("--ctx-array", "--context-array", nargs=3D"*", + help=3D"Comma-separated arrays for each context") + + # Vendor-specific data + g_vendor =3D parser.add_argument_group("Vendor-specific data") + g_vendor.add_argument("--vendor", "--vendor-specific", nargs=3D"+", + help=3D"Vendor-specific byte arrays of data") + + # Add arguments for Generic Error Data + qmp.argparse(parser) + + parser.set_defaults(func=3Dself.send_cper) + + def send_cper(self, args): + """Parse subcommand arguments and send a CPER via QMP""" + + qmp_cmd =3D qmp(args.host, args.port, args.debug) + + # Handle Generic Error Data arguments if any + qmp_cmd.set_args(args) + + is_cpu_type =3D re.compile(r"^([\w+]+\-)?arm\-cpu$") + cpus =3D qmp_cmd.search_qom("/machine/unattached/device", + "type", is_cpu_type) + + cper =3D {} + pei =3D {} + ctx =3D {} + vendor =3D {} + + arg =3D vars(args) + + # Handle global parameters + if args.arm: + arm_valid_init =3D False + cper["valid"] =3D util.get_choice(name=3D"valid", + value=3Dargs.arm, + choices=3Dself.arm_valid_bits, + suffixes=3D["-error", "-err"]) + else: + cper["valid"] =3D 0 + arm_valid_init =3D True + + if "running" in arg: + if args.running: + cper["running-state"] =3D util.bit(0) + else: + cper["running-state"] =3D 0 + else: + cper["running-state"] =3D 0 + + if arm_valid_init: + if args.affinity: + cper["valid"] |=3D self.arm_valid_bits["affinity"] + + if args.mpidr: + cper["valid"] |=3D self.arm_valid_bits["mpidr"] + + if "running-state" in cper: + cper["valid"] |=3D self.arm_valid_bits["running"] + + if args.psci: + cper["valid"] |=3D self.arm_valid_bits["running"] + + # Handle PEI + if not args.type: + args.type =3D ["cache-error"] + + util.get_mult_choices( + pei, + name=3D"valid", + values=3Dargs.pei_valid, + choices=3Dself.pei_valid_bits, + suffixes=3D["-valid", "--addr"], + ) + util.get_mult_choices( + pei, + name=3D"type", + values=3Dargs.type, + choices=3Dself.pei_error_types, + suffixes=3D["-error", "-err"], + ) + util.get_mult_choices( + pei, + name=3D"flags", + values=3Dargs.flags, + choices=3Dself.pei_flags, + suffixes=3D["-error", "-cap"], + ) + util.get_mult_int(pei, "error-info", args.error_info) + util.get_mult_int(pei, "multiple-error", args.multiple_error) + util.get_mult_int(pei, "phy-addr", args.physical_address) + util.get_mult_int(pei, "virt-addr", args.virtual_address) + + # Handle context + util.get_mult_int(ctx, "type", args.ctx_type, allow_zero=3DTrue) + util.get_mult_int(ctx, "minimal-size", args.ctx_size, allow_zero= =3DTrue) + util.get_mult_array(ctx, "register", args.ctx_array, allow_zero=3D= True) + + util.get_mult_array(vendor, "bytes", args.vendor, max_val=3D255) + + # Store PEI + pei_data =3D bytearray() + default_flags =3D self.pei_flags["first"] + default_flags |=3D self.pei_flags["last"] + + error_info_num =3D 0 + + for i, p in pei.items(): # pylint: disable=3DW0612 + error_info_num +=3D 1 + + # UEFI 2.10 doesn't define how to encode error information + # when multiple types are raised. So, provide a default only + # if a single type is there + if "error-info" not in p: + if p["type"] =3D=3D util.bit(1): + p["error-info"] =3D 0x0091000F + if p["type"] =3D=3D util.bit(2): + p["error-info"] =3D 0x0054007F + if p["type"] =3D=3D util.bit(3): + p["error-info"] =3D 0x80D6460FFF + if p["type"] =3D=3D util.bit(4): + p["error-info"] =3D 0x78DA03FF + + if "valid" not in p: + p["valid"] =3D 0 + if "multiple-error" in p: + p["valid"] |=3D self.pei_valid_bits["multiple-error"] + + if "flags" in p: + p["valid"] |=3D self.pei_valid_bits["flags"] + + if "error-info" in p: + p["valid"] |=3D self.pei_valid_bits["error-info"] + + if "phy-addr" in p: + p["valid"] |=3D self.pei_valid_bits["phy-addr"] + + if "virt-addr" in p: + p["valid"] |=3D self.pei_valid_bits["virt-addr"] + + # Version + util.data_add(pei_data, 0, 1) + + util.data_add(pei_data, + self.ACPI_GHES_ARM_CPER_PEI_LENGTH, 1) + + util.data_add(pei_data, p["valid"], 2) + util.data_add(pei_data, p["type"], 1) + util.data_add(pei_data, p.get("multiple-error", 1), 2) + util.data_add(pei_data, p.get("flags", default_flags), 1) + util.data_add(pei_data, p.get("error-info", 0), 8) + util.data_add(pei_data, p.get("virt-addr", 0xDEADBEEF), 8) + util.data_add(pei_data, p.get("phy-addr", 0xABBA0BAD), 8) + + # Store Context + ctx_data =3D bytearray() + context_info_num =3D 0 + + if ctx: + ret =3D qmp_cmd.send_cmd("query-target", may_open=3DTrue) + + default_ctx =3D self.CONTEXT_MISC_REG + + if "arch" in ret: + if ret["arch"] =3D=3D "aarch64": + default_ctx =3D self.CONTEXT_AARCH64_EL1 + elif ret["arch"] =3D=3D "arm": + default_ctx =3D self.CONTEXT_AARCH32_EL1 + + for k in sorted(ctx.keys()): + context_info_num +=3D 1 + + if "type" not in ctx[k]: + ctx[k]["type"] =3D default_ctx + + if "register" not in ctx[k]: + ctx[k]["register"] =3D [] + + reg_size =3D len(ctx[k]["register"]) + size =3D 0 + + if "minimal-size" in ctx: + size =3D ctx[k]["minimal-size"] + + size =3D max(size, reg_size) + + size =3D (size + 1) % 0xFFFE + + # Version + util.data_add(ctx_data, 0, 2) + + util.data_add(ctx_data, ctx[k]["type"], 2) + + util.data_add(ctx_data, 8 * size, 4) + + for r in ctx[k]["register"]: + util.data_add(ctx_data, r, 8) + + for i in range(reg_size, size): # pylint: disable=3DW0612 + util.data_add(ctx_data, 0, 8) + + # Vendor-specific bytes are not grouped + vendor_data =3D bytearray() + if vendor: + for k in sorted(vendor.keys()): + for b in vendor[k]["bytes"]: + util.data_add(vendor_data, b, 1) + + # Encode ARM Processor Error + data =3D bytearray() + + util.data_add(data, cper["valid"], 4) + + util.data_add(data, error_info_num, 2) + util.data_add(data, context_info_num, 2) + + # Calculate the length of the CPER data + cper_length =3D self.ACPI_GHES_ARM_CPER_LENGTH + cper_length +=3D len(pei_data) + cper_length +=3D len(vendor_data) + cper_length +=3D len(ctx_data) + util.data_add(data, cper_length, 4) + + util.data_add(data, arg.get("affinity-level", 0), 1) + + # Reserved + util.data_add(data, 0, 3) + + if "midr-el1" not in arg: + if cpus: + cmd_arg =3D { + 'path': cpus[0], + 'property': "midr" + } + ret =3D qmp_cmd.send_cmd("qom-get", cmd_arg, may_open=3DTr= ue) + if isinstance(ret, int): + arg["midr-el1"] =3D ret + + util.data_add(data, arg.get("mpidr-el1", 0), 8) + util.data_add(data, arg.get("midr-el1", 0), 8) + util.data_add(data, cper["running-state"], 4) + util.data_add(data, arg.get("psci-state", 0), 4) + + # Add PEI + data.extend(pei_data) + data.extend(ctx_data) + data.extend(vendor_data) + + self.data =3D data + + qmp_cmd.send_cper(cper_guid.CPER_PROC_ARM, self.data) diff --git a/scripts/ghes_inject.py b/scripts/ghes_inject.py new file mode 100755 index 000000000000..9a235201418b --- /dev/null +++ b/scripts/ghes_inject.py @@ -0,0 +1,51 @@ +#!/usr/bin/env python3 +# +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright (C) 2024-2025 Mauro Carvalho Chehab + +""" +Handle ACPI GHESv2 error injection logic QEMU QMP interface. +""" + +import argparse +import sys + +from arm_processor_error import ArmProcessorEinj + +EINJ_DESC =3D """ +Handle ACPI GHESv2 error injection logic QEMU QMP interface. + +It allows using UEFI BIOS EINJ features to generate GHES records. + +It helps testing CPER and GHES drivers at the guest OS and how +userspace applications at the guest handle them. +""" + +def main(): + """Main program""" + + # Main parser - handle generic args like QEMU QMP TCP socket options + parser =3D argparse.ArgumentParser(formatter_class=3Dargparse.Argument= DefaultsHelpFormatter, + usage=3D"%(prog)s [options]", + description=3DEINJ_DESC) + + g_options =3D parser.add_argument_group("QEMU QMP socket options") + g_options.add_argument("-H", "--host", default=3D"localhost", type=3Ds= tr, + help=3D"host name") + g_options.add_argument("-P", "--port", default=3D4445, type=3Dint, + help=3D"TCP port number") + g_options.add_argument('-d', '--debug', action=3D'store_true') + + subparsers =3D parser.add_subparsers() + + ArmProcessorEinj(subparsers) + + args =3D parser.parse_args() + if "func" in args: + args.func(args) + else: + sys.exit(f"Please specify a valid command for {sys.argv[0]}") + +if __name__ =3D=3D "__main__": + main() diff --git a/scripts/qmp_helper.py b/scripts/qmp_helper.py new file mode 100755 index 000000000000..c1e7e0fd80ce --- /dev/null +++ b/scripts/qmp_helper.py @@ -0,0 +1,703 @@ +#!/usr/bin/env python3 +# +# pylint: disable=3DC0103,E0213,E1135,E1136,E1137,R0902,R0903,R0912,R0913,= R0917 +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright (C) 2024-2025 Mauro Carvalho Chehab + +""" +Helper classes to be used by ghes_inject command classes. +""" + +import json +import sys + +from datetime import datetime +from os import path as os_path + +try: + qemu_dir =3D os_path.abspath(os_path.dirname(os_path.dirname(__file__)= )) + sys.path.append(os_path.join(qemu_dir, 'python')) + + from qemu.qmp.legacy import QEMUMonitorProtocol + +except ModuleNotFoundError as exc: + print(f"Module '{exc.name}' not found.") + print("Try export PYTHONPATH=3Dtop-qemu-dir/python or run from top-qem= u-dir") + sys.exit(1) + +from base64 import b64encode + +class util: + """ + Ancillary functions to deal with bitmaps, parse arguments, + generate GUID and encode data on a bytearray buffer. + """ + + # + # Helper routines to handle multiple choice arguments + # + def get_choice(name, value, choices, suffixes=3DNone, bitmask=3DTrue): + """Produce a list from multiple choice argument""" + + new_values =3D 0 + + if not value: + return new_values + + for val in value.split(","): + val =3D val.lower() + + if suffixes: + for suffix in suffixes: + val =3D val.removesuffix(suffix) + + if val not in choices.keys(): + if suffixes: + for suffix in suffixes: + if val + suffix in choices.keys(): + val +=3D suffix + break + + if val not in choices.keys(): + sys.exit(f"Error on '{name}': choice '{val}' is invalid.") + + val =3D choices[val] + + if bitmask: + new_values |=3D val + else: + if new_values: + sys.exit(f"Error on '{name}': only one value is accept= ed.") + + new_values =3D val + + return new_values + + def get_array(name, values, max_val=3DNone): + """Add numbered hashes from integer lists into an array""" + + array =3D [] + + for value in values: + for val in value.split(","): + try: + val =3D int(val, 0) + except ValueError: + sys.exit(f"Error on '{name}': {val} is not an integer") + + if val < 0: + sys.exit(f"Error on '{name}': {val} is not unsigned") + + if max_val and val > max_val: + sys.exit(f"Error on '{name}': {val} is too little") + + array.append(val) + + return array + + def get_mult_array(mult, name, values, allow_zero=3DFalse, max_val=3DN= one): + """Add numbered hashes from integer lists""" + + if not allow_zero: + if not values: + return + else: + if values is None: + return + + if not values: + i =3D 0 + if i not in mult: + mult[i] =3D {} + + mult[i][name] =3D [] + return + + i =3D 0 + for value in values: + for val in value.split(","): + try: + val =3D int(val, 0) + except ValueError: + sys.exit(f"Error on '{name}': {val} is not an integer") + + if val < 0: + sys.exit(f"Error on '{name}': {val} is not unsigned") + + if max_val and val > max_val: + sys.exit(f"Error on '{name}': {val} is too little") + + if i not in mult: + mult[i] =3D {} + + if name not in mult[i]: + mult[i][name] =3D [] + + mult[i][name].append(val) + + i +=3D 1 + + + def get_mult_choices(mult, name, values, choices, + suffixes=3DNone, allow_zero=3DFalse): + """Add numbered hashes from multiple choice arguments""" + + if not allow_zero: + if not values: + return + else: + if values is None: + return + + i =3D 0 + for val in values: + new_values =3D util.get_choice(name, val, choices, suffixes) + + if i not in mult: + mult[i] =3D {} + + mult[i][name] =3D new_values + i +=3D 1 + + + def get_mult_int(mult, name, values, allow_zero=3DFalse): + """Add numbered hashes from integer arguments""" + if not allow_zero: + if not values: + return + else: + if values is None: + return + + i =3D 0 + for val in values: + try: + val =3D int(val, 0) + except ValueError: + sys.exit(f"Error on '{name}': {val} is not an integer") + + if val < 0: + sys.exit(f"Error on '{name}': {val} is not unsigned") + + if i not in mult: + mult[i] =3D {} + + mult[i][name] =3D val + i +=3D 1 + + + # + # Data encode helper functions + # + def bit(b): + """Simple macro to define a bit on a bitmask""" + return 1 << b + + + def data_add(data, value, num_bytes): + """Adds bytes from value inside a bitarray""" + + data.extend(value.to_bytes(num_bytes, byteorder=3D"little")) # py= lint: disable=3DE1101 + + def dump_bytearray(name, data): + """Does an hexdump of a byte array, grouping in bytes""" + + print(f"{name} ({len(data)} bytes):") + + for ln_start in range(0, len(data), 16): + ln_end =3D min(ln_start + 16, len(data)) + print(f" {ln_start:08x} ", end=3D"") + for i in range(ln_start, ln_end): + print(f"{data[i]:02x} ", end=3D"") + for i in range(ln_end, ln_start + 16): + print(" ", end=3D"") + print(" ", end=3D"") + for i in range(ln_start, ln_end): + if data[i] >=3D 32 and data[i] < 127: + print(chr(data[i]), end=3D"") + else: + print(".", end=3D"") + + print() + print() + + def time(string): + """Handle BCD timestamps used on Generic Error Data Block""" + + time =3D None + + # Formats to be used when parsing time stamps + formats =3D [ + "%Y-%m-%d %H:%M:%S", + ] + + if string =3D=3D "now": + time =3D datetime.now() + + if time is None: + for fmt in formats: + try: + time =3D datetime.strptime(string, fmt) + break + except ValueError: + pass + + if time is None: + raise ValueError("Invalid time format") + + return time + +class guid: + """ + Simple class to handle GUID fields. + """ + + def __init__(self, time_low, time_mid, time_high, nodes): + """Initialize a GUID value""" + + assert len(nodes) =3D=3D 8 + + self.time_low =3D time_low + self.time_mid =3D time_mid + self.time_high =3D time_high + self.nodes =3D nodes + + @classmethod + def UUID(cls, guid_str): + """Initialize a GUID using a string on its standard format""" + + if len(guid_str) !=3D 36: + print("Size not 36") + raise ValueError('Invalid GUID size') + + # It is easier to parse without separators. So, drop them + guid_str =3D guid_str.replace('-', '') + + if len(guid_str) !=3D 32: + print("Size not 32", guid_str, len(guid_str)) + raise ValueError('Invalid GUID hex size') + + time_low =3D 0 + time_mid =3D 0 + time_high =3D 0 + nodes =3D [] + + for i in reversed(range(16, 32, 2)): + h =3D guid_str[i:i + 2] + value =3D int(h, 16) + nodes.insert(0, value) + + time_high =3D int(guid_str[12:16], 16) + time_mid =3D int(guid_str[8:12], 16) + time_low =3D int(guid_str[0:8], 16) + + return cls(time_low, time_mid, time_high, nodes) + + def __str__(self): + """Output a GUID value on its default string representation""" + + clock =3D self.nodes[0] << 8 | self.nodes[1] + + node =3D 0 + for i in range(2, len(self.nodes)): + node =3D node << 8 | self.nodes[i] + + s =3D f"{self.time_low:08x}-{self.time_mid:04x}-" + s +=3D f"{self.time_high:04x}-{clock:04x}-{node:012x}" + return s + + def to_bytes(self): + """Output a GUID value in bytes""" + + data =3D bytearray() + + util.data_add(data, self.time_low, 4) + util.data_add(data, self.time_mid, 2) + util.data_add(data, self.time_high, 2) + data.extend(bytearray(self.nodes)) + + return data + +class qmp: + """ + Opens a connection and send/receive QMP commands. + """ + + def send_cmd(self, command, args=3DNone, may_open=3DFalse, return_erro= r=3DTrue): + """Send a command to QMP, optinally opening a connection""" + + if may_open: + self._connect() + elif not self.connected: + return False + + msg =3D { 'execute': command } + if args: + msg['arguments'] =3D args + + try: + obj =3D self.qmp_monitor.cmd_obj(msg) + # Can we use some other exception class here? + except Exception as e: # pylint: disable= =3DW0718 + print(f"Command: {command}") + print(f"Failed to inject error: {e}.") + return None + + if "return" in obj: + if isinstance(obj.get("return"), dict): + if obj["return"]: + return obj["return"] + return "OK" + + return obj["return"] + + if isinstance(obj.get("error"), dict): + error =3D obj["error"] + if return_error: + print(f"Command: {msg}") + print(f'{error["class"]}: {error["desc"]}') + else: + print(json.dumps(obj)) + + return None + + def _close(self): + """Shutdown and close the socket, if opened""" + if not self.connected: + return + + self.qmp_monitor.close() + self.connected =3D False + + def _connect(self): + """Connect to a QMP TCP/IP port, if not connected yet""" + + if self.connected: + return True + + try: + self.qmp_monitor.connect(negotiate=3DTrue) + except ConnectionError: + sys.exit(f"Can't connect to QMP host {self.host}:{self.port}") + + self.connected =3D True + + return True + + BLOCK_STATUS_BITS =3D { + "uncorrectable": util.bit(0), + "correctable": util.bit(1), + "multi-uncorrectable": util.bit(2), + "multi-correctable": util.bit(3), + } + + ERROR_SEVERITY =3D { + "recoverable": 0, + "fatal": 1, + "corrected": 2, + "none": 3, + } + + VALIDATION_BITS =3D { + "fru-id": util.bit(0), + "fru-text": util.bit(1), + "timestamp": util.bit(2), + } + + GEDB_FLAGS_BITS =3D { + "recovered": util.bit(0), + "prev-error": util.bit(1), + "simulated": util.bit(2), + } + + GENERIC_DATA_SIZE =3D 72 + + def argparse(parser): + """Prepare a parser group to query generic error data""" + + block_status_bits =3D ",".join(qmp.BLOCK_STATUS_BITS.keys()) + error_severity_enum =3D ",".join(qmp.ERROR_SEVERITY.keys()) + validation_bits =3D ",".join(qmp.VALIDATION_BITS.keys()) + gedb_flags_bits =3D ",".join(qmp.GEDB_FLAGS_BITS.keys()) + + g_gen =3D parser.add_argument_group("Generic Error Data") # pylin= t: disable=3DE1101 + g_gen.add_argument("--block-status", + help=3Df"block status bits: {block_status_bits}= ") + g_gen.add_argument("--raw-data", nargs=3D"+", + help=3D"Raw data inside the Error Status Block") + g_gen.add_argument("--error-severity", "--severity", + help=3Df"error severity: {error_severity_enum}") + g_gen.add_argument("--gen-err-valid-bits", + "--generic-error-validation-bits", + help=3Df"validation bits: {validation_bits}") + g_gen.add_argument("--fru-id", type=3Dguid.UUID, + help=3D"GUID representing a physical device") + g_gen.add_argument("--fru-text", + help=3D"ASCII string identifying the FRU hardwa= re") + g_gen.add_argument("--timestamp", type=3Dutil.time, + help=3D"Time when the error info was collected") + g_gen.add_argument("--precise", "--precise-timestamp", + action=3D'store_true', + help=3D"Marks the timestamp as precise if --tim= estamp is used") + g_gen.add_argument("--gedb-flags", + help=3Df"General Error Data Block flags: {gedb_= flags_bits}") + + def set_args(self, args): + """Set the arguments optionally defined via self.argparse()""" + + if args.block_status: + self.block_status =3D util.get_choice(name=3D"block-status", + value=3Dargs.block_status, + choices=3Dself.BLOCK_STATU= S_BITS, + bitmask=3DFalse) + if args.raw_data: + self.raw_data =3D util.get_array("raw-data", args.raw_data, + max_val=3D255) + print(self.raw_data) + + if args.error_severity: + self.error_severity =3D util.get_choice(name=3D"error-severity= ", + value=3Dargs.error_sever= ity, + choices=3Dself.ERROR_SEV= ERITY, + bitmask=3DFalse) + + if args.fru_id: + self.fru_id =3D args.fru_id.to_bytes() + if not args.gen_err_valid_bits: + self.validation_bits |=3D self.VALIDATION_BITS["fru-id"] + + if args.fru_text: + text =3D bytearray(args.fru_text.encode('ascii')) + if len(text) > 20: + sys.exit("FRU text is too big to fit") + + self.fru_text =3D text + if not args.gen_err_valid_bits: + self.validation_bits |=3D self.VALIDATION_BITS["fru-text"] + + if args.timestamp: + time =3D args.timestamp + century =3D int(time.year / 100) + + bcd =3D bytearray() + util.data_add(bcd, (time.second // 10) << 4 | (time.second % 1= 0), 1) + util.data_add(bcd, (time.minute // 10) << 4 | (time.minute % 1= 0), 1) + util.data_add(bcd, (time.hour // 10) << 4 | (time.hour % 10), = 1) + + if args.precise: + util.data_add(bcd, 1, 1) + else: + util.data_add(bcd, 0, 1) + + util.data_add(bcd, (time.day // 10) << 4 | (time.day % 10), 1) + util.data_add(bcd, (time.month // 10) << 4 | (time.month % 10)= , 1) + util.data_add(bcd, + ((time.year % 100) // 10) << 4 | (time.year % 10= ), 1) + util.data_add(bcd, ((century % 100) // 10) << 4 | (century % 1= 0), 1) + + self.timestamp =3D bcd + if not args.gen_err_valid_bits: + self.validation_bits |=3D self.VALIDATION_BITS["timestamp"] + + if args.gen_err_valid_bits: + self.validation_bits =3D util.get_choice(name=3D"validation", + value=3Dargs.gen_err_va= lid_bits, + choices=3Dself.VALIDATI= ON_BITS) + + def __init__(self, host, port, debug=3DFalse): + """Initialize variables used by the QMP send logic""" + + self.connected =3D False + self.host =3D host + self.port =3D port + self.debug =3D debug + + # ACPI 6.1: 18.3.2.7.1 Generic Error Data: Generic Error Status Bl= ock + self.block_status =3D self.BLOCK_STATUS_BITS["uncorrectable"] + self.raw_data =3D [] + self.error_severity =3D self.ERROR_SEVERITY["recoverable"] + + # ACPI 6.1: 18.3.2.7.1 Generic Error Data: Generic Error Data Entry + self.validation_bits =3D 0 + self.flags =3D 0 + self.fru_id =3D bytearray(16) + self.fru_text =3D bytearray(20) + self.timestamp =3D bytearray(8) + + self.qmp_monitor =3D QEMUMonitorProtocol(address=3D(self.host, sel= f.port)) + + # + # Socket QMP send command + # + def send_cper_raw(self, cper_data): + """Send a raw CPER data to QEMU though QMP TCP socket""" + + data =3D b64encode(bytes(cper_data)).decode('ascii') + + cmd_arg =3D { + 'cper': data + } + + self._connect() + + if self.send_cmd("inject-ghes-v2-error", cmd_arg): + print("Error injected.") + + def send_cper(self, notif_type, payload): + """Send commands to QEMU though QMP TCP socket""" + + # Fill CPER record header + + # NOTE: bits 4 to 13 of block status contain the number of + # data entries in the data section. This is currently unsupported. + + cper_length =3D len(payload) + data_length =3D cper_length + len(self.raw_data) + self.GENERIC_DA= TA_SIZE + + # Generic Error Data Entry + gede =3D bytearray() + + gede.extend(notif_type.to_bytes()) + util.data_add(gede, self.error_severity, 4) + util.data_add(gede, 0x300, 2) + util.data_add(gede, self.validation_bits, 1) + util.data_add(gede, self.flags, 1) + util.data_add(gede, cper_length, 4) + gede.extend(self.fru_id) + gede.extend(self.fru_text) + gede.extend(self.timestamp) + + # Generic Error Status Block + gebs =3D bytearray() + + if self.raw_data: + raw_data_offset =3D len(gebs) + else: + raw_data_offset =3D 0 + + util.data_add(gebs, self.block_status, 4) + util.data_add(gebs, raw_data_offset, 4) + util.data_add(gebs, len(self.raw_data), 4) + util.data_add(gebs, data_length, 4) + util.data_add(gebs, self.error_severity, 4) + + cper_data =3D bytearray() + cper_data.extend(gebs) + cper_data.extend(gede) + cper_data.extend(bytearray(self.raw_data)) + cper_data.extend(bytearray(payload)) + + if self.debug: + print(f"GUID: {notif_type}") + + util.dump_bytearray("Generic Error Status Block", gebs) + util.dump_bytearray("Generic Error Data Entry", gede) + + if self.raw_data: + util.dump_bytearray("Raw data", bytearray(self.raw_data)) + + util.dump_bytearray("Payload", payload) + + self.send_cper_raw(cper_data) + + + def search_qom(self, path, prop, regex): + """ + Return a list of devices that match path array like: + + /machine/unattached/device + /machine/peripheral-anon/device + ... + """ + + found =3D [] + + i =3D 0 + while 1: + dev =3D f"{path}[{i}]" + args =3D { + 'path': dev, + 'property': prop + } + ret =3D self.send_cmd("qom-get", args, may_open=3DTrue, + return_error=3DFalse) + if not ret: + break + + if isinstance(ret, str): + if regex.search(ret): + found.append(dev) + + i +=3D 1 + if i > 10000: + print("Too many objects returned by qom-get!") + break + + return found + +class cper_guid: + """ + Contains CPER GUID, as per: + https://uefi.org/specs/UEFI/2.10/Apx_N_Common_Platform_Error_Record.ht= ml + """ + + CPER_PROC_GENERIC =3D guid(0x9876CCAD, 0x47B4, 0x4bdb, + [0xB6, 0x5E, 0x16, 0xF1, + 0x93, 0xC4, 0xF3, 0xDB]) + + CPER_PROC_X86 =3D guid(0xDC3EA0B0, 0xA144, 0x4797, + [0xB9, 0x5B, 0x53, 0xFA, + 0x24, 0x2B, 0x6E, 0x1D]) + + CPER_PROC_ITANIUM =3D guid(0xe429faf1, 0x3cb7, 0x11d4, + [0xbc, 0xa7, 0x00, 0x80, + 0xc7, 0x3c, 0x88, 0x81]) + + CPER_PROC_ARM =3D guid(0xE19E3D16, 0xBC11, 0x11E4, + [0x9C, 0xAA, 0xC2, 0x05, + 0x1D, 0x5D, 0x46, 0xB0]) + + CPER_PLATFORM_MEM =3D guid(0xA5BC1114, 0x6F64, 0x4EDE, + [0xB8, 0x63, 0x3E, 0x83, + 0xED, 0x7C, 0x83, 0xB1]) + + CPER_PLATFORM_MEM2 =3D guid(0x61EC04FC, 0x48E6, 0xD813, + [0x25, 0xC9, 0x8D, 0xAA, + 0x44, 0x75, 0x0B, 0x12]) + + CPER_PCIE =3D guid(0xD995E954, 0xBBC1, 0x430F, + [0xAD, 0x91, 0xB4, 0x4D, + 0xCB, 0x3C, 0x6F, 0x35]) + + CPER_PCI_BUS =3D guid(0xC5753963, 0x3B84, 0x4095, + [0xBF, 0x78, 0xED, 0xDA, + 0xD3, 0xF9, 0xC9, 0xDD]) + + CPER_PCI_DEV =3D guid(0xEB5E4685, 0xCA66, 0x4769, + [0xB6, 0xA2, 0x26, 0x06, + 0x8B, 0x00, 0x13, 0x26]) + + CPER_FW_ERROR =3D guid(0x81212A96, 0x09ED, 0x4996, + [0x94, 0x71, 0x8D, 0x72, + 0x9C, 0x8E, 0x69, 0xED]) + + CPER_DMA_GENERIC =3D guid(0x5B51FEF7, 0xC79D, 0x4434, + [0x8F, 0x1B, 0xAA, 0x62, + 0xDE, 0x3E, 0x2C, 0x64]) + + CPER_DMA_VT =3D guid(0x71761D37, 0x32B2, 0x45cd, + [0xA7, 0xD0, 0xB0, 0xFE, + 0xDD, 0x93, 0xE8, 0xCF]) + + CPER_DMA_IOMMU =3D guid(0x036F84E1, 0x7F37, 0x428c, + [0xA7, 0x9E, 0x57, 0x5F, + 0xDF, 0xAA, 0x84, 0xEC]) + + CPER_CCIX_PER =3D guid(0x91335EF6, 0xEBFB, 0x4478, + [0xA6, 0xA6, 0x88, 0xB7, + 0x28, 0xCF, 0x75, 0xD7]) + + CPER_CXL_PROT_ERR =3D guid(0x80B9EFB4, 0x52B5, 0x4DE3, + [0xA7, 0x77, 0x68, 0x78, + 0x4B, 0x77, 0x10, 0x48]) --=20 2.49.0