From nobody Fri Oct 10 17:21:33 2025 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 8AC6223183A for ; Fri, 13 Jun 2025 06:43:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749797041; cv=none; b=mwcVEp4T1ovrZaV6I+URVCvjsIOQ70bp6ZMlk6kOa8RKQ4/jccFYAIi0peksGpWQujaGaaqRq+jbnsFGI8tHOFHO1hCTS00SPVOClrQtljn5KFLiuuyUYC2qkPOdjdbkD8U10EZhSbnHz+Ls3rSNIh/4yRv98dUkMhlVUlUrQg0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749797041; c=relaxed/simple; bh=5LGpi/0/IYeDL/SR2uzMo3apMopbBY7CX8wthzRs/wQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=QvKew7bgpAHzwN0zcPC9XOwGnny98vYb45QRYko5l3VUwHTz8rCL08vvQoPm9r9FcFbaLYB1caxIDOw4mu/jF/9K1KXCAIIeWoK6bdLa/2Uu8pbJmZWWpSCVVsKfPXY2j6365D2B/R1KvrvHPCE7acujY0my1UH4qBYORsJHlp8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [223.64.68.149]) by gateway (Coremail) with SMTP id _____8AxaeGsyEtokowVAQ--.8325S3; Fri, 13 Jun 2025 14:43:56 +0800 (CST) Received: from localhost.localdomain (unknown [223.64.68.149]) by front1 (Coremail) with SMTP id qMiowMBx3MSlyEto29MYAQ--.8851S3; Fri, 13 Jun 2025 14:43:55 +0800 (CST) From: Binbin Zhou To: Binbin Zhou , Huacai Chen , Lee Jones , Corey Minyard Cc: Huacai Chen , Xuerui Wang , loongarch@lists.linux.dev, linux-kernel@vger.kernel.org, openipmi-developer@lists.sourceforge.net, jeffbai@aosc.io, kexybiscuit@aosc.io, wangyao@lemote.com, Binbin Zhou , Chong Qiao Subject: [PATCH v4 1/3] mfd: ls2kbmc: Introduce Loongson-2K BMC core driver Date: Fri, 13 Jun 2025 14:43:39 +0800 Message-ID: <3560d2b571ec76b2260fd3a594c09cdc09786ab4.1749731531.git.zhoubinbin@loongson.cn> X-Mailer: git-send-email 2.47.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMBx3MSlyEto29MYAQ--.8851S3 X-CM-SenderInfo: p2kr3uplqex0o6or00hjvr0hdfq/ X-Coremail-Antispam: 1Uk129KBj93XoW3Jr4UZry7Xw1UXFyrGF1DCFX_yoW3Jw15p3 WxCay5Crs5AF17Wa9xZr1UuFW3ua9aq3y5tay3Xw1aka93Aa4kXw4ktFyYvF9rJFykKFy2 qF9rXr17Can8JFcCm3ZEXasCq-sJn29KB7ZKAUJUUUU3529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUB0b4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r1q6r4UM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Gr0_Cr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_ GcCE3s1ln4kS14v26r126r1DM2AIxVAIcxkEcVAq07x20xvEncxIr21l57IF6xkI12xvs2 x26I8E6xACxx1l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r1q6rW5 McIj6I8E87Iv67AKxVW8JVWxJwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr4 1lc7CjxVAaw2AFwI0_JF0_Jw1l42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_ Gr1l4IxYO2xFxVAFwI0_JF0_Jw1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8GjcxK67 AKxVWUGVWUWwC2zVAF1VAY17CE14v26r1q6r43MIIYrxkI7VAKI48JMIIF0xvE2Ix0cI8I cVAFwI0_Gr0_Xr1lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4j6F4UMIIF0xvE42xK8VAvwI 8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVW8JVWxJwCI42IY6I8E87Iv6xkF7I0E14v2 6r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjxUFwIDUUUUU Content-Type: text/plain; charset="utf-8" The Loongson-2K Board Management Controller provides an PCIe interface to the host to access the feature implemented in the BMC. The BMC is assembled on a server similar to the server machine with Loongson-3 CPU. It supports multiple sub-devices like DRM or IPMI. Reviewed-by: Huacai Chen Co-developed-by: Chong Qiao Signed-off-by: Chong Qiao Signed-off-by: Binbin Zhou --- drivers/mfd/Kconfig | 12 +++ drivers/mfd/Makefile | 2 + drivers/mfd/ls2kbmc-mfd.c | 156 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 170 insertions(+) create mode 100644 drivers/mfd/ls2kbmc-mfd.c diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 96992af22565..10e3d1728e13 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -2389,6 +2389,18 @@ config MFD_INTEL_M10_BMC_PMCI additional drivers must be enabled in order to use the functionality of the device. =20 +config MFD_LS2K_BMC + bool "Loongson-2K Board Management Controller Support" + depends on LOONGARCH + default y if LOONGARCH + select MFD_CORE + help + Say yes here to add support for the Loongson-2K BMC which is a Board + Management Controller connected to the PCIe bus. The device supports + multiple sub-devices like DRM. This driver provides common support for + accessing the devices; additional drivers must be enabled in order to + use the functionality of the BMC device. + config MFD_QNAP_MCU tristate "QNAP microcontroller unit core driver" depends on SERIAL_DEV_BUS diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index 5e5cc279af60..bd4282c36ed2 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -282,6 +282,8 @@ obj-$(CONFIG_MFD_INTEL_M10_BMC_CORE) +=3D intel-m10-b= mc-core.o obj-$(CONFIG_MFD_INTEL_M10_BMC_SPI) +=3D intel-m10-bmc-spi.o obj-$(CONFIG_MFD_INTEL_M10_BMC_PMCI) +=3D intel-m10-bmc-pmci.o =20 +obj-$(CONFIG_MFD_LS2K_BMC) +=3D ls2kbmc-mfd.o + obj-$(CONFIG_MFD_ATC260X) +=3D atc260x-core.o obj-$(CONFIG_MFD_ATC260X_I2C) +=3D atc260x-i2c.o =20 diff --git a/drivers/mfd/ls2kbmc-mfd.c b/drivers/mfd/ls2kbmc-mfd.c new file mode 100644 index 000000000000..310ca70700c0 --- /dev/null +++ b/drivers/mfd/ls2kbmc-mfd.c @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Loongson-2K Board Management Controller (BMC) Core Driver. + * + * Copyright (C) 2024-2025 Loongson Technology Corporation Limited. + * + * Authors: + * Chong Qiao + * Binbin Zhou + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* LS2K BMC resources */ +#define LS2K_DISPLAY_RES_START (SZ_16M + SZ_2M) +#define LS2K_IPMI_RES_SIZE 0x1C +#define LS2K_IPMI0_RES_START (SZ_16M + 0xF00000) +#define LS2K_IPMI1_RES_START (LS2K_IPMI0_RES_START + LS2K_IPMI_RES_SIZE) +#define LS2K_IPMI2_RES_START (LS2K_IPMI1_RES_START + LS2K_IPMI_RES_SIZE) +#define LS2K_IPMI3_RES_START (LS2K_IPMI2_RES_START + LS2K_IPMI_RES_SIZE) +#define LS2K_IPMI4_RES_START (LS2K_IPMI3_RES_START + LS2K_IPMI_RES_SIZE) + +static struct resource ls2k_display_resources[] =3D { + DEFINE_RES_MEM_NAMED(LS2K_DISPLAY_RES_START, SZ_4M, "simpledrm-res"), +}; + +static struct resource ls2k_ipmi0_resources[] =3D { + DEFINE_RES_MEM_NAMED(LS2K_IPMI0_RES_START, LS2K_IPMI_RES_SIZE, "ipmi0-res= "), +}; + +static struct resource ls2k_ipmi1_resources[] =3D { + DEFINE_RES_MEM_NAMED(LS2K_IPMI1_RES_START, LS2K_IPMI_RES_SIZE, "ipmi1-res= "), +}; + +static struct resource ls2k_ipmi2_resources[] =3D { + DEFINE_RES_MEM_NAMED(LS2K_IPMI2_RES_START, LS2K_IPMI_RES_SIZE, "ipmi2-res= "), +}; + +static struct resource ls2k_ipmi3_resources[] =3D { + DEFINE_RES_MEM_NAMED(LS2K_IPMI3_RES_START, LS2K_IPMI_RES_SIZE, "ipmi3-res= "), +}; + +static struct resource ls2k_ipmi4_resources[] =3D { + DEFINE_RES_MEM_NAMED(LS2K_IPMI4_RES_START, LS2K_IPMI_RES_SIZE, "ipmi4-res= "), +}; + +static struct mfd_cell ls2k_bmc_cells[] =3D { + MFD_CELL_RES("simple-framebuffer", ls2k_display_resources), + MFD_CELL_RES("ls2k-ipmi-si", ls2k_ipmi0_resources), + MFD_CELL_RES("ls2k-ipmi-si", ls2k_ipmi1_resources), + MFD_CELL_RES("ls2k-ipmi-si", ls2k_ipmi2_resources), + MFD_CELL_RES("ls2k-ipmi-si", ls2k_ipmi3_resources), + MFD_CELL_RES("ls2k-ipmi-si", ls2k_ipmi4_resources), +}; + +/* + * Currently the Loongson-2K BMC hardware does not have an I2C interface t= o adapt to the + * resolution. We set the resolution by presetting "video=3D1280x1024-16@2= M" to the BMC memory. + */ +static int ls2k_bmc_parse_mode(struct pci_dev *pdev, struct simplefb_platf= orm_data *pd) +{ + char *mode; + int depth, ret; + + /* The last 16M of PCI BAR0 is used to store the resolution string. */ + mode =3D devm_ioremap(&pdev->dev, pci_resource_start(pdev, 0) + SZ_16M, S= Z_16M); + if (!mode) + return -ENOMEM; + + /* The resolution field starts with the flag "video=3D". */ + if (!strncmp(mode, "video=3D", 6)) + mode =3D mode + 6; + + ret =3D kstrtoint(strsep(&mode, "x"), 10, &pd->width); + if (ret) + return ret; + + ret =3D kstrtoint(strsep(&mode, "-"), 10, &pd->height); + if (ret) + return ret; + + ret =3D kstrtoint(strsep(&mode, "@"), 10, &depth); + if (ret) + return ret; + + pd->stride =3D pd->width * depth / 8; + pd->format =3D depth =3D=3D 32 ? "a8r8g8b8" : "r5g6b5"; + + return 0; +} + +static int ls2k_bmc_probe(struct pci_dev *dev, const struct pci_device_id = *id) +{ + struct simplefb_platform_data pd; + resource_size_t base; + int ret; + + ret =3D pci_enable_device(dev); + if (ret) + return ret; + + ret =3D ls2k_bmc_parse_mode(dev, &pd); + if (ret) + goto disable_pci; + + ls2k_bmc_cells[0].platform_data =3D &pd; + ls2k_bmc_cells[0].pdata_size =3D sizeof(pd); + base =3D dev->resource[0].start + LS2K_DISPLAY_RES_START; + + /* Remove conflicting efifb device */ + ret =3D aperture_remove_conflicting_devices(base, SZ_4M, "simple-framebuf= fer"); + if (ret) { + dev_err(&dev->dev, "Failed to removed firmware framebuffers: %d\n", ret); + goto disable_pci; + } + + return devm_mfd_add_devices(&dev->dev, PLATFORM_DEVID_AUTO, + ls2k_bmc_cells, ARRAY_SIZE(ls2k_bmc_cells), + &dev->resource[0], 0, NULL); + +disable_pci: + pci_disable_device(dev); + return ret; +} + +static void ls2k_bmc_remove(struct pci_dev *dev) +{ + pci_disable_device(dev); +} + +static struct pci_device_id ls2k_bmc_devices[] =3D { + { PCI_DEVICE(PCI_VENDOR_ID_LOONGSON, 0x1a05) }, + { } +}; +MODULE_DEVICE_TABLE(pci, ls2k_bmc_devices); + +static struct pci_driver ls2k_bmc_driver =3D { + .name =3D "ls2k-bmc", + .id_table =3D ls2k_bmc_devices, + .probe =3D ls2k_bmc_probe, + .remove =3D ls2k_bmc_remove, +}; +module_pci_driver(ls2k_bmc_driver); + +MODULE_DESCRIPTION("Loongson-2K BMC driver"); +MODULE_AUTHOR("Loongson Technology Corporation Limited"); +MODULE_LICENSE("GPL"); --=20 2.47.1 From nobody Fri Oct 10 17:21:33 2025 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 9ABB8253958 for ; Fri, 13 Jun 2025 06:43:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749797042; cv=none; b=cXgj8IJTz0wG7aTmmDT9ck/VQbX0/SqpKd1t4YOZK4xF+Nk51oqXiDkP2CpMl76XVCUBTFwWJqw/MKAPzhAkY8NBle4/KS5AG1ddp+9WyDw/Fvv2chyRcvekQ2mJZw37mF7sTVGotogNhsjt80nDoqPtkkdbw7J9q5/oUksA/jE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749797042; c=relaxed/simple; bh=qGRo/LeHnn3EneogrZ3xW9B4B2ley7iRPD+A9wJTf1k=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=JZ3Ugtn1EFJ4dbNdn59Z0bkz9XdEsm8tQmYAD+RZOL1uCcoCeDTgTdlrJjSgxNUNH6AIRFJLA1KMZpah/EYXrs/4+A2v0Wd8zQglY/uIObGDK4CIFhlJZXrX9QE0oOCMpNNkJhXTHHdIz4ektEYuWol7zNJYK3gVkR+K975WOJ0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [223.64.68.149]) by gateway (Coremail) with SMTP id _____8AxLOKtyEtomowVAQ--.10705S3; Fri, 13 Jun 2025 14:43:57 +0800 (CST) Received: from localhost.localdomain (unknown [223.64.68.149]) by front1 (Coremail) with SMTP id qMiowMBx3MSlyEto29MYAQ--.8851S4; Fri, 13 Jun 2025 14:43:56 +0800 (CST) From: Binbin Zhou To: Binbin Zhou , Huacai Chen , Lee Jones , Corey Minyard Cc: Huacai Chen , Xuerui Wang , loongarch@lists.linux.dev, linux-kernel@vger.kernel.org, openipmi-developer@lists.sourceforge.net, jeffbai@aosc.io, kexybiscuit@aosc.io, wangyao@lemote.com, Binbin Zhou , Chong Qiao Subject: [PATCH v4 2/3] mfd: ls2kbmc: Add Loongson-2K BMC reset function support Date: Fri, 13 Jun 2025 14:43:40 +0800 Message-ID: <76640fb04a67d25bda6423450dddbc2706643a7d.1749731531.git.zhoubinbin@loongson.cn> X-Mailer: git-send-email 2.47.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMBx3MSlyEto29MYAQ--.8851S4 X-CM-SenderInfo: p2kr3uplqex0o6or00hjvr0hdfq/ X-Coremail-Antispam: 1Uk129KBj9fXoW3tF4DXrW3KFWDGryfGFW3urX_yoW8GFW5Co WfuFWfZw18Jr17Aa1ftF17Ka4UW3y0qas3Aws7CryqgFyxAasrJFy5GanrZw1fZr4fK345 Zr95W3WxAFW3tr17l-sFpf9Il3svdjkaLaAFLSUrUUUUnb8apTn2vfkv8UJUUUU8wcxFpf 9Il3svdxBIdaVrn0xqx4xG64xvF2IEw4CE5I8CrVC2j2Jv73VFW2AGmfu7bjvjm3AaLaJ3 UjIYCTnIWjp_UUUYX7kC6x804xWl14x267AKxVWUJVW8JwAFc2x0x2IEx4CE42xK8VAvwI 8IcIk0rVWrJVCq3wAFIxvE14AKwVWUAVWUZwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xG Y2AK021l84ACjcxK6xIIjxv20xvE14v26ryj6F1UM28EF7xvwVC0I7IYx2IY6xkF7I0E14 v26F4j6r4UJwA2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x0267AK xVW0oVCq3wAaw2AFwI0_JF0_Jw1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqjxCEc2xF0c Ia020Ex4CE44I27wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_Jw0_ WrylYx0Ex4A2jsIE14v26r4j6F4UMcvjeVCFs4IE7xkEbVWUJVW8JwACjcxG0xvY0x0EwI xGrwCY1x0262kKe7AKxVWUAVWUtwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWU JVW8JwCFI7km07C267AKxVWUAVWUtwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4 vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jw0_GFylIxkGc2Ij64vIr41lIxAIcVC0I7IY x2IY67AKxVW5JVW7JwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1lIxAIcVCF04k26c xKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r4j6F4UMIIF0xvEx4A2jsIEc7CjxVAF wI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x07jr6p9UUUUU= Content-Type: text/plain; charset="utf-8" Since the display is a sub-function of the Loongson-2K BMC, when the BMC reset, the entire BMC PCIe is disconnected, including the display which is interrupted. Quick overview of the entire LS2K BMC reset process: There are two types of reset methods: soft reset (BMC-initiated reboot of IPMI reset command) and BMC watchdog reset (watchdog timeout). First, regardless of the method, an interrupt is generated (PCIe interrupt for soft reset/GPIO interrupt for watchdog reset); Second, during the interrupt process, the system enters bmc_reset_work, clears the bus/IO/mem resources of the LS7A PCI-E bridge, waits for the BMC reset to begin, then restores the parent device's PCI configuration space, waits for the BMC reset to complete, and finally restores the BMC PCI configuration space. Display restoration occurs last. Reviewed-by: Huacai Chen Co-developed-by: Chong Qiao Signed-off-by: Chong Qiao Signed-off-by: Binbin Zhou --- drivers/mfd/ls2kbmc-mfd.c | 329 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 329 insertions(+) diff --git a/drivers/mfd/ls2kbmc-mfd.c b/drivers/mfd/ls2kbmc-mfd.c index 310ca70700c0..2c8e86194cb3 100644 --- a/drivers/mfd/ls2kbmc-mfd.c +++ b/drivers/mfd/ls2kbmc-mfd.c @@ -10,8 +10,12 @@ */ =20 #include +#include +#include #include #include +#include +#include #include #include #include @@ -19,6 +23,8 @@ #include #include #include +#include +#include =20 /* LS2K BMC resources */ #define LS2K_DISPLAY_RES_START (SZ_16M + SZ_2M) @@ -29,6 +35,48 @@ #define LS2K_IPMI3_RES_START (LS2K_IPMI2_RES_START + LS2K_IPMI_RES_SIZE) #define LS2K_IPMI4_RES_START (LS2K_IPMI3_RES_START + LS2K_IPMI_RES_SIZE) =20 +#define LS7A_PCI_CFG_SIZE 0x100 + +/* LS7A bridge registers */ +#define LS7A_PCIE_PORT_CTL0 0x0 +#define LS7A_PCIE_PORT_STS1 0xC +#define LS7A_GEN2_CTL 0x80C +#define LS7A_SYMBOL_TIMER 0x71C + +/* Bits of LS7A_PCIE_PORT_CTL0 */ +#define LS2K_BMC_PCIE_LTSSM_ENABLE BIT(3) + +/* Bits of LS7A_PCIE_PORT_STS1 */ +#define LS2K_BMC_PCIE_LTSSM_STS GENMASK(5, 0) +#define LS2K_BMC_PCIE_CONNECTED 0x11 + +#define LS2K_BMC_PCIE_DELAY_US 1000 +#define LS2K_BMC_PCIE_TIMEOUT_US 1000000 + +/* Bits of LS7A_GEN2_CTL */ +#define LS7A_GEN2_SPEED_CHANG BIT(17) +#define LS7A_CONF_PHY_TX BIT(18) + +/* Bits of LS7A_SYMBOL_TIMER */ +#define LS7A_MASK_LEN_MATCH BIT(26) + +/* Interval between interruptions */ +#define LS2K_BMC_INT_INTERVAL (60 * HZ) + +/* Maximum time to wait for U-Boot and DDR to be ready with ms. */ +#define LS2K_BMC_RESET_WAIT_TIME 10000 + +/* It's an experience value */ +#define LS7A_BAR0_CHECK_MAX_TIMES 2000 + +#define LS2K_BMC_RESET_GPIO 14 +#define LOONGSON_GPIO_REG_BASE 0x1FE00500 +#define LOONGSON_GPIO_REG_SIZE 0x18 +#define LOONGSON_GPIO_OEN 0x0 +#define LOONGSON_GPIO_FUNC 0x4 +#define LOONGSON_GPIO_INTPOL 0x10 +#define LOONGSON_GPIO_INTEN 0x14 + static struct resource ls2k_display_resources[] =3D { DEFINE_RES_MEM_NAMED(LS2K_DISPLAY_RES_START, SZ_4M, "simpledrm-res"), }; @@ -62,6 +110,274 @@ static struct mfd_cell ls2k_bmc_cells[] =3D { MFD_CELL_RES("ls2k-ipmi-si", ls2k_ipmi4_resources), }; =20 +/* Index of the BMC PCI configuration space to be restored at BMC reset. */ +struct ls2k_bmc_pci_data { + u32 pci_command; + u32 base_address0; + u32 interrupt_line; +}; + +/* Index of the parent PCI configuration space to be restored at BMC reset= . */ +struct ls2k_bmc_bridge_pci_data { + u32 pci_command; + u32 base_address[6]; + u32 rom_addreess; + u32 interrupt_line; + u32 msi_hi; + u32 msi_lo; + u32 devctl; + u32 linkcap; + u32 linkctl_sts; + u32 symbol_timer; + u32 gen2_ctrl; +}; + +struct ls2k_bmc_pdata { + struct device *dev; + struct work_struct bmc_reset_work; + struct ls2k_bmc_pci_data bmc_pci_data; + struct ls2k_bmc_bridge_pci_data bridge_pci_data; +}; + +static bool ls2k_bmc_bar0_addr_is_set(struct pci_dev *ppdev) +{ + u32 addr; + + pci_read_config_dword(ppdev, PCI_BASE_ADDRESS_0, &addr); + + return addr & PCI_BASE_ADDRESS_MEM_MASK ? true : false; +} + +static bool ls2k_bmc_pcie_is_connected(struct pci_dev *parent, struct ls2k= _bmc_pdata *priv) +{ + void __iomem *base; + int sts, ret; + + base =3D pci_iomap(parent, 0, LS7A_PCI_CFG_SIZE); + if (!base) + return false; + + writel(readl(base + LS7A_PCIE_PORT_CTL0) | LS2K_BMC_PCIE_LTSSM_ENABLE, + base + LS7A_PCIE_PORT_CTL0); + + ret =3D readl_poll_timeout_atomic(base + LS7A_PCIE_PORT_STS1, sts, + (sts & LS2K_BMC_PCIE_LTSSM_STS) =3D=3D LS2K_BMC_PCIE_CONNECTED, + LS2K_BMC_PCIE_DELAY_US, LS2K_BMC_PCIE_TIMEOUT_US); + if (ret) { + pci_iounmap(parent, base); + dev_err(priv->dev, "PCIE train failed status=3D0x%x\n", sts); + return false; + } + + pci_iounmap(parent, base); + return true; +} + +static void ls2k_bmc_restore_bridge_pci_data(struct pci_dev *parent, struc= t ls2k_bmc_pdata *priv) +{ + int base, i =3D 0; + + pci_write_config_dword(parent, PCI_COMMAND, priv->bridge_pci_data.pci_com= mand); + + for (base =3D PCI_BASE_ADDRESS_0; base <=3D PCI_BASE_ADDRESS_5; base +=3D= 4, i++) + pci_write_config_dword(parent, base, priv->bridge_pci_data.base_address[= i]); + + pci_write_config_dword(parent, PCI_ROM_ADDRESS, priv->bridge_pci_data.rom= _addreess); + pci_write_config_dword(parent, PCI_INTERRUPT_LINE, priv->bridge_pci_data.= interrupt_line); + + pci_write_config_dword(parent, parent->msi_cap + PCI_MSI_ADDRESS_LO, + priv->bridge_pci_data.msi_lo); + pci_write_config_dword(parent, parent->msi_cap + PCI_MSI_ADDRESS_HI, + priv->bridge_pci_data.msi_hi); + pci_write_config_dword(parent, parent->pcie_cap + PCI_EXP_DEVCTL, + priv->bridge_pci_data.devctl); + pci_write_config_dword(parent, parent->pcie_cap + PCI_EXP_LNKCAP, + priv->bridge_pci_data.linkcap); + pci_write_config_dword(parent, parent->pcie_cap + PCI_EXP_LNKCTL, + priv->bridge_pci_data.linkctl_sts); + + pci_write_config_dword(parent, LS7A_GEN2_CTL, priv->bridge_pci_data.gen2_= ctrl); + pci_write_config_dword(parent, LS7A_SYMBOL_TIMER, priv->bridge_pci_data.s= ymbol_timer); +} + +static int ls2k_bmc_recover_pci_data(void *data) +{ + struct ls2k_bmc_pdata *priv =3D data; + struct pci_dev *pdev =3D to_pci_dev(priv->dev); + struct pci_dev *parent =3D pdev->bus->self; + u32 i; + + /* + * Clear the bus, io and mem resources of the PCI-E bridge to zero, so th= at + * the processor can not access the LS2K PCI-E port, to avoid crashing du= e to + * the lack of return signal from accessing the LS2K PCI-E port. + */ + pci_write_config_dword(parent, PCI_BASE_ADDRESS_2, 0); + pci_write_config_dword(parent, PCI_BASE_ADDRESS_3, 0); + pci_write_config_dword(parent, PCI_BASE_ADDRESS_4, 0); + + /* + * When the LS2K BMC is reset, the LS7A PCI-E port is also reset, and its= PCI + * BAR0 register is cleared. Due to the time gap between the GPIO interru= pt + * generation and the LS2K BMC reset, the LS7A PCI BAR0 register is read = to + * determine whether the reset has begun. + */ + for (i =3D LS7A_BAR0_CHECK_MAX_TIMES; i > 0 ; i--) { + if (!ls2k_bmc_bar0_addr_is_set(parent)) + break; + mdelay(1); + }; + + if (i =3D=3D 0) + return false; + + ls2k_bmc_restore_bridge_pci_data(parent, priv); + + /* Check if PCI-E is connected */ + if (!ls2k_bmc_pcie_is_connected(parent, priv)) + return false; + + /* Waiting for U-Boot and DDR ready */ + mdelay(LS2K_BMC_RESET_WAIT_TIME); + if (!ls2k_bmc_bar0_addr_is_set(parent)) + return false; + + /* Restore LS2K BMC PCI-E config data */ + pci_write_config_dword(pdev, PCI_COMMAND, priv->bmc_pci_data.pci_command); + pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, priv->bmc_pci_data.base_= address0); + pci_write_config_dword(pdev, PCI_INTERRUPT_LINE, priv->bmc_pci_data.inter= rupt_line); + + return 0; +} + +static void ls2k_bmc_events_fn(struct work_struct *work) +{ + struct ls2k_bmc_pdata *priv =3D container_of(work, struct ls2k_bmc_pdata,= bmc_reset_work); + + /* + * The PCI-E is lost when the BMC resets, at which point access to the PC= I-E + * from other CPUs is suspended to prevent a crash. + */ + stop_machine(ls2k_bmc_recover_pci_data, priv, NULL); + +#ifdef CONFIG_VT + /* Re-push the display due to previous PCI-E loss. */ + set_console(vt_move_to_console(MAX_NR_CONSOLES - 1, 1)); +#endif +} + +static irqreturn_t ls2k_bmc_interrupt(int irq, void *arg) +{ + struct ls2k_bmc_pdata *priv =3D arg; + static unsigned long last_jiffies; + + if (system_state !=3D SYSTEM_RUNNING) + return IRQ_HANDLED; + + /* Skip interrupt in LS2K_BMC_INT_INTERVAL */ + if (time_after(jiffies, last_jiffies + LS2K_BMC_INT_INTERVAL)) { + schedule_work(&priv->bmc_reset_work); + last_jiffies =3D jiffies; + } + + return IRQ_HANDLED; +} + +/* + * Saves the BMC parent device (LS7A) and its own PCI configuration space = registers + * that need to be restored after BMC reset. + */ +static void ls2k_bmc_save_pci_data(struct pci_dev *pdev, struct ls2k_bmc_p= data *priv) +{ + struct pci_dev *parent =3D pdev->bus->self; + int base, i =3D 0; + + pci_read_config_dword(parent, PCI_COMMAND, &priv->bridge_pci_data.pci_com= mand); + + for (base =3D PCI_BASE_ADDRESS_0; base <=3D PCI_BASE_ADDRESS_5; base +=3D= 4, i++) + pci_read_config_dword(parent, base, &priv->bridge_pci_data.base_address[= i]); + + pci_read_config_dword(parent, PCI_ROM_ADDRESS, &priv->bridge_pci_data.rom= _addreess); + pci_read_config_dword(parent, PCI_INTERRUPT_LINE, &priv->bridge_pci_data.= interrupt_line); + + pci_read_config_dword(parent, parent->msi_cap + PCI_MSI_ADDRESS_LO, + &priv->bridge_pci_data.msi_lo); + pci_read_config_dword(parent, parent->msi_cap + PCI_MSI_ADDRESS_HI, + &priv->bridge_pci_data.msi_hi); + + pci_read_config_dword(parent, parent->pcie_cap + PCI_EXP_DEVCTL, + &priv->bridge_pci_data.devctl); + pci_read_config_dword(parent, parent->pcie_cap + PCI_EXP_LNKCAP, + &priv->bridge_pci_data.linkcap); + pci_read_config_dword(parent, parent->pcie_cap + PCI_EXP_LNKCTL, + &priv->bridge_pci_data.linkctl_sts); + + pci_read_config_dword(parent, LS7A_GEN2_CTL, &priv->bridge_pci_data.gen2_= ctrl); + priv->bridge_pci_data.gen2_ctrl |=3D FIELD_PREP(LS7A_GEN2_SPEED_CHANG, 0x= 1) + | FIELD_PREP(LS7A_CONF_PHY_TX, 0x0); + + pci_read_config_dword(parent, LS7A_SYMBOL_TIMER, &priv->bridge_pci_data.s= ymbol_timer); + priv->bridge_pci_data.symbol_timer |=3D LS7A_MASK_LEN_MATCH; + + pci_read_config_dword(pdev, PCI_COMMAND, &priv->bmc_pci_data.pci_command); + pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &priv->bmc_pci_data.base_= address0); + pci_read_config_dword(pdev, PCI_INTERRUPT_LINE, &priv->bmc_pci_data.inter= rupt_line); +} + +static int ls2k_bmc_pdata_initial(struct pci_dev *pdev, struct ls2k_bmc_pd= ata *priv) +{ + int gsi =3D 16 + (LS2K_BMC_RESET_GPIO & 7); + void __iomem *gpio_base; + int irq, ret; + + ls2k_bmc_save_pci_data(pdev, priv); + + INIT_WORK(&priv->bmc_reset_work, ls2k_bmc_events_fn); + + ret =3D devm_request_irq(&pdev->dev, pdev->irq, ls2k_bmc_interrupt, + IRQF_SHARED | IRQF_TRIGGER_FALLING, "ls2kbmc pcie", priv); + if (ret) { + dev_err(priv->dev, "LS2KBMC PCI-E request_irq(%d) failed\n", pdev->irq); + return ret; + } + + /* + * Since Loongson-3 hardware does not support GPIO interrupt cascade, + * chip->gpio_to_irq() cannot be implemented, here acpi_register_gsi() is= used + * to get the GPIO irq. + * The GPIO interrupt is a watchdog interrupt that is triggered when the = BMC resets. + */ + irq =3D acpi_register_gsi(NULL, gsi, ACPI_EDGE_SENSITIVE, ACPI_ACTIVE_LOW= ); + if (irq < 0) + return irq; + + gpio_base =3D ioremap(LOONGSON_GPIO_REG_BASE, LOONGSON_GPIO_REG_SIZE); + if (!gpio_base) { + ret =3D PTR_ERR(gpio_base); + goto acpi_failed; + } + + writel(readl(gpio_base + LOONGSON_GPIO_OEN) | BIT(LS2K_BMC_RESET_GPIO), + gpio_base + LOONGSON_GPIO_OEN); + writel(readl(gpio_base + LOONGSON_GPIO_FUNC) & ~BIT(LS2K_BMC_RESET_GPIO), + gpio_base + LOONGSON_GPIO_FUNC); + writel(readl(gpio_base + LOONGSON_GPIO_INTPOL) & ~BIT(LS2K_BMC_RESET_GPIO= ), + gpio_base + LOONGSON_GPIO_INTPOL); + writel(readl(gpio_base + LOONGSON_GPIO_INTEN) | BIT(LS2K_BMC_RESET_GPIO), + gpio_base + LOONGSON_GPIO_INTEN); + + ret =3D devm_request_irq(priv->dev, irq, ls2k_bmc_interrupt, + IRQF_SHARED | IRQF_TRIGGER_FALLING, "ls2kbmc gpio", priv); + if (ret) + dev_err(priv->dev, "LS2KBMC GPIO request_irq(%d) failed\n", irq); + + iounmap(gpio_base); + +acpi_failed: + acpi_unregister_gsi(gsi); + return ret; +} + /* * Currently the Loongson-2K BMC hardware does not have an I2C interface t= o adapt to the * resolution. We set the resolution by presetting "video=3D1280x1024-16@2= M" to the BMC memory. @@ -101,6 +417,7 @@ static int ls2k_bmc_parse_mode(struct pci_dev *pdev, st= ruct simplefb_platform_da static int ls2k_bmc_probe(struct pci_dev *dev, const struct pci_device_id = *id) { struct simplefb_platform_data pd; + struct ls2k_bmc_pdata *priv; resource_size_t base; int ret; =20 @@ -108,6 +425,18 @@ static int ls2k_bmc_probe(struct pci_dev *dev, const s= truct pci_device_id *id) if (ret) return ret; =20 + priv =3D devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL); + if (IS_ERR(priv)) { + ret =3D -ENOMEM; + goto disable_pci; + } + + priv->dev =3D &dev->dev; + + ret =3D ls2k_bmc_pdata_initial(dev, priv); + if (ret) + goto disable_pci; + ret =3D ls2k_bmc_parse_mode(dev, &pd); if (ret) goto disable_pci; --=20 2.47.1 From nobody Fri Oct 10 17:21:33 2025 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 9799325BEF0 for ; Fri, 13 Jun 2025 06:44:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749797048; cv=none; b=Spp+paW6V4yELnhFbd8ZRnNbhUc4s8uIqnJCOYePq/zoDe9snxV/liHHZxt+eWMBN7IjcdpeqTA23+d5uYJhthO8rL1IStW/TfKGYnL+4HlvaNzysfyINEeFhFyk1Dn3yMiAm/EJt492lQ3/0qjUqB8T78P1OaQ+O/0fnnYOJtw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749797048; c=relaxed/simple; bh=PEKi0DGSwdKIODhslH3SRmuFPbO/SNtjwACOkygV81k=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GzqkZQtlvyxG9QCfVxpUIwiOOGUpV1ExpoxjZ7r3Ra2CXf+HPLadxcoLRs8cqoUXtJXktBMWE1mOmaztE7P7DOyroB2mb0I/FHR76mFwMezPwo6TI/kikQONNSPKwyqJD84lqBYcWDSG4UGwGaU4yzgvkP/sbaF7IiSmf2kuEnU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [223.64.68.149]) by gateway (Coremail) with SMTP id _____8AxLOKyyEtoqYwVAQ--.10707S3; Fri, 13 Jun 2025 14:44:02 +0800 (CST) Received: from localhost.localdomain (unknown [223.64.68.149]) by front1 (Coremail) with SMTP id qMiowMBx3MSlyEto29MYAQ--.8851S5; Fri, 13 Jun 2025 14:43:57 +0800 (CST) From: Binbin Zhou To: Binbin Zhou , Huacai Chen , Lee Jones , Corey Minyard Cc: Huacai Chen , Xuerui Wang , loongarch@lists.linux.dev, linux-kernel@vger.kernel.org, openipmi-developer@lists.sourceforge.net, jeffbai@aosc.io, kexybiscuit@aosc.io, wangyao@lemote.com, Binbin Zhou , Chong Qiao Subject: [PATCH v4 3/3] ipmi: Add Loongson-2K BMC support Date: Fri, 13 Jun 2025 14:43:41 +0800 Message-ID: <705a60677e848449f414206ae56515c767c12d8c.1749731531.git.zhoubinbin@loongson.cn> X-Mailer: git-send-email 2.47.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMBx3MSlyEto29MYAQ--.8851S5 X-CM-SenderInfo: p2kr3uplqex0o6or00hjvr0hdfq/ X-Coremail-Antispam: 1Uk129KBj93XoW3Ar1xAw48JrW5Gr15uF48uFX_yoW3uw1rp3 Waya43Cr48tF47K39rZryDWFyrCwnxW3Wrtr47W34ruFWj9w1vgrn2yaySyry7ta40q3y3 JrZxArW3WF13JwcCm3ZEXasCq-sJn29KB7ZKAUJUUUU3529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUBYb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r126r13M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Ar0_tr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Cr0_Gr1UM28EF7xvwVC2z280aVAFwI0_GcCE3s1l84ACjcxK6I8E87Iv6xkF7I0E14v2 6rxl6s0DM2kKe7AKxVWUAVWUtwAS0I0E0xvYzxvE52x082IY62kv0487Mc804VCY07AIYI kI8VC2zVCFFI0UMc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2IY67AKxVWrXVW3 AwAv7VC2z280aVAFwI0_Gr0_Cr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0Y48IcxkI7VAKI4 8JMxkF7I0En4kS14v26r126r1DMxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j 6r4UMxCIbckI1I0E14v26r126r1DMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwV AFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUtVW8ZwCIc40Y0x0EwIxGrwCI42IY6xIIjxv2 0xvE14v26ryj6F1UMIIF0xvE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwCI42IY6xAIw20EY4 v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Gr0_Cr1lIxAIcVC2z280aVCY1x0267AK xVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7IU0XzstUUUUU== Content-Type: text/plain; charset="utf-8" This patch adds Loongson-2K BMC IPMI support. According to the existing design, we use software simulation to implement the KCS interface registers: Stauts/Command/Data_Out/Data_In. Also since both host side and BMC side read and write kcs status, fifo flag is used to ensure data consistency. The single KCS message block is as follows: +-------------------------------------------------------------------------+ |FIFO flags| KCS register data | CMD data | KCS version | WR REQ | WR ACK | +-------------------------------------------------------------------------+ Reviewed-by: Huacai Chen Co-developed-by: Chong Qiao Signed-off-by: Chong Qiao Signed-off-by: Binbin Zhou --- drivers/char/ipmi/Makefile | 1 + drivers/char/ipmi/ipmi_si.h | 7 ++ drivers/char/ipmi/ipmi_si_intf.c | 3 + drivers/char/ipmi/ipmi_si_ls2k.c | 189 +++++++++++++++++++++++++++++++ 4 files changed, 200 insertions(+) create mode 100644 drivers/char/ipmi/ipmi_si_ls2k.c diff --git a/drivers/char/ipmi/Makefile b/drivers/char/ipmi/Makefile index e0944547c9d0..17308dd6be20 100644 --- a/drivers/char/ipmi/Makefile +++ b/drivers/char/ipmi/Makefile @@ -8,6 +8,7 @@ ipmi_si-y :=3D ipmi_si_intf.o ipmi_kcs_sm.o ipmi_smic_sm.o = ipmi_bt_sm.o \ ipmi_si_mem_io.o ipmi_si-$(CONFIG_HAS_IOPORT) +=3D ipmi_si_port_io.o ipmi_si-$(CONFIG_PCI) +=3D ipmi_si_pci.o +ipmi_si-$(CONFIG_MFD_LS2K_BMC) +=3D ipmi_si_ls2k.o ipmi_si-$(CONFIG_PARISC) +=3D ipmi_si_parisc.o =20 obj-$(CONFIG_IPMI_HANDLER) +=3D ipmi_msghandler.o diff --git a/drivers/char/ipmi/ipmi_si.h b/drivers/char/ipmi/ipmi_si.h index 508c3fd45877..f38ea4f4c891 100644 --- a/drivers/char/ipmi/ipmi_si.h +++ b/drivers/char/ipmi/ipmi_si.h @@ -101,6 +101,13 @@ void ipmi_si_pci_shutdown(void); static inline void ipmi_si_pci_init(void) { } static inline void ipmi_si_pci_shutdown(void) { } #endif +#ifdef CONFIG_MFD_LS2K_BMC +void ipmi_si_ls2k_init(void); +void ipmi_si_ls2k_shutdown(void); +#else +static inline void ipmi_si_ls2k_init(void) { } +static inline void ipmi_si_ls2k_shutdown(void) { } +#endif #ifdef CONFIG_PARISC void ipmi_si_parisc_init(void); void ipmi_si_parisc_shutdown(void); diff --git a/drivers/char/ipmi/ipmi_si_intf.c b/drivers/char/ipmi/ipmi_si_i= ntf.c index 7fe891783a37..c13d5132fffc 100644 --- a/drivers/char/ipmi/ipmi_si_intf.c +++ b/drivers/char/ipmi/ipmi_si_intf.c @@ -2120,6 +2120,8 @@ static int __init init_ipmi_si(void) =20 ipmi_si_pci_init(); =20 + ipmi_si_ls2k_init(); + ipmi_si_parisc_init(); =20 mutex_lock(&smi_infos_lock); @@ -2334,6 +2335,8 @@ static void cleanup_ipmi_si(void) =20 ipmi_si_pci_shutdown(); =20 + ipmi_si_ls2k_shutdown(); + ipmi_si_parisc_shutdown(); =20 ipmi_si_platform_shutdown(); diff --git a/drivers/char/ipmi/ipmi_si_ls2k.c b/drivers/char/ipmi/ipmi_si_l= s2k.c new file mode 100644 index 000000000000..7b360056f9c5 --- /dev/null +++ b/drivers/char/ipmi/ipmi_si_ls2k.c @@ -0,0 +1,189 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Driver for Loongson-2K BMC IPMI + * + * Copyright (C) 2024-2025 Loongson Technology Corporation Limited. + * + * Authors: + * Chong Qiao + * Binbin Zhou + */ + +#include +#include +#include +#include + +#include "ipmi_si.h" + +#define LS2K_KCS_FIFO_IBFH 0x0 +#define LS2K_KCS_FIFO_IBFT 0x1 +#define LS2K_KCS_FIFO_OBFH 0x2 +#define LS2K_KCS_FIFO_OBFT 0x3 + +/* KCS registers */ +#define LS2K_KCS_REG_STS 0x4 +#define LS2K_KCS_REG_DATA_OUT 0x5 +#define LS2K_KCS_REG_DATA_IN 0x6 +#define LS2K_KCS_REG_CMD 0x8 + +#define LS2K_KCS_CMD_DATA 0xa +#define LS2K_KCS_VERSION 0xb +#define LS2K_KCS_WR_REQ 0xc +#define LS2K_KCS_WR_ACK 0x10 + +#define LS2K_KCS_STS_OBF BIT(0) +#define LS2K_KCS_STS_IBF BIT(1) +#define LS2K_KCS_STS_SMS_ATN BIT(2) +#define LS2K_KCS_STS_CMD BIT(3) + +#define LS2K_KCS_DATA_MASK (LS2K_KCS_STS_OBF | LS2K_KCS_STS_IBF | LS2K_KCS= _STS_CMD) + +static bool ls2k_registered; + +static unsigned char ls2k_mem_inb_v0(const struct si_sm_io *io, unsigned i= nt offset) +{ + void __iomem *addr =3D io->addr; + int reg_offset; + + if (offset & BIT(0)) { + reg_offset =3D LS2K_KCS_REG_STS; + } else { + writeb(readb(addr + LS2K_KCS_REG_STS) & ~LS2K_KCS_STS_OBF, addr + LS2K_K= CS_REG_STS); + reg_offset =3D LS2K_KCS_REG_DATA_OUT; + } + + return readb(addr + reg_offset); +} + +static unsigned char ls2k_mem_inb_v1(const struct si_sm_io *io, unsigned i= nt offset) +{ + void __iomem *addr =3D io->addr; + unsigned char inb =3D 0, cmd; + bool obf, ibf; + + obf =3D readb(addr + LS2K_KCS_FIFO_OBFH) ^ readb(addr + LS2K_KCS_FIFO_OBF= T); + ibf =3D readb(addr + LS2K_KCS_FIFO_IBFH) ^ readb(addr + LS2K_KCS_FIFO_IBF= T); + cmd =3D readb(addr + LS2K_KCS_CMD_DATA); + + if (offset & BIT(0)) { + inb =3D readb(addr + LS2K_KCS_REG_STS) & ~LS2K_KCS_DATA_MASK; + inb |=3D FIELD_PREP(LS2K_KCS_STS_OBF, obf) + | FIELD_PREP(LS2K_KCS_STS_IBF, ibf) + | FIELD_PREP(LS2K_KCS_STS_CMD, cmd); + } else { + inb =3D readb(addr + LS2K_KCS_REG_DATA_OUT); + writeb(readb(addr + LS2K_KCS_FIFO_OBFH), addr + LS2K_KCS_FIFO_OBFT); + } + + return inb; +} + +static void ls2k_mem_outb_v0(const struct si_sm_io *io, unsigned int offse= t, + unsigned char val) +{ + void __iomem *addr =3D io->addr; + unsigned char sts =3D readb(addr + LS2K_KCS_REG_STS); + int reg_offset; + + if (sts & LS2K_KCS_STS_IBF) + return; + + if (offset & BIT(0)) { + reg_offset =3D LS2K_KCS_REG_CMD; + sts |=3D LS2K_KCS_STS_CMD; + } else { + reg_offset =3D LS2K_KCS_REG_DATA_IN; + sts &=3D ~LS2K_KCS_STS_CMD; + } + + writew(val, addr + reg_offset); + writeb(sts | LS2K_KCS_STS_IBF, addr + LS2K_KCS_REG_STS); + writel(readl(addr + LS2K_KCS_WR_REQ) + 1, addr + LS2K_KCS_WR_REQ); +} + +static void ls2k_mem_outb_v1(const struct si_sm_io *io, unsigned int offse= t, + unsigned char val) +{ + void __iomem *addr =3D io->addr; + unsigned char ibfh, ibft; + int reg_offset; + + ibfh =3D readb(addr + LS2K_KCS_FIFO_IBFH); + ibft =3D readb(addr + LS2K_KCS_FIFO_IBFT); + + if (ibfh ^ ibft) + return; + + reg_offset =3D (offset & BIT(0)) ? LS2K_KCS_REG_CMD : LS2K_KCS_REG_DATA_I= N; + writew(val, addr + reg_offset); + + writeb(offset & BIT(0), addr + LS2K_KCS_CMD_DATA); + writeb(!ibft, addr + LS2K_KCS_FIFO_IBFH); + writel(readl(addr + LS2K_KCS_WR_REQ) + 1, addr + LS2K_KCS_WR_REQ); +} + +static void ls2k_mem_cleanup(struct si_sm_io *io) +{ + if (io->addr) + iounmap(io->addr); +} + +static int ipmi_ls2k_mem_setup(struct si_sm_io *io) +{ + unsigned char version; + + io->addr =3D ioremap(io->addr_data, io->regspacing); + if (!io->addr) + return -EIO; + + version =3D readb(io->addr + LS2K_KCS_VERSION); + + io->inputb =3D version ? ls2k_mem_inb_v1 : ls2k_mem_inb_v0; + io->outputb =3D version ? ls2k_mem_outb_v1 : ls2k_mem_outb_v0; + io->io_cleanup =3D ls2k_mem_cleanup; + + return 0; +} + +static int ipmi_ls2k_probe(struct platform_device *pdev) +{ + struct si_sm_io io; + + memset(&io, 0, sizeof(io)); + + io.si_info =3D &ipmi_kcs_si_info; + io.io_setup =3D ipmi_ls2k_mem_setup; + io.addr_data =3D pdev->resource[0].start; + io.regspacing =3D resource_size(&pdev->resource[0]); + io.dev =3D &pdev->dev; + + dev_dbg(&pdev->dev, "addr 0x%lx, spacing %d.\n", io.addr_data, io.regspac= ing); + + return ipmi_si_add_smi(&io); +} + +static void ipmi_ls2k_remove(struct platform_device *pdev) +{ + ipmi_si_remove_by_dev(&pdev->dev); +} + +struct platform_driver ipmi_ls2k_platform_driver =3D { + .driver =3D { + .name =3D "ls2k-ipmi-si", + }, + .probe =3D ipmi_ls2k_probe, + .remove =3D ipmi_ls2k_remove, +}; + +void ipmi_si_ls2k_init(void) +{ + platform_driver_register(&ipmi_ls2k_platform_driver); + ls2k_registered =3D true; +} + +void ipmi_si_ls2k_shutdown(void) +{ + if (ls2k_registered) + platform_driver_unregister(&ipmi_ls2k_platform_driver); +} --=20 2.47.1