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Tue, 10 Jun 2025 12:05:33 -0700 (PDT) Received: from geday ([2804:7f2:800b:5a56::dead:c001]) by smtp.gmail.com with ESMTPSA id 71dfb90a1353d-531224b91aesm192109e0c.8.2025.06.10.12.05.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Jun 2025 12:05:33 -0700 (PDT) Date: Tue, 10 Jun 2025 16:05:28 -0300 From: Geraldo Nascimento To: linux-rockchip@lists.infradead.org Cc: Hugh Cole-Baker , Shawn Lin , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH v3 1/3] PCI: rockchip-host: reorder rockchip_pcie_set_vpcie() Message-ID: <55166f9fb72229f9cfd40b5334083b8837548a18.1749582046.git.geraldogabriel@gmail.com> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" rockchip_pcie_set_vpcie() is needed for re-enabling power regulators after disabling them, if link training fails. This permits quirky endpoint devices to complete link training, enumerate sucessfully on the PCI bus and generally work with RK3399 PCIe. Reorder the function - no functional change intended. Signed-off-by: Geraldo Nascimento --- drivers/pci/controller/pcie-rockchip-host.c | 94 ++++++++++----------- 1 file changed, 47 insertions(+), 47 deletions(-) diff --git a/drivers/pci/controller/pcie-rockchip-host.c b/drivers/pci/cont= roller/pcie-rockchip-host.c index b9e7a8710cf0..2a1071cd3241 100644 --- a/drivers/pci/controller/pcie-rockchip-host.c +++ b/drivers/pci/controller/pcie-rockchip-host.c @@ -284,6 +284,53 @@ static void rockchip_pcie_set_power_limit(struct rockc= hip_pcie *rockchip) rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_DCR); } =20 +static int rockchip_pcie_set_vpcie(struct rockchip_pcie *rockchip) +{ + struct device *dev =3D rockchip->dev; + int err; + + if (!IS_ERR(rockchip->vpcie12v)) { + err =3D regulator_enable(rockchip->vpcie12v); + if (err) { + dev_err(dev, "fail to enable vpcie12v regulator\n"); + goto err_out; + } + } + + if (!IS_ERR(rockchip->vpcie3v3)) { + err =3D regulator_enable(rockchip->vpcie3v3); + if (err) { + dev_err(dev, "fail to enable vpcie3v3 regulator\n"); + goto err_disable_12v; + } + } + + err =3D regulator_enable(rockchip->vpcie1v8); + if (err) { + dev_err(dev, "fail to enable vpcie1v8 regulator\n"); + goto err_disable_3v3; + } + + err =3D regulator_enable(rockchip->vpcie0v9); + if (err) { + dev_err(dev, "fail to enable vpcie0v9 regulator\n"); + goto err_disable_1v8; + } + + return 0; + +err_disable_1v8: + regulator_disable(rockchip->vpcie1v8); +err_disable_3v3: + if (!IS_ERR(rockchip->vpcie3v3)) + regulator_disable(rockchip->vpcie3v3); +err_disable_12v: + if (!IS_ERR(rockchip->vpcie12v)) + regulator_disable(rockchip->vpcie12v); +err_out: + return err; +} + /** * rockchip_pcie_host_init_port - Initialize hardware * @rockchip: PCIe port information @@ -613,53 +660,6 @@ static int rockchip_pcie_parse_host_dt(struct rockchip= _pcie *rockchip) return 0; } =20 -static int rockchip_pcie_set_vpcie(struct rockchip_pcie *rockchip) -{ - struct device *dev =3D rockchip->dev; - int err; - - if (!IS_ERR(rockchip->vpcie12v)) { - err =3D regulator_enable(rockchip->vpcie12v); - if (err) { - dev_err(dev, "fail to enable vpcie12v regulator\n"); - goto err_out; - } - } - - if (!IS_ERR(rockchip->vpcie3v3)) { - err =3D regulator_enable(rockchip->vpcie3v3); - if (err) { - dev_err(dev, "fail to enable vpcie3v3 regulator\n"); - goto err_disable_12v; - } - } - - err =3D regulator_enable(rockchip->vpcie1v8); - if (err) { - dev_err(dev, "fail to enable vpcie1v8 regulator\n"); - goto err_disable_3v3; - } - - err =3D regulator_enable(rockchip->vpcie0v9); - if (err) { - dev_err(dev, "fail to enable vpcie0v9 regulator\n"); - goto err_disable_1v8; - } - - return 0; - -err_disable_1v8: - regulator_disable(rockchip->vpcie1v8); -err_disable_3v3: - if (!IS_ERR(rockchip->vpcie3v3)) - regulator_disable(rockchip->vpcie3v3); -err_disable_12v: - if (!IS_ERR(rockchip->vpcie12v)) - regulator_disable(rockchip->vpcie12v); -err_out: - return err; -} - static void rockchip_pcie_enable_interrupts(struct rockchip_pcie *rockchip) { rockchip_pcie_write(rockchip, (PCIE_CLIENT_INT_CLI << 16) & --=20 2.49.0 From nobody Sat Oct 11 08:26:22 2025 Received: from mail-vk1-f177.google.com (mail-vk1-f177.google.com [209.85.221.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5AB4F25F995; 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Tue, 10 Jun 2025 12:05:46 -0700 (PDT) Received: from geday ([2804:7f2:800b:5a56::dead:c001]) by smtp.gmail.com with ESMTPSA id ada2fe7eead31-4e7bb060aaasm150155137.24.2025.06.10.12.05.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Jun 2025 12:05:45 -0700 (PDT) Date: Tue, 10 Jun 2025 16:05:40 -0300 From: Geraldo Nascimento To: linux-rockchip@lists.infradead.org Cc: Hugh Cole-Baker , Shawn Lin , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH v3 2/3] PCI: rockchip-host: Retry link training on failure without PERST# Message-ID: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" After almost 30 days of battling with RK3399 buggy PCIe on my Rock Pi N10 through trial-and-error debugging, I finally got positive results with enumeration on the PCI bus for both a Realtek 8111E NIC and a Samsung PM981a SSD. The NIC was connected to a M.2->PCIe x4 riser card and it would get stuck on Polling.Compliance, without breaking electrical idle on the Host RX side. The Samsung PM981a SSD is directly connected to M.2 connector and that SSD is known to be quirky (OEM... no support) and non-functional on the RK3399 platform. The Samsung SSD was even worse than the NIC - it would get stuck on Detect.Active like a bricked card, even though it was fully functional via USB adapter. It seems both devices benefit from retrying Link Training if - big if here - PERST# is not toggled during retry. For retry to work, flow must be exactly as handled by present patch, that is, we must cut power, disable the clocks, then re-enable both clocks and power regulators and go through initialization without touching PERST#. Then quirky devices are able to sucessfully enumerate. No functional change intended for already working devices. Signed-off-by: Geraldo Nascimento --- drivers/pci/controller/pcie-rockchip-host.c | 47 ++++++++++++++++++--- 1 file changed, 40 insertions(+), 7 deletions(-) diff --git a/drivers/pci/controller/pcie-rockchip-host.c b/drivers/pci/cont= roller/pcie-rockchip-host.c index 2a1071cd3241..67b3b379d277 100644 --- a/drivers/pci/controller/pcie-rockchip-host.c +++ b/drivers/pci/controller/pcie-rockchip-host.c @@ -338,11 +338,14 @@ static int rockchip_pcie_set_vpcie(struct rockchip_pc= ie *rockchip) static int rockchip_pcie_host_init_port(struct rockchip_pcie *rockchip) { struct device *dev =3D rockchip->dev; - int err, i =3D MAX_LANE_NUM; + int err, i =3D MAX_LANE_NUM, is_reinit =3D 0; u32 status; =20 - gpiod_set_value_cansleep(rockchip->perst_gpio, 0); + if (!is_reinit) { + gpiod_set_value_cansleep(rockchip->perst_gpio, 0); + } =20 +reinit: err =3D rockchip_pcie_init_port(rockchip); if (err) return err; @@ -369,16 +372,46 @@ static int rockchip_pcie_host_init_port(struct rockch= ip_pcie *rockchip) rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE, PCIE_CLIENT_CONFIG); =20 - msleep(PCIE_T_PVPERL_MS); - gpiod_set_value_cansleep(rockchip->perst_gpio, 1); - - msleep(PCIE_T_RRS_READY_MS); + if (!is_reinit) { + msleep(PCIE_T_PVPERL_MS); + gpiod_set_value_cansleep(rockchip->perst_gpio, 1); + msleep(PCIE_T_RRS_READY_MS); + } =20 /* 500ms timeout value should be enough for Gen1/2 training */ err =3D readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_BASIC_STATUS1, status, PCIE_LINK_UP(status), 20, 500 * USEC_PER_MSEC); - if (err) { + + if (err && !is_reinit) { + while (i--) + phy_power_off(rockchip->phys[i]); + i =3D MAX_LANE_NUM; + while (i--) + phy_exit(rockchip->phys[i]); + i =3D MAX_LANE_NUM; + is_reinit =3D 1; + dev_dbg(dev, "Will reinit PCIe without toggling PERST#"); + if (!IS_ERR(rockchip->vpcie12v)) + regulator_disable(rockchip->vpcie12v); + if (!IS_ERR(rockchip->vpcie3v3)) + regulator_disable(rockchip->vpcie3v3); + regulator_disable(rockchip->vpcie1v8); + regulator_disable(rockchip->vpcie0v9); + rockchip_pcie_disable_clocks(rockchip); + err =3D rockchip_pcie_enable_clocks(rockchip); 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Tue, 10 Jun 2025 12:05:59 -0700 (PDT) Received: from geday ([2804:7f2:800b:5a56::dead:c001]) by smtp.gmail.com with ESMTPSA id 71dfb90a1353d-53113bf5a61sm1854439e0c.25.2025.06.10.12.05.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Jun 2025 12:05:59 -0700 (PDT) Date: Tue, 10 Jun 2025 16:05:53 -0300 From: Geraldo Nascimento To: linux-rockchip@lists.infradead.org Cc: Hugh Cole-Baker , Shawn Lin , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH v3 3/3] arm64: dts: rockchip: drop PCIe 3v3 always-on and boot-on Message-ID: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Example commit of needed dropping of regulator always-on/boot-on declarations to make sure quirky devices known to not be working on RK3399 are able to enumerate on second try without assertion/deassertion of PERST# in-band PCIe reset signal. One example only, to avoid patch-bomb. Signed-off-by: Geraldo Nascimento --- arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi b/arch/a= rm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi index 8ce7cee92af0..d31fd3d34cda 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi @@ -25,8 +25,6 @@ vcc3v3_pcie: regulator-vcc-pcie { pinctrl-names =3D "default"; pinctrl-0 =3D <&pcie_pwr>; regulator-name =3D "vcc3v3_pcie"; - regulator-always-on; - regulator-boot-on; vin-supply =3D <&vcc5v0_sys>; }; =20 --=20 2.49.0