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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 May 2025 19:52:13.4253 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8949ffc4-61a3-43b5-b62a-08dd996a25c2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BY1PEPF0001AE1A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6590 Content-Type: text/plain; charset="utf-8" Smart Data Cache Injection (SDCI) is a mechanism that enables direct insertion of data from I/O devices into the L3 cache. By directly caching data from I/O devices rather than first storing the I/O data in DRAM, SDCI reduces demands on DRAM bandwidth and reduces latency to the processor consuming the I/O data. The SDCIAE (SDCI Allocation Enforcement) PQE feature allows system software to control the portion of the L3 cache used for SDCI. When enabled, SDCIAE forces all SDCI lines to be placed into the L3 cache partitions identified by the highest-supported L3_MASK_n register, where n is the maximum supported CLOSID. Add CPUID feature bit that can be used to configure SDCIAE. The feature details are documented in APM listed below [1]. [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming Publication # 24593 Revision 3.41 section 19.4.7 L3 Smart Data Cache Injection Allocation Enforcement (SDCIAE) Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537 Signed-off-by: Babu Moger --- v5: No changes. v4: Resolved a minor conflict in cpufeatures.h. v3: No changes. v2: Added dependancy on X86_FEATURE_CAT_L3 Removed the "" in CPU feature definition. Minor text changes. --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/cpuid-deps.c | 1 + arch/x86/kernel/cpu/scattered.c | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index 6c2c152d8a67..8dfbea91bef6 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -481,6 +481,7 @@ #define X86_FEATURE_AMD_HETEROGENEOUS_CORES (21*32 + 6) /* Heterogeneous C= ore Topology */ #define X86_FEATURE_AMD_WORKLOAD_CLASS (21*32 + 7) /* Workload Classificat= ion */ #define X86_FEATURE_PREFER_YMM (21*32 + 8) /* Avoid ZMM registers due to = downclocking */ +#define X86_FEATURE_SDCIAE (21*32 + 9) /* L3 Smart Data Cache Injection A= llocation Enforcement */ =20 /* * BUG word(s) diff --git a/arch/x86/kernel/cpu/cpuid-deps.c b/arch/x86/kernel/cpu/cpuid-d= eps.c index a2fbea0be535..2687ae01a471 100644 --- a/arch/x86/kernel/cpu/cpuid-deps.c +++ b/arch/x86/kernel/cpu/cpuid-deps.c @@ -71,6 +71,7 @@ static const struct cpuid_dep cpuid_deps[] =3D { { X86_FEATURE_CQM_MBM_LOCAL, X86_FEATURE_CQM_LLC }, { X86_FEATURE_BMEC, X86_FEATURE_CQM_MBM_TOTAL }, { X86_FEATURE_BMEC, X86_FEATURE_CQM_MBM_LOCAL }, + { X86_FEATURE_SDCIAE, X86_FEATURE_CAT_L3 }, { X86_FEATURE_AVX512_BF16, X86_FEATURE_AVX512VL }, { X86_FEATURE_AVX512_FP16, X86_FEATURE_AVX512BW }, { X86_FEATURE_ENQCMD, X86_FEATURE_XSAVES }, diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattere= d.c index 16f3ca30626a..d18a7ce16388 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -49,6 +49,7 @@ static const struct cpuid_bit cpuid_bits[] =3D { { X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 }, { X86_FEATURE_SMBA, CPUID_EBX, 2, 0x80000020, 0 }, { X86_FEATURE_BMEC, CPUID_EBX, 3, 0x80000020, 0 }, + { X86_FEATURE_SDCIAE, CPUID_EBX, 6, 0x80000020, 0 }, { X86_FEATURE_AMD_WORKLOAD_CLASS, CPUID_EAX, 22, 0x80000021, 0 }, { X86_FEATURE_PERFMON_V2, CPUID_EAX, 0, 0x80000022, 0 }, { X86_FEATURE_AMD_LBR_V2, CPUID_EAX, 1, 0x80000022, 0 }, --=20 2.34.1 From nobody Sun Dec 14 06:34:44 2025 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2076.outbound.protection.outlook.com [40.107.92.76]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E5E471F5846; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 May 2025 19:52:22.2763 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e84ccc94-05b0-4729-517b-08dd996a2b08 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BY1PEPF0001AE1D.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS2PR12MB9687 Content-Type: text/plain; charset="utf-8" Add the command line options to enable or disable the new resctrl feature L3 Smart Data Cache Injection Allocation Enforcement (SDCIAE). Signed-off-by: Babu Moger --- v5: No changes. v4: No changes. v3: No changes. v2: No changes. --- Documentation/admin-guide/kernel-parameters.txt | 2 +- arch/x86/kernel/cpu/resctrl/core.c | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentatio= n/admin-guide/kernel-parameters.txt index d9fd26b95b34..f63aa8c5671d 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -5988,7 +5988,7 @@ rdt=3D [HW,X86,RDT] Turn on/off individual RDT features. List is: cmt, mbmtotal, mbmlocal, l3cat, l3cdp, l2cat, l2cdp, - mba, smba, bmec. + mba, smba, bmec, sdciae. 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 May 2025 19:52:34.0942 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 820efd53-6ca8-4b09-6af5-08dd996a3214 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BY1PEPF0001AE1D.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA5PPF6407DD448 Content-Type: text/plain; charset="utf-8" Smart Data Cache Injection (SDCI) is a mechanism that enables direct insertion of data from I/O devices into the L3 cache. It can the demands on DRAM bandwidth and reduces latency to the processor consuming the I/O data. Introduce cache resource property "io_alloc_capable" that an architecture can set if a portion of the L3 cache can be allocated for I/O traffic. Set this property on x86 systems that support SDCIAE (L3 Smart Data Cache Injection Allocation Enforcement). Signed-off-by: Babu Moger --- v5: No changes. v4: Updated the commit message and code comment based on feedback. v3: Rewrote commit log. Changed the text to bit generic than the AMD specif= ic. Renamed the rdt_get_sdciae_alloc_cfg() to rdt_set_io_alloc_capable(). Removed leftover comment from v2. v2: Changed sdciae_capable to io_alloc_capable to make it generic feature. Also moved the io_alloc_capable in struct resctrl_cache. --- arch/x86/kernel/cpu/resctrl/core.c | 7 +++++++ include/linux/resctrl.h | 3 +++ 2 files changed, 10 insertions(+) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index 2161520114dc..1cbcf70d6036 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -273,6 +273,11 @@ static void rdt_get_cdp_config(int level) rdt_resources_all[level].r_resctrl.cdp_capable =3D true; } =20 +static void rdt_set_io_alloc_capable(struct rdt_resource *r) +{ + r->cache.io_alloc_capable =3D true; +} + static void rdt_get_cdp_l3_config(void) { rdt_get_cdp_config(RDT_RESOURCE_L3); @@ -839,6 +844,8 @@ static __init bool get_rdt_alloc_resources(void) rdt_get_cache_alloc_cfg(1, r); if (rdt_cpu_has(X86_FEATURE_CDP_L3)) rdt_get_cdp_l3_config(); + if (rdt_cpu_has(X86_FEATURE_SDCIAE)) + rdt_set_io_alloc_capable(r); ret =3D true; } if (rdt_cpu_has(X86_FEATURE_CAT_L2)) { diff --git a/include/linux/resctrl.h b/include/linux/resctrl.h index 9ba771f2ddea..0e8641e41100 100644 --- a/include/linux/resctrl.h +++ b/include/linux/resctrl.h @@ -191,6 +191,8 @@ struct rdt_mon_domain { * @arch_has_sparse_bitmasks: True if a bitmask like f00f is valid. * @arch_has_per_cpu_cfg: True if QOS_CFG register for this cache * level has CPU scope. + * @io_alloc_capable: True if portion of the cache can be allocated + * for I/O traffic. */ struct resctrl_cache { unsigned int cbm_len; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 May 2025 19:52:41.7072 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9d59c1a7-41f7-4509-5612-08dd996a369e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BY1PEPF0001AE1D.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5756 Content-Type: text/plain; charset="utf-8" "io_alloc" enables direct insertion of data from I/O devices into the L3 cache. On AMD, "io_alloc" feature is backed by L3 Smart Data Cache Injection Allocation Enforcement (SDCIAE). Change SDCIAE state by setting (to enable) or clearing (to disable) bit 1 of MSR L3_QOS_EXT_CFG on all logical processors within the cache domain. Introduce architecture-specific handlers to enable and disable the feature. The SDCIAE feature details are available in APM listed below [1]. [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming Publication # 24593 Revision 3.41 section 19.4.7 L3 Smart Data Cache Injection Allocation Enforcement (SDCIAE) Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537 Signed-off-by: Babu Moger --- v5: Resolved conflicts due to recent resctrl FS/ARCH code restructure. The files monitor.c/rdtgroup.c have been split between FS and ARCH dire= ctories. Moved prototypes of resctrl_arch_io_alloc_enable() and resctrl_arch_get_io_alloc_enabled() to include/linux/resctrl.h. v4: Updated the commit log to address the feedback. v3: Passed the struct rdt_resource to resctrl_arch_get_io_alloc_enabled() i= nstead of resource id. Renamed the _resctrl_io_alloc_enable() to _resctrl_sdciae_enable() as i= t is arch specific. Changed the return to void in _resctrl_sdciae_enable() instead of int. Added more context in commit log and fixed few typos. v2: Renamed the functions to simplify the code. Renamed sdciae_capable to io_alloc_capable. Changed the name of few arch functions similar to ABMC series. resctrl_arch_get_io_alloc_enabled() resctrl_arch_io_alloc_enable() --- arch/x86/include/asm/msr-index.h | 1 + arch/x86/kernel/cpu/resctrl/internal.h | 5 ++++ arch/x86/kernel/cpu/resctrl/rdtgroup.c | 37 ++++++++++++++++++++++++++ include/linux/resctrl.h | 15 +++++++++++ 4 files changed, 58 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-in= dex.h index e6134ef2263d..3970e0b16e47 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -1203,6 +1203,7 @@ /* - AMD: */ #define MSR_IA32_MBA_BW_BASE 0xc0000200 #define MSR_IA32_SMBA_BW_BASE 0xc0000280 +#define MSR_IA32_L3_QOS_EXT_CFG 0xc00003ff #define MSR_IA32_EVT_CFG_BASE 0xc0000400 =20 /* AMD-V MSRs */ diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index 5e3c41b36437..cfa519ea2875 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -37,6 +37,9 @@ struct arch_mbm_state { u64 prev_msr; }; =20 +/* Setting bit 1 in L3_QOS_EXT_CFG enables the SDCIAE feature. */ +#define SDCIAE_ENABLE_BIT 1 + /** * struct rdt_hw_ctrl_domain - Arch private attributes of a set of CPUs th= at share * a resource for a control function @@ -102,6 +105,7 @@ struct msr_param { * @mon_scale: cqm counter * mon_scale =3D occupancy in bytes * @mbm_width: Monitor width, to detect and correct for overflow. * @cdp_enabled: CDP state of this resource + * @sdciae_enabled: SDCIAE feature is enabled * * Members of this structure are either private to the architecture * e.g. mbm_width, or accessed via helpers that provide abstraction. e.g. @@ -115,6 +119,7 @@ struct rdt_hw_resource { unsigned int mon_scale; unsigned int mbm_width; bool cdp_enabled; + bool sdciae_enabled; }; =20 static inline struct rdt_hw_resource *resctrl_to_arch_res(struct rdt_resou= rce *r) diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index c7a7f0ae373a..e7c03d4e3d4a 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -228,6 +228,43 @@ bool resctrl_arch_get_cdp_enabled(enum resctrl_res_lev= el l) return rdt_resources_all[l].cdp_enabled; } =20 +inline bool resctrl_arch_get_io_alloc_enabled(struct rdt_resource *r) +{ + return resctrl_to_arch_res(r)->sdciae_enabled; +} + +static void resctrl_sdciae_set_one_amd(void *arg) +{ + bool *enable =3D arg; + + if (*enable) + msr_set_bit(MSR_IA32_L3_QOS_EXT_CFG, SDCIAE_ENABLE_BIT); + else + msr_clear_bit(MSR_IA32_L3_QOS_EXT_CFG, SDCIAE_ENABLE_BIT); +} + +static void _resctrl_sdciae_enable(struct rdt_resource *r, bool enable) +{ + struct rdt_ctrl_domain *d; + + /* Update L3_QOS_EXT_CFG MSR on all the CPUs in all domains */ + list_for_each_entry(d, &r->ctrl_domains, hdr.list) + on_each_cpu_mask(&d->hdr.cpu_mask, resctrl_sdciae_set_one_amd, &enable, = 1); +} + +int resctrl_arch_io_alloc_enable(struct rdt_resource *r, bool enable) +{ + struct rdt_hw_resource *hw_res =3D resctrl_to_arch_res(r); + + if (hw_res->r_resctrl.cache.io_alloc_capable && + hw_res->sdciae_enabled !=3D enable) { + _resctrl_sdciae_enable(r, enable); + hw_res->sdciae_enabled =3D enable; + } + + return 0; +} + void resctrl_arch_reset_all_ctrls(struct rdt_resource *r) { struct rdt_hw_resource *hw_res =3D resctrl_to_arch_res(r); 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Thu, 22 May 2025 14:52:47 -0500 From: Babu Moger To: , , , , , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 5/8] x86/resctrl: Add user interface to enable/disable io_alloc feature Date: Thu, 22 May 2025 14:51:36 -0500 Message-ID: <3946e8cfd3ce77028cdcf79a1ff5d5f70a714698.1747943499.git.babu.moger@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BY1PEPF0001AE1B:EE_|IA0PR12MB7699:EE_ X-MS-Office365-Filtering-Correlation-Id: 77332d79-60ad-469b-fda7-08dd996a3bce X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|7416014|1800799024|82310400026|13003099007; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 May 2025 19:52:50.4213 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 77332d79-60ad-469b-fda7-08dd996a3bce X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BY1PEPF0001AE1B.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB7699 Content-Type: text/plain; charset="utf-8" The io_alloc feature in resctrl is a mechanism that enables direct insertion of data from I/O devices into the L3 cache. On AMD systems, io_alloc feature is backed by SDCIAE (L3 Smart Data Cache Injection Allocation Enforcement). When enabled, SDCIAE forces all SDCI lines to be placed into the L3 cache partitions identified by the highest-supported L3_MASK_n register as reported by CPUID Fn0000_0010_EDX_x1.MAX_COS. For example, if MAX_COS=3D15, SDCI lines will be allocated into the L3 cache partitions determined by the bitmask in the L3_MASK_15 register. When CDP is enabled, io_alloc routes I/O traffic using the highest CLOSID allocated for the instruction cache (L3CODE). Introduce user interface to enable/disable "io_alloc" feature. Signed-off-by: Babu Moger --- v5: Resolved conflicts due to recent resctrl FS/ARCH code restructure. Used rdt_kn_name to get the rdtgroup name instead of accesssing it dire= ctly while printing group name used by the io_alloc_closid. Updated bit_usage to reflect the io_alloc CBM as discussed in the threa= d: https://lore.kernel.org/lkml/3ca0a5dc-ad9c-4767-9011-b79d986e1e8d@intel= .com/ Modified rdt_bit_usage_show() to read io_alloc_cbm in hw_shareable, ens= uring that bit_usage accurately represents the CBMs. Updated the code to modify io_alloc either with L3CODE or L3DATA. https://lore.kernel.org/lkml/c00c00ea-a9ac-4c56-961c-dc5bf633476b@intel= .com/ v4: Updated the change log. Updated the user doc. The "io_alloc" interface will report "enabled/disabled/not supported". Updated resctrl_io_alloc_closid_get() to verify the max closid availabi= lity. Updated the documentation for "shareable_bits" and "bit_usage". Introduced io_alloc_init() to initialize fflags. Printed the group name when io_alloc enablement fails. NOTE: io_alloc is about specific CLOS. rdt_bit_usage_show() is not desi= gned handle bit_usage for specific CLOS. Its about overall system. So, we ca= nnot really tell the user which CLOS is shared across both hardware and soft= ware. We need to discuss this. v3: Rewrote the change to make it generic. Rewrote the documentation in resctrl.rst to be generic and added AMD feature details in the end. Added the check to verify if MAX CLOSID availability on the system. Added CDP check to make sure io_alloc is configured in CDP_CODE. Added resctrl_io_alloc_closid_free() to free the io_alloc CLOSID. Added errors in few cases when CLOSID allocation fails. Fixes splat reported when info/L3/bit_usage is accesed when io_alloc is enabled. https://lore.kernel.org/lkml/SJ1PR11MB60837B532254E7B23BC27E84FC052@SJ1= PR11MB6083.namprd11.prod.outlook.com/ v2: Renamed the feature to "io_alloc". Added generic texts for the feature in commit log and resctrl.rst doc. Added resctrl_io_alloc_init_cat() to initialize io_alloc to default values when enabled. Fixed io_alloc show functinality to display only on L3 resource. --- Documentation/filesystems/resctrl.rst | 34 ++++ fs/resctrl/rdtgroup.c | 214 +++++++++++++++++++++++++- 2 files changed, 247 insertions(+), 1 deletion(-) diff --git a/Documentation/filesystems/resctrl.rst b/Documentation/filesyst= ems/resctrl.rst index c7949dd44f2f..5594422f133f 100644 --- a/Documentation/filesystems/resctrl.rst +++ b/Documentation/filesystems/resctrl.rst @@ -95,6 +95,11 @@ related to allocation: some platforms support devices that have their own settings for cache use which can over-ride these bits. + + When the "io_alloc" feature is enabled, a portion of the cache + is reserved for shared use between hardware and software. Refer + to "bit_usage" to see which portion is allocated for this purpose. + "bit_usage": Annotated capacity bitmasks showing how all instances of the resource are used. The legend is: @@ -135,6 +140,35 @@ related to allocation: "1": Non-contiguous 1s value in CBM is supported. =20 +"io_alloc": + The "io_alloc" enables system software to configure the portion + of the L3 cache allocated for I/O traffic. + + The feature routes the I/O traffic via specific CLOSID reserved + for io_alloc feature. By configuring the CBM (Capacity Bit Mask) + for the CLOSID, users can control the L3 portions available for + I/0 traffic. The reserved CLOSID will be excluded for group creation. + + The interface provides a means to query the status of feature support. + + Example:: + + # cat /sys/fs/resctrl/info/L3/io_alloc + disabled + + Feature can be enabled/disabled by writing to the interface. + Example:: + + # echo 1 > /sys/fs/resctrl/info/L3/io_alloc + # cat /sys/fs/resctrl/info/L3/io_alloc + enabled + + On AMD systems, the io_alloc feature is supported by the L3 Smart + Data Cache Injection Allocation Enforcement (SDCIAE). The CLOSID for + io_alloc is determined by the highest CLOSID supported by the resource. + When CDP is enabled, io_alloc routes I/O traffic using the highest + CLOSID allocated for the instruction cache (L3CODE). + Memory bandwidth(MB) subdirectory contains the following files with respect to allocation: =20 diff --git a/fs/resctrl/rdtgroup.c b/fs/resctrl/rdtgroup.c index cc37f58b47dd..f5b79c73fae2 100644 --- a/fs/resctrl/rdtgroup.c +++ b/fs/resctrl/rdtgroup.c @@ -70,6 +70,7 @@ static struct seq_buf last_cmd_status; static char last_cmd_status_buf[512]; =20 static int rdtgroup_setup_root(struct rdt_fs_context *ctx); +static int rdtgroup_init_cat(struct resctrl_schema *s, u32 closid); =20 static void rdtgroup_destroy_root(void); =20 @@ -232,6 +233,19 @@ bool closid_allocated(unsigned int closid) return !test_bit(closid, closid_free_map); } =20 +static int resctrl_io_alloc_closid_alloc(u32 io_alloc_closid) +{ + if (__test_and_clear_bit(io_alloc_closid, closid_free_map)) + return io_alloc_closid; + else + return -ENOSPC; +} + +static void resctrl_io_alloc_closid_free(u32 io_alloc_closid) +{ + closid_free(io_alloc_closid); +} + /** * rdtgroup_mode_by_closid - Return mode of resource group with closid * @closid: closid if the resource group @@ -1028,6 +1042,29 @@ static int rdt_shareable_bits_show(struct kernfs_ope= n_file *of, return 0; } =20 +/* + * resctrl_io_alloc_closid_get - io_alloc feature uses max CLOSID to route + * the IO traffic. Get the max CLOSID and verify if the CLOSID is availabl= e. + * + * The total number of CLOSIDs is determined in closid_init(), based on t= he + * minimum supported across all resources. If CDP (Code Data Prioritizatio= n) + * is enabled, the number of CLOSIDs is halved. The final value is returned + * by closids_supported(). Make sure this value aligns with the maximum + * CLOSID supported by the respective resource. + */ +static int resctrl_io_alloc_closid_get(struct rdt_resource *r) +{ + int num_closids =3D closids_supported(); + + if (resctrl_arch_get_cdp_enabled(r->rid)) + num_closids *=3D 2; + + if (num_closids !=3D resctrl_arch_get_num_closid(r)) + return -ENOSPC; + + return closids_supported() - 1; +} + /* * rdt_bit_usage_show - Display current usage of resources * @@ -1056,6 +1093,7 @@ static int rdt_bit_usage_show(struct kernfs_open_file= *of, struct rdt_ctrl_domain *dom; int i, hwb, swb, excl, psl; enum rdtgrp_mode mode; + int io_alloc_closid; bool sep =3D false; u32 ctrl_val; =20 @@ -1069,7 +1107,9 @@ static int rdt_bit_usage_show(struct kernfs_open_file= *of, exclusive =3D 0; seq_printf(seq, "%d=3D", dom->hdr.id); for (i =3D 0; i < closids_supported(); i++) { - if (!closid_allocated(i)) + if (!closid_allocated(i) || + (resctrl_arch_get_io_alloc_enabled(r) && + i =3D=3D resctrl_io_alloc_closid_get(r))) continue; ctrl_val =3D resctrl_arch_get_config(r, dom, i, s->conf_type); @@ -1097,6 +1137,24 @@ static int rdt_bit_usage_show(struct kernfs_open_fil= e *of, break; } } + + /* + * When the "io_alloc" feature is enabled, a portion of the + * cache is reserved for shared use between hardware and software. + */ + if (resctrl_arch_get_io_alloc_enabled(r)) { + io_alloc_closid =3D resctrl_io_alloc_closid_get(r); + if (resctrl_arch_get_cdp_enabled(r->rid)) + ctrl_val =3D resctrl_arch_get_config(r, dom, + io_alloc_closid, + CDP_CODE); + else + ctrl_val =3D resctrl_arch_get_config(r, dom, + io_alloc_closid, + CDP_NONE); + hw_shareable |=3D ctrl_val; + } + for (i =3D r->cache.cbm_len - 1; i >=3D 0; i--) { pseudo_locked =3D dom->plr ? dom->plr->cbm : 0; hwb =3D test_bit(i, &hw_shareable); @@ -1801,6 +1859,142 @@ static ssize_t mbm_local_bytes_config_write(struct = kernfs_open_file *of, return ret ?: nbytes; } =20 +static int resctrl_io_alloc_show(struct kernfs_open_file *of, + struct seq_file *seq, void *v) +{ + struct resctrl_schema *s =3D rdt_kn_parent_priv(of->kn); + struct rdt_resource *r =3D s->res; + + if (r->cache.io_alloc_capable) { + if (resctrl_arch_get_io_alloc_enabled(r)) + seq_puts(seq, "enabled\n"); + else + seq_puts(seq, "disabled\n"); + } else { + seq_puts(seq, "not supported\n"); + } + + return 0; +} + +/* + * Initialize io_alloc CLOSID cache resource with default CBM values. + */ +static int resctrl_io_alloc_init_cat(struct rdt_resource *r, + struct resctrl_schema *s, u32 closid) +{ + int ret; + + rdt_staged_configs_clear(); + + ret =3D rdtgroup_init_cat(s, closid); + if (ret < 0) + goto out_init_cat; + + ret =3D resctrl_arch_update_domains(r, closid); + +out_init_cat: + rdt_staged_configs_clear(); + return ret; +} + +static const char *rdtgroup_name_by_closid(int closid) +{ + struct rdtgroup *rdtgrp; + + list_for_each_entry(rdtgrp, &rdt_all_groups, rdtgroup_list) { + if (rdtgrp->closid =3D=3D closid) + return rdt_kn_name(rdtgrp->kn); + } + + return NULL; +} + +/* + * When CDP is enabled, io_alloc directs traffic using the highest CLOSID + * linked to an L3CODE resource. Although CBMs can be accessed through + * either L3CODE or L3DATA resources, any updates to the schemata must + * always be performed on L3CODE. + */ +static struct resctrl_schema *resctrl_schema_io_alloc(struct resctrl_schem= a *s) +{ + struct resctrl_schema *schema; + + if (s->conf_type =3D=3D CDP_DATA) { + list_for_each_entry(schema, &resctrl_schema_all, list) { + if (schema->conf_type =3D=3D CDP_CODE) + return schema; + } + } + + return s; +} + +static ssize_t resctrl_io_alloc_write(struct kernfs_open_file *of, char *b= uf, + size_t nbytes, loff_t off) +{ + struct resctrl_schema *s =3D rdt_kn_parent_priv(of->kn); + struct rdt_resource *r =3D s->res; + char const *grp_name; + u32 io_alloc_closid; + bool enable; + int ret; + + ret =3D kstrtobool(buf, &enable); + if (ret) + return ret; + + cpus_read_lock(); + mutex_lock(&rdtgroup_mutex); + + rdt_last_cmd_clear(); + + if (!r->cache.io_alloc_capable) { + rdt_last_cmd_puts("io_alloc feature is not supported on the resource\n"); + ret =3D -ENODEV; + goto out_io_alloc; + } + + io_alloc_closid =3D resctrl_io_alloc_closid_get(r); + if (io_alloc_closid < 0) { + rdt_last_cmd_puts("Max CLOSID to support io_alloc is not available\n"); + ret =3D -EINVAL; + goto out_io_alloc; + } + + if (resctrl_arch_get_io_alloc_enabled(r) !=3D enable) { + if (enable) { + ret =3D resctrl_io_alloc_closid_alloc(io_alloc_closid); + if (ret < 0) { + grp_name =3D rdtgroup_name_by_closid(io_alloc_closid); + rdt_last_cmd_printf("CLOSID for io_alloc is used by %s group\n", + grp_name ? grp_name : "another"); + ret =3D -EINVAL; + goto out_io_alloc; + } + + ret =3D resctrl_io_alloc_init_cat(r, resctrl_schema_io_alloc(s), + io_alloc_closid); + if (ret) { + rdt_last_cmd_puts("Failed to initialize io_alloc allocations\n"); + resctrl_io_alloc_closid_free(io_alloc_closid); + goto out_io_alloc; + } + + } else { + resctrl_io_alloc_closid_free(io_alloc_closid); + } + + ret =3D resctrl_arch_io_alloc_enable(r, enable); + } + +out_io_alloc: + mutex_unlock(&rdtgroup_mutex); + cpus_read_unlock(); + + return ret ?: nbytes; +} + /* rdtgroup information files for one cache resource. */ static struct rftype res_common_files[] =3D { { @@ -1953,6 +2147,13 @@ static struct rftype res_common_files[] =3D { .seq_show =3D rdtgroup_schemata_show, .fflags =3D RFTYPE_CTRL_BASE, }, + { + .name =3D "io_alloc", + .mode =3D 0644, + .kf_ops =3D &rdtgroup_kf_single_ops, + .seq_show =3D resctrl_io_alloc_show, + .write =3D resctrl_io_alloc_write, + }, { .name =3D "mba_MBps_event", .mode =3D 0644, @@ -2060,6 +2261,15 @@ static void thread_throttle_mode_init(void) RFTYPE_CTRL_INFO | RFTYPE_RES_MB); } =20 +static void io_alloc_init(void) +{ + struct rdt_resource *r =3D resctrl_arch_get_resource(RDT_RESOURCE_L3); + + if (r->cache.io_alloc_capable) + resctrl_file_fflags_init("io_alloc", + RFTYPE_CTRL_INFO | RFTYPE_RES_CACHE); +} + void resctrl_file_fflags_init(const char *config, unsigned long fflags) { struct rftype *rft; @@ -4245,6 +4455,8 @@ int resctrl_init(void) =20 thread_throttle_mode_init(); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 May 2025 19:52:59.7223 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 01beabf9-6a98-4347-09d2-08dd996a415a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BY1PEPF0001AE16.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7732 Content-Type: text/plain; charset="utf-8" The io_alloc feature in resctrl enables system software to configure the portion of the L3 cache allocated for I/O traffic. Add the interface to display CBMs (Capacity Bit Mask) of io_alloc feature. The CBM interface file io_alloc_cbm will reside in the info directory (e.g., /sys/fs/resctrl/info/L3/). Displaying the resource name is not necessary. Pass the resource name to show_doms() and print it only if the name is valid. For io_alloc, pass NULL to suppress printing the resource name. When CDP is enabled, io_alloc routes traffic using the highest CLOSID associated with an L3CODE resource. However, CBMs can be accessed via either L3CODE or L3DATA resources. Signed-off-by: Babu Moger --- v5: Resolved conflicts due to recent resctrl FS/ARCH code restructure. Updated show_doms() to print the resource if only it is valid. Pass NUL= L while printing io_alloc CBM. Changed the code to access the CBMs via either L3CODE or L3DATA resourc= es. v4: Updated the change log. Added rdtgroup_mutex before rdt_last_cmd_puts(). Returned -ENODEV when resource type is CDP_DATA. Kept the resource name while printing the CBM (L3:0=3Dfff) that way I dont have to change show_doms() just for this feature and it is consistant across all the schemata display. v3: Minor changes due to changes in resctrl_arch_get_io_alloc_enabled() and resctrl_io_alloc_closid_get(). Added the check to verify CDP resource type. Updated the commit log. v2: Fixed to display only on L3 resources. Added the locks while processing. Rename the displat to io_alloc_cbm (from sdciae_cmd). --- fs/resctrl/ctrlmondata.c | 8 ++++--- fs/resctrl/internal.h | 2 ++ fs/resctrl/rdtgroup.c | 51 +++++++++++++++++++++++++++++++++++++++- 3 files changed, 57 insertions(+), 4 deletions(-) diff --git a/fs/resctrl/ctrlmondata.c b/fs/resctrl/ctrlmondata.c index 6ed2dfd4dbbd..ea039852569a 100644 --- a/fs/resctrl/ctrlmondata.c +++ b/fs/resctrl/ctrlmondata.c @@ -381,7 +381,8 @@ ssize_t rdtgroup_schemata_write(struct kernfs_open_file= *of, return ret ?: nbytes; } =20 -static void show_doms(struct seq_file *s, struct resctrl_schema *schema, i= nt closid) +void show_doms(struct seq_file *s, struct resctrl_schema *schema, char *re= source_name, + int closid) { struct rdt_resource *r =3D schema->res; struct rdt_ctrl_domain *dom; @@ -391,7 +392,8 @@ static void show_doms(struct seq_file *s, struct resctr= l_schema *schema, int clo /* Walking r->domains, ensure it can't race with cpuhp */ lockdep_assert_cpus_held(); =20 - seq_printf(s, "%*s:", max_name_width, schema->name); + if (resource_name) + seq_printf(s, "%*s:", max_name_width, resource_name); list_for_each_entry(dom, &r->ctrl_domains, hdr.list) { if (sep) seq_puts(s, ";"); @@ -437,7 +439,7 @@ int rdtgroup_schemata_show(struct kernfs_open_file *of, closid =3D rdtgrp->closid; list_for_each_entry(schema, &resctrl_schema_all, list) { if (closid < schema->num_closid) - show_doms(s, schema, closid); + show_doms(s, schema, schema->name, closid); } } } else { diff --git a/fs/resctrl/internal.h b/fs/resctrl/internal.h index 9a8cf6f11151..14f3697c1187 100644 --- a/fs/resctrl/internal.h +++ b/fs/resctrl/internal.h @@ -374,6 +374,8 @@ void rdt_staged_configs_clear(void); bool closid_allocated(unsigned int closid); =20 int resctrl_find_cleanest_closid(void); +void show_doms(struct seq_file *s, struct resctrl_schema *schema, + char *name, int closid); =20 #ifdef CONFIG_RESCTRL_FS_PSEUDO_LOCK int rdtgroup_locksetup_enter(struct rdtgroup *rdtgrp); diff --git a/fs/resctrl/rdtgroup.c b/fs/resctrl/rdtgroup.c index f5b79c73fae2..9277b9c146bd 100644 --- a/fs/resctrl/rdtgroup.c +++ b/fs/resctrl/rdtgroup.c @@ -1995,6 +1995,46 @@ static ssize_t resctrl_io_alloc_write(struct kernfs_= open_file *of, char *buf, return ret ?: nbytes; } =20 +static int resctrl_io_alloc_cbm_show(struct kernfs_open_file *of, + struct seq_file *seq, void *v) +{ + struct resctrl_schema *s =3D rdt_kn_parent_priv(of->kn); + struct rdt_resource *r =3D s->res; + u32 io_alloc_closid; + int ret =3D 0; + + cpus_read_lock(); + mutex_lock(&rdtgroup_mutex); + + rdt_last_cmd_clear(); + + if (!r->cache.io_alloc_capable) { + rdt_last_cmd_puts("io_alloc feature is not supported on the resource\n"); + ret =3D -ENODEV; + goto cbm_show_out; + } + + if (!resctrl_arch_get_io_alloc_enabled(r)) { + rdt_last_cmd_puts("io_alloc feature is not enabled\n"); + ret =3D -EINVAL; + goto cbm_show_out; + } + + io_alloc_closid =3D resctrl_io_alloc_closid_get(r); + if (io_alloc_closid < 0) { + rdt_last_cmd_puts("Max CLOSID to support io_alloc is not available\n"); + ret =3D -EINVAL; + goto cbm_show_out; + } + + show_doms(seq, resctrl_schema_io_alloc(s), NULL, io_alloc_closid); + +cbm_show_out: + mutex_unlock(&rdtgroup_mutex); + cpus_read_unlock(); + return ret; +} + /* rdtgroup information files for one cache resource. */ static struct rftype res_common_files[] =3D { { @@ -2154,6 +2194,12 @@ static struct rftype res_common_files[] =3D { .seq_show =3D resctrl_io_alloc_show, .write =3D resctrl_io_alloc_write, }, + { + .name =3D "io_alloc_cbm", + .mode =3D 0444, + .kf_ops =3D &rdtgroup_kf_single_ops, + .seq_show =3D resctrl_io_alloc_cbm_show, + }, { .name =3D "mba_MBps_event", .mode =3D 0644, @@ -2265,9 +2311,12 @@ static void io_alloc_init(void) { struct rdt_resource *r =3D resctrl_arch_get_resource(RDT_RESOURCE_L3); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 May 2025 19:53:09.0512 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6e74e7d6-3170-469d-04e4-08dd996a46eb X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BY1PEPF0001AE19.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6258 Content-Type: text/plain; charset="utf-8" The functions parse_cbm() and parse_bw() require mode and CLOSID to validate the Capacity Bit Mask (CBM). It is passed through struct rdtgroup in rdt_parse_data. Instead of passing them through struct rdtgroup, pass mode and closid directly. This change enables parse_cbm() to be used for verifying CBM in io_alloc feature. Signed-off-by: Babu Moger --- v5: Resolved conflicts due to recent resctrl FS/ARCH code restructure. v4: New patch to call parse_cbm() directly to avoid code duplication. --- fs/resctrl/ctrlmondata.c | 29 +++++++++++++---------------- fs/resctrl/internal.h | 6 ++++++ 2 files changed, 19 insertions(+), 16 deletions(-) diff --git a/fs/resctrl/ctrlmondata.c b/fs/resctrl/ctrlmondata.c index ea039852569a..6409637b4de6 100644 --- a/fs/resctrl/ctrlmondata.c +++ b/fs/resctrl/ctrlmondata.c @@ -23,11 +23,6 @@ =20 #include "internal.h" =20 -struct rdt_parse_data { - struct rdtgroup *rdtgrp; - char *buf; -}; - typedef int (ctrlval_parser_t)(struct rdt_parse_data *data, struct resctrl_schema *s, struct rdt_ctrl_domain *d); @@ -77,8 +72,8 @@ static int parse_bw(struct rdt_parse_data *data, struct r= esctrl_schema *s, struct rdt_ctrl_domain *d) { struct resctrl_staged_config *cfg; - u32 closid =3D data->rdtgrp->closid; struct rdt_resource *r =3D s->res; + u32 closid =3D data->closid; u32 bw_val; =20 cfg =3D &d->staged_config[s->conf_type]; @@ -156,9 +151,10 @@ static bool cbm_validate(char *buf, u32 *data, struct = rdt_resource *r) static int parse_cbm(struct rdt_parse_data *data, struct resctrl_schema *s, struct rdt_ctrl_domain *d) { - struct rdtgroup *rdtgrp =3D data->rdtgrp; + enum rdtgrp_mode mode =3D data->mode; struct resctrl_staged_config *cfg; struct rdt_resource *r =3D s->res; + u32 closid =3D data->closid; u32 cbm_val; =20 cfg =3D &d->staged_config[s->conf_type]; @@ -171,7 +167,7 @@ static int parse_cbm(struct rdt_parse_data *data, struc= t resctrl_schema *s, * Cannot set up more than one pseudo-locked region in a cache * hierarchy. */ - if (rdtgrp->mode =3D=3D RDT_MODE_PSEUDO_LOCKSETUP && + if (mode =3D=3D RDT_MODE_PSEUDO_LOCKSETUP && rdtgroup_pseudo_locked_in_hierarchy(d)) { rdt_last_cmd_puts("Pseudo-locked region in hierarchy\n"); return -EINVAL; @@ -180,9 +176,9 @@ static int parse_cbm(struct rdt_parse_data *data, struc= t resctrl_schema *s, if (!cbm_validate(data->buf, &cbm_val, r)) return -EINVAL; =20 - if ((rdtgrp->mode =3D=3D RDT_MODE_EXCLUSIVE || - rdtgrp->mode =3D=3D RDT_MODE_SHAREABLE) && - rdtgroup_cbm_overlaps_pseudo_locked(d, cbm_val)) { + if ((mode =3D=3D RDT_MODE_EXCLUSIVE || + mode =3D=3D RDT_MODE_SHAREABLE) && + rdtgroup_cbm_overlaps_pseudo_locked(d, cbm_val)) { rdt_last_cmd_puts("CBM overlaps with pseudo-locked region\n"); return -EINVAL; } @@ -191,14 +187,14 @@ static int parse_cbm(struct rdt_parse_data *data, str= uct resctrl_schema *s, * The CBM may not overlap with the CBM of another closid if * either is exclusive. */ - if (rdtgroup_cbm_overlaps(s, d, cbm_val, rdtgrp->closid, true)) { + if (rdtgroup_cbm_overlaps(s, d, cbm_val, closid, true)) { rdt_last_cmd_puts("Overlaps with exclusive group\n"); return -EINVAL; } =20 - if (rdtgroup_cbm_overlaps(s, d, cbm_val, rdtgrp->closid, false)) { - if (rdtgrp->mode =3D=3D RDT_MODE_EXCLUSIVE || - rdtgrp->mode =3D=3D RDT_MODE_PSEUDO_LOCKSETUP) { + if (rdtgroup_cbm_overlaps(s, d, cbm_val, closid, false)) { + if (mode =3D=3D RDT_MODE_EXCLUSIVE || + mode =3D=3D RDT_MODE_PSEUDO_LOCKSETUP) { rdt_last_cmd_puts("Overlaps with other group\n"); return -EINVAL; } @@ -262,7 +258,8 @@ static int parse_line(char *line, struct resctrl_schema= *s, list_for_each_entry(d, &r->ctrl_domains, hdr.list) { if (d->hdr.id =3D=3D dom_id) { data.buf =3D dom; - data.rdtgrp =3D rdtgrp; + data.closid =3D rdtgrp->closid; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 May 2025 19:53:18.4828 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b576d57e-d1ea-4c3d-ab9b-08dd996a4c88 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BY1PEPF0001AE1C.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6259 Content-Type: text/plain; charset="utf-8" "io_alloc" feature is a mechanism that enables direct insertion of data from I/O devices into the L3 cache. By directly caching data from I/O devices rather than first storing the I/O data in DRAM, it reduces the demands on DRAM bandwidth and reduces latency to the processor consuming the I/O data. "io_alloc" feature uses the highest CLOSID to route the traffic from I/O devices. Provide the interface to modify io_alloc CBMs (Capacity Bit Mask) when feature is enabled. Signed-off-by: Babu Moger --- v5: Changes due to FS/ARCH code restructure. The files monitor.c/rdtgroup.c have been split between FS and ARCH directories. Changed the code to access the CBMs via either L3CODE or L3DATA resourc= es. v4: Removed resctrl_io_alloc_parse_cbm and called parse_cbm() directly. v3: Minor changes due to changes in resctrl_arch_get_io_alloc_enabled() and resctrl_io_alloc_closid_get(). Taken care of handling the CBM update when CDP is enabled. Updated the commit log to make it generic. v2: Added more generic text in documentation. --- Documentation/filesystems/resctrl.rst | 23 +++++++ fs/resctrl/ctrlmondata.c | 4 +- fs/resctrl/internal.h | 2 + fs/resctrl/rdtgroup.c | 89 ++++++++++++++++++++++++++- 4 files changed, 115 insertions(+), 3 deletions(-) diff --git a/Documentation/filesystems/resctrl.rst b/Documentation/filesyst= ems/resctrl.rst index 5594422f133f..59697c99a22e 100644 --- a/Documentation/filesystems/resctrl.rst +++ b/Documentation/filesystems/resctrl.rst @@ -169,6 +169,29 @@ related to allocation: When CDP is enabled, io_alloc routes I/O traffic using the highest CLOSID allocated for the instruction cache (L3CODE). =20 +"io_alloc_cbm": + Capacity Bit Masks (CBMs) available to supported IO devices which + can directly insert cache lines in L3 which can help to reduce the + latency. CBM can be configured by writing to the interface in the + following format:: + + :=3D;=3D;... + + Example:: + + # cat /sys/fs/resctrl/info/L3/io_alloc_cbm + L3:0=3Dffff;1=3Dffff + + # echo L3:1=3DFF > /sys/fs/resctrl/info/L3/io_alloc_cbm + # cat /sys/fs/resctrl/info/L3/io_alloc_cbm + L3:0=3Dffff;1=3D00ff + + When CDP is enabled, io_alloc directs traffic using the highest CLOSID + linked to an L3CODE resource. Although CBMs can be accessed through + either L3CODE or L3DATA resources, any updates to the schemata are + always routed through L3CODE. + + Memory bandwidth(MB) subdirectory contains the following files with respect to allocation: =20 diff --git a/fs/resctrl/ctrlmondata.c b/fs/resctrl/ctrlmondata.c index 6409637b4de6..f3e5e697945c 100644 --- a/fs/resctrl/ctrlmondata.c +++ b/fs/resctrl/ctrlmondata.c @@ -148,8 +148,8 @@ static bool cbm_validate(char *buf, u32 *data, struct r= dt_resource *r) * Read one cache bit mask (hex). Check that it is valid for the current * resource type. */ -static int parse_cbm(struct rdt_parse_data *data, struct resctrl_schema *s, - struct rdt_ctrl_domain *d) +int parse_cbm(struct rdt_parse_data *data, struct resctrl_schema *s, + struct rdt_ctrl_domain *d) { enum rdtgrp_mode mode =3D data->mode; struct resctrl_staged_config *cfg; diff --git a/fs/resctrl/internal.h b/fs/resctrl/internal.h index 10a3188ffa54..755f23934295 100644 --- a/fs/resctrl/internal.h +++ b/fs/resctrl/internal.h @@ -382,6 +382,8 @@ bool closid_allocated(unsigned int closid); int resctrl_find_cleanest_closid(void); void show_doms(struct seq_file *s, struct resctrl_schema *schema, char *name, int closid); +int parse_cbm(struct rdt_parse_data *data, struct resctrl_schema *s, + struct rdt_ctrl_domain *d); =20 #ifdef CONFIG_RESCTRL_FS_PSEUDO_LOCK int rdtgroup_locksetup_enter(struct rdtgroup *rdtgrp); diff --git a/fs/resctrl/rdtgroup.c b/fs/resctrl/rdtgroup.c index 9277b9c146bd..b84fee51c57d 100644 --- a/fs/resctrl/rdtgroup.c +++ b/fs/resctrl/rdtgroup.c @@ -2035,6 +2035,92 @@ static int resctrl_io_alloc_cbm_show(struct kernfs_o= pen_file *of, return ret; } =20 +static int resctrl_io_alloc_parse_line(char *line, struct rdt_resource *r, + struct resctrl_schema *s, u32 closid) +{ + struct rdt_parse_data data; + struct rdt_ctrl_domain *d; + char *dom =3D NULL, *id; + unsigned long dom_id; + +next: + if (!line || line[0] =3D=3D '\0') + return 0; + + dom =3D strsep(&line, ";"); + id =3D strsep(&dom, "=3D"); + if (!dom || kstrtoul(id, 10, &dom_id)) { + rdt_last_cmd_puts("Missing '=3D' or non-numeric domain\n"); + return -EINVAL; + } + + dom =3D strim(dom); + list_for_each_entry(d, &r->ctrl_domains, hdr.list) { + if (d->hdr.id =3D=3D dom_id) { + data.buf =3D dom; + data.mode =3D RDT_MODE_SHAREABLE; + data.closid =3D closid; + if (parse_cbm(&data, s, d)) + return -EINVAL; + goto next; + } + } + return -EINVAL; +} + +static ssize_t resctrl_io_alloc_cbm_write(struct kernfs_open_file *of, + char *buf, size_t nbytes, loff_t off) +{ + struct resctrl_schema *s =3D rdt_kn_parent_priv(of->kn); + struct rdt_resource *r =3D s->res; + u32 io_alloc_closid; + int ret =3D 0; + + /* Valid input requires a trailing newline */ + if (nbytes =3D=3D 0 || buf[nbytes - 1] !=3D '\n') + return -EINVAL; + + buf[nbytes - 1] =3D '\0'; + + if (!r->cache.io_alloc_capable) { + rdt_last_cmd_puts("io_alloc feature is not supported on the resource\n"); + return -EINVAL; + } + + cpus_read_lock(); + mutex_lock(&rdtgroup_mutex); + + rdt_last_cmd_clear(); + rdt_staged_configs_clear(); + + if (!resctrl_arch_get_io_alloc_enabled(r)) { + rdt_last_cmd_puts("io_alloc feature is not enabled\n"); + ret =3D -EINVAL; + goto cbm_write_out; + } + + io_alloc_closid =3D resctrl_io_alloc_closid_get(r); + if (io_alloc_closid < 0) { + rdt_last_cmd_puts("Max CLOSID to support io_alloc is not available\n"); + ret =3D -EINVAL; + goto cbm_write_out; + } + + ret =3D resctrl_io_alloc_parse_line(buf, r, resctrl_schema_io_alloc(s), + io_alloc_closid); + if (ret) + goto cbm_write_out; + + ret =3D resctrl_arch_update_domains(r, io_alloc_closid); + +cbm_write_out: + rdt_staged_configs_clear(); + mutex_unlock(&rdtgroup_mutex); + cpus_read_unlock(); + + return ret ?: nbytes; +} + /* rdtgroup information files for one cache resource. */ static struct rftype res_common_files[] =3D { { @@ -2196,9 +2282,10 @@ static struct rftype res_common_files[] =3D { }, { .name =3D "io_alloc_cbm", - .mode =3D 0444, + .mode =3D 0644, .kf_ops =3D &rdtgroup_kf_single_ops, .seq_show =3D resctrl_io_alloc_cbm_show, + .write =3D resctrl_io_alloc_cbm_write, }, { .name =3D "mba_MBps_event", --=20 2.34.1