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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 May 2025 10:52:24.6776 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 112194ad-ab12-4714-67d7-08dd8d554053 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF0000000A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6098 Content-Type: text/plain; charset="utf-8" Current AMD IOMMU assumes Host Address Translation (HAT) is always supported, and Linux kernel enables this capability by default. However, in case of emulated and virtualized IOMMU, this might not be the case. For example,current QEMU-emulated AMD vIOMMU does not support host translation for VFIO pass-through device, but the interrupt remapping support is required for x2APIC (i.e. kvm-msi-ext-dest-id is also not supported by the guest OS). This would require the guest kernel to boot with guest kernel option iommu=3Dpt to by-pass the initialization of host (v1) table. The AMD I/O Virtualization Technology (IOMMU) Specification Rev 3.10 [1] introduces a new flag 'HATDis' in the IVHD 11h IOMMU attributes to indicate that HAT is not supported on a particular IOMMU instance. Therefore, modifies the AMD IOMMU driver to detect the new HATDis attributes, and disable host translation and switch to use guest translation if it is available. Otherwise, the driver will disable DMA translation. [1] https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/sp= ecifications/48882_IOMMU.pdf Reviewed-by: Suravee Suthikulpanit Signed-off-by: Ankit Soni --- drivers/iommu/amd/amd_iommu.h | 1 + drivers/iommu/amd/amd_iommu_types.h | 6 +++++- drivers/iommu/amd/init.c | 21 ++++++++++++++++++++- drivers/iommu/amd/iommu.c | 13 +++++++++++++ 4 files changed, 39 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index 220c598b7e14..bb14c4800dd0 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -43,6 +43,7 @@ extern int amd_iommu_guest_ir; extern enum protection_domain_mode amd_iommu_pgtable; extern int amd_iommu_gpt_level; extern unsigned long amd_iommu_pgsize_bitmap; +extern bool amd_iommu_hatdis; =20 /* Protection domain ops */ void amd_iommu_init_identity_domain(void); diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_io= mmu_types.h index 5089b58e528a..284ff4309660 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -460,6 +460,9 @@ /* IOMMU Feature Reporting Field (for IVHD type 10h */ #define IOMMU_FEAT_GASUP_SHIFT 6 =20 +/* IOMMU HATDIS for IVHD type 11h and 40h */ +#define IOMMU_IVHD_ATTR_HATDIS_SHIFT 0 + /* IOMMU Extended Feature Register (EFR) */ #define IOMMU_EFR_XTSUP_SHIFT 2 #define IOMMU_EFR_GASUP_SHIFT 7 @@ -558,7 +561,8 @@ struct amd_io_pgtable { }; =20 enum protection_domain_mode { - PD_MODE_V1 =3D 1, + PD_MODE_NONE, + PD_MODE_V1, PD_MODE_V2, }; =20 diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index 14aa0d77df26..cfda9f89fe1d 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -168,6 +168,9 @@ static int amd_iommu_target_ivhd_type; u64 amd_iommu_efr; u64 amd_iommu_efr2; =20 +/* Host (v1) page table is not supported*/ +bool amd_iommu_hatdis; + /* SNP is enabled on the system? */ bool amd_iommu_snp_en; EXPORT_SYMBOL(amd_iommu_snp_en); @@ -1798,6 +1801,11 @@ static int __init init_iommu_one(struct amd_iommu *i= ommu, struct ivhd_header *h, if (h->efr_reg & BIT(IOMMU_EFR_XTSUP_SHIFT)) amd_iommu_xt_mode =3D IRQ_REMAP_X2APIC_MODE; =20 + if (h->efr_attr & BIT(IOMMU_IVHD_ATTR_HATDIS_SHIFT)) { + pr_warn_once("Host Address Translation is not supported.\n"); + amd_iommu_hatdis =3D true; + } + early_iommu_features_init(iommu, h); =20 break; @@ -2582,7 +2590,7 @@ static void init_device_table_dma(struct amd_iommu_pc= i_seg *pci_seg) u32 devid; struct dev_table_entry *dev_table =3D pci_seg->dev_table; =20 - if (dev_table =3D=3D NULL) + if (!dev_table || amd_iommu_pgtable =3D=3D PD_MODE_NONE) return; =20 for (devid =3D 0; devid <=3D pci_seg->last_bdf; ++devid) { @@ -3095,6 +3103,17 @@ static int __init early_amd_iommu_init(void) } } =20 + if (amd_iommu_hatdis) { + /* + * Host (v1) page table is not available. Attempt to use + * Guest (v2) page table. + */ + if (amd_iommu_v2_pgtbl_supported()) + amd_iommu_pgtable =3D PD_MODE_V2; + else + amd_iommu_pgtable =3D PD_MODE_NONE; + } + /* Disable any previously enabled IOMMUs */ if (!is_kdump_kernel() || amd_iommu_disabled) disable_iommus(); diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index f34209b08b4c..4e9a57377b8c 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -2393,6 +2393,13 @@ static struct iommu_device *amd_iommu_probe_device(s= truct device *dev) pci_max_pasids(to_pci_dev(dev))); } =20 + if (amd_iommu_pgtable =3D=3D PD_MODE_NONE) { + pr_warn_once("%s: DMA translation not supported by iommu.\n", + __func__); + iommu_dev =3D ERR_PTR(-ENODEV); + goto out_err; + } + out_err: =20 iommu_completion_wait(iommu); @@ -2480,6 +2487,9 @@ static int pdom_setup_pgtable(struct protection_domai= n *domain, case PD_MODE_V2: fmt =3D AMD_IOMMU_V2; break; + case PD_MODE_NONE: + WARN_ON_ONCE(1); + return -EPERM; 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Wed, 7 May 2025 10:52:43 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CH3PEPF00000010.mail.protection.outlook.com (10.167.244.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8722.18 via Frontend Transport; Wed, 7 May 2025 10:52:43 +0000 Received: from BLRANKISONI.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Wed, 7 May 2025 05:52:38 -0500 From: Ankit Soni To: CC: , , , , , Subject: [PATCH v2 2/2] iommu/amd: Add efr[HATS] max v1 page table level Date: Wed, 7 May 2025 10:51:48 +0000 Message-ID: <96b1109a095fa343e5c8a0dc6b8e1dd1f39605c4.1746613368.git.Ankit.Soni@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF00000010:EE_|MN0PR12MB6150:EE_ X-MS-Office365-Filtering-Correlation-Id: c378ba56-8372-40b1-cb72-08dd8d554b57 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|36860700013|1800799024; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 May 2025 10:52:43.1581 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c378ba56-8372-40b1-cb72-08dd8d554b57 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF00000010.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6150 Content-Type: text/plain; charset="utf-8" The EFR[HATS] bits indicate maximum host translation level supported by IOMMU. Adding support to set the maximum host page table level as indicated by EFR[HATS]. If the HATS=3D11b (reserved), the driver will attempt to use guest page table for DMA API. Reviewed-by: Vasant Hegde Reviewed-by: Suravee Suthikulpanit Signed-off-by: Ankit Soni --- drivers/iommu/amd/amd_iommu.h | 1 + drivers/iommu/amd/amd_iommu_types.h | 1 + drivers/iommu/amd/init.c | 16 ++++++++++++++++ drivers/iommu/amd/io_pgtable.c | 4 ++-- drivers/iommu/amd/iommu.c | 2 +- 5 files changed, 21 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index bb14c4800dd0..0286120ad4a5 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -42,6 +42,7 @@ int amd_iommu_enable_faulting(unsigned int cpu); extern int amd_iommu_guest_ir; extern enum protection_domain_mode amd_iommu_pgtable; extern int amd_iommu_gpt_level; +extern u8 amd_iommu_hpt_level; extern unsigned long amd_iommu_pgsize_bitmap; extern bool amd_iommu_hatdis; =20 diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_io= mmu_types.h index 284ff4309660..6bf81197c2c8 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -96,6 +96,7 @@ #define FEATURE_GA BIT_ULL(7) #define FEATURE_HE BIT_ULL(8) #define FEATURE_PC BIT_ULL(9) +#define FEATURE_HATS GENMASK_ULL(11, 10) #define FEATURE_GATS GENMASK_ULL(13, 12) #define FEATURE_GLX GENMASK_ULL(15, 14) #define FEATURE_GAM_VAPIC BIT_ULL(21) diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index cfda9f89fe1d..311c2ae45d09 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -152,6 +152,8 @@ bool amd_iommu_dump; bool amd_iommu_irq_remap __read_mostly; =20 enum protection_domain_mode amd_iommu_pgtable =3D PD_MODE_V1; +/* Host page table level */ +u8 amd_iommu_hpt_level; /* Guest page table level */ int amd_iommu_gpt_level =3D PAGE_MODE_4_LEVEL; =20 @@ -3052,6 +3054,7 @@ static int __init early_amd_iommu_init(void) struct acpi_table_header *ivrs_base; int ret; acpi_status status; + u8 efr_hats; =20 if (!amd_iommu_detected) return -ENODEV; @@ -3096,6 +3099,19 @@ static int __init early_amd_iommu_init(void) FIELD_GET(FEATURE_GATS, amd_iommu_efr) =3D=3D GUEST_PGTABLE_5_LEVEL) amd_iommu_gpt_level =3D PAGE_MODE_5_LEVEL; =20 + efr_hats =3D FIELD_GET(FEATURE_HATS, amd_iommu_efr); + if (efr_hats !=3D 0x3) { + /* + * efr[HATS] bits specify the maximum host translation level + * supported, with LEVEL 4 being initial max level. + */ + amd_iommu_hpt_level =3D efr_hats + PAGE_MODE_4_LEVEL; + } else { + pr_warn_once(FW_BUG "Disable host address translation due to invalid tra= nslation level (%#x).\n", + efr_hats); + amd_iommu_hatdis =3D true; + } + if (amd_iommu_pgtable =3D=3D PD_MODE_V2) { if (!amd_iommu_v2_pgtbl_supported()) { pr_warn("Cannot enable v2 page table for DMA-API. Fallback to v1.\n"); diff --git a/drivers/iommu/amd/io_pgtable.c b/drivers/iommu/amd/io_pgtable.c index 26cf562dde11..0d8bc06f63d7 100644 --- a/drivers/iommu/amd/io_pgtable.c +++ b/drivers/iommu/amd/io_pgtable.c @@ -132,7 +132,7 @@ static bool increase_address_space(struct amd_io_pgtabl= e *pgtable, goto out; =20 ret =3D false; - if (WARN_ON_ONCE(pgtable->mode =3D=3D PAGE_MODE_6_LEVEL)) + if (WARN_ON_ONCE(pgtable->mode =3D=3D amd_iommu_hpt_level)) goto out; =20 *pte =3D PM_LEVEL_PDE(pgtable->mode, iommu_virt_to_phys(pgtable->root)); @@ -531,7 +531,7 @@ static void v1_free_pgtable(struct io_pgtable *iop) =20 /* Page-table is not visible to IOMMU anymore, so free it */ BUG_ON(pgtable->mode < PAGE_MODE_NONE || - pgtable->mode > PAGE_MODE_6_LEVEL); + pgtable->mode > amd_iommu_hpt_level); =20 free_sub_pt(pgtable->root, pgtable->mode, &freelist); iommu_put_pages_list(&freelist); diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 4e9a57377b8c..f7e641571127 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -2503,7 +2503,7 @@ static int pdom_setup_pgtable(struct protection_domai= n *domain, static inline u64 dma_max_address(enum protection_domain_mode pgtable) { if (pgtable =3D=3D PD_MODE_V1) - return ~0ULL; + return PM_LEVEL_SIZE(amd_iommu_hpt_level); =20 /* V2 with 4/5 level page table */ return ((1ULL << PM_LEVEL_SHIFT(amd_iommu_gpt_level)) - 1); --=20 2.43.0