From nobody Wed Feb 11 02:24:40 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BE1CF1D88AC; Tue, 6 May 2025 20:05:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746561935; cv=none; b=CsO/zBK7Bt1RFGqirI/taZJjw3K9NRN0bXiAYnVJ2leluf+tBaExBoMplqgZwmBXg2JEiKoJvvCRor1AhnZj7gsb0oaWUdoCdxlbBocKw/JYBBMdLU7AUAWKw4EqjSxpMM7bh5basSczJyA1IhGXKbXeJIqFWR385Jnp63BnkN0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746561935; c=relaxed/simple; bh=v1/WaetPPLIbLAn+oTP+5ur1UuwyBHGcg4dgKfrOu4U=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=F8JvqSPTCEqQdOHM78c+s9sTl7hdn1qYXo1P9kcbe0UjCUw+u1+8UPwYN/7uDf7H9S2yX45q6TgdbTBo4k3m7Z/4+wYKwxgiDfXH0u/SUhgxzqegFtdE4ooODVF0nDVFz4VoVDb3YwveO2SsFZ3NKOKKtjgyIrivhkKBuggTFC4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=w5WfUMcU; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="w5WfUMcU" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1746561933; x=1778097933; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=v1/WaetPPLIbLAn+oTP+5ur1UuwyBHGcg4dgKfrOu4U=; b=w5WfUMcUz41TEBN4IgbdImfV7T8O7Er23ULDdR/ThbmQdjewNBMleO5/ hW6/BP4UldhBLJWcct2cyvhkL/USehBdKcs35ui7mJ8qNBRdpRta1TQkZ Jw6HNTu6DHAQ0/QRNlBa92guNzSvvJLIa1C5JMZjvy5kNFmCn3+s8IxCW 9MSUpHHwAFB0iqchJsiiDbIKUToYf4gBLOQlCKpJn3eoOoneXcg47ol4b 4Sm0CAxJDt1q483TZAjGpFo2ECAS7SF2h7g9deM1uMy6DTdzK5DWLZliQ aBJvwL8Q88pMJaSjhqqtgZDfUIBDCefdJ6CX5/4nXMnZOkYAASvum+QTm A==; X-CSE-ConnectionGUID: dUBqohHAQlqcpEGq8j09lg== X-CSE-MsgGUID: YIJGv1ATSQ2Tmu2fBmv5Ig== X-IronPort-AV: E=Sophos;i="6.15,267,1739862000"; d="scan'208";a="208799759" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 06 May 2025 13:05:32 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Tue, 6 May 2025 13:05:12 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Tue, 6 May 2025 13:05:12 -0700 From: To: , , , , , , , CC: , , , , Ryan Wanner Subject: [PATCH v3 1/4] clk: at91: sckc: Fix parent_data struct for slow osc Date: Tue, 6 May 2025 13:04:56 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Ryan Wanner The slow xtal is not described correctly as a parent, the driver looks for a "slow_xtal" string which is incorrect and will not work with the new formating of xtals. To avoid this and keep this driver backwards compatible the parent_data.fw_name is replaced with parent_data.name and the original parent_data.name is replaced with parent_data.index. Using the index is safe due to the driver requiring only 1 xtal. Fixes: 8aa1db9ccee0e ("clk: at91: sckc: switch to parent_data/parent_hw") Signed-off-by: Ryan Wanner --- drivers/clk/at91/sckc.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c index 021d1b412af4..952a805b6f7e 100644 --- a/drivers/clk/at91/sckc.c +++ b/drivers/clk/at91/sckc.c @@ -374,7 +374,7 @@ static void __init at91sam9x5_sckc_register(struct devi= ce_node *np, const char *xtal_name; struct clk_hw *slow_rc, *slow_osc, *slowck; static struct clk_parent_data parent_data =3D { - .name =3D "slow_xtal", + .index =3D 0, }; const struct clk_hw *parent_hws[2]; bool bypass; @@ -407,7 +407,7 @@ static void __init at91sam9x5_sckc_register(struct devi= ce_node *np, if (!xtal_name) goto unregister_slow_rc; =20 - parent_data.fw_name =3D xtal_name; + parent_data.name =3D xtal_name; =20 slow_osc =3D at91_clk_register_slow_osc(regbase, "slow_osc", &parent_data, 1200000, bypass, bits); @@ -476,7 +476,7 @@ static void __init of_sam9x60_sckc_setup(struct device_= node *np) const char *xtal_name; const struct clk_hw *parent_hws[2]; static struct clk_parent_data parent_data =3D { - .name =3D "slow_xtal", + .index =3D 0, }; bool bypass; int ret; @@ -494,7 +494,7 @@ static void __init of_sam9x60_sckc_setup(struct device_= node *np) if (!xtal_name) goto unregister_slow_rc; =20 - parent_data.fw_name =3D xtal_name; + parent_data.name =3D xtal_name; bypass =3D of_property_read_bool(np, "atmel,osc-bypass"); slow_osc =3D at91_clk_register_slow_osc(regbase, "slow_osc", &parent_data, 5000000, bypass, @@ -592,7 +592,7 @@ static void __init of_sama5d4_sckc_setup(struct device_= node *np) const char *xtal_name; const struct clk_hw *parent_hws[2]; static struct clk_parent_data parent_data =3D { - .name =3D "slow_xtal", + .index =3D 0, }; int ret; =20 @@ -609,7 +609,7 @@ static void __init of_sama5d4_sckc_setup(struct device_= node *np) xtal_name =3D of_clk_get_parent_name(np, 0); if (!xtal_name) goto unregister_slow_rc; - parent_data.fw_name =3D xtal_name; + parent_data.name =3D xtal_name; =20 osc =3D kzalloc(sizeof(*osc), GFP_KERNEL); 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charset="utf-8" From: Ryan Wanner The main_xtal clk_hw struct is not passed into parent_data.hw causing the main_osc to not have a parent causing a corrupted clock tree. Passing the main_xtal struct into the parent_data struct will ensure the correct parent structure for main_osc and a correct clock tree. Signed-off-by: Ryan Wanner --- drivers/clk/at91/sama7d65.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/at91/sama7d65.c b/drivers/clk/at91/sama7d65.c index a5d40df8b2f2..1e9d3c393883 100644 --- a/drivers/clk/at91/sama7d65.c +++ b/drivers/clk/at91/sama7d65.c @@ -1100,7 +1100,7 @@ static void __init sama7d65_pmc_setup(struct device_n= ode *np) struct regmap *regmap; struct clk_hw *hw, *main_rc_hw, *main_osc_hw, *main_xtal_hw; struct clk_hw *td_slck_hw, *md_slck_hw; - static struct clk_parent_data parent_data; + static struct clk_parent_data parent_data =3D {0}; struct clk_hw *parent_hws[10]; bool bypass; int i, j; @@ -1138,6 +1138,7 @@ static void __init sama7d65_pmc_setup(struct device_n= ode *np) =20 parent_data.name =3D main_xtal_name; parent_data.fw_name =3D main_xtal_name; + parent_data.hw =3D main_xtal_hw; main_osc_hw =3D at91_clk_register_main_osc(regmap, "main_osc", NULL, &parent_data, bypass); if (IS_ERR(main_osc_hw)) --=20 2.43.0 From nobody Wed Feb 11 02:24:40 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 179931EB5C9; Tue, 6 May 2025 20:05:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746561937; cv=none; b=a/3N+BScL2lX6MYHBEoY7gxblcPSCErqMA8SJs82r7U+7H1LEVC8A8WRob8DaxMwuA+06YHbx2bdP36Fh6sBWdmyPXLqBjV4td+3bi3BAbmJnjwMmVMWdg9fra+/z7rmUnjN+GfstvHIO4bNFLYGVmd3MkKZdM98O9/u9AzYl+w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746561937; c=relaxed/simple; bh=NMKgRBD0SSTJXoMrnuHZxQQt4FlqkPpKB0zFXsFFbdI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=DcaI340vynX/s+gx5O8ycV1DXM1mSoi6zUXREC0Wj2rDqK3iHGsK0FXL8enTZ0fmRxf4XZh0T6ITr/De1j4Acxx3oc61hFaMDyRZr9JMaXw/ARDFlsC9Ro+oCTFlLi/dEqBdP90OZobuY/UMbi+Rl4lTgRd2u88p1xfFcZEU8UA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=eUPffv0e; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="eUPffv0e" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1746561936; x=1778097936; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=NMKgRBD0SSTJXoMrnuHZxQQt4FlqkPpKB0zFXsFFbdI=; b=eUPffv0ekIwOTPVR2kh1CQU2j7qLmYzHjkYvZkO5g3nSwlcKrG4sWsuQ EhWtZCw7ZdF8EhvR2o1zZ13eAp+Cfz2VpxhVUVetWBIKUl0r4uqE9WENY EL9CNwY8DYyAR3b3tJiVlgDWVATeJCTxu5MrZ6OSJDTohxCrDrUU5LUhQ UFtwMoatxPHoK24Yt2vRo3T5QqLE6Wl2O3j+xyggDKf3eBhPwbvR3PoTr FmAiWbMCG7dI0ULLK5aAIBnn5IJh70Fu2LC99TIdPfhLzHu5QZdZ7WJps riVdP8IGdE+2qj98QGuFyUgC+oxu73Zlr2qBhAUs/fQycZGoX0qTz6hUe Q==; X-CSE-ConnectionGUID: dUBqohHAQlqcpEGq8j09lg== X-CSE-MsgGUID: l0q/rBYOTH+bvad5qc+02Q== X-IronPort-AV: E=Sophos;i="6.15,267,1739862000"; d="scan'208";a="208799763" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 06 May 2025 13:05:33 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Tue, 6 May 2025 13:05:12 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Tue, 6 May 2025 13:05:12 -0700 From: To: , , , , , , , CC: , , , , Ryan Wanner Subject: [PATCH v3 3/4] clk: at91: sama7g5: Add missing clk_hw to parent_data Date: Tue, 6 May 2025 13:04:58 -0700 Message-ID: <3578873346318562c2c44f81409a5cee03721fd0.1746561722.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Ryan Wanner The main_xtal clk_hw struct is not passed into parent_data.hw causing the main_osc to not have a parent and corrupting the clock tree. Passing the main_xtal struct into the parent_data struct will ensure the correct parent structure. Signed-off-by: Ryan Wanner --- drivers/clk/at91/sama7g5.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index 8385badc1c70..b4eefca0b6d5 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -979,7 +979,7 @@ static void __init sama7g5_pmc_setup(struct device_node= *np) struct regmap *regmap; struct clk_hw *hw, *main_rc_hw, *main_osc_hw, *main_xtal_hw; struct clk_hw *td_slck_hw, *md_slck_hw; - static struct clk_parent_data parent_data; + static struct clk_parent_data parent_data =3D {0}; struct clk_hw *parent_hws[10]; bool bypass; int i, j; @@ -1017,6 +1017,7 @@ static void __init sama7g5_pmc_setup(struct device_no= de *np) =20 parent_data.name =3D main_xtal_name; parent_data.fw_name =3D main_xtal_name; + parent_data.hw =3D main_xtal_hw; main_osc_hw =3D at91_clk_register_main_osc(regmap, "main_osc", NULL, &parent_data, bypass); if (IS_ERR(main_osc_hw)) --=20 2.43.0 From nobody Wed Feb 11 02:24:40 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 53DAE1FA178; Tue, 6 May 2025 20:05:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746561938; cv=none; b=nD0s6zhGcPt0oIk3RLCu07YJnRQ3kLLfKT/YYUp4pMLErI/qfEqtlB8SvGM2i0sKNT6RAA/8hG5t8kWc/qZ1Ze7fd7C8LTx6M/UKdGmAf1a1xgtgMA+jrDfuO+4zYO3Z7WvZ778Q1zf2d7X+fJGZ29Pbo6otpuYG5PwHxK4GAtE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746561938; c=relaxed/simple; bh=jfgSiqLCqwkZI4qYAO/dSdiUYlqbnqAIsGKA2fS7izw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=PoYbSxd5Mbl7IYDqvLgfHc4RW5NKBQ/aoXoT+fRmKA9lSrxfpUoCxRlXqQYeOJp++L+XSlV6fXVSrtiy4dAHrAxg05gKuQVpJ47ToNb45F74SiWO0U4RFiBed4GkPTEK22MA8BhR0hsQ7L+z1kMZHVDr2YqgjQBSj7x3iy1fy+4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=xnInx0XX; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="xnInx0XX" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1746561937; x=1778097937; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=jfgSiqLCqwkZI4qYAO/dSdiUYlqbnqAIsGKA2fS7izw=; b=xnInx0XXrLTPWCuPj38ji8G/z+GU/Oj0UgXc5lD1tS3OmD/BV6CS+91O 4KDpt8iXPnRDIU0ThFVMg2Hnax9P69qvWmCAE6GqVkTIqQj4ooSa5kV/U 1MjNw1jYhDj3+nijmI34+sSwd9XaoyawJRfuWXBpVRyv20AbbjWHzAunx 24QFd3v5G+imkVyppZWeD3KJkoAy4eAV9xKjkqKQLvDIx2EUpHGUTR/0Y zcgk6L/tZpFJ2A/B1Ag9jriJXNitE5S2Jv2Yuha+8ob2iD6GqWgNTnnLs 0McFFlKl5wAQzK//5cC/pPTtDPgVp0NC59UDbfANozbYBMFP8NQtQbTET Q==; X-CSE-ConnectionGUID: dUBqohHAQlqcpEGq8j09lg== X-CSE-MsgGUID: BzcJr+ljReaz+1R4R6gYiw== X-IronPort-AV: E=Sophos;i="6.15,267,1739862000"; d="scan'208";a="208799764" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 06 May 2025 13:05:33 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Tue, 6 May 2025 13:05:12 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Tue, 6 May 2025 13:05:12 -0700 From: To: , , , , , , , CC: , , , , Ryan Wanner Subject: [PATCH v3 4/4] ARM: dts: microchip: sama7g5: Adjust clock xtal phandle Date: Tue, 6 May 2025 13:04:59 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Ryan Wanner Adjust clock xtal phandles to match the new xtal phandle formatting. Signed-off-by: Ryan Wanner --- arch/arm/boot/dts/microchip/at91-sama7g5ek.dts | 18 ++++++++---------- arch/arm/boot/dts/microchip/sama7g5.dtsi | 4 ++-- 2 files changed, 10 insertions(+), 12 deletions(-) diff --git a/arch/arm/boot/dts/microchip/at91-sama7g5ek.dts b/arch/arm/boot= /dts/microchip/at91-sama7g5ek.dts index 2543599013b1..79bf58f8c02e 100644 --- a/arch/arm/boot/dts/microchip/at91-sama7g5ek.dts +++ b/arch/arm/boot/dts/microchip/at91-sama7g5ek.dts @@ -35,16 +35,6 @@ aliases { i2c2 =3D &i2c9; }; =20 - clocks { - slow_xtal { - clock-frequency =3D <32768>; - }; - - main_xtal { - clock-frequency =3D <24000000>; - }; - }; - gpio-keys { compatible =3D "gpio-keys"; =20 @@ -512,6 +502,10 @@ spi11: spi@400 { }; }; =20 +&main_xtal { + clock-frequency =3D <24000000>; +}; + &gmac0 { #address-cells =3D <1>; #size-cells =3D <0>; @@ -917,3 +911,7 @@ &vddout25 { vin-supply =3D <&vdd_3v3>; status =3D "okay"; }; + +&slow_xtal { + clock-frequency =3D <32768>; +}; diff --git a/arch/arm/boot/dts/microchip/sama7g5.dtsi b/arch/arm/boot/dts/m= icrochip/sama7g5.dtsi index 17bcdcf0cf4a..250c9e98a8bb 100644 --- a/arch/arm/boot/dts/microchip/sama7g5.dtsi +++ b/arch/arm/boot/dts/microchip/sama7g5.dtsi @@ -117,12 +117,12 @@ map1 { }; =20 clocks { - slow_xtal: slow_xtal { + slow_xtal: clock-slowxtal { compatible =3D "fixed-clock"; #clock-cells =3D <0>; }; =20 - main_xtal: main_xtal { + main_xtal: clock-mainxtal { compatible =3D "fixed-clock"; #clock-cells =3D <0>; }; --=20 2.43.0