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Sun, 27 Apr 2025 20:12:05 -0400 From: Jonathan Santos To: , , , CC: Jonathan Santos , , , , , , , , , , , , , , , Subject: [PATCH v6 01/11] dt-bindings: trigger-source: add generic GPIO trigger source Date: Sun, 27 Apr 2025 21:12:02 -0300 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-GUID: F7kClBVzU12lb3L9ItWmqvlX5b3BHDsa X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNDI3MDIwMiBTYWx0ZWRfX/ZtrlEO5AO0i dMP3PBX5sgujWFFAGKW79KDpdH69fU3d2BwaEijo2rX7LQvMEseOwwDNpBP/1hbdDJC1YT/Gx2Z hp17chMuA4Iixy90TXRFp9wSzYt+545Mgyp9qlNOyKWFp/d0op41g+uAyECkpcE2RC0eR6yowkY L0nlSKFRXhqamqbuLuOWC2FAsWwjlKfSlkfLrSfGnIBMdt0rh5C6b9kmDkmL2yI3fegVamM1TJw wJwL2fAW6boBEpbxLC8U0ts2N1OA9xsCTXu66B09HgFFulQ5ntGHNegX4RRETlybbEcsOl3Fwsg JFLKwntq/n5pW71aderbNstds+8ITXixP6zBSXrE53bqme/jzVjfmSNy9InduUozpXrJ8piEKZ1 ineFvvsz1r0jIcKr1h3OT4nnWPBPAUkWNVvVQG2pylHPW28s1DQpgBkTk4WCwvs4YPSOaS/o X-Proofpoint-ORIG-GUID: F7kClBVzU12lb3L9ItWmqvlX5b3BHDsa X-Authority-Analysis: v=2.4 cv=HPzDFptv c=1 sm=1 tr=0 ts=680ec7e5 cx=c_pps a=PpDZqlmH/M8setHirZLBMw==:117 a=PpDZqlmH/M8setHirZLBMw==:17 a=XR8D0OoHHMoA:10 a=VwQbUJbxAAAA:8 a=IpJZQVW2AAAA:8 a=gEfo2CItAAAA:8 a=gAnH3GRIAAAA:8 a=HlNMbzSOJvU92ae2w24A:9 a=IawgGOuG5U0WyFbmm1f5:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-04-27_08,2025-04-24_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 adultscore=0 suspectscore=0 impostorscore=0 phishscore=0 mlxscore=0 malwarescore=0 priorityscore=1501 bulkscore=0 lowpriorityscore=0 clxscore=1011 spamscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2504270202 Content-Type: text/plain; charset="utf-8" Inspired by pwm-trigger, create a new binding for using a GPIO line as a trigger source. Link: https://lore.kernel.org/linux-iio/20250207-dlech-mainline-spi-engine-= offload-2-v8-3-e48a489be48c@baylibre.com/ Signed-off-by: Jonathan Santos Reviewed-by: David Lechner Reviewed-by: Linus Walleij --- v6 Changes: * Changed description. * Fixed typos and replaced GPIO pin with GPIO line. * Added link reference for pwm-trigger. v5 Changes: * New patch in v5. --- .../bindings/trigger-source/gpio-trigger.yaml | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/devicetree/bindings/trigger-source/gpio-t= rigger.yaml diff --git a/Documentation/devicetree/bindings/trigger-source/gpio-trigger.= yaml b/Documentation/devicetree/bindings/trigger-source/gpio-trigger.yaml new file mode 100644 index 000000000000..1331d153ee82 --- /dev/null +++ b/Documentation/devicetree/bindings/trigger-source/gpio-trigger.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/trigger-source/gpio-trigger.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Generic trigger source using GPIO + +description: A GPIO used as a trigger source. + +maintainers: + - Jonathan Santos + +properties: + compatible: + const: gpio-trigger + + '#trigger-source-cells': + const: 0 + + gpios: + maxItems: 1 + description: GPIO to be used as a trigger source. + +required: + - compatible + - '#trigger-source-cells' + - gpios + +additionalProperties: false + +examples: + - | + #include + + trigger { + compatible =3D "gpio-trigger"; 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Sun, 27 Apr 2025 20:12:32 -0400 Received: from ASHBMBX8.ad.analog.com (10.64.17.5) by ASHBCASHYB4.ad.analog.com (10.64.17.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Sun, 27 Apr 2025 20:12:32 -0400 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Sun, 27 Apr 2025 20:12:32 -0400 Received: from JSANTO12-L01.ad.analog.com ([10.65.60.206]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 53S0CHJQ014439; Sun, 27 Apr 2025 20:12:19 -0400 From: Jonathan Santos To: , , , CC: Jonathan Santos , , , , , , , , , , , , , , , Subject: [PATCH v6 02/11] dt-bindings: iio: adc: ad7768-1: add trigger-sources property Date: Sun, 27 Apr 2025 21:12:16 -0300 Message-ID: <128de2793d6d5424ad152c394faf1d51f0d56e0b.1745605382.git.Jonathan.Santos@analog.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNDI3MDIwMiBTYWx0ZWRfXy0hVxil0bB2w zpk5+70/lJC99Ge/gwFQghafu8q3xxpBP3jYlBreVhkq8hjHpYUEWtXJ3ly4gdikES5nhz7ib/9 wrYXkwtVDLIET63a1+wGCgU71aJwZkNYAzzJJRHL5xCQYiUV9k/TGU9DF7vJQ/fJOwwDbcKlejZ /t7WUOX2Yk0dGTFOYyaixjbj3N9uzUxX6NGTxVO8Hv346tDc+pfCFbOVLwZnivQYgvT/0xwa++E YH/u7rvE9090+vg7czS+0nKq/lfYGHyKPr1sM8rvhyYmmppmgkK3rxrOyHWudnFQPQb7y24TWch yTuIgdmQp7TsECtEBYdZcOpyGmZu5yNn/TCsH6AN/BbCFkfxymcPC9at7pH6MnRJOR828VG8unY 0qE0ugnWJbEY4HKTF+VV8ORD8U3hHxt8H1N9zmxMNzuzlKZk87e1AOX/rr4cRvfmSXdKo5t1 X-Proofpoint-ORIG-GUID: yM0ILI6ewh8-TKa18JkkLv5fu0G9_rhZ X-Proofpoint-GUID: yM0ILI6ewh8-TKa18JkkLv5fu0G9_rhZ X-Authority-Analysis: v=2.4 cv=crybk04i c=1 sm=1 tr=0 ts=680ec7f1 cx=c_pps a=PpDZqlmH/M8setHirZLBMw==:117 a=PpDZqlmH/M8setHirZLBMw==:17 a=XR8D0OoHHMoA:10 a=gAnH3GRIAAAA:8 a=o4psIgTgk-Asirc5avcA:9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-04-27_08,2025-04-24_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=950 malwarescore=0 clxscore=1015 impostorscore=0 bulkscore=0 priorityscore=1501 mlxscore=0 spamscore=0 phishscore=0 adultscore=0 lowpriorityscore=0 suspectscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2504270202 Content-Type: text/plain; charset="utf-8" In addition to GPIO synchronization, The AD7768-1 also supports synchronization over SPI, which use is recommended when the GPIO cannot provide a pulse synchronous with the base MCLK signal. It consists of looping back the SYNC_OUT to the SYNC_IN pin and send a command via SPI to trigger the synchronization. Introduce the 'trigger-sources' property to enable SPI-based synchronization via SYNC_OUT pin, along with additional optional entries for GPIO3 and DRDY pins. Also create #trigger-source-cells property to differentiate the trigger sources provided by the ADC. To improve readability, create a adi,ad7768-1.h header with the macros for the cell values. While at it, add description to the interrupts property. Signed-off-by: Jonathan Santos Reviewed-by: David Lechner --- v6 Changes: * Removed references to offload. * Changed trigger-sources-cells description. Each cell value indicates a gpio line from the ADC. * Added adi,ad7768-1.h header with macros for the trigger source cells. * Removed offload trigger entry from trigger-sources. v5 Changes: * Include START pin and DRDY in the trigger-sources description. * Fixed "#trigger-source-cells" value and description. * sync-in-gpios is represented in the trigger-sources property. v4 Changes: * none v3 Changes: * Fixed dt-bindings errors. * Trigger-source is set as an alternative to sync-in-gpios, so we don't break the previous ABI. * increased maxItems from trigger-sources to 2. v2 Changes: * Patch added as replacement for adi,sync-in-spi patch. * addressed the request for a description to interrupts property. --- .../bindings/iio/adc/adi,ad7768-1.yaml | 31 ++++++++++++++++++- include/dt-bindings/iio/adc/adi,ad7768-1.h | 10 ++++++ 2 files changed, 40 insertions(+), 1 deletion(-) create mode 100644 include/dt-bindings/iio/adc/adi,ad7768-1.h diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7768-1.yaml b/= Documentation/devicetree/bindings/iio/adc/adi,ad7768-1.yaml index 3ce59d4d065f..1f476aa15305 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7768-1.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7768-1.yaml @@ -26,7 +26,28 @@ properties: clock-names: const: mclk =20 + trigger-sources: + $ref: /schemas/types.yaml#/definitions/phandle-array + minItems: 1 + maxItems: 2 + description: | + A list of phandles referencing trigger source providers. Each entry + represents a trigger source for the ADC: + + - First entry specifies the device responsible for driving the + synchronization (SYNC_IN) pin, as an alternative to adi,sync-in-= gpios. + This can be a `gpio-trigger` or another `ad7768-1` device. If the + device's own SYNC_OUT pin is internally connected to its SYNC_IN= pin, + reference the device itself or omit this property. + - Second entry optionally defines a GPIO3 pin used as a START sign= al trigger. + + Use the accompanying trigger source cell to identify the type of eac= h entry. + interrupts: + description: + Specifies the interrupt line associated with the ADC. This refers + to the DRDY (Data Ready) pin, which signals when conversion results = are + available. maxItems: 1 =20 '#address-cells': @@ -57,6 +78,15 @@ properties: "#io-channel-cells": const: 1 =20 + "#trigger-source-cells": + description: | + Cell indicates the trigger output signal: 0 =3D SYNC_OUT, 1 =3D GPIO= 3, + 2 =3D DRDY. + + For better readability, macros for these values are available in + dt-bindings/iio/adc/adi,ad7768-1.h. + const: 1 + required: - compatible - reg @@ -65,7 +95,6 @@ required: - vref-supply - spi-cpol - spi-cpha - - adi,sync-in-gpios =20 patternProperties: "^channel@([0-9]|1[0-5])$": diff --git a/include/dt-bindings/iio/adc/adi,ad7768-1.h b/include/dt-bindin= gs/iio/adc/adi,ad7768-1.h new file mode 100644 index 000000000000..34d92856a50b --- /dev/null +++ b/include/dt-bindings/iio/adc/adi,ad7768-1.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_ADI_AD7768_1_H +#define _DT_BINDINGS_ADI_AD7768_1_H + +#define AD7768_TRIGGER_SOURCE_SYNC_OUT 0 +#define AD7768_TRIGGER_SOURCE_GPIO3 1 +#define AD7768_TRIGGER_SOURCE_DRDY 2 + +#endif /* _DT_BINDINGS_ADI_AD7768_1_H */ --=20 2.34.1 From nobody Fri Dec 19 20:10:29 2025 Received: from mx0b-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D470F487BE; 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charset="utf-8" The AD7768-1 ADC exports four bidirectional GPIOs accessible via register map. Document GPIO properties necessary to enable GPIO controller for this device. Acked-by: Bartosz Golaszewski Reviewed-by: Linus Walleij Reviewed-by: Rob Herring (Arm) Signed-off-by: Jonathan Santos --- v6 Changes: * none. v5 Changes: * none. v4 Changes: * none. v3 Changes: * none. v2 Changes: * New patch in v2. --- .../devicetree/bindings/iio/adc/adi,ad7768-1.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7768-1.yaml b/= Documentation/devicetree/bindings/iio/adc/adi,ad7768-1.yaml index 1f476aa15305..25d4995c63a5 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7768-1.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7768-1.yaml @@ -87,6 +87,14 @@ properties: dt-bindings/iio/adc/adi,ad7768-1.h. const: 1 =20 + gpio-controller: true + + "#gpio-cells": + const: 2 + description: | + The first cell is for the GPIO number: 0 to 3. + The second cell takes standard GPIO flags. + required: - compatible - reg @@ -134,6 +142,8 @@ examples: spi-max-frequency =3D <2000000>; spi-cpol; spi-cpha; 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charset="utf-8" The AD7768-1 provides a buffered common-mode voltage output on the VCM pin that can be used to bias analog input signals. Add regulators property to enable the use of the VCM output, referenced here as vcm-output, by any other device. Acked-by: Conor Dooley Signed-off-by: Jonathan Santos --- v6 Changes: * None. v5 Changes: * removed `regulator-min-microvolt` and `regulator-max-microvolt`.=20 v4 Changes: * replace "vcm_output" property name for "vcm-output".=20 v3 Changes: * VCM is now provided as a regulator within the device, instead of a=20 custom property. v2 Changes: * New patch in v2. --- .../bindings/iio/adc/adi,ad7768-1.yaml | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7768-1.yaml b/= Documentation/devicetree/bindings/iio/adc/adi,ad7768-1.yaml index 25d4995c63a5..5083ee7c0256 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7768-1.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7768-1.yaml @@ -68,6 +68,19 @@ properties: in any way, for example if the filter decimation rate changes. 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charset="utf-8" The VCM output voltage can be used as a common-mode voltage within the amplifier preconditioning circuits external to the AD7768-1. This change allows the user to configure VCM output using the regulator framework. Acked-by: Marcelo Schmitt Signed-off-by: Jonathan Santos Reviewed-by: David Lechner --- v6 Changes: * Rearranged iio_device_release_direct() calls to avoid some gotos. * removed of_match_ptr() from regulator_desc. * Addressed other nits. v5 Changes: * enforce AD7768_REG_ANALOG2_VCM macro argument evaluation. * switched to the new iio_device_claim/release_direct() functions. v4 Changes: * Added iio_device_claim_direct_mode() to regulator callbacks to avoid regi= ster access while in buffered mode. * Changed regulator name to "ad7768-1-vcm". * When regulator enable is called, it will set the last voltage selector co= nfigured. * Disabled regulator before configuring it. * Addressed other nits. v3 Changes: * Register VCM output via the regulator framework for improved flexibility and external integration. v2 Changes: * VCM output support is now defined by a devicetree property, instead of=20 and IIO attribute. --- drivers/iio/adc/Kconfig | 1 + drivers/iio/adc/ad7768-1.c | 173 +++++++++++++++++++++++++++++++++++++ 2 files changed, 174 insertions(+) diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index ad06cf556785..8dc4cc4c25af 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -329,6 +329,7 @@ config AD7766 config AD7768_1 tristate "Analog Devices AD7768-1 ADC driver" depends on SPI + select REGULATOR select REGMAP_SPI select IIO_BUFFER select IIO_TRIGGER diff --git a/drivers/iio/adc/ad7768-1.c b/drivers/iio/adc/ad7768-1.c index 09e4ab76e2b6..0364d73329b0 100644 --- a/drivers/iio/adc/ad7768-1.c +++ b/drivers/iio/adc/ad7768-1.c @@ -12,8 +12,10 @@ #include #include #include +#include #include #include +#include #include #include =20 @@ -80,6 +82,12 @@ #define AD7768_CONV_MODE_MSK GENMASK(2, 0) #define AD7768_CONV_MODE(x) FIELD_PREP(AD7768_CONV_MODE_MSK, x) =20 +/* AD7768_REG_ANALOG2 */ +#define AD7768_REG_ANALOG2_VCM_MSK GENMASK(2, 0) +#define AD7768_REG_ANALOG2_VCM(x) FIELD_PREP(AD7768_REG_ANALOG2_VCM_MSK, (= x)) + +#define AD7768_VCM_OFF 0x07 + enum ad7768_conv_mode { AD7768_CONTINUOUS, AD7768_ONE_SHOT, @@ -157,6 +165,8 @@ struct ad7768_state { struct regmap *regmap; struct regmap *regmap24; struct regulator *vref; + struct regulator_dev *vcm_rdev; + unsigned int vcm_output_sel; struct clk *mclk; unsigned int mclk_freq; unsigned int samp_freq; @@ -644,6 +654,164 @@ static int ad7768_triggered_buffer_alloc(struct iio_d= ev *indio_dev) &ad7768_buffer_ops); } =20 +static int ad7768_vcm_enable(struct regulator_dev *rdev) +{ + struct iio_dev *indio_dev =3D rdev_get_drvdata(rdev); + struct ad7768_state *st =3D iio_priv(indio_dev); + int ret, regval; + + if (!indio_dev) + return -EINVAL; + + if (!iio_device_claim_direct(indio_dev)) + return -EBUSY; + + /* To enable, set the last selected output */ + regval =3D AD7768_REG_ANALOG2_VCM(st->vcm_output_sel + 1); + ret =3D regmap_update_bits(st->regmap, AD7768_REG_ANALOG2, + AD7768_REG_ANALOG2_VCM_MSK, regval); + iio_device_release_direct(indio_dev); + + return ret; +} + +static int ad7768_vcm_disable(struct regulator_dev *rdev) +{ + struct iio_dev *indio_dev =3D rdev_get_drvdata(rdev); + struct ad7768_state *st =3D iio_priv(indio_dev); + int ret; + + if (!indio_dev) + return -EINVAL; + + if (!iio_device_claim_direct(indio_dev)) + return -EBUSY; + + ret =3D regmap_update_bits(st->regmap, AD7768_REG_ANALOG2, + AD7768_REG_ANALOG2_VCM_MSK, AD7768_VCM_OFF); + iio_device_release_direct(indio_dev); + + return ret; +} + +static int ad7768_vcm_is_enabled(struct regulator_dev *rdev) +{ + struct iio_dev *indio_dev =3D rdev_get_drvdata(rdev); + struct ad7768_state *st =3D iio_priv(indio_dev); + int ret, val; + + if (!indio_dev) + return -EINVAL; + + if (!iio_device_claim_direct(indio_dev)) + return -EBUSY; + + ret =3D regmap_read(st->regmap, AD7768_REG_ANALOG2, &val); + iio_device_release_direct(indio_dev); + if (ret) + return ret; + + return FIELD_GET(AD7768_REG_ANALOG2_VCM_MSK, val) !=3D AD7768_VCM_OFF; +} + +static int ad7768_set_voltage_sel(struct regulator_dev *rdev, + unsigned int selector) +{ + unsigned int regval =3D AD7768_REG_ANALOG2_VCM(selector + 1); + struct iio_dev *indio_dev =3D rdev_get_drvdata(rdev); + struct ad7768_state *st =3D iio_priv(indio_dev); + int ret; + + if (!indio_dev) + return -EINVAL; + + if (!iio_device_claim_direct(indio_dev)) + return -EBUSY; + + ret =3D regmap_update_bits(st->regmap, AD7768_REG_ANALOG2, + AD7768_REG_ANALOG2_VCM_MSK, regval); + iio_device_release_direct(indio_dev); + if (ret) + return ret; + + st->vcm_output_sel =3D selector; + + return 0; +} + +static int ad7768_get_voltage_sel(struct regulator_dev *rdev) +{ + struct iio_dev *indio_dev =3D rdev_get_drvdata(rdev); + struct ad7768_state *st =3D iio_priv(indio_dev); + int ret, val; + + if (!indio_dev) + return -EINVAL; + + if (!iio_device_claim_direct(indio_dev)) + return -EBUSY; + + ret =3D regmap_read(st->regmap, AD7768_REG_ANALOG2, &val); + iio_device_release_direct(indio_dev); + if (ret) + return ret; + + val =3D FIELD_GET(AD7768_REG_ANALOG2_VCM_MSK, val); + return clamp(val, 1, (int)rdev->desc->n_voltages) - 1; +} + +static const struct regulator_ops vcm_regulator_ops =3D { + .enable =3D ad7768_vcm_enable, + .disable =3D ad7768_vcm_disable, + .is_enabled =3D ad7768_vcm_is_enabled, + .list_voltage =3D regulator_list_voltage_table, + .set_voltage_sel =3D ad7768_set_voltage_sel, + .get_voltage_sel =3D ad7768_get_voltage_sel, +}; + +static const unsigned int vcm_voltage_table[] =3D { + 2500000, + 2050000, + 1650000, + 1900000, + 1100000, + 900000, +}; + +static const struct regulator_desc vcm_desc =3D { + .name =3D "ad7768-1-vcm", + .of_match =3D "vcm-output", + .regulators_node =3D "regulators", + .n_voltages =3D ARRAY_SIZE(vcm_voltage_table), + .volt_table =3D vcm_voltage_table, + .ops =3D &vcm_regulator_ops, + .type =3D REGULATOR_VOLTAGE, + .owner =3D THIS_MODULE, +}; + +static int ad7768_register_regulators(struct device *dev, struct ad7768_st= ate *st, + struct iio_dev *indio_dev) +{ + struct regulator_config config =3D { + .dev =3D dev, + .driver_data =3D indio_dev, + }; + int ret; + + /* Disable the regulator before registering it */ + ret =3D regmap_update_bits(st->regmap, AD7768_REG_ANALOG2, + AD7768_REG_ANALOG2_VCM_MSK, AD7768_VCM_OFF); + if (ret) + return ret; + + st->vcm_rdev =3D devm_regulator_register(dev, &vcm_desc, &config); + if (IS_ERR(st->vcm_rdev)) + return dev_err_probe(dev, PTR_ERR(st->vcm_rdev), + "failed to register VCM regulator\n"); + + return 0; +} + static int ad7768_probe(struct spi_device *spi) { struct ad7768_state *st; @@ -708,6 +876,11 @@ static int ad7768_probe(struct spi_device *spi) indio_dev->info =3D &ad7768_info; indio_dev->modes =3D INDIO_DIRECT_MODE; =20 + /* Register VCM output regulator */ + ret =3D ad7768_register_regulators(&spi->dev, st, indio_dev); + if (ret) + return ret; + ret =3D ad7768_setup(st); if (ret < 0) { dev_err(&spi->dev, "AD7768 setup failed\n"); --=20 2.34.1 From nobody Fri Dec 19 20:10:29 2025 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2B6F320ED; Mon, 28 Apr 2025 00:13:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745799224; cv=none; b=pACwQLjo9UAtZ/Ph2Dszuj8JPAtxXfl4UW7d71pS9GA1Izji89YFuokm6U8An2nQldEBoh6GCaCD9RL4neYDRe1QnUzqFn78I60vGUUz963pkImd28JBYx4dWCzfZMXnoQdKj9H0z9MJrQg9Y0CE7HDCuosA6q2RMrVx2Gl6Ctw= ARC-Message-Signature: i=1; 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charset="utf-8" From: Sergiu Cuciurean The AD7768-1 has the ability to control other local hardware (such as gain stages),to power down other blocks in the signal chain, or read local status signals over the SPI interface. Add direct mode conditional locks in the gpio callbacks to prevent register access when the device is in buffered mode. This change exports the AD7768-1's four gpios and makes them accessible at an upper layer. Reviewed-by: Marcelo Schmitt Acked-by: Bartosz Golaszewski Reviewed-by: Linus Walleij Signed-off-by: Sergiu Cuciurean Co-developed-by: Jonathan Santos Signed-off-by: Jonathan Santos --- v6 Changes: * Replaced deprecated .set callback with .set_rv. v5 Changes: * Use the new new iio_device_claim/release_direct() functions. * replaced gpiochip_add_data() for devm_gpiochip_add_data(). v4 Changes: * Mentioned in the commit message that we cannot tweak the GPIO controller when the device is not in direct mode. v3 Changes: * Fixed SoB order. * Added missing iio_device_release_direct_mode(). * Simplified some regmap writes. * Removed ad7768_gpio_request() callback. * Fixed line wrapping. v2 Changes: * Replaced mutex for iio_device_claim_direct_mode(). * Use gpio-controller property to conditionally enable the GPIO support. * OBS: when the GPIO is configured as output, we should read=20 the current state value from AD7768_REG_GPIO_WRITE. --- drivers/iio/adc/ad7768-1.c | 141 ++++++++++++++++++++++++++++++++++++- 1 file changed, 139 insertions(+), 2 deletions(-) diff --git a/drivers/iio/adc/ad7768-1.c b/drivers/iio/adc/ad7768-1.c index 0364d73329b0..1a546a0dc654 100644 --- a/drivers/iio/adc/ad7768-1.c +++ b/drivers/iio/adc/ad7768-1.c @@ -9,6 +9,8 @@ #include #include #include +#include +#include #include #include #include @@ -86,6 +88,16 @@ #define AD7768_REG_ANALOG2_VCM_MSK GENMASK(2, 0) #define AD7768_REG_ANALOG2_VCM(x) FIELD_PREP(AD7768_REG_ANALOG2_VCM_MSK, (= x)) =20 +/* AD7768_REG_GPIO_CONTROL */ +#define AD7768_GPIO_UNIVERSAL_EN BIT(7) +#define AD7768_GPIO_CONTROL_MSK GENMASK(3, 0) + +/* AD7768_REG_GPIO_WRITE */ +#define AD7768_GPIO_WRITE_MSK GENMASK(3, 0) + +/* AD7768_REG_GPIO_READ */ +#define AD7768_GPIO_READ_MSK GENMASK(3, 0) + #define AD7768_VCM_OFF 0x07 =20 enum ad7768_conv_mode { @@ -168,6 +180,7 @@ struct ad7768_state { struct regulator_dev *vcm_rdev; unsigned int vcm_output_sel; struct clk *mclk; + struct gpio_chip gpiochip; unsigned int mclk_freq; unsigned int samp_freq; struct completion completion; @@ -353,6 +366,122 @@ static int ad7768_set_dig_fil(struct ad7768_state *st, return 0; } =20 +static int ad7768_gpio_direction_input(struct gpio_chip *chip, unsigned in= t offset) +{ + struct iio_dev *indio_dev =3D gpiochip_get_data(chip); + struct ad7768_state *st =3D iio_priv(indio_dev); + int ret; + + if (!iio_device_claim_direct(indio_dev)) + return -EBUSY; + + ret =3D regmap_clear_bits(st->regmap, AD7768_REG_GPIO_CONTROL, + BIT(offset)); + iio_device_release_direct(indio_dev); + + return ret; +} + +static int ad7768_gpio_direction_output(struct gpio_chip *chip, + unsigned int offset, int value) +{ + struct iio_dev *indio_dev =3D gpiochip_get_data(chip); + struct ad7768_state *st =3D iio_priv(indio_dev); + int ret; + + if (!iio_device_claim_direct(indio_dev)) + return -EBUSY; + + ret =3D regmap_set_bits(st->regmap, AD7768_REG_GPIO_CONTROL, + BIT(offset)); + iio_device_release_direct(indio_dev); + + return ret; +} + +static int ad7768_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + struct iio_dev *indio_dev =3D gpiochip_get_data(chip); + struct ad7768_state *st =3D iio_priv(indio_dev); + unsigned int val; + int ret; + + if (!iio_device_claim_direct(indio_dev)) + return -EBUSY; + + ret =3D regmap_read(st->regmap, AD7768_REG_GPIO_CONTROL, &val); + if (ret) + goto err_release; + + /* + * If the GPIO is configured as an output, read the current value from + * AD7768_REG_GPIO_WRITE. Otherwise, read the input value from + * AD7768_REG_GPIO_READ. + */ + if (val & BIT(offset)) + ret =3D regmap_read(st->regmap, AD7768_REG_GPIO_WRITE, &val); + else + ret =3D regmap_read(st->regmap, AD7768_REG_GPIO_READ, &val); + if (ret) + goto err_release; + + ret =3D !!(val & BIT(offset)); +err_release: + iio_device_release_direct(indio_dev); + + return ret; +} + +static int ad7768_gpio_set(struct gpio_chip *chip, unsigned int offset, in= t value) +{ + struct iio_dev *indio_dev =3D gpiochip_get_data(chip); + struct ad7768_state *st =3D iio_priv(indio_dev); + unsigned int val; + int ret; + + if (!iio_device_claim_direct(indio_dev)) + return -EBUSY; + + ret =3D regmap_read(st->regmap, AD7768_REG_GPIO_CONTROL, &val); + if (ret) + goto err_release; + + if (val & BIT(offset)) + ret =3D regmap_update_bits(st->regmap, AD7768_REG_GPIO_WRITE, + BIT(offset), value << offset); + +err_release: + iio_device_release_direct(indio_dev); + + return ret; +} + +static int ad7768_gpio_init(struct iio_dev *indio_dev) +{ + struct ad7768_state *st =3D iio_priv(indio_dev); + int ret; + + ret =3D regmap_write(st->regmap, AD7768_REG_GPIO_CONTROL, + AD7768_GPIO_UNIVERSAL_EN); + if (ret) + return ret; + + st->gpiochip =3D (struct gpio_chip) { + .label =3D "ad7768_1_gpios", + .base =3D -1, + .ngpio =3D 4, + .parent =3D &st->spi->dev, + .can_sleep =3D true, + .direction_input =3D ad7768_gpio_direction_input, + .direction_output =3D ad7768_gpio_direction_output, + .get =3D ad7768_gpio_get, + .set_rv =3D ad7768_gpio_set, + .owner =3D THIS_MODULE, + }; + + return devm_gpiochip_add_data(&st->spi->dev, &st->gpiochip, indio_dev); +} + static int ad7768_set_freq(struct ad7768_state *st, unsigned int freq) { @@ -494,8 +623,9 @@ static const struct iio_info ad7768_info =3D { .debugfs_reg_access =3D &ad7768_reg_access, }; =20 -static int ad7768_setup(struct ad7768_state *st) +static int ad7768_setup(struct iio_dev *indio_dev) { + struct ad7768_state *st =3D iio_priv(indio_dev); int ret; =20 st->gpio_reset =3D devm_gpiod_get_optional(&st->spi->dev, "reset", @@ -528,6 +658,13 @@ static int ad7768_setup(struct ad7768_state *st) if (IS_ERR(st->gpio_sync_in)) return PTR_ERR(st->gpio_sync_in); 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Sun, 27 Apr 2025 20:13:32 -0400 From: Jonathan Santos To: , , , CC: Jonathan Santos , , , , , , , , , , , , , , , , "David Lechner" Subject: [PATCH v6 07/11] iio: adc: ad7768-1: add multiple scan types to support 16-bits mode Date: Sun, 27 Apr 2025 21:13:29 -0300 Message-ID: <0a214d5dfacc3976db71af8a80f9dcf2887fe6cc.1745605382.git.Jonathan.Santos@analog.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNDI3MDIwMiBTYWx0ZWRfX3CjuUs9PP1BI H14YKdaqOouaq10RFbzTv5LPfWLm7mHf73vfQJjway1mqtdO/kBwR4IbBOYqAcY/KPudqA5ca8l m/5ZCT3g4/1FpwZ3nBvBMR025L2VLrTqouq4P7CdXQDSuRDzKDMKLdQM1x+he7TrMS598cP0tz+ UqEijiNlYVrQ2+Iju8kpQSjEG2AxXVtGsRGHVe5dK8uJK4NsuOR2vfpob8aQJsLJoW3GBLTJEDh VWngs2AOkcuc+guX2HSrmLpv4uk0tR7Kfbp+gvqguwWXimzjTQUFr86M0+Yw0oTugzcCFpRMU9h Br34j1VsXG1pP1VIdVFH7J7CDUnmZuZFLuTzkgt+q+aC+cllhwhQ8crL7YEUD+ecNAglfno/ZyN lCc1QmID0mBA/9P+Avz4jaCIe5xubWuUf1Nbqd87a+OANkwiJ7OIBIctd8YLNd7dZqMMG4T6 X-Proofpoint-ORIG-GUID: n8diwT2mKXJ6795OnBxYcNHJc4UG7ve7 X-Proofpoint-GUID: n8diwT2mKXJ6795OnBxYcNHJc4UG7ve7 X-Authority-Analysis: v=2.4 cv=crybk04i c=1 sm=1 tr=0 ts=680ec83f cx=c_pps a=PpDZqlmH/M8setHirZLBMw==:117 a=PpDZqlmH/M8setHirZLBMw==:17 a=XR8D0OoHHMoA:10 a=ajdmHsczAAAA:8 a=gAnH3GRIAAAA:8 a=TVenB2Com6UDTqQwcj8A:9 a=Cd2TjbhyRiE6FbCepFud:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-04-27_08,2025-04-24_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 malwarescore=0 clxscore=1011 impostorscore=0 bulkscore=0 priorityscore=1501 mlxscore=0 spamscore=0 phishscore=0 adultscore=0 lowpriorityscore=0 suspectscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2504270202 Content-Type: text/plain; charset="utf-8" When the device is configured to decimation x8, only possible in the sinc5 filter, output data is reduced to 16-bits in order to support 1 MHz of sampling frequency due to clock limitation. Use multiple scan types feature to enable the driver to switch scan type in runtime, making possible to support both 24-bit and 16-bit resolution. Reviewed-by: David Lechner Signed-off-by: Jonathan Santos Reviewed-by: Marcelo Schmitt --- v6 Changes: * None. v5 Changes: * None. v4 Changes: * None. v3 Changes: * Decreased storagebits to 16 for AD7768_SCAN_TYPE_HIGH_SPEED scan type. v2 Changes: * Included the ".shift" value back to scan_type. * Changed the number of bytes from regmap_read instead of shifting the=20 ADC sample value when the word size is lower (16-bits). --- drivers/iio/adc/ad7768-1.c | 74 ++++++++++++++++++++++++++++++++------ 1 file changed, 64 insertions(+), 10 deletions(-) diff --git a/drivers/iio/adc/ad7768-1.c b/drivers/iio/adc/ad7768-1.c index 1a546a0dc654..087478afb5bf 100644 --- a/drivers/iio/adc/ad7768-1.c +++ b/drivers/iio/adc/ad7768-1.c @@ -139,6 +139,15 @@ struct ad7768_clk_configuration { enum ad7768_pwrmode pwrmode; }; =20 +enum ad7768_scan_type { + AD7768_SCAN_TYPE_NORMAL, + AD7768_SCAN_TYPE_HIGH_SPEED, +}; + +static const int ad7768_mclk_div_rates[4] =3D { + 16, 8, 4, 2, +}; + static const struct ad7768_clk_configuration ad7768_clk_config[] =3D { { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_8, 16, AD7768_FAST_MODE }, { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_16, 32, AD7768_FAST_MODE }, @@ -153,6 +162,22 @@ static const struct ad7768_clk_configuration ad7768_cl= k_config[] =3D { { AD7768_MCLK_DIV_16, AD7768_DEC_RATE_1024, 16384, AD7768_ECO_MODE }, }; =20 +static const struct iio_scan_type ad7768_scan_type[] =3D { + [AD7768_SCAN_TYPE_NORMAL] =3D { + .sign =3D 's', + .realbits =3D 24, + .storagebits =3D 32, + .shift =3D 8, + .endianness =3D IIO_BE, + }, + [AD7768_SCAN_TYPE_HIGH_SPEED] =3D { + .sign =3D 's', + .realbits =3D 16, + .storagebits =3D 16, + .endianness =3D IIO_BE, + }, +}; + static const struct iio_chan_spec ad7768_channels[] =3D { { .type =3D IIO_VOLTAGE, @@ -162,13 +187,9 @@ static const struct iio_chan_spec ad7768_channels[] = =3D { .indexed =3D 1, .channel =3D 0, .scan_index =3D 0, - .scan_type =3D { - .sign =3D 's', - .realbits =3D 24, - .storagebits =3D 32, - .shift =3D 8, - .endianness =3D IIO_BE, - }, + .has_ext_scan_type =3D 1, + .ext_scan_type =3D ad7768_scan_type, + .num_ext_scan_type =3D ARRAY_SIZE(ad7768_scan_type), }, }; =20 @@ -182,6 +203,7 @@ struct ad7768_state { struct clk *mclk; struct gpio_chip gpiochip; unsigned int mclk_freq; + unsigned int dec_rate; unsigned int samp_freq; struct completion completion; struct iio_trigger *trig; @@ -300,6 +322,15 @@ static int ad7768_scan_direct(struct iio_dev *indio_de= v) if (ret) return ret; =20 + /* + * When the decimation rate is set to x8, the ADC data precision is + * reduced from 24 bits to 16 bits. Since the AD7768_REG_ADC_DATA + * register provides 24-bit data, the precision is reduced by + * right-shifting the read value by 8 bits. + */ + if (st->dec_rate =3D=3D 8) + readval >>=3D 8; + /* * Any SPI configuration of the AD7768-1 can only be * performed in continuous conversion mode. @@ -516,6 +547,8 @@ static int ad7768_set_freq(struct ad7768_state *st, if (ret < 0) return ret; =20 + st->dec_rate =3D ad7768_clk_config[idx].clk_div / + ad7768_mclk_div_rates[ad7768_clk_config[idx].mclk_div]; st->samp_freq =3D DIV_ROUND_CLOSEST(st->mclk_freq, ad7768_clk_config[idx].clk_div); =20 @@ -549,8 +582,13 @@ static int ad7768_read_raw(struct iio_dev *indio_dev, int *val, int *val2, long info) { struct ad7768_state *st =3D iio_priv(indio_dev); + const struct iio_scan_type *scan_type; int scale_uv, ret; =20 + scan_type =3D iio_get_current_scan_type(indio_dev, chan); + if (IS_ERR(scan_type)) + return PTR_ERR(scan_type); + switch (info) { case IIO_CHAN_INFO_RAW: if (!iio_device_claim_direct(indio_dev)) @@ -561,7 +599,7 @@ static int ad7768_read_raw(struct iio_dev *indio_dev, iio_device_release_direct(indio_dev); if (ret < 0) return ret; - *val =3D sign_extend32(ret, chan->scan_type.realbits - 1); + *val =3D sign_extend32(ret, scan_type->realbits - 1); =20 return IIO_VAL_INT; =20 @@ -571,7 +609,7 @@ static int ad7768_read_raw(struct iio_dev *indio_dev, return scale_uv; =20 *val =3D (scale_uv * 2) / 1000; - *val2 =3D chan->scan_type.realbits; + *val2 =3D scan_type->realbits; =20 return IIO_VAL_FRACTIONAL_LOG2; =20 @@ -615,11 +653,21 @@ static const struct attribute_group ad7768_group =3D { .attrs =3D ad7768_attributes, }; =20 +static int ad7768_get_current_scan_type(const struct iio_dev *indio_dev, + const struct iio_chan_spec *chan) +{ + struct ad7768_state *st =3D iio_priv(indio_dev); + + return st->dec_rate =3D=3D 8 ? AD7768_SCAN_TYPE_HIGH_SPEED : + AD7768_SCAN_TYPE_NORMAL; +} + static const struct iio_info ad7768_info =3D { .attrs =3D &ad7768_group, .read_raw =3D &ad7768_read_raw, .write_raw =3D &ad7768_write_raw, .read_label =3D ad7768_read_label, + .get_current_scan_type =3D &ad7768_get_current_scan_type, .debugfs_reg_access =3D &ad7768_reg_access, }; =20 @@ -674,9 +722,15 @@ static irqreturn_t ad7768_trigger_handler(int irq, voi= d *p) struct iio_poll_func *pf =3D p; struct iio_dev *indio_dev =3D pf->indio_dev; struct ad7768_state *st =3D iio_priv(indio_dev); + const struct iio_scan_type *scan_type; int ret; =20 - ret =3D spi_read(st->spi, &st->data.scan.chan, 3); + scan_type =3D iio_get_current_scan_type(indio_dev, &indio_dev->channels[0= ]); + if (IS_ERR(scan_type)) + return PTR_ERR(scan_type); + + ret =3D spi_read(st->spi, &st->data.scan.chan, + BITS_TO_BYTES(scan_type->realbits)); if (ret < 0) goto out; =20 --=20 2.34.1 From nobody Fri Dec 19 20:10:29 2025 Received: from mx0b-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A4A528691; 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charset="utf-8" The synchronization method using GPIO requires the generated pulse to be truly synchronous with the base MCLK signal. When it is not possible to do that in hardware, the datasheet recommends using synchronization over SPI, where the generated pulse is already synchronous with MCLK. This requires the SYNC_OUT pin to be connected to SYNC_IN pin. Use trigger-sources property to enable device synchronization over SPI and multi-device synchronization, as an alternative to adi,sync-in-gpios property. Signed-off-by: Jonathan Santos --- v6 Changes: * Created macro for the SYNC index from trigger-sources. * Check trigger source by the compatible string (and the dev node for the self triggering). * Check nargs before accessing the args array. * Use `trigger-sources` as an alternative to `adi,sync-in-gpios` (now optional), instead of replacing it.=20 v5 Changes: * Allow omitting trigger-sources property. * include gpio-trigger to trigger-sources to replace adi,sync-in-gpios property. * Read trigger-sources cell value to differentiate the trigger type. v4 Changes: * None. v3 Changes: * Fixed args.fwnode leakage in the trigger-sources parsing. * Synchronization over spi is enabled when the trigger-sources references the own device. * Synchronization is kept within the device, and return error if the gpio is not defined and the trigger-sources reference does not match the current device.=20 v2 Changes: * Synchronization via SPI is enabled when the Sync GPIO is not defined. * now trigger-sources property indicates the synchronization provider or main device. The main device will be used to drive the SYNC_IN when requested (via GPIO or SPI). --- drivers/iio/adc/ad7768-1.c | 126 +++++++++++++++++++++++++++++++++++-- 1 file changed, 120 insertions(+), 6 deletions(-) diff --git a/drivers/iio/adc/ad7768-1.c b/drivers/iio/adc/ad7768-1.c index 087478afb5bf..c00571f17254 100644 --- a/drivers/iio/adc/ad7768-1.c +++ b/drivers/iio/adc/ad7768-1.c @@ -28,6 +28,8 @@ #include #include =20 +#include + /* AD7768 registers definition */ #define AD7768_REG_CHIP_TYPE 0x3 #define AD7768_REG_PROD_ID_L 0x4 @@ -100,6 +102,8 @@ =20 #define AD7768_VCM_OFF 0x07 =20 +#define AD7768_TRIGGER_SOURCE_SYNC_IDX 0 + enum ad7768_conv_mode { AD7768_CONTINUOUS, AD7768_ONE_SHOT, @@ -209,6 +213,7 @@ struct ad7768_state { struct iio_trigger *trig; struct gpio_desc *gpio_sync_in; struct gpio_desc *gpio_reset; + bool en_spi_sync; const char *labels[ARRAY_SIZE(ad7768_channels)]; /* * DMA (thus cache coherency maintenance) may require the @@ -295,6 +300,19 @@ static const struct regmap_config ad7768_regmap24_conf= ig =3D { .max_register =3D AD7768_REG24_COEFF_DATA, }; =20 +static int ad7768_send_sync_pulse(struct ad7768_state *st) +{ + if (st->en_spi_sync) + return regmap_write(st->regmap, AD7768_REG_SYNC_RESET, 0x00); + + if (st->gpio_sync_in) { + gpiod_set_value_cansleep(st->gpio_sync_in, 1); + gpiod_set_value_cansleep(st->gpio_sync_in, 0); + } + + return 0; +} + static int ad7768_set_mode(struct ad7768_state *st, enum ad7768_conv_mode mode) { @@ -391,10 +409,7 @@ static int ad7768_set_dig_fil(struct ad7768_state *st, return ret; =20 /* A sync-in pulse is required every time the filter dec rate changes */ - gpiod_set_value(st->gpio_sync_in, 1); - gpiod_set_value(st->gpio_sync_in, 0); - - return 0; + return ad7768_send_sync_pulse(st); } =20 static int ad7768_gpio_direction_input(struct gpio_chip *chip, unsigned in= t offset) @@ -671,6 +686,94 @@ static const struct iio_info ad7768_info =3D { .debugfs_reg_access =3D &ad7768_reg_access, }; =20 +static struct gpio_desc *ad7768_trigger_source_get_gpio(struct device *dev, + struct fwnode_handle *fwnode) +{ + const char *value; + int ret; + + ret =3D fwnode_property_read_string(fwnode, "compatible", &value); + if (ret) + return ERR_PTR(ret); + + if (strcmp("gpio-trigger", value)) + return ERR_PTR(-EINVAL); + + return devm_fwnode_gpiod_get_index(dev, fwnode, NULL, 0, + GPIOD_OUT_LOW, "sync-in"); +} + +static int ad7768_trigger_sources_get_sync(struct device *dev, + struct ad7768_state *st) +{ + struct fwnode_reference_args args; + struct fwnode_handle *fwnode =3D NULL; + int ret; + + /* + * The AD7768-1 allows two primary methods for driving the SYNC_IN pin + * to synchronize one or more devices: + * 1. Using an external GPIO. + * 2. Using a SPI command, where the SYNC_OUT pin generates a + * synchronization pulse that drives the SYNC_IN pin. + */ + if (!device_property_present(dev, "trigger-sources")) { + /* + * In the absence of trigger-sources property, enable self + * synchronization over SPI (SYNC_OUT). + */ + st->en_spi_sync =3D true; + return 0; + } + + ret =3D fwnode_property_get_reference_args(dev_fwnode(dev), + "trigger-sources", + "#trigger-source-cells", + 0, + AD7768_TRIGGER_SOURCE_SYNC_IDX, + &args); + if (ret) + return ret; + + fwnode =3D args.fwnode; + /* + * First, try getting the GPIO trigger source and fallback to + * synchronization over SPI in case of failure. + */ + st->gpio_sync_in =3D ad7768_trigger_source_get_gpio(dev, fwnode); + if (IS_ERR(st->gpio_sync_in)) { + /* + * For this case, it requires one argument, which indicates the + * output pin referenced. + */ + if (args.nargs < 1) + goto err_not_supp; + + if (args.args[0] !=3D AD7768_TRIGGER_SOURCE_SYNC_OUT) + goto err_not_supp; + + /* + * Only self trigger is supported for now, i.e., + * external SYNC_OUT is not allowed. + */ + if (fwnode->dev =3D=3D dev) { + st->en_spi_sync =3D true; + goto out_put_node; + } + + goto err_not_supp; + } + + goto out_put_node; + +err_not_supp: + ret =3D dev_err_probe(dev, -EOPNOTSUPP, + "Invalid synchronization trigger source"); +out_put_node: + fwnode_handle_put(args.fwnode); + return ret; +} + static int ad7768_setup(struct iio_dev *indio_dev) { struct ad7768_state *st =3D iio_priv(indio_dev); @@ -701,11 +804,22 @@ static int ad7768_setup(struct iio_dev *indio_dev) return ret; } =20 - st->gpio_sync_in =3D devm_gpiod_get(&st->spi->dev, "adi,sync-in", - GPIOD_OUT_LOW); + /* For backwards compatibility, try the adi,sync-in-gpios property */ + st->gpio_sync_in =3D devm_gpiod_get_optional(&st->spi->dev, "adi,sync-in", + GPIOD_OUT_LOW); if (IS_ERR(st->gpio_sync_in)) return PTR_ERR(st->gpio_sync_in); =20 + /* + * If the synchronization is not defined by adi,sync-in-gpios, try the + * trigger-sources. + */ + if (!st->gpio_sync_in) { + ret =3D ad7768_trigger_sources_get_sync(&st->spi->dev, st); + if (ret) + return ret; + } + /* Only create a Chip GPIO if flagged for it */ if (device_property_read_bool(&st->spi->dev, "gpio-controller")) { ret =3D ad7768_gpio_init(indio_dev); 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Sun, 27 Apr 2025 20:14:07 -0400 From: Jonathan Santos To: , , , CC: Jonathan Santos , , , , , , , , , , , , , , , Subject: [PATCH v6 09/11] iio: adc: ad7768-1: replace manual attribute declaration Date: Sun, 27 Apr 2025 21:14:01 -0300 Message-ID: <7c308dac8869a0152c09f6218df32bbc516594d4.1745605382.git.Jonathan.Santos@analog.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-GUID: lFtg0Wa9_XH9ZK8fa5U-3EbhOdy5hV6e X-Authority-Analysis: v=2.4 cv=b+Wy4sGx c=1 sm=1 tr=0 ts=680ec85d cx=c_pps a=PpDZqlmH/M8setHirZLBMw==:117 a=PpDZqlmH/M8setHirZLBMw==:17 a=XR8D0OoHHMoA:10 a=IpJZQVW2AAAA:8 a=gAnH3GRIAAAA:8 a=8rrw0zspLT4GB54sGJwA:9 a=IawgGOuG5U0WyFbmm1f5:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNDI3MDIwMiBTYWx0ZWRfX5ksmkXItbf4/ inKhQ2txVV5NvG9Lsu1Fk5TzrE5KvlHMTCcIQ7FxW5fvZQbyaOhPzNv/J2Iqi3kqgtETJci0lsE BHgxuj2W8gDVzYgAqxwoDmglEdiA46NOqZnZdPCjPeqFEFNeC9KGdQ3rmxIpLm2hzFXMKpSMSiD 5fdxS6radmQ47gZUPz0uaOUxjMwKUl9hYJViJ4obVPyo4Gf+VS+AFZkthtllZ06YwZCD1mUR7E8 1v1qKng/lZZ/Tx4NILyPL7ZPaerJ1NZDNFKKPY5cTjbML0olArJlDuQaVnFS82G1VQKExssKtbE wLUen7WJKCUAZ4pTJ6zBPJrQwypFypEa4jIAugXSD2x/UHzwD34oo6Dz99OdUCjhE58IGHcv1Mu F5l332BePSE8pjNCxZVbGCnNiOJuHVvVB2XdCHCiwmmxNWxvGGU6tIiPBMvvZGE8gImYxW9a X-Proofpoint-ORIG-GUID: lFtg0Wa9_XH9ZK8fa5U-3EbhOdy5hV6e X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-04-27_08,2025-04-24_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 lowpriorityscore=0 suspectscore=0 phishscore=0 priorityscore=1501 adultscore=0 mlxscore=0 spamscore=0 bulkscore=0 impostorscore=0 clxscore=1015 mlxlogscore=999 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2504270202 Content-Type: text/plain; charset="utf-8" Use read_avail callback from struct iio_info to replace the manual declaration of sampling_frequency_available attribute. Reviewed-by: David Lechner Reviewed-by: Marcelo Schmitt Signed-off-by: Jonathan Santos --- v6 Changes: * none. v5 Changes: * none. v4 Changes: * Added ad7768_fill_samp_freq_tbl() helper function. * Sampling frequency table is precomputed at probe. v3 Changes: * New patch in v3. --- drivers/iio/adc/ad7768-1.c | 63 +++++++++++++++++++------------------- 1 file changed, 31 insertions(+), 32 deletions(-) diff --git a/drivers/iio/adc/ad7768-1.c b/drivers/iio/adc/ad7768-1.c index c00571f17254..10791a85d2c5 100644 --- a/drivers/iio/adc/ad7768-1.c +++ b/drivers/iio/adc/ad7768-1.c @@ -188,6 +188,7 @@ static const struct iio_chan_spec ad7768_channels[] =3D= { .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW), .info_mask_shared_by_type =3D BIT(IIO_CHAN_INFO_SCALE), .info_mask_shared_by_all =3D BIT(IIO_CHAN_INFO_SAMP_FREQ), + .info_mask_shared_by_all_available =3D BIT(IIO_CHAN_INFO_SAMP_FREQ), .indexed =3D 1, .channel =3D 0, .scan_index =3D 0, @@ -209,6 +210,7 @@ struct ad7768_state { unsigned int mclk_freq; unsigned int dec_rate; unsigned int samp_freq; + unsigned int samp_freq_avail[ARRAY_SIZE(ad7768_clk_config)]; struct completion completion; struct iio_trigger *trig; struct gpio_desc *gpio_sync_in; @@ -313,6 +315,15 @@ static int ad7768_send_sync_pulse(struct ad7768_state = *st) return 0; } =20 +static void ad7768_fill_samp_freq_tbl(struct ad7768_state *st) +{ + int i; + + for (i =3D 0; i < ARRAY_SIZE(ad7768_clk_config); i++) + st->samp_freq_avail[i] =3D DIV_ROUND_CLOSEST(st->mclk_freq, + ad7768_clk_config[i].clk_div); +} + static int ad7768_set_mode(struct ad7768_state *st, enum ad7768_conv_mode mode) { @@ -570,28 +581,6 @@ static int ad7768_set_freq(struct ad7768_state *st, return 0; } =20 -static ssize_t ad7768_sampling_freq_avail(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - struct iio_dev *indio_dev =3D dev_to_iio_dev(dev); - struct ad7768_state *st =3D iio_priv(indio_dev); - unsigned int freq; - int i, len =3D 0; - - for (i =3D 0; i < ARRAY_SIZE(ad7768_clk_config); i++) { - freq =3D DIV_ROUND_CLOSEST(st->mclk_freq, - ad7768_clk_config[i].clk_div); - len +=3D scnprintf(buf + len, PAGE_SIZE - len, "%d ", freq); - } - - buf[len - 1] =3D '\n'; - - return len; -} - -static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(ad7768_sampling_freq_avail); - static int ad7768_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long info) @@ -637,6 +626,24 @@ static int ad7768_read_raw(struct iio_dev *indio_dev, return -EINVAL; } =20 +static int ad7768_read_avail(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + const int **vals, int *type, int *length, + long info) +{ + struct ad7768_state *st =3D iio_priv(indio_dev); + + switch (info) { + case IIO_CHAN_INFO_SAMP_FREQ: + *vals =3D (int *)st->samp_freq_avail; + *length =3D ARRAY_SIZE(ad7768_clk_config); + *type =3D IIO_VAL_INT; + return IIO_AVAIL_LIST; + default: + return -EINVAL; + } +} + static int ad7768_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int val, int val2, long info) @@ -659,15 +666,6 @@ static int ad7768_read_label(struct iio_dev *indio_dev, return sprintf(label, "%s\n", st->labels[chan->channel]); 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Sun, 27 Apr 2025 20:14:21 -0400 From: Jonathan Santos To: , , , CC: Jonathan Santos , , , , , , , , , , , , , , , , "Pop Paul" Subject: [PATCH v6 10/11] iio: adc: ad7768-1: add filter type and oversampling ratio attributes Date: Sun, 27 Apr 2025 21:14:17 -0300 Message-ID: <4493dc2e3e0fb61ba3e8a0e54571998aaaaf46c8.1745605382.git.Jonathan.Santos@analog.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-GUID: NaWKEUnf7UqYyD9AFpbGM3-gQIZOTvPp X-Authority-Analysis: v=2.4 cv=b+Wy4sGx c=1 sm=1 tr=0 ts=680ec86b cx=c_pps a=PpDZqlmH/M8setHirZLBMw==:117 a=PpDZqlmH/M8setHirZLBMw==:17 a=XR8D0OoHHMoA:10 a=IpJZQVW2AAAA:8 a=gAnH3GRIAAAA:8 a=PqQXOG8vFxuAHkRQ7a0A:9 a=IawgGOuG5U0WyFbmm1f5:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNDI3MDIwMiBTYWx0ZWRfXxphXPBtbxfuc xuGp2l68w1eAXbo6e/KdS5BLdVKr3jIrD2Iro5SPgqjs0tvqzLyCbFYev0y0WmdXAKOSujZj6Vl OnFyZ6a5rNQ8wPEuYwoIk1XePYItd90jl6tlTsihhVxMEChbCVPwZt++tCmvAu//Cy4mtEdPyQ4 7NdV+HSseyyyubL6Oyg2YunAFSAZFj1kbhfJatUFY1vkljIhdnUU6r89C8fhyw2jvAhQlQI9xcx 8JoqyEntTpK6F8m3PHpoTkJFBW7LbNivCzt3+leZn9P5QYj0pf94rVW/Fu+Z9WLw4ZBFFI2yzMU xA7ds67IfXSDRAZU75BNJ9poh4+JkmOE6zin4WB4h/OD3rF5GSje5uMEVk911OfG9Jjf9xYqTTL nKvVaQApVYS+DDh6/grrVcjJaq8eRS8/0KzMITbrPvJdx4hqS6vklKvS3d6pV71J8j/qx0nF X-Proofpoint-ORIG-GUID: NaWKEUnf7UqYyD9AFpbGM3-gQIZOTvPp X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-04-27_08,2025-04-24_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 lowpriorityscore=0 suspectscore=0 phishscore=0 priorityscore=1501 adultscore=0 mlxscore=0 spamscore=0 bulkscore=0 impostorscore=0 clxscore=1015 mlxlogscore=999 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2504270202 Content-Type: text/plain; charset="utf-8" Separate filter type and decimation rate from the sampling frequency attribute. The new filter type attribute enables sinc3, sinc3+rej60 and wideband filters, which were previously unavailable. Previously, combining decimation and MCLK divider in the sampling frequency obscured performance trade-offs. Lower MCLK divider settings increase power usage, while lower decimation rates reduce precision by decreasing averaging. By creating an oversampling attribute, which controls the decimation, users gain finer control over performance. The addition of those attributes allows a wider range of sampling frequencies and more access to the device features. Sampling frequency table is updated after every digital filter parameter change. Reviewed-by: David Lechner Co-developed-by: Pop Paul Signed-off-by: Pop Paul Signed-off-by: Jonathan Santos --- v6 Changes: * Made sinc3 decimation rate calculation clearer as requested. * Renamed some filter functions to clarify the purpose. * Other nits. v5 Changes: * Addressed some nits. * Use the new new iio_device_claim/release_direct() functions. v4 Changes: * Sampling frequency table is dynamically updated after every filter configuration. v3 Changes: * removed unused variables. * included sinc3+rej60 filter type. * oversampling_ratio moved to info_mask_shared_by_type. * reordered functions to avoid forward declaration. * simplified regmap writes. * Removed locking. * replaced some helper functions for direct regmap_update_bits calls. * Addressed other nits. v2 Changes: * Decimation_rate attribute replaced for oversampling_ratio. --- drivers/iio/adc/ad7768-1.c | 363 ++++++++++++++++++++++++++++++------- 1 file changed, 293 insertions(+), 70 deletions(-) diff --git a/drivers/iio/adc/ad7768-1.c b/drivers/iio/adc/ad7768-1.c index 10791a85d2c5..e2b8f12260a5 100644 --- a/drivers/iio/adc/ad7768-1.c +++ b/drivers/iio/adc/ad7768-1.c @@ -20,6 +20,8 @@ #include #include #include +#include +#include =20 #include #include @@ -77,7 +79,7 @@ #define AD7768_PWR_PWRMODE(x) FIELD_PREP(AD7768_PWR_PWRMODE_MSK, x) =20 /* AD7768_REG_DIGITAL_FILTER */ -#define AD7768_DIG_FIL_FIL_MSK GENMASK(6, 4) +#define AD7768_DIG_FIL_FIL_MSK GENMASK(7, 4) #define AD7768_DIG_FIL_FIL(x) FIELD_PREP(AD7768_DIG_FIL_FIL_MSK, x) #define AD7768_DIG_FIL_DEC_MSK GENMASK(2, 0) #define AD7768_DIG_FIL_DEC_RATE(x) FIELD_PREP(AD7768_DIG_FIL_DEC_MSK, x) @@ -125,22 +127,20 @@ enum ad7768_mclk_div { AD7768_MCLK_DIV_2 }; =20 -enum ad7768_dec_rate { - AD7768_DEC_RATE_32 =3D 0, - AD7768_DEC_RATE_64 =3D 1, - AD7768_DEC_RATE_128 =3D 2, - AD7768_DEC_RATE_256 =3D 3, - AD7768_DEC_RATE_512 =3D 4, - AD7768_DEC_RATE_1024 =3D 5, - AD7768_DEC_RATE_8 =3D 9, - AD7768_DEC_RATE_16 =3D 10 +enum ad7768_filter_type { + AD7768_FILTER_SINC5, + AD7768_FILTER_SINC3, + AD7768_FILTER_WIDEBAND, + AD7768_FILTER_SINC3_REJ60, }; =20 -struct ad7768_clk_configuration { - enum ad7768_mclk_div mclk_div; - enum ad7768_dec_rate dec_rate; - unsigned int clk_div; - enum ad7768_pwrmode pwrmode; +enum ad7768_filter_regval { + AD7768_FILTER_REGVAL_SINC5 =3D 0, + AD7768_FILTER_REGVAL_SINC5_X8 =3D 1, + AD7768_FILTER_REGVAL_SINC5_X16 =3D 2, + AD7768_FILTER_REGVAL_SINC3 =3D 3, + AD7768_FILTER_REGVAL_WIDEBAND =3D 4, + AD7768_FILTER_REGVAL_SINC3_REJ60 =3D 11, }; =20 enum ad7768_scan_type { @@ -152,18 +152,39 @@ static const int ad7768_mclk_div_rates[4] =3D { 16, 8, 4, 2, }; =20 -static const struct ad7768_clk_configuration ad7768_clk_config[] =3D { - { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_8, 16, AD7768_FAST_MODE }, - { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_16, 32, AD7768_FAST_MODE }, - { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_32, 64, AD7768_FAST_MODE }, - { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_64, 128, AD7768_FAST_MODE }, - { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_128, 256, AD7768_FAST_MODE }, - { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_128, 512, AD7768_MED_MODE }, - { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_256, 1024, AD7768_MED_MODE }, - { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_512, 2048, AD7768_MED_MODE }, - { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_1024, 4096, AD7768_MED_MODE }, - { AD7768_MCLK_DIV_8, AD7768_DEC_RATE_1024, 8192, AD7768_MED_MODE }, - { AD7768_MCLK_DIV_16, AD7768_DEC_RATE_1024, 16384, AD7768_ECO_MODE }, +static const int ad7768_dec_rate_values[8] =3D { + 8, 16, 32, 64, 128, 256, 512, 1024, +}; + +/* Decimation Rate range for each filter type */ +static const int ad7768_dec_rate_range[][3] =3D { + [AD7768_FILTER_SINC5] =3D { 8, 8, 1024 }, + [AD7768_FILTER_SINC3] =3D { 32, 32, 163840 }, + [AD7768_FILTER_WIDEBAND] =3D { 32, 32, 1024 }, + [AD7768_FILTER_SINC3_REJ60] =3D { 32, 32, 163840 }, +}; + +/* + * The AD7768-1 supports three primary filter types: + * Sinc5, Sinc3, and Wideband. + * However, the filter register values can also encode additional paramete= rs + * such as decimation rates and 60Hz rejection. This utility array separat= es + * the filter type from these parameters. + */ +static const int ad7768_filter_regval_to_type[] =3D { + [AD7768_FILTER_REGVAL_SINC5] =3D AD7768_FILTER_SINC5, + [AD7768_FILTER_REGVAL_SINC5_X8] =3D AD7768_FILTER_SINC5, + [AD7768_FILTER_REGVAL_SINC5_X16] =3D AD7768_FILTER_SINC5, + [AD7768_FILTER_REGVAL_SINC3] =3D AD7768_FILTER_SINC3, + [AD7768_FILTER_REGVAL_WIDEBAND] =3D AD7768_FILTER_WIDEBAND, + [AD7768_FILTER_REGVAL_SINC3_REJ60] =3D AD7768_FILTER_SINC3_REJ60, +}; + +static const char * const ad7768_filter_enum[] =3D { + [AD7768_FILTER_SINC5] =3D "sinc5", + [AD7768_FILTER_SINC3] =3D "sinc3", + [AD7768_FILTER_WIDEBAND] =3D "wideband", + [AD7768_FILTER_SINC3_REJ60] =3D "sinc3+rej60" }; =20 static const struct iio_scan_type ad7768_scan_type[] =3D { @@ -182,13 +203,34 @@ static const struct iio_scan_type ad7768_scan_type[] = =3D { }, }; =20 +static int ad7768_get_filter_type_attr(struct iio_dev *dev, + const struct iio_chan_spec *chan); +static int ad7768_set_fil_type_attr(struct iio_dev *dev, + const struct iio_chan_spec *chan, unsigned int filter); + +static const struct iio_enum ad7768_filter_type_iio_enum =3D { + .items =3D ad7768_filter_enum, + .num_items =3D ARRAY_SIZE(ad7768_filter_enum), + .set =3D ad7768_set_fil_type_attr, + .get =3D ad7768_get_filter_type_attr, +}; + +static struct iio_chan_spec_ext_info ad7768_ext_info[] =3D { + IIO_ENUM("filter_type", IIO_SHARED_BY_ALL, &ad7768_filter_type_iio_enum), + IIO_ENUM_AVAILABLE("filter_type", IIO_SHARED_BY_ALL, &ad7768_filter_type_= iio_enum), + { } +}; + static const struct iio_chan_spec ad7768_channels[] =3D { { .type =3D IIO_VOLTAGE, .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW), - .info_mask_shared_by_type =3D BIT(IIO_CHAN_INFO_SCALE), + .info_mask_shared_by_type =3D BIT(IIO_CHAN_INFO_SCALE) | + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), + .info_mask_shared_by_type_available =3D BIT(IIO_CHAN_INFO_OVERSAMPLING_R= ATIO), .info_mask_shared_by_all =3D BIT(IIO_CHAN_INFO_SAMP_FREQ), .info_mask_shared_by_all_available =3D BIT(IIO_CHAN_INFO_SAMP_FREQ), + .ext_info =3D ad7768_ext_info, .indexed =3D 1, .channel =3D 0, .scan_index =3D 0, @@ -208,9 +250,12 @@ struct ad7768_state { struct clk *mclk; struct gpio_chip gpiochip; unsigned int mclk_freq; - unsigned int dec_rate; + unsigned int mclk_div; + unsigned int oversampling_ratio; + enum ad7768_filter_type filter_type; unsigned int samp_freq; - unsigned int samp_freq_avail[ARRAY_SIZE(ad7768_clk_config)]; + unsigned int samp_freq_avail[ARRAY_SIZE(ad7768_mclk_div_rates)]; + unsigned int samp_freq_avail_len; struct completion completion; struct iio_trigger *trig; struct gpio_desc *gpio_sync_in; @@ -317,11 +362,35 @@ static int ad7768_send_sync_pulse(struct ad7768_state= *st) =20 static void ad7768_fill_samp_freq_tbl(struct ad7768_state *st) { - int i; + int i, freq_filtered, len =3D 0; + + freq_filtered =3D DIV_ROUND_CLOSEST(st->mclk_freq, st->oversampling_ratio= ); + for (i =3D 0; i < ARRAY_SIZE(ad7768_mclk_div_rates); i++) { + st->samp_freq_avail[len] =3D DIV_ROUND_CLOSEST(freq_filtered, + ad7768_mclk_div_rates[i]); + /* Sampling frequency cannot be lower than the minimum of 50 SPS */ + if (st->samp_freq_avail[len] >=3D 50) + len++; + } + st->samp_freq_avail_len =3D len; +} + +static int ad7768_set_mclk_div(struct ad7768_state *st, unsigned int mclk_= div) +{ + unsigned int mclk_div_value; =20 - for (i =3D 0; i < ARRAY_SIZE(ad7768_clk_config); i++) - st->samp_freq_avail[i] =3D DIV_ROUND_CLOSEST(st->mclk_freq, - ad7768_clk_config[i].clk_div); + mclk_div_value =3D AD7768_PWR_MCLK_DIV(mclk_div); + /* + * Set power mode based on mclk_div value. + * ECO_MODE is only recommended for MCLK_DIV 16 + */ + mclk_div_value |=3D mclk_div > AD7768_MCLK_DIV_16 ? + AD7768_PWR_PWRMODE(AD7768_FAST_MODE) : + AD7768_PWR_PWRMODE(AD7768_ECO_MODE); + + return regmap_update_bits(st->regmap, AD7768_REG_POWER_CLOCK, + AD7768_PWR_MCLK_DIV_MSK | AD7768_PWR_PWRMODE_MSK, + mclk_div_value); } =20 static int ad7768_set_mode(struct ad7768_state *st, @@ -357,7 +426,7 @@ static int ad7768_scan_direct(struct iio_dev *indio_dev) * register provides 24-bit data, the precision is reduced by * right-shifting the read value by 8 bits. */ - if (st->dec_rate =3D=3D 8) + if (st->oversampling_ratio =3D=3D 8) readval >>=3D 8; =20 /* @@ -404,22 +473,110 @@ static int ad7768_reg_access(struct iio_dev *indio_d= ev, return ret; } =20 -static int ad7768_set_dig_fil(struct ad7768_state *st, - enum ad7768_dec_rate dec_rate) +static int ad7768_set_sinc3_dec_rate(struct ad7768_state *st, + unsigned int dec_rate) { - unsigned int mode; + unsigned int max_dec_rate; + u8 dec_rate_reg[2]; + u16 regval; int ret; =20 - if (dec_rate =3D=3D AD7768_DEC_RATE_8 || dec_rate =3D=3D AD7768_DEC_RATE_= 16) - mode =3D AD7768_DIG_FIL_FIL(dec_rate); - else - mode =3D AD7768_DIG_FIL_DEC_RATE(dec_rate); + /* + * Maximum dec_rate is limited by the MCLK_DIV value + * and by the ODR. The edge case is for MCLK_DIV =3D 2 + * ODR =3D 50 SPS. + * max_dec_rate <=3D MCLK / (2 * 50) + */ + max_dec_rate =3D st->mclk_freq / 100; + dec_rate =3D clamp_t(unsigned int, dec_rate, 32, max_dec_rate); + /* + * Calculate the equivalent value to sinc3 decimation ratio + * to be written on the SINC3_DEC_RATE register: + * Value =3D (DEC_RATE / 32) -1 + */ + dec_rate =3D DIV_ROUND_UP(dec_rate, 32) - 1; =20 - ret =3D regmap_write(st->regmap, AD7768_REG_DIGITAL_FILTER, mode); - if (ret < 0) + /* + * The SINC3_DEC_RATE value is a 13-bit value split across two + * registers: MSB [12:8] and LSB [7:0]. Prepare the 13-bit value using + * FIELD_PREP and store it with the right endianness in dec_rate_reg. + */ + regval =3D FIELD_PREP(GENMASK(12, 0), dec_rate); + put_unaligned_be16(regval, dec_rate_reg); + ret =3D regmap_bulk_write(st->regmap, AD7768_REG_SINC3_DEC_RATE_MSB, + dec_rate_reg, 2); + if (ret) + return ret; + + st->oversampling_ratio =3D (dec_rate + 1) * 32; + + return 0; +} + +static int ad7768_configure_dig_fil(struct iio_dev *dev, + enum ad7768_filter_type filter_type, + unsigned int dec_rate) +{ + struct ad7768_state *st =3D iio_priv(dev); + unsigned int dec_rate_idx, dig_filter_regval; + int ret; + + switch (filter_type) { + case AD7768_FILTER_SINC3: + dig_filter_regval =3D AD7768_DIG_FIL_FIL(AD7768_FILTER_REGVAL_SINC3); + break; + case AD7768_FILTER_SINC3_REJ60: + dig_filter_regval =3D AD7768_DIG_FIL_FIL(AD7768_FILTER_REGVAL_SINC3_REJ6= 0); + break; + case AD7768_FILTER_WIDEBAND: + /* Skip decimations 8 and 16, not supported by the wideband filter */ + dec_rate_idx =3D find_closest(dec_rate, &ad7768_dec_rate_values[2], + ARRAY_SIZE(ad7768_dec_rate_values) - 2); + dig_filter_regval =3D AD7768_DIG_FIL_FIL(AD7768_FILTER_REGVAL_WIDEBAND) | + AD7768_DIG_FIL_DEC_RATE(dec_rate_idx); + /* Correct the index offset */ + dec_rate_idx +=3D 2; + break; + case AD7768_FILTER_SINC5: + dec_rate_idx =3D find_closest(dec_rate, ad7768_dec_rate_values, + ARRAY_SIZE(ad7768_dec_rate_values)); + + /* + * Decimations 8 (idx 0) and 16 (idx 1) are set in the + * FILTER[6:4] field. The other decimations are set in the + * DEC_RATE[2:0] field, and the idx need to be offsetted by two. + */ + if (dec_rate_idx =3D=3D 0) + dig_filter_regval =3D AD7768_DIG_FIL_FIL(AD7768_FILTER_REGVAL_SINC5_X8); + else if (dec_rate_idx =3D=3D 1) + dig_filter_regval =3D AD7768_DIG_FIL_FIL(AD7768_FILTER_REGVAL_SINC5_X16= ); + else + dig_filter_regval =3D AD7768_DIG_FIL_FIL(AD7768_FILTER_REGVAL_SINC5) | + AD7768_DIG_FIL_DEC_RATE(dec_rate_idx - 2); + break; + } + + ret =3D regmap_write(st->regmap, AD7768_REG_DIGITAL_FILTER, dig_filter_re= gval); + if (ret) return ret; =20 - /* A sync-in pulse is required every time the filter dec rate changes */ + st->filter_type =3D filter_type; + /* + * The decimation for SINC3 filters are configured in different + * registers + */ + if (filter_type =3D=3D AD7768_FILTER_SINC3 || + filter_type =3D=3D AD7768_FILTER_SINC3_REJ60) { + ret =3D ad7768_set_sinc3_dec_rate(st, dec_rate); + if (ret) + return ret; + } else { + st->oversampling_ratio =3D ad7768_dec_rate_values[dec_rate_idx]; + } + + ad7768_fill_samp_freq_tbl(st); + + /* A sync-in pulse is required after every configuration change */ return ad7768_send_sync_pulse(st); } =20 @@ -542,43 +699,69 @@ static int ad7768_gpio_init(struct iio_dev *indio_dev) static int ad7768_set_freq(struct ad7768_state *st, unsigned int freq) { - unsigned int diff_new, diff_old, pwr_mode, i, idx; + unsigned int diff_new, diff_old, i, idx; int res, ret; =20 + freq =3D clamp_t(unsigned int, freq, 50, 1024000); diff_old =3D U32_MAX; idx =3D 0; =20 - res =3D DIV_ROUND_CLOSEST(st->mclk_freq, freq); + if (freq =3D=3D 0) + return -EINVAL; + + res =3D DIV_ROUND_CLOSEST(st->mclk_freq, freq * st->oversampling_ratio); =20 /* Find the closest match for the desired sampling frequency */ - for (i =3D 0; i < ARRAY_SIZE(ad7768_clk_config); i++) { - diff_new =3D abs(res - ad7768_clk_config[i].clk_div); + for (i =3D 0; i < ARRAY_SIZE(ad7768_mclk_div_rates); i++) { + diff_new =3D abs(res - ad7768_mclk_div_rates[i]); if (diff_new < diff_old) { diff_old =3D diff_new; idx =3D i; } } =20 - /* - * Set both the mclk_div and pwrmode with a single write to the - * POWER_CLOCK register - */ - pwr_mode =3D AD7768_PWR_MCLK_DIV(ad7768_clk_config[idx].mclk_div) | - AD7768_PWR_PWRMODE(ad7768_clk_config[idx].pwrmode); - ret =3D regmap_write(st->regmap, AD7768_REG_POWER_CLOCK, pwr_mode); - if (ret < 0) + /* Set both the mclk_div and pwrmode */ + ret =3D ad7768_set_mclk_div(st, idx); + if (ret) return ret; =20 - ret =3D ad7768_set_dig_fil(st, ad7768_clk_config[idx].dec_rate); - if (ret < 0) + st->samp_freq =3D DIV_ROUND_CLOSEST(st->mclk_freq, + ad7768_mclk_div_rates[idx] * st->oversampling_ratio); + + /* A sync-in pulse is required after every configuration change */ + return ad7768_send_sync_pulse(st); +} + +static int ad7768_set_fil_type_attr(struct iio_dev *dev, + const struct iio_chan_spec *chan, + unsigned int filter) +{ + struct ad7768_state *st =3D iio_priv(dev); + int ret; + + ret =3D ad7768_configure_dig_fil(dev, filter, st->oversampling_ratio); + if (ret) return ret; =20 - st->dec_rate =3D ad7768_clk_config[idx].clk_div / - ad7768_mclk_div_rates[ad7768_clk_config[idx].mclk_div]; - st->samp_freq =3D DIV_ROUND_CLOSEST(st->mclk_freq, - ad7768_clk_config[idx].clk_div); + /* Update sampling frequency */ + return ad7768_set_freq(st, st->samp_freq); +} =20 - return 0; +static int ad7768_get_filter_type_attr(struct iio_dev *dev, + const struct iio_chan_spec *chan) +{ + struct ad7768_state *st =3D iio_priv(dev); + int ret; + unsigned int mode; + + ret =3D regmap_read(st->regmap, AD7768_REG_DIGITAL_FILTER, &mode); + if (ret) + return ret; + + mode =3D FIELD_GET(AD7768_DIG_FIL_FIL_MSK, mode); + + /* From the register value, get the corresponding filter type */ + return ad7768_filter_regval_to_type[mode]; } =20 static int ad7768_read_raw(struct iio_dev *indio_dev, @@ -620,6 +803,11 @@ static int ad7768_read_raw(struct iio_dev *indio_dev, case IIO_CHAN_INFO_SAMP_FREQ: *val =3D st->samp_freq; =20 + return IIO_VAL_INT; + + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: + *val =3D st->oversampling_ratio; + return IIO_VAL_INT; } =20 @@ -634,9 +822,13 @@ static int ad7768_read_avail(struct iio_dev *indio_dev, struct ad7768_state *st =3D iio_priv(indio_dev); =20 switch (info) { + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: + *vals =3D (int *)ad7768_dec_rate_range[st->filter_type]; + *type =3D IIO_VAL_INT; + return IIO_AVAIL_RANGE; case IIO_CHAN_INFO_SAMP_FREQ: *vals =3D (int *)st->samp_freq_avail; - *length =3D ARRAY_SIZE(ad7768_clk_config); + *length =3D st->samp_freq_avail_len; *type =3D IIO_VAL_INT; return IIO_AVAIL_LIST; default: @@ -644,20 +836,44 @@ static int ad7768_read_avail(struct iio_dev *indio_de= v, } } =20 -static int ad7768_write_raw(struct iio_dev *indio_dev, - struct iio_chan_spec const *chan, - int val, int val2, long info) +static int __ad7768_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int val, int val2, long info) { struct ad7768_state *st =3D iio_priv(indio_dev); + int ret; =20 switch (info) { case IIO_CHAN_INFO_SAMP_FREQ: return ad7768_set_freq(st, val); + + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: + ret =3D ad7768_configure_dig_fil(indio_dev, st->filter_type, val); + if (ret) + return ret; + + /* Update sampling frequency */ + return ad7768_set_freq(st, st->samp_freq); default: return -EINVAL; } } =20 +static int ad7768_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int val, int val2, long info) +{ + int ret; + + if (!iio_device_claim_direct(indio_dev)) + return -EBUSY; + + ret =3D __ad7768_write_raw(indio_dev, chan, val, val2, info); + iio_device_release_direct(indio_dev); + + return ret; +} + static int ad7768_read_label(struct iio_dev *indio_dev, const struct iio_chan_spec *chan, char *label) { @@ -671,7 +887,7 @@ static int ad7768_get_current_scan_type(const struct ii= o_dev *indio_dev, { struct ad7768_state *st =3D iio_priv(indio_dev); =20 - return st->dec_rate =3D=3D 8 ? AD7768_SCAN_TYPE_HIGH_SPEED : + return st->oversampling_ratio =3D=3D 8 ? AD7768_SCAN_TYPE_HIGH_SPEED : AD7768_SCAN_TYPE_NORMAL; } =20 @@ -825,6 +1041,14 @@ static int ad7768_setup(struct iio_dev *indio_dev) return ret; } =20 + /* + * Set Default Digital Filter configuration: + * SINC5 filter with x32 Decimation rate + */ + ret =3D ad7768_configure_dig_fil(indio_dev, AD7768_FILTER_SINC5, 32); + if (ret) + return ret; + /* Set the default sampling frequency to 32000 kSPS */ return ad7768_set_freq(st, 32000); } @@ -1172,7 +1396,6 @@ static int ad7768_probe(struct spi_device *spi) return PTR_ERR(st->mclk); =20 st->mclk_freq =3D clk_get_rate(st->mclk); - ad7768_fill_samp_freq_tbl(st); =20 indio_dev->channels =3D ad7768_channels; indio_dev->num_channels =3D ARRAY_SIZE(ad7768_channels); --=20 2.34.1 From nobody Fri Dec 19 20:10:29 2025 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 958D6200A3; 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Sun, 27 Apr 2025 20:14:35 -0400 From: Jonathan Santos To: , , , CC: Jonathan Santos , , , , , , , , , , , , , , , Subject: [PATCH v6 11/11] iio: adc: ad7768-1: add low pass -3dB cutoff attribute Date: Sun, 27 Apr 2025 21:14:31 -0300 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-GUID: YjB5Dyu6SRonN2jxxWurk39tJ3h__fwO X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNDI3MDIwMiBTYWx0ZWRfXxdqgZTIrRRM/ njO/MI+OKNZ4zD3hBmkJhmJqbGLTh/YBbwqZ/irlRhMXofoHAe5mPvTwTdhvqKzp7DixI+JE+HH U1MFRo9MU706wjeDn9V6Wr4NJYDlDCbBKZeR+cgU1Tmcfvb+2XIqmC8xkeIhnZvGZk7rDLKMTFd CickwaRlxPbWxkO0xKAxmH/yeFBP/y6J7JJG7gs89l3cN57NKoPnY+zy8p5VbLq9tuQmzR5ZtQ0 mbXbX6Ieo1J6PJJ/8J4dWt5vEk5Y9drlSi8/VRPL0gcYieQOw/ozFefH/cmla8JRd6IjLLFBR+Y oq3YtSRNBWAMaTWJzjPLswwNwpfEkEXTQ0uKpgI0a8kIxbfz2qy7Iz9pZERxLuBSzkttu/8+CFp YxKJqV7B+ovpZf6RKtKy8GMtIAq2UmyU+8sOWVBbubi/zLetfMzxc6Keib2WaMcARwvz/i/Z X-Proofpoint-ORIG-GUID: YjB5Dyu6SRonN2jxxWurk39tJ3h__fwO X-Authority-Analysis: v=2.4 cv=HPzDFptv c=1 sm=1 tr=0 ts=680ec87c cx=c_pps a=PpDZqlmH/M8setHirZLBMw==:117 a=PpDZqlmH/M8setHirZLBMw==:17 a=XR8D0OoHHMoA:10 a=gAnH3GRIAAAA:8 a=IpJZQVW2AAAA:8 a=ZkoTrUv0hqWFqrPu6skA:9 a=IawgGOuG5U0WyFbmm1f5:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-04-27_08,2025-04-24_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 adultscore=0 suspectscore=0 impostorscore=0 phishscore=0 mlxscore=0 malwarescore=0 priorityscore=1501 bulkscore=0 lowpriorityscore=0 clxscore=1015 spamscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2504270202 Content-Type: text/plain; charset="utf-8" Ad7768-1 has a different -3db frequency multiplier depending on the filter type configured. The cutoff frequency also varies according to the current ODR. Add a readonly low pass -3dB frequency cutoff attribute to clarify to the user which bandwidth is being allowed depending on the filter configurations. Reviewed-by: Marcelo Schmitt Reviewed-by: David Lechner Signed-off-by: Jonathan Santos --- v6 Changes: * None v5 Changes: * None v4 Changes: * None v3 Changes: * None v2 Changes: * New patch in v2. --- drivers/iio/adc/ad7768-1.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/drivers/iio/adc/ad7768-1.c b/drivers/iio/adc/ad7768-1.c index e2b8f12260a5..8734859fc24e 100644 --- a/drivers/iio/adc/ad7768-1.c +++ b/drivers/iio/adc/ad7768-1.c @@ -148,6 +148,17 @@ enum ad7768_scan_type { AD7768_SCAN_TYPE_HIGH_SPEED, }; =20 +/* + * -3dB cutoff frequency multipliers (relative to ODR) for + * each filter type. Values are multiplied by 1000. + */ +static const int ad7768_filter_3db_odr_multiplier[] =3D { + [AD7768_FILTER_SINC5] =3D 204, + [AD7768_FILTER_SINC3] =3D 262, + [AD7768_FILTER_SINC3_REJ60] =3D 262, + [AD7768_FILTER_WIDEBAND] =3D 433, +}; + static const int ad7768_mclk_div_rates[4] =3D { 16, 8, 4, 2, }; @@ -226,7 +237,8 @@ static const struct iio_chan_spec ad7768_channels[] =3D= { .type =3D IIO_VOLTAGE, .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW), .info_mask_shared_by_type =3D BIT(IIO_CHAN_INFO_SCALE) | - BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO) | + BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), .info_mask_shared_by_type_available =3D BIT(IIO_CHAN_INFO_OVERSAMPLING_R= ATIO), .info_mask_shared_by_all =3D BIT(IIO_CHAN_INFO_SAMP_FREQ), .info_mask_shared_by_all_available =3D BIT(IIO_CHAN_INFO_SAMP_FREQ), @@ -770,7 +782,7 @@ static int ad7768_read_raw(struct iio_dev *indio_dev, { struct ad7768_state *st =3D iio_priv(indio_dev); const struct iio_scan_type *scan_type; - int scale_uv, ret; + int scale_uv, ret, temp; =20 scan_type =3D iio_get_current_scan_type(indio_dev, chan); if (IS_ERR(scan_type)) @@ -808,6 +820,12 @@ static int ad7768_read_raw(struct iio_dev *indio_dev, case IIO_CHAN_INFO_OVERSAMPLING_RATIO: *val =3D st->oversampling_ratio; =20 + return IIO_VAL_INT; + + case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: + temp =3D st->samp_freq * ad7768_filter_3db_odr_multiplier[st->filter_typ= e]; + *val =3D DIV_ROUND_CLOSEST(temp, 1000); + return IIO_VAL_INT; } =20 --=20 2.34.1