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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Apr 2025 22:44:18.3452 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d17c70f3-c0ee-40e0-87f4-08dd81260d08 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B36D.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5890 Content-Type: text/plain; charset="utf-8" Smart Data Cache Injection (SDCI) is a mechanism that enables direct insertion of data from I/O devices into the L3 cache. By directly caching data from I/O devices rather than first storing the I/O data in DRAM, SDCI reduces demands on DRAM bandwidth and reduces latency to the processor consuming the I/O data. The SDCIAE (SDCI Allocation Enforcement) PQE feature allows system software to control the portion of the L3 cache used for SDCI. When enabled, SDCIAE forces all SDCI lines to be placed into the L3 cache partitions identified by the highest-supported L3_MASK_n register, where n is the maximum supported CLOSID. Add CPUID feature bit that can be used to configure SDCIAE. The feature details are documented in APM listed below [1]. [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming Publication # 24593 Revision 3.41 section 19.4.7 L3 Smart Data Cache Injection Allocation Enforcement (SDCIAE) Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537 Signed-off-by: Babu Moger --- v4: Resolved a minor conflict in cpufeatures.h. v3: No changes. v2: Added dependancy on X86_FEATURE_CAT_L3 Removed the "" in CPU feature definition. Minor text changes. --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/cpuid-deps.c | 1 + arch/x86/kernel/cpu/scattered.c | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index 6c2c152d8a67..8dfbea91bef6 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -481,6 +481,7 @@ #define X86_FEATURE_AMD_HETEROGENEOUS_CORES (21*32 + 6) /* Heterogeneous C= ore Topology */ #define X86_FEATURE_AMD_WORKLOAD_CLASS (21*32 + 7) /* Workload Classificat= ion */ #define X86_FEATURE_PREFER_YMM (21*32 + 8) /* Avoid ZMM registers due to = downclocking */ +#define X86_FEATURE_SDCIAE (21*32 + 9) /* L3 Smart Data Cache Injection A= llocation Enforcement */ =20 /* * BUG word(s) diff --git a/arch/x86/kernel/cpu/cpuid-deps.c b/arch/x86/kernel/cpu/cpuid-d= eps.c index 94c062cddfa4..24ff4a98d204 100644 --- a/arch/x86/kernel/cpu/cpuid-deps.c +++ b/arch/x86/kernel/cpu/cpuid-deps.c @@ -71,6 +71,7 @@ static const struct cpuid_dep cpuid_deps[] =3D { { X86_FEATURE_CQM_MBM_LOCAL, X86_FEATURE_CQM_LLC }, { X86_FEATURE_BMEC, X86_FEATURE_CQM_MBM_TOTAL }, { X86_FEATURE_BMEC, X86_FEATURE_CQM_MBM_LOCAL }, + { X86_FEATURE_SDCIAE, X86_FEATURE_CAT_L3 }, { X86_FEATURE_AVX512_BF16, X86_FEATURE_AVX512VL }, { X86_FEATURE_AVX512_FP16, X86_FEATURE_AVX512BW }, { X86_FEATURE_ENQCMD, X86_FEATURE_XSAVES }, diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattere= d.c index 16f3ca30626a..d18a7ce16388 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -49,6 +49,7 @@ static const struct cpuid_bit cpuid_bits[] =3D { { X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 }, { X86_FEATURE_SMBA, CPUID_EBX, 2, 0x80000020, 0 }, { X86_FEATURE_BMEC, CPUID_EBX, 3, 0x80000020, 0 }, + { X86_FEATURE_SDCIAE, CPUID_EBX, 6, 0x80000020, 0 }, { X86_FEATURE_AMD_WORKLOAD_CLASS, CPUID_EAX, 22, 0x80000021, 0 }, { X86_FEATURE_PERFMON_V2, CPUID_EAX, 0, 0x80000022, 0 }, { X86_FEATURE_AMD_LBR_V2, CPUID_EAX, 1, 0x80000022, 0 }, --=20 2.34.1 From nobody Wed Dec 17 03:13:27 2025 Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2075.outbound.protection.outlook.com [40.107.237.75]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4FFD422A80D; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Apr 2025 22:44:26.5033 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 82960449-8af8-441c-6eb0-08dd812611e5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B36D.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6389 Content-Type: text/plain; charset="utf-8" Add the command line options to enable or disable the new resctrl feature L3 Smart Data Cache Injection Allocation Enforcement (SDCIAE). Signed-off-by: Babu Moger --- v4: No changes. v3: No changes. v2: No changes. --- Documentation/admin-guide/kernel-parameters.txt | 2 +- arch/x86/kernel/cpu/resctrl/core.c | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentatio= n/admin-guide/kernel-parameters.txt index 76e538c77e31..5e5abc270f91 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -5991,7 +5991,7 @@ rdt=3D [HW,X86,RDT] Turn on/off individual RDT features. List is: cmt, mbmtotal, mbmlocal, l3cat, l3cdp, l2cat, l2cdp, - mba, smba, bmec. + mba, smba, bmec, sdciae. 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Apr 2025 22:44:34.7804 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 76af3e2b-08e8-4225-157a-08dd812616d4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B370.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN7PPF9507C739C Content-Type: text/plain; charset="utf-8" Data from I/O devices can be inserted directly into L3 cache. This reduces demands on DRAM bandwidth and reduces latency to the processor consuming the I/O data. Introduce cache resource property "io_alloc_capable" that an architecture can set if a portion of the L3 cache can be allocated for I/O traffic. Set this property on x86 systems that support SDCIAE (L3 Smart Data Cache Injection Allocation Enforcement). Signed-off-by: Babu Moger --- v4: Updated the commit message and code comment based on feedback. v3: Rewrote commit log. Changed the text to bit generic than the AMD specif= ic. Renamed the rdt_get_sdciae_alloc_cfg() to rdt_set_io_alloc_capable(). Removed leftover comment from v2. v2: Changed sdciae_capable to io_alloc_capable to make it generic feature. Also moved the io_alloc_capable in struct resctrl_cache. --- arch/x86/kernel/cpu/resctrl/core.c | 7 +++++++ include/linux/resctrl.h | 3 +++ 2 files changed, 10 insertions(+) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index 422083dc4651..c478f591b7c1 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -292,6 +292,11 @@ static void rdt_get_cdp_config(int level) rdt_resources_all[level].r_resctrl.cdp_capable =3D true; } =20 +static void rdt_set_io_alloc_capable(struct rdt_resource *r) +{ + r->cache.io_alloc_capable =3D true; +} + static void rdt_get_cdp_l3_config(void) { rdt_get_cdp_config(RDT_RESOURCE_L3); @@ -858,6 +863,8 @@ static __init bool get_rdt_alloc_resources(void) rdt_get_cache_alloc_cfg(1, r); if (rdt_cpu_has(X86_FEATURE_CDP_L3)) rdt_get_cdp_l3_config(); + if (rdt_cpu_has(X86_FEATURE_SDCIAE)) + rdt_set_io_alloc_capable(r); ret =3D true; } if (rdt_cpu_has(X86_FEATURE_CAT_L2)) { diff --git a/include/linux/resctrl.h b/include/linux/resctrl.h index 880351ca3dfc..dd09bb9a173b 100644 --- a/include/linux/resctrl.h +++ b/include/linux/resctrl.h @@ -177,6 +177,8 @@ struct rdt_mon_domain { * @arch_has_sparse_bitmasks: True if a bitmask like f00f is valid. * @arch_has_per_cpu_cfg: True if QOS_CFG register for this cache * level has CPU scope. + * @io_alloc_capable: True if portion of the cache can be allocated + * for I/O traffic. */ struct resctrl_cache { unsigned int cbm_len; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Apr 2025 22:44:42.7711 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 97f1ae64-4f5e-4887-8ce5-08dd81261b97 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B372.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9283 Content-Type: text/plain; charset="utf-8" "io_alloc" enables direct insertion of data from I/O devices into the L3 cache. On AMD, "io_alloc" feature is backed by L3 Smart Data Cache Injection Allocation Enforcement (SDCIAE). Change SDCIAE state by setting (to enable) or clearing (to disable) bit 1 of MSR L3_QOS_EXT_CFG on all logical processors within the cache domain. Introduce architecture-specific handlers to enable and disable the feature. The SDCIAE feature details are available in APM listed below [1]. [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming Publication # 24593 Revision 3.41 section 19.4.7 L3 Smart Data Cache Injection Allocation Enforcement (SDCIAE) Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537 Signed-off-by: Babu Moger --- v4: Updated the commit log to address the feedback. v3: Passed the struct rdt_resource to resctrl_arch_get_io_alloc_enabled() i= nstead of resource id. Renamed the _resctrl_io_alloc_enable() to _resctrl_sdciae_enable() as i= t is arch specific. Changed the return to void in _resctrl_sdciae_enable() instead of int. Added more context in commit log and fixed few typos. v2: Renamed the functions to simplify the code. Renamed sdciae_capable to io_alloc_capable. Changed the name of few arch functions similar to ABMC series. resctrl_arch_get_io_alloc_enabled() resctrl_arch_io_alloc_enable() --- arch/x86/include/asm/msr-index.h | 1 + arch/x86/kernel/cpu/resctrl/internal.h | 10 ++++++++ arch/x86/kernel/cpu/resctrl/rdtgroup.c | 32 ++++++++++++++++++++++++++ include/linux/resctrl.h | 9 ++++++++ 4 files changed, 52 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-in= dex.h index e6134ef2263d..3970e0b16e47 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -1203,6 +1203,7 @@ /* - AMD: */ #define MSR_IA32_MBA_BW_BASE 0xc0000200 #define MSR_IA32_SMBA_BW_BASE 0xc0000280 +#define MSR_IA32_L3_QOS_EXT_CFG 0xc00003ff #define MSR_IA32_EVT_CFG_BASE 0xc0000400 =20 /* AMD-V MSRs */ diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index eaae99602b61..6ead222904fe 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -32,6 +32,9 @@ */ #define MBM_CNTR_WIDTH_OFFSET_MAX (62 - MBM_CNTR_WIDTH_BASE) =20 +/* Setting bit 1 in L3_QOS_EXT_CFG enables the SDCIAE feature. */ +#define SDCIAE_ENABLE_BIT 1 + /** * cpumask_any_housekeeping() - Choose any CPU in @mask, preferring those = that * aren't marked nohz_full @@ -381,6 +384,7 @@ struct msr_param { * @mon_scale: cqm counter * mon_scale =3D occupancy in bytes * @mbm_width: Monitor width, to detect and correct for overflow. * @cdp_enabled: CDP state of this resource + * @sdciae_enabled: SDCIAE feature is enabled * * Members of this structure are either private to the architecture * e.g. mbm_width, or accessed via helpers that provide abstraction. e.g. @@ -394,6 +398,7 @@ struct rdt_hw_resource { unsigned int mon_scale; unsigned int mbm_width; bool cdp_enabled; + bool sdciae_enabled; }; =20 static inline struct rdt_hw_resource *resctrl_to_arch_res(struct rdt_resou= rce *r) @@ -420,6 +425,11 @@ static inline bool resctrl_arch_get_cdp_enabled(enum r= esctrl_res_level l) =20 int resctrl_arch_set_cdp_enabled(enum resctrl_res_level l, bool enable); =20 +static inline bool resctrl_arch_get_io_alloc_enabled(struct rdt_resource *= r) +{ + return resctrl_to_arch_res(r)->sdciae_enabled; +} + void arch_mon_domain_online(struct rdt_resource *r, struct rdt_mon_domain = *d); =20 /* CPUID.(EAX=3D10H, ECX=3DResID=3D1).EAX */ diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 93ec829015f1..85796a186374 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1845,6 +1845,38 @@ static ssize_t mbm_local_bytes_config_write(struct k= ernfs_open_file *of, return ret ?: nbytes; } =20 +static void resctrl_sdciae_set_one_amd(void *arg) +{ + bool *enable =3D arg; + + if (*enable) + msr_set_bit(MSR_IA32_L3_QOS_EXT_CFG, SDCIAE_ENABLE_BIT); + else + msr_clear_bit(MSR_IA32_L3_QOS_EXT_CFG, SDCIAE_ENABLE_BIT); +} + +static void _resctrl_sdciae_enable(struct rdt_resource *r, bool enable) +{ + struct rdt_ctrl_domain *d; + + /* Update L3_QOS_EXT_CFG MSR on all the CPUs in all domains */ + list_for_each_entry(d, &r->ctrl_domains, hdr.list) + on_each_cpu_mask(&d->hdr.cpu_mask, resctrl_sdciae_set_one_amd, &enable, = 1); +} + +int resctrl_arch_io_alloc_enable(struct rdt_resource *r, bool enable) +{ + struct rdt_hw_resource *hw_res =3D resctrl_to_arch_res(r); + + if (hw_res->r_resctrl.cache.io_alloc_capable && + hw_res->sdciae_enabled !=3D enable) { + _resctrl_sdciae_enable(r, enable); + hw_res->sdciae_enabled =3D enable; + } + + return 0; +} + /* rdtgroup information files for one cache resource. */ static struct rftype res_common_files[] =3D { { diff --git a/include/linux/resctrl.h b/include/linux/resctrl.h index dd09bb9a173b..92e242c13719 100644 --- a/include/linux/resctrl.h +++ b/include/linux/resctrl.h @@ -514,6 +514,15 @@ void resctrl_arch_reset_rmid_all(struct rdt_resource *= r, struct rdt_mon_domain * */ void resctrl_arch_reset_all_ctrls(struct rdt_resource *r); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Apr 2025 22:44:52.5939 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a1420f62-4e03-484c-20d3-08dd81262172 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B36E.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB6706 Content-Type: text/plain; charset="utf-8" The io_alloc feature in resctrl is a mechanism that enables direct insertion of data from I/O devices into the L3 cache. On AMD systems, io_alloc feature is backed by SDCIAE (L3 Smart Data Cache Injection Allocation Enforcement). When enabled, SDCIAE forces all SDCI lines to be placed into the L3 cache partitions identified by the highest-supported L3_MASK_n register as reported by CPUID Fn0000_0010_EDX_x1.MAX_COS. For example, if MAX_COS=3D15, SDCI lines will be allocated into the L3 cache partitions determined by the bitmask in the L3_MASK_15 register. When CDP is enabled, io_alloc routes I/O traffic using the highest CLOSID allocated for the instruction cache (L3CODE). Introduce user interface to enable/disable "io_alloc" feature. Signed-off-by: Babu Moger --- v4: Updated the change log. Updated the user doc. The "io_alloc" interface will report "enabled/disabled/not supported". Updated resctrl_io_alloc_closid_get() to verify the max closid availabi= lity. Updated the documentation for "shareable_bits" and "bit_usage". Introduced io_alloc_init() to initialize fflags. Printed the group name when io_alloc enablement fails. NOTE: io_alloc is about specific CLOS. rdt_bit_usage_show() is not desi= gned handle bit_usage for specific CLOS. Its about overall system. So, we ca= nnot really tell the user which CLOS is shared across both hardware and soft= ware. We need to discuss this. v3: Rewrote the change to make it generic. Rewrote the documentation in resctrl.rst to be generic and added AMD feature details in the end. Added the check to verify if MAX CLOSID availability on the system. Added CDP check to make sure io_alloc is configured in CDP_CODE. Added resctrl_io_alloc_closid_free() to free the io_alloc CLOSID. Added errors in few cases when CLOSID allocation fails. Fixes splat reported when info/L3/bit_usage is accesed when io_alloc is enabled. https://lore.kernel.org/lkml/SJ1PR11MB60837B532254E7B23BC27E84FC052@SJ1= PR11MB6083.namprd11.prod.outlook.com/ v2: Renamed the feature to "io_alloc". Added generic texts for the feature in commit log and resctrl.rst doc. Added resctrl_io_alloc_init_cat() to initialize io_alloc to default values when enabled. Fixed io_alloc show functinality to display only on L3 resource. --- Documentation/arch/x86/resctrl.rst | 34 +++++ arch/x86/kernel/cpu/resctrl/rdtgroup.c | 185 ++++++++++++++++++++++++- 2 files changed, 218 insertions(+), 1 deletion(-) diff --git a/Documentation/arch/x86/resctrl.rst b/Documentation/arch/x86/re= sctrl.rst index 6768fc1fad16..7672c5c52c1a 100644 --- a/Documentation/arch/x86/resctrl.rst +++ b/Documentation/arch/x86/resctrl.rst @@ -95,6 +95,11 @@ related to allocation: some platforms support devices that have their own settings for cache use which can over-ride these bits. + + When the "io_alloc" feature is enabled, a portion of the cache + is reserved for shared use between hardware and software. Refer + to "bit_usage" to see which portion is allocated for this purpose. + "bit_usage": Annotated capacity bitmasks showing how all instances of the resource are used. The legend is: @@ -135,6 +140,35 @@ related to allocation: "1": Non-contiguous 1s value in CBM is supported. =20 +"io_alloc": + The "io_alloc" enables system software to configure the portion + of the L3 cache allocated for I/O traffic. + + The feature routes the I/O traffic via specific CLOSID reserved + for io_alloc feature. By configuring the CBM (Capacity Bit Mask) + for the CLOSID, users can control the L3 portions available for + I/0 traffic. The reserved CLOSID will be excluded for group creation. + + The interface provides a means to query the status of feature support. + + Example:: + + # cat /sys/fs/resctrl/info/L3/io_alloc + disabled + + Feature can be enabled/disabled by writing to the interface. + Example:: + + # echo 1 > /sys/fs/resctrl/info/L3/io_alloc + # cat /sys/fs/resctrl/info/L3/io_alloc + enabled + + On AMD systems, the io_alloc feature is supported by the L3 Smart + Data Cache Injection Allocation Enforcement (SDCIAE). The CLOSID for + io_alloc is determined by the highest CLOSID supported by the resource. + When CDP is enabled, io_alloc routes I/O traffic using the highest + CLOSID allocated for the instruction cache (L3CODE). + Memory bandwidth(MB) subdirectory contains the following files with respect to allocation: =20 diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 85796a186374..d53a2068cde4 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -68,6 +68,7 @@ static char last_cmd_status_buf[512]; =20 static int rdtgroup_setup_root(struct rdt_fs_context *ctx); static void rdtgroup_destroy_root(void); +static int rdtgroup_init_cat(struct resctrl_schema *s, u32 closid); =20 struct dentry *debugfs_resctrl; =20 @@ -199,6 +200,19 @@ void closid_free(int closid) __set_bit(closid, &closid_free_map); } =20 +static int resctrl_io_alloc_closid_alloc(u32 io_alloc_closid) +{ + if (__test_and_clear_bit(io_alloc_closid, &closid_free_map)) + return io_alloc_closid; + else + return -ENOSPC; +} + +static void resctrl_io_alloc_closid_free(u32 io_alloc_closid) +{ + closid_free(io_alloc_closid); +} + /** * closid_allocated - test if provided closid is in use * @closid: closid to be tested @@ -1033,6 +1047,31 @@ static int rdt_shareable_bits_show(struct kernfs_ope= n_file *of, return 0; } =20 +/* + * resctrl_io_alloc_closid_get - io_alloc feature uses max CLOSID to route + * the IO traffic. Get the max CLOSID and verify if the CLOSID is availabl= e. + * + * The total number of CLOSIDs is determined in closid_init(), based on t= he + * minimum supported across all resources. If CDP (Code Data Prioritizatio= n) + * is enabled, the number of CLOSIDs is halved. The final value is returned + * by closids_supported() and stored in s->num_closid for each resource. + * Make sure this value aligns with the maximum CLOSID supported by the + * respective resource. + */ +static int resctrl_io_alloc_closid_get(struct rdt_resource *r, + struct resctrl_schema *s) +{ + int num_closids =3D closids_supported(); + + if (resctrl_arch_get_cdp_enabled(r->rid)) + num_closids *=3D 2; + + if (num_closids !=3D resctrl_arch_get_num_closid(r)) + return -ENOSPC; + else + return s->num_closid - 1; +} + /* * rdt_bit_usage_show - Display current usage of resources * @@ -1076,9 +1115,20 @@ static int rdt_bit_usage_show(struct kernfs_open_fil= e *of, for (i =3D 0; i < closids_supported(); i++) { if (!closid_allocated(i)) continue; + /* + * If io_alloc is enabled, the CLOSID will be + * allocated but will not be associated with any + * groups. The region is available for sharing with + * io_alloc feature as well as resctrl groups. + */ + if (i =3D=3D resctrl_io_alloc_closid_get(r, s) && + resctrl_arch_get_io_alloc_enabled(r)) + mode =3D RDT_MODE_SHAREABLE; + else + mode =3D rdtgroup_mode_by_closid(i); + ctrl_val =3D resctrl_arch_get_config(r, dom, i, s->conf_type); - mode =3D rdtgroup_mode_by_closid(i); switch (mode) { case RDT_MODE_SHAREABLE: sw_shareable |=3D ctrl_val; @@ -1877,6 +1927,121 @@ int resctrl_arch_io_alloc_enable(struct rdt_resourc= e *r, bool enable) return 0; } =20 +static int resctrl_io_alloc_show(struct kernfs_open_file *of, + struct seq_file *seq, void *v) +{ + struct resctrl_schema *s =3D rdt_kn_parent_priv(of->kn); + struct rdt_resource *r =3D s->res; + + if (r->cache.io_alloc_capable && !(s->conf_type =3D=3D CDP_DATA)) { + if (resctrl_arch_get_io_alloc_enabled(r)) + seq_puts(seq, "enabled\n"); + else + seq_puts(seq, "disabled\n"); + } else { + seq_puts(seq, "not supported\n"); + } + + return 0; +} + +/* + * Initialize io_alloc CLOSID cache resource with default CBM values. + */ +static int resctrl_io_alloc_init_cat(struct rdt_resource *r, + struct resctrl_schema *s, u32 closid) +{ + int ret; + + rdt_staged_configs_clear(); + + ret =3D rdtgroup_init_cat(s, closid); + if (ret < 0) + goto out_init_cat; + + ret =3D resctrl_arch_update_domains(r, closid); + +out_init_cat: + rdt_staged_configs_clear(); + return ret; +} + +static const char *rdtgroup_name_by_closid(int closid) +{ + struct rdtgroup *rdtgrp; + + list_for_each_entry(rdtgrp, &rdt_all_groups, rdtgroup_list) { + if (rdtgrp->closid =3D=3D closid) + return rdtgrp->kn->name; + } + + return NULL; +} + +static ssize_t resctrl_io_alloc_write(struct kernfs_open_file *of, char *b= uf, + size_t nbytes, loff_t off) +{ + struct resctrl_schema *s =3D rdt_kn_parent_priv(of->kn); + struct rdt_resource *r =3D s->res; + char const *grp_name; + u32 io_alloc_closid; + bool enable; + int ret; + + ret =3D kstrtobool(buf, &enable); + if (ret) + return ret; + + cpus_read_lock(); + mutex_lock(&rdtgroup_mutex); + + rdt_last_cmd_clear(); + + if (!r->cache.io_alloc_capable || s->conf_type =3D=3D CDP_DATA) { + rdt_last_cmd_puts("io_alloc feature is not supported on the resource\n"); + ret =3D -ENODEV; + goto out_io_alloc; + } + + io_alloc_closid =3D resctrl_io_alloc_closid_get(r, s); + if (io_alloc_closid < 0) { + rdt_last_cmd_puts("Max CLOSID to support io_alloc is not available\n"); + ret =3D -EINVAL; + goto out_io_alloc; + } + + if (resctrl_arch_get_io_alloc_enabled(r) !=3D enable) { + if (enable) { + ret =3D resctrl_io_alloc_closid_alloc(io_alloc_closid); + if (ret < 0) { + grp_name =3D rdtgroup_name_by_closid(io_alloc_closid); + rdt_last_cmd_printf("CLOSID for io_alloc is used by %s group\n", + grp_name ? grp_name : "another"); + ret =3D -EINVAL; + goto out_io_alloc; + } + + ret =3D resctrl_io_alloc_init_cat(r, s, io_alloc_closid); + if (ret) { + rdt_last_cmd_puts("Failed to initialize io_alloc allocations\n"); + resctrl_io_alloc_closid_free(io_alloc_closid); + goto out_io_alloc; + } + + } else { + resctrl_io_alloc_closid_free(io_alloc_closid); + } + + ret =3D resctrl_arch_io_alloc_enable(r, enable); + } + +out_io_alloc: + mutex_unlock(&rdtgroup_mutex); + cpus_read_unlock(); + + return ret ?: nbytes; +} + /* rdtgroup information files for one cache resource. */ static struct rftype res_common_files[] =3D { { @@ -2029,6 +2194,13 @@ static struct rftype res_common_files[] =3D { .seq_show =3D rdtgroup_schemata_show, .fflags =3D RFTYPE_CTRL_BASE, }, + { + .name =3D "io_alloc", + .mode =3D 0644, + .kf_ops =3D &rdtgroup_kf_single_ops, + .seq_show =3D resctrl_io_alloc_show, + .write =3D resctrl_io_alloc_write, + }, { .name =3D "mba_MBps_event", .mode =3D 0644, @@ -2137,6 +2309,15 @@ static void thread_throttle_mode_init(void) RFTYPE_CTRL_INFO | RFTYPE_RES_MB); } =20 +static void io_alloc_init(void) +{ + struct rdt_resource *r =3D resctrl_arch_get_resource(RDT_RESOURCE_L3); + + if (r->cache.io_alloc_capable) + resctrl_file_fflags_init("io_alloc", + RFTYPE_CTRL_INFO | RFTYPE_RES_CACHE); +} + void resctrl_file_fflags_init(const char *config, unsigned long fflags) { struct rftype *rft; @@ -4381,6 +4562,8 @@ int __init resctrl_init(void) =20 thread_throttle_mode_init(); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Apr 2025 22:44:59.2123 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 58d192c4-ac30-42f1-4b7e-08dd81262565 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B371.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8062 Content-Type: text/plain; charset="utf-8" The io_alloc feature in resctrl enables system software to configure the portion of the L3 cache allocated for I/O traffic. Add the interface to display CBMs (Capacity Bit Mask) of io_alloc feature. When CDP is enabled, io_alloc routes traffic using the highest CLOSID used by a L3CODE resource. Add a check for the CDP resource type. Signed-off-by: Babu Moger --- v4: Updated the change log. Added rdtgroup_mutex before rdt_last_cmd_puts(). Returned -ENODEV when resource type is CDP_DATA. Kept the resource name while printing the CBM (L3:0=3Dfff) that way I dont have to change show_doms() just for this feature and it is consistant across all the schemata display. v3: Minor changes due to changes in resctrl_arch_get_io_alloc_enabled() and resctrl_io_alloc_closid_get(). Added the check to verify CDP resource type. Updated the commit log. v2: Fixed to display only on L3 resources. Added the locks while processing. Rename the displat to io_alloc_cbm (from sdciae_cmd). --- arch/x86/kernel/cpu/resctrl/ctrlmondata.c | 2 +- arch/x86/kernel/cpu/resctrl/internal.h | 1 + arch/x86/kernel/cpu/resctrl/rdtgroup.c | 51 ++++++++++++++++++++++- 3 files changed, 52 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c b/arch/x86/kernel/cp= u/resctrl/ctrlmondata.c index 0a0ac5f6112e..d1a59b56a456 100644 --- a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c +++ b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c @@ -454,7 +454,7 @@ u32 resctrl_arch_get_config(struct rdt_resource *r, str= uct rdt_ctrl_domain *d, return hw_dom->ctrl_val[idx]; } =20 -static void show_doms(struct seq_file *s, struct resctrl_schema *schema, i= nt closid) +void show_doms(struct seq_file *s, struct resctrl_schema *schema, int clos= id) { struct rdt_resource *r =3D schema->res; struct rdt_ctrl_domain *dom; diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index 6ead222904fe..2ac78650500a 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -519,6 +519,7 @@ void resctrl_file_fflags_init(const char *config, unsig= ned long fflags); void rdt_staged_configs_clear(void); bool closid_allocated(unsigned int closid); int resctrl_find_cleanest_closid(void); +void show_doms(struct seq_file *s, struct resctrl_schema *schema, int clos= id); =20 #ifdef CONFIG_RESCTRL_FS_PSEUDO_LOCK int rdtgroup_locksetup_enter(struct rdtgroup *rdtgrp); diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index d53a2068cde4..5633437ea85d 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -2042,6 +2042,46 @@ static ssize_t resctrl_io_alloc_write(struct kernfs_= open_file *of, char *buf, return ret ?: nbytes; } =20 +static int resctrl_io_alloc_cbm_show(struct kernfs_open_file *of, + struct seq_file *seq, void *v) +{ + struct resctrl_schema *s =3D rdt_kn_parent_priv(of->kn); + struct rdt_resource *r =3D s->res; + u32 io_alloc_closid; + int ret =3D 0; + + cpus_read_lock(); + mutex_lock(&rdtgroup_mutex); + + rdt_last_cmd_clear(); + + if (!r->cache.io_alloc_capable || s->conf_type =3D=3D CDP_DATA) { + rdt_last_cmd_puts("io_alloc feature is not supported on the resource\n"); + ret =3D -ENODEV; + goto cbm_show_out; + } + + if (!resctrl_arch_get_io_alloc_enabled(r)) { + rdt_last_cmd_puts("io_alloc feature is not enabled\n"); + ret =3D -EINVAL; + goto cbm_show_out; + } + + io_alloc_closid =3D resctrl_io_alloc_closid_get(r, s); + if (io_alloc_closid < 0) { + rdt_last_cmd_puts("Max CLOSID to support io_alloc is not available\n"); + ret =3D -EINVAL; + goto cbm_show_out; + } + + show_doms(seq, s, io_alloc_closid); + +cbm_show_out: + mutex_unlock(&rdtgroup_mutex); + cpus_read_unlock(); + return ret; +} + /* rdtgroup information files for one cache resource. */ static struct rftype res_common_files[] =3D { { @@ -2201,6 +2241,12 @@ static struct rftype res_common_files[] =3D { .seq_show =3D resctrl_io_alloc_show, .write =3D resctrl_io_alloc_write, }, + { + .name =3D "io_alloc_cbm", + .mode =3D 0444, + .kf_ops =3D &rdtgroup_kf_single_ops, + .seq_show =3D resctrl_io_alloc_cbm_show, + }, { .name =3D "mba_MBps_event", .mode =3D 0644, @@ -2313,9 +2359,12 @@ static void io_alloc_init(void) { struct rdt_resource *r =3D resctrl_arch_get_resource(RDT_RESOURCE_L3); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Apr 2025 22:45:07.1588 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b98e0f5c-8774-42f1-0120-08dd81262a21 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B374.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8301 Content-Type: text/plain; charset="utf-8" The functions parse_cbm() and parse_bw() require mode and CLOSID to validate the Capacity Bit Mask (CBM). It is passed through struct rdtgroup in rdt_parse_data. Instead of passing them through struct rdtgroup, pass mode and closid directly. This change enables parse_cbm() to be used for verifying CBM in io_alloc feature. Signed-off-by: Babu Moger --- v4: New patch to call parse_cbm() directly to avoid code duplication. --- arch/x86/kernel/cpu/resctrl/ctrlmondata.c | 29 ++++++++++------------- arch/x86/kernel/cpu/resctrl/internal.h | 6 +++++ 2 files changed, 19 insertions(+), 16 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c b/arch/x86/kernel/cp= u/resctrl/ctrlmondata.c index d1a59b56a456..e5d1e77e1995 100644 --- a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c +++ b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c @@ -23,11 +23,6 @@ =20 #include "internal.h" =20 -struct rdt_parse_data { - struct rdtgroup *rdtgrp; - char *buf; -}; - typedef int (ctrlval_parser_t)(struct rdt_parse_data *data, struct resctrl_schema *s, struct rdt_ctrl_domain *d); @@ -77,8 +72,8 @@ static int parse_bw(struct rdt_parse_data *data, struct r= esctrl_schema *s, struct rdt_ctrl_domain *d) { struct resctrl_staged_config *cfg; - u32 closid =3D data->rdtgrp->closid; struct rdt_resource *r =3D s->res; + u32 closid =3D data->closid; u32 bw_val; =20 cfg =3D &d->staged_config[s->conf_type]; @@ -156,9 +151,10 @@ static bool cbm_validate(char *buf, u32 *data, struct = rdt_resource *r) static int parse_cbm(struct rdt_parse_data *data, struct resctrl_schema *s, struct rdt_ctrl_domain *d) { - struct rdtgroup *rdtgrp =3D data->rdtgrp; + enum rdtgrp_mode mode =3D data->mode; struct resctrl_staged_config *cfg; struct rdt_resource *r =3D s->res; + u32 closid =3D data->closid; u32 cbm_val; =20 cfg =3D &d->staged_config[s->conf_type]; @@ -171,7 +167,7 @@ static int parse_cbm(struct rdt_parse_data *data, struc= t resctrl_schema *s, * Cannot set up more than one pseudo-locked region in a cache * hierarchy. */ - if (rdtgrp->mode =3D=3D RDT_MODE_PSEUDO_LOCKSETUP && + if (mode =3D=3D RDT_MODE_PSEUDO_LOCKSETUP && rdtgroup_pseudo_locked_in_hierarchy(d)) { rdt_last_cmd_puts("Pseudo-locked region in hierarchy\n"); return -EINVAL; @@ -180,9 +176,9 @@ static int parse_cbm(struct rdt_parse_data *data, struc= t resctrl_schema *s, if (!cbm_validate(data->buf, &cbm_val, r)) return -EINVAL; =20 - if ((rdtgrp->mode =3D=3D RDT_MODE_EXCLUSIVE || - rdtgrp->mode =3D=3D RDT_MODE_SHAREABLE) && - rdtgroup_cbm_overlaps_pseudo_locked(d, cbm_val)) { + if ((mode =3D=3D RDT_MODE_EXCLUSIVE || + mode =3D=3D RDT_MODE_SHAREABLE) && + rdtgroup_cbm_overlaps_pseudo_locked(d, cbm_val)) { rdt_last_cmd_puts("CBM overlaps with pseudo-locked region\n"); return -EINVAL; } @@ -191,14 +187,14 @@ static int parse_cbm(struct rdt_parse_data *data, str= uct resctrl_schema *s, * The CBM may not overlap with the CBM of another closid if * either is exclusive. */ - if (rdtgroup_cbm_overlaps(s, d, cbm_val, rdtgrp->closid, true)) { + if (rdtgroup_cbm_overlaps(s, d, cbm_val, closid, true)) { rdt_last_cmd_puts("Overlaps with exclusive group\n"); return -EINVAL; } =20 - if (rdtgroup_cbm_overlaps(s, d, cbm_val, rdtgrp->closid, false)) { - if (rdtgrp->mode =3D=3D RDT_MODE_EXCLUSIVE || - rdtgrp->mode =3D=3D RDT_MODE_PSEUDO_LOCKSETUP) { + if (rdtgroup_cbm_overlaps(s, d, cbm_val, closid, false)) { + if (mode =3D=3D RDT_MODE_EXCLUSIVE || + mode =3D=3D RDT_MODE_PSEUDO_LOCKSETUP) { rdt_last_cmd_puts("Overlaps with other group\n"); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Apr 2025 22:45:15.3741 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e1adb588-3064-4f0c-7088-08dd81262f06 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B374.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS5PPF5E0E7945E Content-Type: text/plain; charset="utf-8" "io_alloc" feature is a mechanism that enables direct insertion of data from I/O devices into the L3 cache. By directly caching data from I/O devices rather than first storing the I/O data in DRAM, it reduces the demands on DRAM bandwidth and reduces latency to the processor consuming the I/O data. io_alloc feature uses the highest CLOSID to route the traffic from I/O devices. Provide the interface to modify io_alloc CBMs (Capacity Bit Mask) when feature is enabled. Signed-off-by: Babu Moger --- v4: Removed resctrl_io_alloc_parse_cbm and called parse_cbm() directly. v3: Minor changes due to changes in resctrl_arch_get_io_alloc_enabled() and resctrl_io_alloc_closid_get(). Taken care of handling the CBM update when CDP is enabled. Updated the commit log to make it generic. v2: Added more generic text in documentation. --- Documentation/arch/x86/resctrl.rst | 21 +++++ arch/x86/kernel/cpu/resctrl/ctrlmondata.c | 4 +- arch/x86/kernel/cpu/resctrl/internal.h | 2 + arch/x86/kernel/cpu/resctrl/rdtgroup.c | 108 +++++++++++++++++++++- 4 files changed, 132 insertions(+), 3 deletions(-) diff --git a/Documentation/arch/x86/resctrl.rst b/Documentation/arch/x86/re= sctrl.rst index 7672c5c52c1a..6fdea77a1675 100644 --- a/Documentation/arch/x86/resctrl.rst +++ b/Documentation/arch/x86/resctrl.rst @@ -169,6 +169,27 @@ related to allocation: When CDP is enabled, io_alloc routes I/O traffic using the highest CLOSID allocated for the instruction cache (L3CODE). =20 +"io_alloc_cbm": + Capacity Bit Masks (CBMs) available to supported IO devices which + can directly insert cache lines in L3 which can help to reduce the + latency. CBM can be configured by writing to the interface in the + following format:: + + :=3D;=3D;... + + Example:: + + # cat /sys/fs/resctrl/info/L3/io_alloc_cbm + L3:0=3Dffff;1=3Dffff + + # echo L3:1=3DFF > /sys/fs/resctrl/info/L3/io_alloc_cbm + # cat /sys/fs/resctrl/info/L3/io_alloc_cbm + L3:0=3Dffff;1=3D00ff + + When CDP is enabled, L3 control is divided into two separate resources: + L3CODE and L3DATA. However, the CBM can only be updated on the L3CODE + resource. + Memory bandwidth(MB) subdirectory contains the following files with respect to allocation: =20 diff --git a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c b/arch/x86/kernel/cp= u/resctrl/ctrlmondata.c index e5d1e77e1995..315584415cc4 100644 --- a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c +++ b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c @@ -148,8 +148,8 @@ static bool cbm_validate(char *buf, u32 *data, struct r= dt_resource *r) * Read one cache bit mask (hex). Check that it is valid for the current * resource type. */ -static int parse_cbm(struct rdt_parse_data *data, struct resctrl_schema *s, - struct rdt_ctrl_domain *d) +int parse_cbm(struct rdt_parse_data *data, struct resctrl_schema *s, + struct rdt_ctrl_domain *d) { enum rdtgrp_mode mode =3D data->mode; struct resctrl_staged_config *cfg; diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index 92246d2b91c8..1d3b60741a39 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -526,6 +526,8 @@ void rdt_staged_configs_clear(void); bool closid_allocated(unsigned int closid); int resctrl_find_cleanest_closid(void); void show_doms(struct seq_file *s, struct resctrl_schema *schema, int clos= id); +int parse_cbm(struct rdt_parse_data *data, struct resctrl_schema *s, + struct rdt_ctrl_domain *d); =20 #ifdef CONFIG_RESCTRL_FS_PSEUDO_LOCK int rdtgroup_locksetup_enter(struct rdtgroup *rdtgrp); diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 5633437ea85d..73532c363e57 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -2082,6 +2082,111 @@ static int resctrl_io_alloc_cbm_show(struct kernfs_= open_file *of, return ret; } =20 +static int resctrl_io_alloc_parse_line(char *line, struct rdt_resource *r, + struct resctrl_schema *s, u32 closid) +{ + struct rdt_parse_data data; + struct rdt_ctrl_domain *d; + char *dom =3D NULL, *id; + unsigned long dom_id; + +next: + if (!line || line[0] =3D=3D '\0') + return 0; + + dom =3D strsep(&line, ";"); + id =3D strsep(&dom, "=3D"); + if (!dom || kstrtoul(id, 10, &dom_id)) { + rdt_last_cmd_puts("Missing '=3D' or non-numeric domain\n"); + return -EINVAL; + } + + dom =3D strim(dom); + list_for_each_entry(d, &r->ctrl_domains, hdr.list) { + if (d->hdr.id =3D=3D dom_id) { + data.buf =3D dom; + data.mode =3D RDT_MODE_SHAREABLE; + data.closid =3D closid; + if (parse_cbm(&data, s, d)) + return -EINVAL; + goto next; + } + } + return -EINVAL; +} + +static ssize_t resctrl_io_alloc_cbm_write(struct kernfs_open_file *of, + char *buf, size_t nbytes, loff_t off) +{ + struct resctrl_schema *s =3D rdt_kn_parent_priv(of->kn); + struct rdt_resource *r =3D s->res; + u32 io_alloc_closid; + char *resname; + int ret =3D 0; + + /* Valid input requires a trailing newline */ + if (nbytes =3D=3D 0 || buf[nbytes - 1] !=3D '\n') + return -EINVAL; + + buf[nbytes - 1] =3D '\0'; + + if (!r->cache.io_alloc_capable || s->conf_type =3D=3D CDP_DATA) { + rdt_last_cmd_puts("io_alloc feature is not supported on the resource\n"); + return -EINVAL; + } + + cpus_read_lock(); + mutex_lock(&rdtgroup_mutex); + + rdt_last_cmd_clear(); + rdt_staged_configs_clear(); + + if (!resctrl_arch_get_io_alloc_enabled(r)) { + rdt_last_cmd_puts("io_alloc feature is not enabled\n"); + ret =3D -EINVAL; + goto cbm_write_out; + } + + resname =3D strim(strsep(&buf, ":")); + if (!buf) { + rdt_last_cmd_puts("Missing ':'\n"); + ret =3D -EINVAL; + goto cbm_write_out; + } + + if (strcmp(resname, s->name)) { + rdt_last_cmd_printf("Unsupported resource name '%s'\n", resname); + ret =3D -EINVAL; + goto cbm_write_out; + } + + if (buf[0] =3D=3D '\0') { + rdt_last_cmd_printf("Missing '%s' value\n", resname); + ret =3D -EINVAL; + goto cbm_write_out; + } + + io_alloc_closid =3D resctrl_io_alloc_closid_get(r, s); + if (io_alloc_closid < 0) { + rdt_last_cmd_puts("Max CLOSID to support io_alloc is not available\n"); + ret =3D -EINVAL; + goto cbm_write_out; + } + + ret =3D resctrl_io_alloc_parse_line(buf, r, s, io_alloc_closid); + if (ret) + goto cbm_write_out; + + ret =3D resctrl_arch_update_domains(r, io_alloc_closid); + +cbm_write_out: + rdt_staged_configs_clear(); + mutex_unlock(&rdtgroup_mutex); + cpus_read_unlock(); + + return ret ?: nbytes; +} + /* rdtgroup information files for one cache resource. */ static struct rftype res_common_files[] =3D { { @@ -2243,9 +2348,10 @@ static struct rftype res_common_files[] =3D { }, { .name =3D "io_alloc_cbm", - .mode =3D 0444, + .mode =3D 0644, .kf_ops =3D &rdtgroup_kf_single_ops, .seq_show =3D resctrl_io_alloc_cbm_show, + .write =3D resctrl_io_alloc_cbm_write, }, { .name =3D "mba_MBps_event", --=20 2.34.1