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Mon, 14 Apr 2025 21:58:08 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , Subject: [PATCH v2 01/11] iommu/arm-smmu-v3: Pass in vmid to arm_smmu_make_s2_domain_ste() Date: Mon, 14 Apr 2025 21:57:36 -0700 Message-ID: <137d6eb98c2b7ea9d5cc2fb0f44f3c73065aa23a.1744692494.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0002992D:EE_|IA0PR12MB8373:EE_ X-MS-Office365-Filtering-Correlation-Id: 8155f1f0-cd47-4ebc-725b-08dd7bda2614 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|30052699003|1800799024|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?SwhY8zp0IDjlz6a/cHfsgXamb7fOR3Y67jaepVIebjY/boSu4sBqjkpj/A5p?= =?us-ascii?Q?6WMxyUo8FQL4wMNwkpLzlP2cdFTpFxaZDkYg+/AyJxXWHHCZxL3F5RF/hkyq?= =?us-ascii?Q?zlLEpYIhChjNuDgSH/YXzljUIpis3IBylwA8zCWf9081QAG8Iy5pGsreCeGA?= =?us-ascii?Q?1/ZRP58AePkUSUIGMmQ/HkdeIx+6BNAZg8gGMY5k+wm2HHtBEhmdWUm/HYrg?= =?us-ascii?Q?ARWWiIEU1HkZBpKxtIEjC/4Ynnu2mu+RAhjHAgYZ0nGCC+dccar2HzsAiOdc?= =?us-ascii?Q?5nDbALZinYDY9v0mWZgXx82BSjxg4ajruBcBwwuBMhQgrkbAgjnJF+m5yLTP?= =?us-ascii?Q?UuT0sQDfJZ1f44d6YI1gfAutqRQPd1dG+uaDQzhxY6cQOYKRZc7iRYRaas1c?= =?us-ascii?Q?wLm+7YXgXn8nBVal4we8Zw3Xge6fw374+suU1Deu2NheI88xHBUtO5q5eeL8?= =?us-ascii?Q?AarRD3alLgfnjHjuIsabaeBKB5uprMqc/XD2+oA/AW7UC3+qpp+kxMeqxDbj?= =?us-ascii?Q?N073iOwAKOGKH3kk0Q92V3/+H0V3kg7L/ecWrzbOXihJdxFhk0R2OqTR0LC9?= =?us-ascii?Q?+AcMwJt4/nGBKSMI+7EBE6WTALQn1rT3NjJvpdnYrCxxwRohXjJsHCCIhbf6?= =?us-ascii?Q?hXR70isqv5SCZwvw6DDV4rIWaX0Kk/x+58W0xkiTitg35JJ2gCEJQr+7WfZm?= =?us-ascii?Q?xEm1KPtLS/OIVDeMdQcu2zL0A2TXnGYwRMu2e9DdVD0DcOYuHrps+gMdjcNs?= =?us-ascii?Q?6nAfzRazbonwv9rqbO5sK9mZp9v3r2qWrbDWJXGmZrA7GoMSyzLMOwUmBBqF?= =?us-ascii?Q?Saq8tkxoDLr3bri9t6jHUVGDkLePn59qI8HgpjWo3I/sB2MY3RjBNvZoG60P?= =?us-ascii?Q?r/b+Tqva1XOootwMoQ4cGUyW3Lxb+rnTJSk27Trs+pb8BybJCi13FxAffjw4?= =?us-ascii?Q?C8TbQ2Fk1J2NWGLkSWnVuqlHyiajASp5G8wXuYHzjyjxhQcCLR8BBQGcEq8I?= =?us-ascii?Q?iQ9EQSztQ7mLzG4e5T3mR/2ua+WvjNofqeQEgrCGJCB7thkcl0sMxs5k95FR?= =?us-ascii?Q?+mRjgx2ANz9m9KHPc1k/nVmWSl+Pb0qldPw0+DNr+iJEMPvjgqmBY3/hG5/g?= =?us-ascii?Q?bweU+fhDTKMzyjNeLqe1WnUeH5vWEFgLdOqjaBgM3NrdHxo4qp9PhBC0EHTE?= =?us-ascii?Q?exeX2r2tcrOZY4hjz9USdsXIRpBLW6PTJ2ggSGTdYcQaDvI1HPwvClZ2T6Hr?= =?us-ascii?Q?aGgTBr8Cuh6Vnsj5UosivwC0w0VR24pFx0wNJRl68Web2cHy65zbVmoFNn0G?= =?us-ascii?Q?OW8ucHWtJ/vz4xO7gerqmrX7JBFD4fobEiI5/U+5G+HZyZ+/9LyEU4exc3Fa?= =?us-ascii?Q?1WOe7nonUZWe35uXr0M7dqd8sDYtetFRx4GAYdyk8IQoOutVArwnFDzFlMRI?= =?us-ascii?Q?NOznNFtlvuwwTVrHErvFObvwFyRh+2qQaBZgnU2Ft6NhxaAVjlaYvEFOf15K?= =?us-ascii?Q?K9KphwdEN25y1hSaStynQ4YoEqgvZK8Iq5U1?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(30052699003)(1800799024)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Apr 2025 04:58:22.6408 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8155f1f0-cd47-4ebc-725b-08dd7bda2614 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0002992D.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8373 Content-Type: text/plain; charset="utf-8" An stage-2 STE requires a vmid that has been so far allocated per domain, so arm_smmu_make_s2_domain_ste() has been extracting the vmid from the S2 domain. To share an S2 parent domain across vSMMUs in the same VM, a vmid will be no longer allocated for nor stored in the S2 domain, but per vSMMU, which means the arm_smmu_make_s2_domain_ste() can get a vmid either from an S2 domain (non nesting parent) or a vSMMU. Allow to pass in vmid explicitly to arm_smmu_make_s2_domain_ste(), giving its callers a chance to pick the vmid between a domain or a vSMMU. Add a WARN_ON_ONCE to validate the input vmid. Reviewed-by: Jason Gunthorpe Reviewed-by: Pranjal Shrivastava Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 +- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 6 ++++-- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c | 3 ++- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 8 +++++--- 4 files changed, 12 insertions(+), 7 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index dd1ad56ce863..d4837a33fb81 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -894,7 +894,7 @@ struct arm_smmu_entry_writer_ops { void arm_smmu_make_abort_ste(struct arm_smmu_ste *target); void arm_smmu_make_s2_domain_ste(struct arm_smmu_ste *target, struct arm_smmu_master *master, - struct arm_smmu_domain *smmu_domain, + struct arm_smmu_domain *smmu_domain, u16 vmid, bool ats_enabled); =20 #if IS_ENABLED(CONFIG_KUNIT) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c b/drivers/= iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c index e4fd8d522af8..d86dba6691e8 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c @@ -34,8 +34,9 @@ static void arm_smmu_make_nested_cd_table_ste( struct arm_smmu_ste *target, struct arm_smmu_master *master, struct arm_smmu_nested_domain *nested_domain, bool ats_enabled) { - arm_smmu_make_s2_domain_ste( - target, master, nested_domain->vsmmu->s2_parent, ats_enabled); + arm_smmu_make_s2_domain_ste(target, master, + nested_domain->vsmmu->s2_parent, + nested_domain->vsmmu->vmid, ats_enabled); =20 target->data[0] =3D cpu_to_le64(STRTAB_STE_0_V | FIELD_PREP(STRTAB_STE_0_CFG, @@ -78,6 +79,7 @@ static void arm_smmu_make_nested_domain_ste( case STRTAB_STE_0_CFG_BYPASS: arm_smmu_make_s2_domain_ste(target, master, nested_domain->vsmmu->s2_parent, + nested_domain->vsmmu->vmid, ats_enabled); break; case STRTAB_STE_0_CFG_ABORT: diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c b/drivers/iom= mu/arm/arm-smmu-v3/arm-smmu-v3-test.c index d2671bfd3798..7fac5a112c5c 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c @@ -316,7 +316,8 @@ static void arm_smmu_test_make_s2_ste(struct arm_smmu_s= te *ste, io_pgtable.cfg.arm_lpae_s2_cfg.vtcr.sl =3D 3; io_pgtable.cfg.arm_lpae_s2_cfg.vtcr.tsz =3D 4; =20 - arm_smmu_make_s2_domain_ste(ste, &master, &smmu_domain, ats_enabled); + arm_smmu_make_s2_domain_ste(ste, &master, &smmu_domain, + smmu_domain.s2_cfg.vmid, ats_enabled); } =20 static void arm_smmu_v3_write_ste_test_s2_to_abort(struct kunit *test) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index c32c0b92dc69..1ec5efca1d42 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1656,10 +1656,9 @@ EXPORT_SYMBOL_IF_KUNIT(arm_smmu_make_cdtable_ste); =20 void arm_smmu_make_s2_domain_ste(struct arm_smmu_ste *target, struct arm_smmu_master *master, - struct arm_smmu_domain *smmu_domain, + struct arm_smmu_domain *smmu_domain, u16 vmid, bool ats_enabled) { - struct arm_smmu_s2_cfg *s2_cfg =3D &smmu_domain->s2_cfg; const struct io_pgtable_cfg *pgtbl_cfg =3D &io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops)->cfg; typeof(&pgtbl_cfg->arm_lpae_s2_cfg.vtcr) vtcr =3D @@ -1667,6 +1666,8 @@ void arm_smmu_make_s2_domain_ste(struct arm_smmu_ste = *target, u64 vtcr_val; struct arm_smmu_device *smmu =3D master->smmu; =20 + WARN_ON_ONCE(!vmid); + memset(target, 0, sizeof(*target)); target->data[0] =3D cpu_to_le64( STRTAB_STE_0_V | @@ -1690,7 +1691,7 @@ void arm_smmu_make_s2_domain_ste(struct arm_smmu_ste = *target, FIELD_PREP(STRTAB_STE_2_VTCR_S2TG, vtcr->tg) | FIELD_PREP(STRTAB_STE_2_VTCR_S2PS, vtcr->ps); target->data[2] =3D cpu_to_le64( - FIELD_PREP(STRTAB_STE_2_S2VMID, s2_cfg->vmid) | + FIELD_PREP(STRTAB_STE_2_S2VMID, vmid) | FIELD_PREP(STRTAB_STE_2_VTCR, vtcr_val) | STRTAB_STE_2_S2AA64 | #ifdef __BIG_ENDIAN @@ -2990,6 +2991,7 @@ static int arm_smmu_attach_dev(struct iommu_domain *d= omain, struct device *dev) } case ARM_SMMU_DOMAIN_S2: arm_smmu_make_s2_domain_ste(&target, master, smmu_domain, + smmu_domain->s2_cfg.vmid, state.ats_enabled); arm_smmu_install_ste_for_dev(master, &target); arm_smmu_clear_cd(master, IOMMU_NO_PASID); --=20 2.43.0 From nobody Fri Dec 19 16:00:43 2025 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2043.outbound.protection.outlook.com [40.107.243.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 900902459F4 for ; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Apr 2025 04:58:22.3579 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 898d9638-4163-4a31-5a74-08dd7bda25dd X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023CF.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN5PR12MB9510 Content-Type: text/plain; charset="utf-8" What __arm_smmu_tlb_inv_range() really needs is the smmu and iommu_domain pointers from the smmu_domain. For a nest_parent smmu_domain, it will no longer store an smmu pointer as it can be shared across vSMMU instances. A vSMMU structure sharing the S2 smmu_domain instead would hold the smmu pointer. Pass them in explicitly to fit both !nest_parent and nest_parent cases. While changing it, share it in the header with arm-smmu-v3-iommmufd that will call it too. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 4 ++++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 17 +++++++++-------- 2 files changed, 13 insertions(+), 8 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index d4837a33fb81..5dbdc61558a9 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -955,6 +955,10 @@ void arm_smmu_tlb_inv_range_asid(unsigned long iova, s= ize_t size, int asid, struct arm_smmu_domain *smmu_domain); int arm_smmu_atc_inv_domain(struct arm_smmu_domain *smmu_domain, unsigned long iova, size_t size); +void __arm_smmu_tlb_inv_range(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq_ent *cmd, unsigned long iova, + size_t size, size_t granule, + struct iommu_domain *domain); =20 void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, struct arm_smmu_cmdq *cmdq); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 1ec5efca1d42..e9d4bbdacc99 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2267,12 +2267,11 @@ static void arm_smmu_tlb_inv_context(void *cookie) arm_smmu_atc_inv_domain(smmu_domain, 0, 0); } =20 -static void __arm_smmu_tlb_inv_range(struct arm_smmu_cmdq_ent *cmd, - unsigned long iova, size_t size, - size_t granule, - struct arm_smmu_domain *smmu_domain) +void __arm_smmu_tlb_inv_range(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq_ent *cmd, unsigned long iova, + size_t size, size_t granule, + struct iommu_domain *domain) { - struct arm_smmu_device *smmu =3D smmu_domain->smmu; unsigned long end =3D iova + size, num_pages =3D 0, tg =3D 0; size_t inv_range =3D granule; struct arm_smmu_cmdq_batch cmds; @@ -2282,7 +2281,7 @@ static void __arm_smmu_tlb_inv_range(struct arm_smmu_= cmdq_ent *cmd, =20 if (smmu->features & ARM_SMMU_FEAT_RANGE_INV) { /* Get the leaf page size */ - tg =3D __ffs(smmu_domain->domain.pgsize_bitmap); + tg =3D __ffs(domain->pgsize_bitmap); =20 num_pages =3D size >> tg; =20 @@ -2356,7 +2355,8 @@ static void arm_smmu_tlb_inv_range_domain(unsigned lo= ng iova, size_t size, cmd.opcode =3D CMDQ_OP_TLBI_S2_IPA; cmd.tlbi.vmid =3D smmu_domain->s2_cfg.vmid; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Apr 2025 04:58:26.2409 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 763af0f7-64d4-4e17-c72d-08dd7bda2839 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00029927.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS5PPF482CFEB7D Content-Type: text/plain; charset="utf-8" Allow arm-smmu-v3-iommufd to call them for nested/S2 cache invalidations. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 12 ++++++++++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 25 ++++++++++----------- 2 files changed, 24 insertions(+), 13 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 5dbdc61558a9..4f3f4a40a755 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -959,6 +959,8 @@ void __arm_smmu_tlb_inv_range(struct arm_smmu_device *s= mmu, struct arm_smmu_cmdq_ent *cmd, unsigned long iova, size_t size, size_t granule, struct iommu_domain *domain); +void arm_smmu_atc_inv_to_cmd(int ssid, unsigned long iova, size_t size, + struct arm_smmu_cmdq_ent *cmd); =20 void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, struct arm_smmu_cmdq *cmdq); @@ -996,6 +998,16 @@ void arm_smmu_install_ste_for_dev(struct arm_smmu_mast= er *master, int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu, struct arm_smmu_cmdq *cmdq, u64 *cmds, int n, bool sync); +int arm_smmu_cmdq_issue_cmd_with_sync(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq_ent *ent); +void arm_smmu_cmdq_batch_init(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq_batch *cmds, + struct arm_smmu_cmdq_ent *ent); +void arm_smmu_cmdq_batch_add(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq_batch *cmds, + struct arm_smmu_cmdq_ent *cmd); +int arm_smmu_cmdq_batch_submit(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq_batch *cmds); =20 #ifdef CONFIG_ARM_SMMU_V3_SVA bool arm_smmu_sva_supported(struct arm_smmu_device *smmu); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index e9d4bbdacc99..8ad249f7dcbf 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -929,23 +929,23 @@ static int arm_smmu_cmdq_issue_cmd(struct arm_smmu_de= vice *smmu, return __arm_smmu_cmdq_issue_cmd(smmu, ent, false); } =20 -static int arm_smmu_cmdq_issue_cmd_with_sync(struct arm_smmu_device *smmu, - struct arm_smmu_cmdq_ent *ent) +int arm_smmu_cmdq_issue_cmd_with_sync(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq_ent *ent) { return __arm_smmu_cmdq_issue_cmd(smmu, ent, true); } =20 -static void arm_smmu_cmdq_batch_init(struct arm_smmu_device *smmu, - struct arm_smmu_cmdq_batch *cmds, - struct arm_smmu_cmdq_ent *ent) +void arm_smmu_cmdq_batch_init(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq_batch *cmds, + struct arm_smmu_cmdq_ent *ent) { cmds->num =3D 0; cmds->cmdq =3D arm_smmu_get_cmdq(smmu, ent); } =20 -static void arm_smmu_cmdq_batch_add(struct arm_smmu_device *smmu, - struct arm_smmu_cmdq_batch *cmds, - struct arm_smmu_cmdq_ent *cmd) +void arm_smmu_cmdq_batch_add(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq_batch *cmds, + struct arm_smmu_cmdq_ent *cmd) { bool unsupported_cmd =3D !arm_smmu_cmdq_supports_cmd(cmds->cmdq, cmd); bool force_sync =3D (cmds->num =3D=3D CMDQ_BATCH_ENTRIES - 1) && @@ -974,8 +974,8 @@ static void arm_smmu_cmdq_batch_add(struct arm_smmu_dev= ice *smmu, cmds->num++; } =20 -static int arm_smmu_cmdq_batch_submit(struct arm_smmu_device *smmu, - struct arm_smmu_cmdq_batch *cmds) +int arm_smmu_cmdq_batch_submit(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq_batch *cmds) { return arm_smmu_cmdq_issue_cmdlist(smmu, cmds->cmdq, cmds->cmds, cmds->num, true); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Apr 2025 04:58:28.1159 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 516ee6a9-8f8b-477a-e185-08dd7bda2957 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00029927.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8748 Content-Type: text/plain; charset="utf-8" Both arm-smmu-v3 and arm-smmu-v3-iommufd will use this by passing in a vmid from s2_cfg/vsmmu. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 10 ++++++++++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 10 +++------- 2 files changed, 13 insertions(+), 7 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 4f3f4a40a755..2f8928971716 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -1009,6 +1009,16 @@ void arm_smmu_cmdq_batch_add(struct arm_smmu_device = *smmu, int arm_smmu_cmdq_batch_submit(struct arm_smmu_device *smmu, struct arm_smmu_cmdq_batch *cmds); =20 +static inline void arm_smmu_tlb_inv_vmid(struct arm_smmu_device *smmu, u16= vmid) +{ + struct arm_smmu_cmdq_ent cmd =3D { + .opcode =3D CMDQ_OP_TLBI_S12_VMALL, + .tlbi.vmid =3D vmid, + }; + + arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); +} + #ifdef CONFIG_ARM_SMMU_V3_SVA bool arm_smmu_sva_supported(struct arm_smmu_device *smmu); bool arm_smmu_master_sva_supported(struct arm_smmu_master *master); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 8ad249f7dcbf..bafe7c7c2769 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2247,7 +2247,6 @@ static void arm_smmu_tlb_inv_context(void *cookie) { struct arm_smmu_domain *smmu_domain =3D cookie; struct arm_smmu_device *smmu =3D smmu_domain->smmu; - struct arm_smmu_cmdq_ent cmd; =20 /* * NOTE: when io-pgtable is in non-strict mode, we may get here with @@ -2256,13 +2255,10 @@ static void arm_smmu_tlb_inv_context(void *cookie) * insertion to guarantee those are observed before the TLBI. Do be * careful, 007. */ - if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1) { + if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1) arm_smmu_tlb_inv_asid(smmu, smmu_domain->cd.asid); - } else { - cmd.opcode =3D CMDQ_OP_TLBI_S12_VMALL; - cmd.tlbi.vmid =3D smmu_domain->s2_cfg.vmid; - arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); - } + else + arm_smmu_tlb_inv_vmid(smmu, smmu_domain->s2_cfg.vmid); arm_smmu_atc_inv_domain(smmu_domain, 0, 0); } =20 --=20 2.43.0 From nobody Fri Dec 19 16:00:43 2025 Received: from NAM04-MW2-obe.outbound.protection.outlook.com (mail-mw2nam04on2072.outbound.protection.outlook.com [40.107.101.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DA1AC2741D6 for ; Tue, 15 Apr 2025 04:58:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.101.72 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744693114; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Apr 2025 04:58:27.4672 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c5edb401-f33c-457b-fbde-08dd7bda28e8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023CF.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7953 Content-Type: text/plain; charset="utf-8" There is a need of stuffing more vsmmu-related routine into the prepare(). Given that the arm_smmu_attach_prepare_vmaster() is always called when the domain is a nested domain that always has a valid vsmmu pointer. Rename it to arm_vsmmu_attach_prepare(). Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 9 ++++----- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 8 ++++---- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 5 +++-- 3 files changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 2f8928971716..7b47f4408a7a 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -1089,8 +1089,8 @@ struct iommufd_viommu *arm_vsmmu_alloc(struct device = *dev, struct iommu_domain *parent, struct iommufd_ctx *ictx, unsigned int viommu_type); -int arm_smmu_attach_prepare_vmaster(struct arm_smmu_attach_state *state, - struct arm_smmu_nested_domain *nested_domain); +int arm_vsmmu_attach_prepare(struct arm_smmu_attach_state *state, + struct arm_vsmmu *vsmmu); void arm_smmu_attach_commit_vmaster(struct arm_smmu_attach_state *state); void arm_smmu_master_clear_vmaster(struct arm_smmu_master *master); int arm_vmaster_report_event(struct arm_smmu_vmaster *vmaster, u64 *evt); @@ -1098,9 +1098,8 @@ int arm_vmaster_report_event(struct arm_smmu_vmaster = *vmaster, u64 *evt); #define arm_smmu_hw_info NULL #define arm_vsmmu_alloc NULL =20 -static inline int -arm_smmu_attach_prepare_vmaster(struct arm_smmu_attach_state *state, - struct arm_smmu_nested_domain *nested_domain) +static inline int arm_vsmmu_attach_prepare(struct arm_smmu_attach_state *s= tate, + struct arm_vsmmu *vsmmu) { return 0; } diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c b/drivers/= iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c index d86dba6691e8..6cd01536c966 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c @@ -89,8 +89,8 @@ static void arm_smmu_make_nested_domain_ste( } } =20 -int arm_smmu_attach_prepare_vmaster(struct arm_smmu_attach_state *state, - struct arm_smmu_nested_domain *nested_domain) +int arm_vsmmu_attach_prepare(struct arm_smmu_attach_state *state, + struct arm_vsmmu *vsmmu) { struct arm_smmu_vmaster *vmaster; unsigned long vsid; @@ -98,7 +98,7 @@ int arm_smmu_attach_prepare_vmaster(struct arm_smmu_attac= h_state *state, =20 iommu_group_mutex_assert(state->master->dev); =20 - ret =3D iommufd_viommu_get_vdev_id(&nested_domain->vsmmu->core, + ret =3D iommufd_viommu_get_vdev_id(&vsmmu->core, state->master->dev, &vsid); if (ret) return ret; @@ -106,7 +106,7 @@ int arm_smmu_attach_prepare_vmaster(struct arm_smmu_att= ach_state *state, vmaster =3D kzalloc(sizeof(*vmaster), GFP_KERNEL); if (!vmaster) return -ENOMEM; - vmaster->vsmmu =3D nested_domain->vsmmu; + vmaster->vsmmu =3D vsmmu; vmaster->vsid =3D vsid; state->vmaster =3D vmaster; =20 diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index bafe7c7c2769..07d435562da2 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2839,8 +2839,9 @@ int arm_smmu_attach_prepare(struct arm_smmu_attach_st= ate *state, =20 if (smmu_domain) { if (new_domain->type =3D=3D IOMMU_DOMAIN_NESTED) { - ret =3D arm_smmu_attach_prepare_vmaster( - state, to_smmu_nested_domain(new_domain)); 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Mon, 14 Apr 2025 21:58:15 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , Subject: [PATCH v2 06/11] iommu/arm-smmu-v3: Introduce arm_smmu_s2_parent_tlb_ invalidation helpers Date: Mon, 14 Apr 2025 21:57:41 -0700 Message-ID: <61fef9052b2034e5b4ffa1fa6ce481667d8ea6b1.1744692494.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023CC:EE_|CY5PR12MB6347:EE_ X-MS-Office365-Filtering-Correlation-Id: 21cdad51-9e88-4497-497b-08dd7bda29d4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|376014|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?vW+wAczugqUoLIeRsqD8CQQWalcS/r9Fv/WyWeNP37EvMbuvwq2pJ7BNYDmr?= =?us-ascii?Q?/Ji23v/J6CXDSsFbCfWSEzweRCIuVH+0Ji5wMuPGgPdUuVCIhqUSC9I3EoAJ?= =?us-ascii?Q?W0dmYSEMiySgafo8rBynyQlw7R9P4hh0VIHgKceV6RII8yBJhH5jl/rTIfre?= =?us-ascii?Q?pOddW+zpyMkjXFhZtsqu8q3wwX/pElBSNk+zlrf5UHX9+iYQYfCo8gNzZReb?= =?us-ascii?Q?5i8uiZS4ymlgMxodnlWcqremFyKid/PlMk9R9uW7AtDxX8KD5DVN55lzJ+Gg?= =?us-ascii?Q?5/HjmxyU5UUaucgNTI6TthiK/k/aZL4UHERY8HlHIKQeeqsvpMgrJhmj8j70?= =?us-ascii?Q?BMZaUKlLvyhEhMQfLdxKlw8ttEW7na8hGFPdGBSGF7OWRK0xLRk0MzokFJaZ?= =?us-ascii?Q?1BuUVOXkXnBEeqXV0nHInydfqYtCJRzHKIJlL3SxQ7Eg+f2NFjyiyWExSX/I?= =?us-ascii?Q?wpDAEj7cK9v37eWnmSwkOf/cb6y7jD3Qw/KCf9zeyohy3QW0e/WTYljhh77e?= =?us-ascii?Q?2ELeOweX1aMuqBDY4uxK8UWSzoQu+4OYUSYRRqb38sBF3+9Mj1VA5XRtcRwq?= =?us-ascii?Q?iKAj7SQ8CP5vy3q1EpW94Dp8j1bnHzkXEN+j2IYDknsXZGVaKVIxb/6pLsdg?= =?us-ascii?Q?8MtwIFO3TItGLpXUmWIBN9nibWggudvNFtUWzWmzGJobOCDQBB00ooq9z3su?= =?us-ascii?Q?XuUzZWUE4UeELCBzdIkumjGMqwk0BvvHIMRgEzWK/fxX9UHgEWBQGEFawAnl?= =?us-ascii?Q?AeR5yzbtuA5xz6UkNdJNf/dIae88j77O/DGfX1Fcc8svON6dyNHKfDVSf76U?= =?us-ascii?Q?2AWArXlhNl5krs8hsk23YHDeHMgasz0FhxtnbHs/nHr32alu2tYRlvjsy5aT?= =?us-ascii?Q?RTp5/jlvrlgisAm55aGXLqvhgixpGTQZtBHPaoD1AXFDSuia812yWD49GSgA?= =?us-ascii?Q?2lrOY4ZhnC8gcH+8mWhyx8PjcEmzWAyNd4yEXwztpDN8L0qpaptpYJOGm3Ry?= =?us-ascii?Q?JV7mPtd1JDyQ//e+IZW5qmBxT8WaK7azbjsuWHacoiwiZCV07tHzUVLDRMp8?= =?us-ascii?Q?0rLWy3BvCOu29TfJSgOkTghTftqometAsNHo/lydpuYHdzYqNc2BXSqyw8Uy?= =?us-ascii?Q?JiC7cx4HYbAUm3daGZmJGz7BO+FQkEMPt3c4efyS5VePRYSZZwtKXKHtu1in?= =?us-ascii?Q?1PG1G5DrKTDJNjTc45n+TANTvD4qQ9IMJCyX39DK4GvwXCCXuC8d8cHCwto/?= =?us-ascii?Q?mYpnm88NNUngFoZbIl1pB9RmyiuWaw8DFjQn4NaHxaVFBoDdMQR6t1SyVDsw?= =?us-ascii?Q?slzc3BUtIDaM6vpbdFCJ+E+KvM8UY5ygFCpULKz74y4uxpSALLlZKJwP/xWU?= =?us-ascii?Q?Hosn6prxrygMCMcza19bMa71Yjyu469hVRUpgze4/2koUiuARYA3ARCT8smr?= =?us-ascii?Q?m1xbA0KQmFhEW4GOgATYyXWuZM6UbZgy/ODuT3J937dIWYob/2hEI3q48TDu?= =?us-ascii?Q?uOPvFCg4xc++EwConquwEa2WhtDmw1bZ9DVM?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(7416014)(376014)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Apr 2025 04:58:28.9937 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 21cdad51-9e88-4497-497b-08dd7bda29d4 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023CC.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6347 Content-Type: text/plain; charset="utf-8" An S2 nest_parent domain can be shared across vSMMUs in the same VM, since the S2 domain is basically the IPA mappings for the entire RAM of the VM. Meanwhile, each vSMMU can have its own VMID, so the VMID allocation should be done per vSMMU instance v.s. per S2 nest_parent domain. However, an S2 domain can be also allocated when a physical SMMU instance doesn't support S1. So, the structure has to retain the s2_cfg and vmid. Add a per-domain "vsmmus" list pairing with a spinlock, maintaining a list of vSMMUs in the S2 parent domain. Provide two arm_smmu_s2_parent_tlb_ helpers that will be used for nesting cases to invalidate S2 cache using vsmmu->vmid by iterating this "vsmmus" list. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 22 ++++++++ .../arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 53 +++++++++++++++++++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 2 + 3 files changed, 77 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 7b47f4408a7a..7d76d8ac9acc 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -859,6 +859,10 @@ struct arm_smmu_domain { struct arm_smmu_ctx_desc cd; struct arm_smmu_s2_cfg s2_cfg; }; + struct { + struct list_head list; + spinlock_t lock; + } vsmmus; =20 struct iommu_domain domain; =20 @@ -1081,6 +1085,7 @@ struct arm_vsmmu { struct arm_smmu_device *smmu; struct arm_smmu_domain *s2_parent; u16 vmid; + struct list_head vsmmus_elm; /* arm_smmu_domain::vsmmus::list */ }; =20 #if IS_ENABLED(CONFIG_ARM_SMMU_V3_IOMMUFD) @@ -1094,6 +1099,11 @@ int arm_vsmmu_attach_prepare(struct arm_smmu_attach_= state *state, void arm_smmu_attach_commit_vmaster(struct arm_smmu_attach_state *state); void arm_smmu_master_clear_vmaster(struct arm_smmu_master *master); int arm_vmaster_report_event(struct arm_smmu_vmaster *vmaster, u64 *evt); + +void arm_smmu_s2_parent_tlb_inv_domain(struct arm_smmu_domain *s2_parent); +void arm_smmu_s2_parent_tlb_inv_range(struct arm_smmu_domain *s2_parent, + unsigned long iova, size_t size, + size_t granule, bool leaf); #else #define arm_smmu_hw_info NULL #define arm_vsmmu_alloc NULL @@ -1119,6 +1129,18 @@ static inline int arm_vmaster_report_event(struct ar= m_smmu_vmaster *vmaster, { return -EOPNOTSUPP; } + +static inline void +arm_smmu_s2_parent_tlb_inv_domain(struct arm_smmu_domain *s2_parent) +{ +} + +static inline void +arm_smmu_s2_parent_tlb_inv_range(struct arm_smmu_domain *s2_parent, + unsigned long iova, size_t size, + size_t granule, bool leaf) +{ +} #endif /* CONFIG_ARM_SMMU_V3_IOMMUFD */ =20 #endif /* _ARM_SMMU_V3_H */ diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c b/drivers/= iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c index 6cd01536c966..45ba68a1b59a 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c @@ -30,6 +30,54 @@ void *arm_smmu_hw_info(struct device *dev, u32 *length, = u32 *type) return info; } =20 +void arm_smmu_s2_parent_tlb_inv_domain(struct arm_smmu_domain *s2_parent) +{ + struct arm_vsmmu *vsmmu, *next; + unsigned long flags; + + spin_lock_irqsave(&s2_parent->vsmmus.lock, flags); + list_for_each_entry_safe(vsmmu, next, &s2_parent->vsmmus.list, + vsmmus_elm) { + arm_smmu_tlb_inv_vmid(vsmmu->smmu, vsmmu->vmid); + } + spin_unlock_irqrestore(&s2_parent->vsmmus.lock, flags); +} + +void arm_smmu_s2_parent_tlb_inv_range(struct arm_smmu_domain *s2_parent, + unsigned long iova, size_t size, + size_t granule, bool leaf) +{ + struct arm_smmu_cmdq_ent cmd =3D { .tlbi =3D { .leaf =3D leaf } }; + struct arm_vsmmu *vsmmu, *next; + unsigned long flags; + + spin_lock_irqsave(&s2_parent->vsmmus.lock, flags); + list_for_each_entry_safe(vsmmu, next, &s2_parent->vsmmus.list, + vsmmus_elm) { + cmd.tlbi.vmid =3D vsmmu->vmid; + + /* Must flush all the nested S1 ASIDs when S2 domain changes */ + cmd.opcode =3D CMDQ_OP_TLBI_NH_ALL; + arm_smmu_cmdq_issue_cmd_with_sync(vsmmu->smmu, &cmd); + cmd.opcode =3D CMDQ_OP_TLBI_S2_IPA; + __arm_smmu_tlb_inv_range(vsmmu->smmu, &cmd, iova, size, granule, + &s2_parent->domain); + } + spin_unlock_irqrestore(&s2_parent->vsmmus.lock, flags); +} + +static void arm_vsmmu_destroy(struct iommufd_viommu *viommu) +{ + struct arm_vsmmu *vsmmu =3D container_of(viommu, struct arm_vsmmu, core); + unsigned long flags; + + spin_lock_irqsave(&vsmmu->s2_parent->vsmmus.lock, flags); + list_del(&vsmmu->vsmmus_elm); + spin_unlock_irqrestore(&vsmmu->s2_parent->vsmmus.lock, flags); + /* Must flush S2 vmid after delinking vSMMU */ + arm_smmu_tlb_inv_vmid(vsmmu->smmu, vsmmu->vmid); +} + static void arm_smmu_make_nested_cd_table_ste( struct arm_smmu_ste *target, struct arm_smmu_master *master, struct arm_smmu_nested_domain *nested_domain, bool ats_enabled) @@ -380,6 +428,7 @@ static int arm_vsmmu_cache_invalidate(struct iommufd_vi= ommu *viommu, } =20 static const struct iommufd_viommu_ops arm_vsmmu_ops =3D { + .destroy =3D arm_vsmmu_destroy, .alloc_domain_nested =3D arm_vsmmu_alloc_domain_nested, .cache_invalidate =3D arm_vsmmu_cache_invalidate, }; @@ -394,6 +443,7 @@ struct iommufd_viommu *arm_vsmmu_alloc(struct device *d= ev, struct arm_smmu_master *master =3D dev_iommu_priv_get(dev); struct arm_smmu_domain *s2_parent =3D to_smmu_domain(parent); struct arm_vsmmu *vsmmu; + unsigned long flags; =20 if (viommu_type !=3D IOMMU_VIOMMU_TYPE_ARM_SMMUV3) return ERR_PTR(-EOPNOTSUPP); @@ -433,6 +483,9 @@ struct iommufd_viommu *arm_vsmmu_alloc(struct device *d= ev, vsmmu->s2_parent =3D s2_parent; /* FIXME Move VMID allocation from the S2 domain allocation to here */ vsmmu->vmid =3D s2_parent->s2_cfg.vmid; + spin_lock_irqsave(&s2_parent->vsmmus.lock, flags); + list_add_tail(&vsmmu->vsmmus_elm, &s2_parent->vsmmus.list); + spin_unlock_irqrestore(&s2_parent->vsmmus.lock, flags); =20 return &vsmmu->core; } diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 07d435562da2..df87880e2a29 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3256,6 +3256,8 @@ arm_smmu_domain_alloc_paging_flags(struct device *dev= , u32 flags, } smmu_domain->stage =3D ARM_SMMU_DOMAIN_S2; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Apr 2025 04:58:31.6079 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1b20ad59-e03e-49f2-cb67-08dd7bda2b60 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023CF.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6130 Content-Type: text/plain; charset="utf-8" Currently, all nested domains that enable ATS (i.e. nested_ats_flush) are added to the devices list in the S2 parent domain via a master_domain. On the other hand, an S2 parent domain can be shared across vSMMU instances. So, storing all devices behind different vSMMU isntances into a shared S2 parent domain apparently isn't ideal. Add a new per-vSMMU ats_devices list (with a pairing lock), which will be stored the devices if their ATS features are enabled. Using this ats_devices list, add an arm_vsmmu_atc_inv_domain() helper, for the s2_parent invalidation routines to proceed ATC invalidation properly, which sends an ATC invalidation request to all the devices on the list. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 6 +++ .../arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 45 +++++++++++++++++++ 2 files changed, 51 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 7d76d8ac9acc..d130d723cc33 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -840,6 +840,7 @@ struct arm_smmu_master { bool sva_enabled; bool iopf_enabled; unsigned int ssid_bits; + struct list_head devices_elm; /* vsmmu->ats_devices */ }; =20 /* SMMU private data for an IOMMU domain */ @@ -1086,6 +1087,11 @@ struct arm_vsmmu { struct arm_smmu_domain *s2_parent; u16 vmid; struct list_head vsmmus_elm; /* arm_smmu_domain::vsmmus::list */ + /* List of struct arm_smmu_master that enables ATS */ + struct { + struct list_head list; + spinlock_t lock; + } ats_devices; }; =20 #if IS_ENABLED(CONFIG_ARM_SMMU_V3_IOMMUFD) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c b/drivers/= iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c index 45ba68a1b59a..4730ff56cf04 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c @@ -30,6 +30,41 @@ void *arm_smmu_hw_info(struct device *dev, u32 *length, = u32 *type) return info; } =20 +static void arm_vsmmu_cmdq_batch_add_atc_inv(struct arm_vsmmu *vsmmu, + struct arm_smmu_master *master, + struct arm_smmu_cmdq_batch *cmds, + struct arm_smmu_cmdq_ent *cmd) +{ + int i; + + lockdep_assert_held(&vsmmu->ats_devices.lock); + + arm_smmu_atc_inv_to_cmd(IOMMU_NO_PASID, 0, 0, cmd); + for (i =3D 0; i < master->num_streams; i++) { + cmd->atc.sid =3D master->streams[i].id; + arm_smmu_cmdq_batch_add(vsmmu->smmu, cmds, cmd); + } +} + +static int arm_vsmmu_atc_inv_domain(struct arm_vsmmu *vsmmu, unsigned long= iova, + size_t size) +{ + struct arm_smmu_cmdq_ent cmd =3D { .opcode =3D CMDQ_OP_ATC_INV }; + struct arm_smmu_master *master, *next; + struct arm_smmu_cmdq_batch cmds; + unsigned long flags; + + arm_smmu_cmdq_batch_init(vsmmu->smmu, &cmds, &cmd); + + spin_lock_irqsave(&vsmmu->ats_devices.lock, flags); + list_for_each_entry_safe(master, next, &vsmmu->ats_devices.list, + devices_elm) + arm_vsmmu_cmdq_batch_add_atc_inv(vsmmu, master, &cmds, &cmd); + spin_unlock_irqrestore(&vsmmu->ats_devices.lock, flags); + + return arm_smmu_cmdq_batch_submit(vsmmu->smmu, &cmds); +} + void arm_smmu_s2_parent_tlb_inv_domain(struct arm_smmu_domain *s2_parent) { struct arm_vsmmu *vsmmu, *next; @@ -39,6 +74,7 @@ void arm_smmu_s2_parent_tlb_inv_domain(struct arm_smmu_do= main *s2_parent) list_for_each_entry_safe(vsmmu, next, &s2_parent->vsmmus.list, vsmmus_elm) { arm_smmu_tlb_inv_vmid(vsmmu->smmu, vsmmu->vmid); + arm_vsmmu_atc_inv_domain(vsmmu, 0, 0); } spin_unlock_irqrestore(&s2_parent->vsmmus.lock, flags); } @@ -62,6 +98,11 @@ void arm_smmu_s2_parent_tlb_inv_range(struct arm_smmu_do= main *s2_parent, cmd.opcode =3D CMDQ_OP_TLBI_S2_IPA; __arm_smmu_tlb_inv_range(vsmmu->smmu, &cmd, iova, size, granule, &s2_parent->domain); + /* + * Unfortunately, this can't be leaf-only since we may have + * zapped an entire table. + */ + arm_vsmmu_atc_inv_domain(vsmmu, iova, size); } spin_unlock_irqrestore(&s2_parent->vsmmus.lock, flags); } @@ -76,6 +117,7 @@ static void arm_vsmmu_destroy(struct iommufd_viommu *vio= mmu) spin_unlock_irqrestore(&vsmmu->s2_parent->vsmmus.lock, flags); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Apr 2025 04:58:33.9111 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 609de5aa-7a7a-4c8e-d990-08dd7bda2cbd X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023D1.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4251 Content-Type: text/plain; charset="utf-8" Now the driver can do a per-vSMMU S2 cache and ATC invalidations, given a pair of arm_smmu_s2_parent_* helpers. Use them in the arm_smmu_tlb_inv_* functions, replacing the existing per-domain invalidations. This also requires to add/remove the device onto/from the ats_devices list of the vSMMU. Note that this is shifting away from the nested_ats_flush in the struct arm_smmu_master_domain, which now became a dead code, requiring a cleanup. Move the arm_vsmmu_attach_prepare() call in arm_smmu_attach_prepare(), out of the !IOMMU_DOMAIN_NESTED routine, so that it doesn't need to revert the arm_vsmmu_attach_prepare(), which wouldn't only require a simple kfree(). All of these have to be done in one single patch, so nothing is broken. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 7 +++ .../arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 27 ++++++++++- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 45 +++++++++---------- 3 files changed, 55 insertions(+), 24 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index d130d723cc33..c9b9c7921bee 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -1104,6 +1104,8 @@ int arm_vsmmu_attach_prepare(struct arm_smmu_attach_s= tate *state, struct arm_vsmmu *vsmmu); void arm_smmu_attach_commit_vmaster(struct arm_smmu_attach_state *state); void arm_smmu_master_clear_vmaster(struct arm_smmu_master *master); +void arm_vsmmu_remove_ats_device(struct arm_vsmmu *vsmmu, + struct arm_smmu_master *master); int arm_vmaster_report_event(struct arm_smmu_vmaster *vmaster, u64 *evt); =20 void arm_smmu_s2_parent_tlb_inv_domain(struct arm_smmu_domain *s2_parent); @@ -1130,6 +1132,11 @@ arm_smmu_master_clear_vmaster(struct arm_smmu_master= *master) { } =20 +static inline void arm_vsmmu_remove_ats_device(struct arm_vsmmu *vsmmu, + struct arm_smmu_master *master) +{ +} + static inline int arm_vmaster_report_event(struct arm_smmu_vmaster *vmaste= r, u64 *evt) { diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c b/drivers/= iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c index 4730ff56cf04..491f2b88e30b 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c @@ -182,11 +182,13 @@ static void arm_smmu_make_nested_domain_ste( int arm_vsmmu_attach_prepare(struct arm_smmu_attach_state *state, struct arm_vsmmu *vsmmu) { + struct arm_smmu_master *master =3D state->master; struct arm_smmu_vmaster *vmaster; + unsigned long flags; unsigned long vsid; int ret; =20 - iommu_group_mutex_assert(state->master->dev); + iommu_group_mutex_assert(master->dev); =20 ret =3D iommufd_viommu_get_vdev_id(&vsmmu->core, state->master->dev, &vsid); @@ -200,6 +202,12 @@ int arm_vsmmu_attach_prepare(struct arm_smmu_attach_st= ate *state, vmaster->vsid =3D vsid; state->vmaster =3D vmaster; =20 + if (state->ats_enabled) { + spin_lock_irqsave(&vsmmu->ats_devices.lock, flags); + list_add(&master->devices_elm, &vsmmu->ats_devices.list); + spin_unlock_irqrestore(&vsmmu->ats_devices.lock, flags); + } + return 0; } =20 @@ -220,6 +228,23 @@ void arm_smmu_master_clear_vmaster(struct arm_smmu_mas= ter *master) arm_smmu_attach_commit_vmaster(&state); } =20 +void arm_vsmmu_remove_ats_device(struct arm_vsmmu *vsmmu, + struct arm_smmu_master *master) +{ + struct arm_smmu_cmdq_ent cmd =3D { .opcode =3D CMDQ_OP_ATC_INV }; + struct arm_smmu_cmdq_batch cmds; + unsigned long flags; + + arm_smmu_cmdq_batch_init(vsmmu->smmu, &cmds, &cmd); + + spin_lock_irqsave(&vsmmu->ats_devices.lock, flags); + list_del(&master->devices_elm); + arm_vsmmu_cmdq_batch_add_atc_inv(vsmmu, master, &cmds, &cmd); + spin_unlock_irqrestore(&vsmmu->ats_devices.lock, flags); + + arm_smmu_cmdq_batch_submit(vsmmu->smmu, &cmds); +} + static int arm_smmu_attach_dev_nested(struct iommu_domain *domain, struct device *dev) { diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index df87880e2a29..483ef9e2c6b7 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2255,6 +2255,10 @@ static void arm_smmu_tlb_inv_context(void *cookie) * insertion to guarantee those are observed before the TLBI. Do be * careful, 007. */ + + if (smmu_domain->nest_parent) + return arm_smmu_s2_parent_tlb_inv_domain(smmu_domain); + if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1) arm_smmu_tlb_inv_asid(smmu, smmu_domain->cd.asid); else @@ -2342,6 +2346,11 @@ static void arm_smmu_tlb_inv_range_domain(unsigned l= ong iova, size_t size, }, }; =20 + if (smmu_domain->nest_parent) { + return arm_smmu_s2_parent_tlb_inv_range(smmu_domain, iova, size, + granule, leaf); + } + if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1) { cmd.opcode =3D smmu_domain->smmu->features & ARM_SMMU_FEAT_E2H ? CMDQ_OP_TLBI_EL2_VA : CMDQ_OP_TLBI_NH_VA; @@ -2353,15 +2362,6 @@ static void arm_smmu_tlb_inv_range_domain(unsigned l= ong iova, size_t size, __arm_smmu_tlb_inv_range(smmu_domain->smmu, &cmd, iova, size, granule, &smmu_domain->domain); =20 - if (smmu_domain->nest_parent) { - /* - * When the S2 domain changes all the nested S1 ASIDs have to be - * flushed too. - */ - cmd.opcode =3D CMDQ_OP_TLBI_NH_ALL; - arm_smmu_cmdq_issue_cmd_with_sync(smmu_domain->smmu, &cmd); - } - /* * Unfortunately, this can't be leaf-only since we may have * zapped an entire table. @@ -2765,8 +2765,11 @@ static void arm_smmu_remove_master_domain(struct arm= _smmu_master *master, if (!smmu_domain) return; =20 - if (domain->type =3D=3D IOMMU_DOMAIN_NESTED) - nested_ats_flush =3D to_smmu_nested_domain(domain)->enable_ats; + if (domain->type =3D=3D IOMMU_DOMAIN_NESTED && + to_smmu_nested_domain(domain)->enable_ats) { + return arm_vsmmu_remove_ats_device( + to_smmu_nested_domain(domain)->vsmmu, master); + } =20 spin_lock_irqsave(&smmu_domain->devices_lock, flags); master_domain =3D arm_smmu_find_master_domain(smmu_domain, master, ssid, @@ -2837,20 +2840,17 @@ int arm_smmu_attach_prepare(struct arm_smmu_attach_= state *state, arm_smmu_ats_supported(master); } =20 - if (smmu_domain) { - if (new_domain->type =3D=3D IOMMU_DOMAIN_NESTED) { - ret =3D arm_vsmmu_attach_prepare( - state, - to_smmu_nested_domain(new_domain)->vsmmu); - if (ret) - return ret; - } + if (new_domain->type =3D=3D IOMMU_DOMAIN_NESTED) { + struct arm_smmu_nested_domain *nested_domain =3D + to_smmu_nested_domain(new_domain); =20 + ret =3D arm_vsmmu_attach_prepare(state, nested_domain->vsmmu); + if (ret) + return ret; + } else if (smmu_domain) { master_domain =3D kzalloc(sizeof(*master_domain), GFP_KERNEL); - if (!master_domain) { - kfree(state->vmaster); + if (!master_domain) return -ENOMEM; - } master_domain->master =3D master; master_domain->ssid =3D state->ssid; if (new_domain->type =3D=3D IOMMU_DOMAIN_NESTED) @@ -2877,7 +2877,6 @@ int arm_smmu_attach_prepare(struct arm_smmu_attach_st= ate *state, spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Apr 2025 04:58:37.1472 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 47dec1d7-abdf-46bf-8ec7-08dd7bda2eb7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0002992E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7490 Content-Type: text/plain; charset="utf-8" Now the ats_devices list is maintained per vSMMU, since an S2 domain could be shared among vSMMU instances. Drop the nested_ats_flush from struct arm_smmu_master_domain, and clean up the dead code in the related functions. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 - drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 24 ++++----------------- 2 files changed, 4 insertions(+), 21 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index c9b9c7921bee..477d4d2f19a6 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -921,7 +921,6 @@ struct arm_smmu_master_domain { struct list_head devices_elm; struct arm_smmu_master *master; ioasid_t ssid; - bool nested_ats_flush : 1; }; =20 static inline struct arm_smmu_domain *to_smmu_domain(struct iommu_domain *= dom) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 483ef9e2c6b7..4b9cdfb177ca 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2221,16 +2221,7 @@ int arm_smmu_atc_inv_domain(struct arm_smmu_domain *= smmu_domain, if (!master->ats_enabled) continue; =20 - if (master_domain->nested_ats_flush) { - /* - * If a S2 used as a nesting parent is changed we have - * no option but to completely flush the ATC. - */ - arm_smmu_atc_inv_to_cmd(IOMMU_NO_PASID, 0, 0, &cmd); - } else { - arm_smmu_atc_inv_to_cmd(master_domain->ssid, iova, size, - &cmd); - } + arm_smmu_atc_inv_to_cmd(master_domain->ssid, iova, size, &cmd); =20 for (i =3D 0; i < master->num_streams; i++) { cmd.atc.sid =3D master->streams[i].id; @@ -2717,8 +2708,7 @@ static void arm_smmu_disable_pasid(struct arm_smmu_ma= ster *master) =20 static struct arm_smmu_master_domain * arm_smmu_find_master_domain(struct arm_smmu_domain *smmu_domain, - struct arm_smmu_master *master, - ioasid_t ssid, bool nested_ats_flush) + struct arm_smmu_master *master, ioasid_t ssid) { struct arm_smmu_master_domain *master_domain; =20 @@ -2727,8 +2717,7 @@ arm_smmu_find_master_domain(struct arm_smmu_domain *s= mmu_domain, list_for_each_entry(master_domain, &smmu_domain->devices, devices_elm) { if (master_domain->master =3D=3D master && - master_domain->ssid =3D=3D ssid && - master_domain->nested_ats_flush =3D=3D nested_ats_flush) + master_domain->ssid =3D=3D ssid) return master_domain; } return NULL; @@ -2759,7 +2748,6 @@ static void arm_smmu_remove_master_domain(struct arm_= smmu_master *master, { struct arm_smmu_domain *smmu_domain =3D to_smmu_domain_devices(domain); struct arm_smmu_master_domain *master_domain; - bool nested_ats_flush =3D false; unsigned long flags; =20 if (!smmu_domain) @@ -2772,8 +2760,7 @@ static void arm_smmu_remove_master_domain(struct arm_= smmu_master *master, } =20 spin_lock_irqsave(&smmu_domain->devices_lock, flags); - master_domain =3D arm_smmu_find_master_domain(smmu_domain, master, ssid, - nested_ats_flush); + master_domain =3D arm_smmu_find_master_domain(smmu_domain, master, ssid); if (master_domain) { list_del(&master_domain->devices_elm); kfree(master_domain); @@ -2853,9 +2840,6 @@ int arm_smmu_attach_prepare(struct arm_smmu_attach_st= ate *state, return -ENOMEM; master_domain->master =3D master; master_domain->ssid =3D state->ssid; - if (new_domain->type =3D=3D IOMMU_DOMAIN_NESTED) - master_domain->nested_ats_flush =3D - to_smmu_nested_domain(new_domain)->enable_ats; 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Mon, 14 Apr 2025 21:58:20 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , Subject: [PATCH v2 10/11] iommu/arm-smmu-v3: Decouple vmid from S2 nest_parent domain Date: Mon, 14 Apr 2025 21:57:45 -0700 Message-ID: <74495f4edb0d80dff17cf0ab9fe13c29f55b7502.1744692494.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00029927:EE_|SN7PR12MB8817:EE_ X-MS-Office365-Filtering-Correlation-Id: 68572d6e-6665-4165-c15d-08dd7bda2f6c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|7416014|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?bLg0i1QnmpCqVUakPXvuKukKbZnIe9sUEzp605Rc65lXNS0wfTrJdSutBmKa?= =?us-ascii?Q?5GoUpirwfEm5G2MlfCKx40BToFYkfsWDrD+7Oo8dnrjrKL6u90UiMGIywAv7?= =?us-ascii?Q?Wuv+wekVSvo3IZmC8H0shmng3QhP+uhH1st+IaQcxnasZcggIrr6B7oLdJ6U?= =?us-ascii?Q?OF2e8pTKMC9/ZNgcXjVOIpW2YE7KN/oc2mwN4xuFYpZUL6dXpMDzVJD3eKav?= =?us-ascii?Q?NGa0puJ+A2Lqv3L5cCcz1FtrHejh7aMK2BdrY50V8zUK4OL6wi8jzXp7hgXJ?= =?us-ascii?Q?X4WNpNbQYx9qEwXz4uO+iT9SB1TmplFt/vH6/KgXQcbxybluvixvHK4m4mvh?= =?us-ascii?Q?6cmqdvuJtvMgE5Z5lZSkXB7z7EZ6R97Va3Q97zt5DuMd4Co51ikJ4P9I6xfB?= =?us-ascii?Q?zYQwio3p3cyicST+UskmzBw+pL6NVaUiG7krasHIJlLpl3v0a7stLBUx9Vxk?= =?us-ascii?Q?HTRGMWYMQbkQFmJrrCHGF7BtjlG35XGQQ3Jcrhi0u+1IloxtwKak8nPE8Bam?= =?us-ascii?Q?JjkJBO0Di43wmRoH9DLW+Szm3WqilZRD+PCPxMmcWsCEFwDrccItdHoECarj?= =?us-ascii?Q?8ohYsJQykALWuLRUi3VCAWFlaus9huROl8OZ13S6XEXgCaZMSgC/Y9EZRpo9?= =?us-ascii?Q?oqK118b/mICGsqgVkgDe+KB3HjSs2syTxGDmawN8aIH7b6DI48fwnC9lQEDH?= =?us-ascii?Q?9xdXxz+L1KExecG6mW+TYU1y1kSHoSPJDnbyVJ+cRnJpS5+8VURRGRfCeE8u?= =?us-ascii?Q?IFhFQHuXOZKjckWWay3wX5j+WOantHHpHiocTkNuWZQQmEVtze6lGK5MFV7v?= =?us-ascii?Q?C7w5y6clS6YW+0SiH8WWj1I3c9gRosjjr5djzcjhYnewqEt02Dg2Y1yBwVnG?= =?us-ascii?Q?NaocNMTsTdA1cwp5APWSeaJqn8HycsMJ/d2Fj1cuk38z9sOW2+iCawFvH41K?= =?us-ascii?Q?gspgw9XIEyEupmt66Erp//Dng3j/qW4xvIaudJaTonNZQxmrF9DtZRLBoDF6?= =?us-ascii?Q?mrUTBX82AHZVyCKnz4jnmZtNjb2P0UUAzxJKqPImkDc6TysMM2pENX+j541o?= =?us-ascii?Q?RxI8nJLWS1RIrwrN6bygV3EAgz+T8j7n0Xd7Qla0F//egpP5S8m+A6yeX4ox?= =?us-ascii?Q?j7/ReUVMPqKaen+YQXH6dQvK50w6Cgsi6SsGq9Hkbts+jiyVv9CdTjTep6jF?= =?us-ascii?Q?mpfo+KxiABCnoBsJNNyDFq377yLm6/vpEwrT0O2N4ShkHYlUxJVA39dQlTgl?= =?us-ascii?Q?WTqNFo9QKJ9dyJImMkld7CIOgnHqpymjMiYVoKiBBoi5syYwgkpMijqtG3Bu?= =?us-ascii?Q?yHmFQuEohRJvJykuznysBv+RMh6A3P2fNeyB8mYwGsnVAWbIeqI1vM/Ud+4Y?= =?us-ascii?Q?ooER/klJvOMCTB2vb8qWwJINPBC5WExNm2ck5AEyQywRbIeP8XHaGOgcwK6k?= =?us-ascii?Q?/u8voRxRmbXdYzeSH5UayqjAqNoxcQ8tdxAyXhYFkPpkUY9dH6m2pSVgeMKv?= =?us-ascii?Q?UtRl7PekS3IGMcvr5bCTBzGrDq5dgPG9WGiB?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(82310400026)(7416014)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Apr 2025 04:58:38.3190 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 68572d6e-6665-4165-c15d-08dd7bda2f6c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00029927.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB8817 Content-Type: text/plain; charset="utf-8" Now the new S2 invalidation routines in arm-smmu-v3-iommufd are ready to support a shared S2 nest_parent domain across multiple vSMMU instances. Move the vmid allocation/releasing to the vSMMU allocator/destroyer too. Then, move the vsmmus list next to s2_cfg in the struct arm_smmu_domain, as they can be exclusive now. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 12 ++++++------ .../iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 15 ++++++++++++--- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 9 ++++++--- 3 files changed, 24 insertions(+), 12 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 477d4d2f19a6..dfb9d5f935e4 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -857,13 +857,13 @@ struct arm_smmu_domain { =20 enum arm_smmu_domain_stage stage; union { - struct arm_smmu_ctx_desc cd; - struct arm_smmu_s2_cfg s2_cfg; + struct arm_smmu_ctx_desc cd; /* S1 */ + struct arm_smmu_s2_cfg s2_cfg; /* S2 && !nest_parent */ + struct { /* S2 && nest_parent */ + struct list_head list; + spinlock_t lock; + } vsmmus; }; - struct { - struct list_head list; - spinlock_t lock; - } vsmmus; =20 struct iommu_domain domain; =20 diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c b/drivers/= iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c index 491f2b88e30b..5d05f8a78215 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c @@ -118,6 +118,7 @@ static void arm_vsmmu_destroy(struct iommufd_viommu *vi= ommu) /* Must flush S2 vmid after delinking vSMMU */ arm_smmu_tlb_inv_vmid(vsmmu->smmu, vsmmu->vmid); arm_vsmmu_atc_inv_domain(vsmmu, 0, 0); + ida_free(&vsmmu->smmu->vmid_map, vsmmu->vmid); } =20 static void arm_smmu_make_nested_cd_table_ste( @@ -511,6 +512,7 @@ struct iommufd_viommu *arm_vsmmu_alloc(struct device *d= ev, struct arm_smmu_domain *s2_parent =3D to_smmu_domain(parent); struct arm_vsmmu *vsmmu; unsigned long flags; + int vmid; =20 if (viommu_type !=3D IOMMU_VIOMMU_TYPE_ARM_SMMUV3) return ERR_PTR(-EOPNOTSUPP); @@ -541,15 +543,22 @@ struct iommufd_viommu *arm_vsmmu_alloc(struct device = *dev, !(smmu->features & ARM_SMMU_FEAT_S2FWB)) return ERR_PTR(-EOPNOTSUPP); =20 + vmid =3D ida_alloc_range(&smmu->vmid_map, 1, (1 << smmu->vmid_bits) - 1, + GFP_KERNEL); + if (vmid < 0) + return ERR_PTR(vmid); + vsmmu =3D iommufd_viommu_alloc(ictx, struct arm_vsmmu, core, &arm_vsmmu_ops); - if (IS_ERR(vsmmu)) + if (IS_ERR(vsmmu)) { + ida_free(&smmu->vmid_map, vmid); return ERR_CAST(vsmmu); + } =20 vsmmu->smmu =3D smmu; + vsmmu->vmid =3D (u16)vmid; vsmmu->s2_parent =3D s2_parent; - /* FIXME Move VMID allocation from the S2 domain allocation to here */ - vsmmu->vmid =3D s2_parent->s2_cfg.vmid; + spin_lock_irqsave(&s2_parent->vsmmus.lock, flags); list_add_tail(&vsmmu->vsmmus_elm, &s2_parent->vsmmus.list); spin_unlock_irqrestore(&s2_parent->vsmmus.lock, flags); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 4b9cdfb177ca..8047b60ec024 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2474,7 +2474,7 @@ static void arm_smmu_domain_free_paging(struct iommu_= domain *domain) mutex_lock(&arm_smmu_asid_lock); xa_erase(&arm_smmu_asid_xa, smmu_domain->cd.asid); mutex_unlock(&arm_smmu_asid_lock); - } else { + } else if (!smmu_domain->nest_parent) { struct arm_smmu_s2_cfg *cfg =3D &smmu_domain->s2_cfg; if (cfg->vmid) ida_free(&smmu->vmid_map, cfg->vmid); @@ -2503,7 +2503,10 @@ static int arm_smmu_domain_finalise_s2(struct arm_sm= mu_device *smmu, struct arm_smmu_domain *smmu_domain) { int vmid; - struct arm_smmu_s2_cfg *cfg =3D &smmu_domain->s2_cfg; + + /* nest_parent stores vmid in vSMMU instead of a shared S2 domain */ + if (smmu_domain->nest_parent) + return 0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Apr 2025 04:58:39.6003 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6e74d588-f5c6-4b84-e04d-08dd7bda302d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0002992E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6844 Content-Type: text/plain; charset="utf-8" An S2 nest_parent domain used by one vSMMU can be shared with another vSMMU so long as the underlying stage-2 page table is compatible by the physical SMMU instance. There is no direct information about the page table from the master device, but a comparison can be done between the physical SMMU that the nest_parent domain was allocated for and the physical SMMU that the device is behind. Replace the smmu test in arm_vsmmu_alloc() with a compatibility test, which goes through the physical SMMU parameters that were used to decide the page table formats. Signed-off-by: Nicolin Chen --- .../arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 21 ++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c b/drivers/= iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c index 5d05f8a78215..f654e665739a 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c @@ -501,6 +501,25 @@ static const struct iommufd_viommu_ops arm_vsmmu_ops = =3D { .cache_invalidate =3D arm_vsmmu_cache_invalidate, }; =20 +static bool arm_smmu_s2_parent_can_share(struct arm_smmu_domain *s2_parent, + struct arm_smmu_device *smmu) +{ + struct arm_smmu_device *s2_smmu =3D s2_parent->smmu; + + if (s2_smmu =3D=3D smmu) + return true; + if (s2_smmu->iommu.ops !=3D smmu->iommu.ops) + return false; + if (s2_smmu->ias > smmu->ias || s2_smmu->oas > smmu->oas) + return false; + if (s2_smmu->pgsize_bitmap !=3D smmu->pgsize_bitmap) + return false; + if ((s2_smmu->features & ARM_SMMU_FEAT_COHERENCY) !=3D + (smmu->features & ARM_SMMU_FEAT_COHERENCY)) + return false; + return true; +} + struct iommufd_viommu *arm_vsmmu_alloc(struct device *dev, struct iommu_domain *parent, struct iommufd_ctx *ictx, @@ -520,7 +539,7 @@ struct iommufd_viommu *arm_vsmmu_alloc(struct device *d= ev, if (!(smmu->features & ARM_SMMU_FEAT_NESTING)) return ERR_PTR(-EOPNOTSUPP); =20 - if (s2_parent->smmu !=3D master->smmu) + if (!arm_smmu_s2_parent_can_share(s2_parent, master->smmu)) return ERR_PTR(-EINVAL); =20 /* --=20 2.43.0