From nobody Wed Dec 17 05:26:35 2025 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8B95B1EEA30; Wed, 26 Mar 2025 13:25:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742995525; cv=none; b=h+DICB+BGIKfoWNZL7FfgWE6aAirAlLS7lsMrwhP+7/YOpUWoAZVnJEL6q2IdcN/iP7tb85HI88WJOkQReWCJMzlxP8gf3CtbgZ98ZPykvTZfDNeFmD40zYNuDXPh63RCl1V2pCHJHLMR0Q/3dk/7XgacPQYfc/XExLu3wH55Kc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742995525; c=relaxed/simple; bh=T7AKEp33FinQDBuj6W+pPA/RFwe0xNOiM8N+Q9YaAUs=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=S0mb+a6EH5QClPQeeQ+C5kRmZ6S7J+gyPAMk/PnmLE9a6XKYI0AHH2SBx0QHdKPRE6Vrccx00W2pQAEcUy8jyOhNaSsC8c68AquvVTIvnE5aVz7XuQF25CnCxTFJkuSW+P4sE/tYk81fm86xPVV8kruXkycfuV0aUxiVl5+A0P8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=RxCtcvlL; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="RxCtcvlL" Received: from pps.filterd (m0167089.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 52QDHOE6023639; Wed, 26 Mar 2025 09:25:03 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=pgSLK i2nfucshzXq1XZsjAiZfLo08ipcyAm7amO+EEU=; b=RxCtcvlLnY0X/RtwAUaKE ICLtzpw59nZLn0RbPrjHhwFp8Zq0RoTfQsnGaCi+FuBQ5YMb+5S4NcbbK4vgseHl bM8mQg6IHHOopGxdcaMGbQj8pC0ID2gV6gq8oCLN9v8IPBOPAqm8bp8Ll6XEU7Dk zTYHzsUAZbWiJeXFg+p9I8PwdvZ6reXvalKmsU062PGH+RVqN1aw0Ir9QX+TlkjM 2/PGK0wH4GAe6fMkGyPjJYuuWbkHzL3ncVYJ9lm14wwlshGM3sPSLD7qumV1vYeZ wrRc/ykY7N2utNPjCnjp9bPa7NO0Xk2JG5DJnSVQ3w90rOWvYk0zCnZH7spECnyq Q== Received: from nwd2mta3.analog.com ([137.71.173.56]) by mx0a-00128a01.pphosted.com (PPS) with ESMTPS id 45krwh7652-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 26 Mar 2025 09:25:02 -0400 (EDT) Received: from ASHBMBX9.ad.analog.com (ASHBMBX9.ad.analog.com [10.64.17.10]) by nwd2mta3.analog.com (8.14.7/8.14.7) with ESMTP id 52QDP1L1043053 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 26 Mar 2025 09:25:01 -0400 Received: from ASHBMBX9.ad.analog.com (10.64.17.10) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Wed, 26 Mar 2025 09:25:01 -0400 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Wed, 26 Mar 2025 09:25:01 -0400 Received: from work.ad.analog.com (HYB-hERzalRezfV.ad.analog.com [10.65.205.9]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 52QDOmjc007530; Wed, 26 Mar 2025 09:24:51 -0400 From: Marcelo Schmitt To: , , CC: , , , , , Subject: [PATCH v3 1/4] iio: adc: ad4000: Add support for SPI offload Date: Wed, 26 Mar 2025 10:24:47 -0300 Message-ID: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-GUID: CF0sEdWiaFrAQu81us57ItKkX00aM0Zf X-Proofpoint-ORIG-GUID: CF0sEdWiaFrAQu81us57ItKkX00aM0Zf X-Authority-Analysis: v=2.4 cv=IuAecK/g c=1 sm=1 tr=0 ts=67e4002f cx=c_pps a=PpDZqlmH/M8setHirZLBMw==:117 a=PpDZqlmH/M8setHirZLBMw==:17 a=Vs1iUdzkB0EA:10 a=gAnH3GRIAAAA:8 a=75lZUFS3Gz1GdICV1XEA:9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-26_06,2025-03-26_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 malwarescore=0 impostorscore=0 clxscore=1015 lowpriorityscore=0 priorityscore=1501 phishscore=0 spamscore=0 adultscore=0 bulkscore=0 mlxlogscore=999 mlxscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2503260082 Content-Type: text/plain; charset="utf-8" FPGA HDL projects can include a PWM generator in addition to SPI-Engine. The PWM IP is used to trigger SPI-Engine offload modules that in turn set SPI-Engine to execute transfers to poll data from the ADC. That allows data to be read at the maximum sample rates. Also, it is possible to set a specific sample rate by setting the proper PWM duty cycle and related state parameters, thus allowing an adjustable ADC sample rate when a PWM (offload trigger) is used in combination with SPI-Engine. Add support for SPI offload. Signed-off-by: Marcelo Schmitt --- Ideally, we should do something to provide tquiet1 (if using offload) or tc= onv (is not using turbo mode) delay but, when testing with AD7687 and ADAQ4003 = on cora with offload support, I saw no issue in running the transfers without = the CS/CNV high delay. Without the preparatory/dummy transfer, offload messages became equal so I dropped one of them. Also, despite SPI-Engine not support= ing it, I set cs_inactive which semantic seems to match the CS high delay we wa= nt for these transfers. drivers/iio/adc/Kconfig | 7 +- drivers/iio/adc/ad4000.c | 405 +++++++++++++++++++++++++++++++++++---- 2 files changed, 378 insertions(+), 34 deletions(-) diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index b7ae6e0ae0df..1cfa3a32f3a7 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -25,10 +25,15 @@ config AD4000 tristate "Analog Devices AD4000 ADC Driver" depends on SPI select IIO_BUFFER + select IIO_BUFFER_DMAENGINE select IIO_TRIGGERED_BUFFER + select SPI_OFFLOAD help Say yes here to build support for Analog Devices AD4000 high speed - SPI analog to digital converters (ADC). + SPI analog to digital converters (ADC). If intended to use with + SPI offloading support, it is recommended to enable + CONFIG_SPI_AXI_SPI_ENGINE, CONFIG_PWM_AXI_PWMGEN, and + CONFIG_SPI_OFFLOAD_TRIGGER_PWM. =20 To compile this driver as a module, choose M here: the module will be called ad4000. diff --git a/drivers/iio/adc/ad4000.c b/drivers/iio/adc/ad4000.c index 4fe8dee48da9..9fc56853265e 100644 --- a/drivers/iio/adc/ad4000.c +++ b/drivers/iio/adc/ad4000.c @@ -16,11 +16,13 @@ #include #include #include +#include #include #include #include =20 #include +#include #include #include =20 @@ -32,10 +34,11 @@ /* AD4000 Configuration Register programmable bits */ #define AD4000_CFG_SPAN_COMP BIT(3) /* Input span compression */ #define AD4000_CFG_HIGHZ BIT(2) /* High impedance mode */ +#define AD4000_CFG_TURBO BIT(1) /* Turbo mode */ =20 #define AD4000_SCALE_OPTIONS 2 =20 -#define __AD4000_DIFF_CHANNEL(_sign, _real_bits, _storage_bits, _reg_acces= s) \ +#define __AD4000_DIFF_CHANNEL(_sign, _real_bits, _storage_bits, _reg_acces= s, _offl)\ { \ .type =3D IIO_VOLTAGE, \ .indexed =3D 1, \ @@ -43,54 +46,65 @@ .channel =3D 0, \ .channel2 =3D 1, \ .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) | \ - BIT(IIO_CHAN_INFO_SCALE), \ + BIT(IIO_CHAN_INFO_SCALE) | \ + (_offl ? BIT(IIO_CHAN_INFO_SAMP_FREQ) : 0), \ .info_mask_separate_available =3D _reg_access ? BIT(IIO_CHAN_INFO_SCALE) = : 0,\ .scan_index =3D 0, \ .scan_type =3D { \ .sign =3D _sign, \ .realbits =3D _real_bits, \ .storagebits =3D _storage_bits, \ - .shift =3D _storage_bits - _real_bits, \ - .endianness =3D IIO_BE, \ + .shift =3D (_offl ? 0 : _storage_bits - _real_bits), \ + .endianness =3D _offl ? IIO_CPU : IIO_BE \ }, \ } =20 -#define AD4000_DIFF_CHANNEL(_sign, _real_bits, _reg_access) \ +#define AD4000_DIFF_CHANNEL(_sign, _real_bits, _reg_access, _offl) \ __AD4000_DIFF_CHANNEL((_sign), (_real_bits), \ - ((_real_bits) > 16 ? 32 : 16), (_reg_access)) + (((_offl) || ((_real_bits) > 16)) ? 32 : 16), \ + (_reg_access), (_offl)) =20 +/* + * When SPI offload is configured, transfers are executed withouth CPU + * intervention so no soft timestamp can be recorded when transfers run. + * Because of that, the macros that set timestamp channel are only used wh= en + * transfers are not offloaded. + */ #define AD4000_DIFF_CHANNELS(_sign, _real_bits, _reg_access) \ { \ - AD4000_DIFF_CHANNEL(_sign, _real_bits, _reg_access), \ + AD4000_DIFF_CHANNEL(_sign, _real_bits, _reg_access, 0), \ IIO_CHAN_SOFT_TIMESTAMP(1), \ } =20 -#define __AD4000_PSEUDO_DIFF_CHANNEL(_sign, _real_bits, _storage_bits, _re= g_access)\ +#define __AD4000_PSEUDO_DIFF_CHANNEL(_sign, _real_bits, _storage_bits, \ + _reg_access, _offl) \ { \ .type =3D IIO_VOLTAGE, \ .indexed =3D 1, \ .channel =3D 0, \ .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) | \ BIT(IIO_CHAN_INFO_SCALE) | \ - BIT(IIO_CHAN_INFO_OFFSET), \ + BIT(IIO_CHAN_INFO_OFFSET) | \ + (_offl ? BIT(IIO_CHAN_INFO_SAMP_FREQ) : 0), \ .info_mask_separate_available =3D _reg_access ? BIT(IIO_CHAN_INFO_SCALE) = : 0,\ .scan_index =3D 0, \ .scan_type =3D { \ .sign =3D _sign, \ .realbits =3D _real_bits, \ .storagebits =3D _storage_bits, \ - .shift =3D _storage_bits - _real_bits, \ - .endianness =3D IIO_BE, \ + .shift =3D (_offl ? 0 : _storage_bits - _real_bits), \ + .endianness =3D _offl ? IIO_CPU : IIO_BE \ }, \ } =20 -#define AD4000_PSEUDO_DIFF_CHANNEL(_sign, _real_bits, _reg_access) \ +#define AD4000_PSEUDO_DIFF_CHANNEL(_sign, _real_bits, _reg_access, _offl) \ __AD4000_PSEUDO_DIFF_CHANNEL((_sign), (_real_bits), \ - ((_real_bits) > 16 ? 32 : 16), (_reg_access)) + (((_offl) || ((_real_bits) > 16)) ? 32 : 16),\ + (_reg_access), (_offl)) =20 #define AD4000_PSEUDO_DIFF_CHANNELS(_sign, _real_bits, _reg_access) \ { \ - AD4000_PSEUDO_DIFF_CHANNEL(_sign, _real_bits, _reg_access), \ + AD4000_PSEUDO_DIFF_CHANNEL(_sign, _real_bits, _reg_access, 0), \ IIO_CHAN_SOFT_TIMESTAMP(1), \ } =20 @@ -120,6 +134,7 @@ static const int ad4000_gains[] =3D { =20 struct ad4000_time_spec { int t_conv_ns; + int t_quiet1_ns; int t_quiet2_ns; }; =20 @@ -129,54 +144,63 @@ struct ad4000_time_spec { */ static const struct ad4000_time_spec ad4000_t_spec =3D { .t_conv_ns =3D 320, + .t_quiet1_ns =3D 190, .t_quiet2_ns =3D 60, }; =20 /* AD4020, AD4021, AD4022 */ static const struct ad4000_time_spec ad4020_t_spec =3D { .t_conv_ns =3D 350, + .t_quiet1_ns =3D 200, .t_quiet2_ns =3D 60, }; =20 /* AD7983, AD7984 */ static const struct ad4000_time_spec ad7983_t_spec =3D { .t_conv_ns =3D 500, + .t_quiet1_ns =3D 0, .t_quiet2_ns =3D 0, }; =20 /* AD7980, AD7982 */ static const struct ad4000_time_spec ad7980_t_spec =3D { .t_conv_ns =3D 800, + .t_quiet1_ns =3D 0, .t_quiet2_ns =3D 0, }; =20 /* AD7946, AD7686, AD7688, AD7988-5, AD7693 */ static const struct ad4000_time_spec ad7686_t_spec =3D { .t_conv_ns =3D 1600, + .t_quiet1_ns =3D 0, .t_quiet2_ns =3D 0, }; =20 /* AD7690 */ static const struct ad4000_time_spec ad7690_t_spec =3D { .t_conv_ns =3D 2100, + .t_quiet1_ns =3D 0, .t_quiet2_ns =3D 0, }; =20 /* AD7942, AD7685, AD7687 */ static const struct ad4000_time_spec ad7687_t_spec =3D { .t_conv_ns =3D 3200, + .t_quiet1_ns =3D 0, .t_quiet2_ns =3D 0, }; =20 /* AD7691 */ static const struct ad4000_time_spec ad7691_t_spec =3D { .t_conv_ns =3D 3700, + .t_quiet1_ns =3D 0, .t_quiet2_ns =3D 0, }; =20 /* AD7988-1 */ static const struct ad4000_time_spec ad7988_1_t_spec =3D { .t_conv_ns =3D 9500, + .t_quiet1_ns =3D 0, .t_quiet2_ns =3D 0, }; =20 @@ -184,212 +208,299 @@ struct ad4000_chip_info { const char *dev_name; struct iio_chan_spec chan_spec[2]; struct iio_chan_spec reg_access_chan_spec[2]; + struct iio_chan_spec offload_chan_spec; + struct iio_chan_spec reg_access_offload_chan_spec; const struct ad4000_time_spec *time_spec; bool has_hardware_gain; + int max_rate_hz; }; =20 static const struct ad4000_chip_info ad4000_chip_info =3D { .dev_name =3D "ad4000", .chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 0), .reg_access_chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 1), + .offload_chan_spec =3D AD4000_PSEUDO_DIFF_CHANNEL('u', 16, 0, 1), + .reg_access_offload_chan_spec =3D AD4000_PSEUDO_DIFF_CHANNEL('u', 16, 1, = 1), .time_spec =3D &ad4000_t_spec, + .max_rate_hz =3D 2 * MEGA, }; =20 static const struct ad4000_chip_info ad4001_chip_info =3D { .dev_name =3D "ad4001", .chan_spec =3D AD4000_DIFF_CHANNELS('s', 16, 0), .reg_access_chan_spec =3D AD4000_DIFF_CHANNELS('s', 16, 1), + .offload_chan_spec =3D AD4000_DIFF_CHANNEL('s', 16, 0, 1), + .reg_access_offload_chan_spec =3D AD4000_DIFF_CHANNEL('s', 16, 1, 1), .time_spec =3D &ad4000_t_spec, + .max_rate_hz =3D 2 * MEGA, }; =20 static const struct ad4000_chip_info ad4002_chip_info =3D { .dev_name =3D "ad4002", .chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 18, 0), .reg_access_chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 18, 1), + .offload_chan_spec =3D AD4000_PSEUDO_DIFF_CHANNEL('u', 18, 0, 1), + .reg_access_offload_chan_spec =3D AD4000_PSEUDO_DIFF_CHANNEL('u', 18, 1, = 1), .time_spec =3D &ad4000_t_spec, + .max_rate_hz =3D 2 * MEGA, }; =20 static const struct ad4000_chip_info ad4003_chip_info =3D { .dev_name =3D "ad4003", .chan_spec =3D AD4000_DIFF_CHANNELS('s', 18, 0), .reg_access_chan_spec =3D AD4000_DIFF_CHANNELS('s', 18, 1), + .offload_chan_spec =3D AD4000_DIFF_CHANNEL('s', 18, 0, 1), + .reg_access_offload_chan_spec =3D AD4000_DIFF_CHANNEL('s', 18, 1, 1), .time_spec =3D &ad4000_t_spec, + .max_rate_hz =3D 2 * MEGA, }; =20 static const struct ad4000_chip_info ad4004_chip_info =3D { .dev_name =3D "ad4004", .chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 0), .reg_access_chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 1), + .offload_chan_spec =3D AD4000_PSEUDO_DIFF_CHANNEL('u', 16, 0, 1), + .reg_access_offload_chan_spec =3D AD4000_PSEUDO_DIFF_CHANNEL('u', 16, 1, = 1), .time_spec =3D &ad4000_t_spec, + .max_rate_hz =3D 1 * MEGA, }; =20 static const struct ad4000_chip_info ad4005_chip_info =3D { .dev_name =3D "ad4005", .chan_spec =3D AD4000_DIFF_CHANNELS('s', 16, 0), .reg_access_chan_spec =3D AD4000_DIFF_CHANNELS('s', 16, 1), + .offload_chan_spec =3D AD4000_DIFF_CHANNEL('s', 16, 0, 1), + .reg_access_offload_chan_spec =3D AD4000_DIFF_CHANNEL('s', 16, 1, 1), .time_spec =3D &ad4000_t_spec, + .max_rate_hz =3D 1 * MEGA, }; =20 static const struct ad4000_chip_info ad4006_chip_info =3D { .dev_name =3D "ad4006", .chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 18, 0), .reg_access_chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 18, 1), + .offload_chan_spec =3D AD4000_PSEUDO_DIFF_CHANNEL('u', 18, 0, 1), + .reg_access_offload_chan_spec =3D AD4000_PSEUDO_DIFF_CHANNEL('u', 18, 1, = 1), .time_spec =3D &ad4000_t_spec, + .max_rate_hz =3D 1 * MEGA, }; =20 static const struct ad4000_chip_info ad4007_chip_info =3D { .dev_name =3D "ad4007", .chan_spec =3D AD4000_DIFF_CHANNELS('s', 18, 0), .reg_access_chan_spec =3D AD4000_DIFF_CHANNELS('s', 18, 1), + .offload_chan_spec =3D AD4000_DIFF_CHANNEL('s', 18, 0, 1), + .reg_access_offload_chan_spec =3D AD4000_DIFF_CHANNEL('s', 18, 1, 1), .time_spec =3D &ad4000_t_spec, + .max_rate_hz =3D 1 * MEGA, }; =20 static const struct ad4000_chip_info ad4008_chip_info =3D { .dev_name =3D "ad4008", .chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 0), .reg_access_chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 1), + .offload_chan_spec =3D AD4000_PSEUDO_DIFF_CHANNEL('u', 16, 0, 1), + .reg_access_offload_chan_spec =3D AD4000_PSEUDO_DIFF_CHANNEL('u', 16, 1, = 1), .time_spec =3D &ad4000_t_spec, + .max_rate_hz =3D 500 * KILO, }; =20 static const struct ad4000_chip_info ad4010_chip_info =3D { .dev_name =3D "ad4010", .chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 18, 0), .reg_access_chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 18, 1), + .offload_chan_spec =3D AD4000_PSEUDO_DIFF_CHANNEL('u', 18, 0, 1), + .reg_access_offload_chan_spec =3D AD4000_PSEUDO_DIFF_CHANNEL('u', 18, 1, = 1), .time_spec =3D &ad4000_t_spec, + .max_rate_hz =3D 500 * KILO, }; =20 static const struct ad4000_chip_info ad4011_chip_info =3D { .dev_name =3D "ad4011", .chan_spec =3D AD4000_DIFF_CHANNELS('s', 18, 0), .reg_access_chan_spec =3D AD4000_DIFF_CHANNELS('s', 18, 1), + .offload_chan_spec =3D AD4000_DIFF_CHANNEL('s', 18, 0, 1), + .reg_access_offload_chan_spec =3D AD4000_DIFF_CHANNEL('s', 18, 1, 1), .time_spec =3D &ad4000_t_spec, + .max_rate_hz =3D 500 * KILO, }; =20 static const struct ad4000_chip_info ad4020_chip_info =3D { .dev_name =3D "ad4020", .chan_spec =3D AD4000_DIFF_CHANNELS('s', 20, 0), .reg_access_chan_spec =3D AD4000_DIFF_CHANNELS('s', 20, 1), + .offload_chan_spec =3D AD4000_DIFF_CHANNEL('s', 20, 0, 1), + .reg_access_offload_chan_spec =3D AD4000_DIFF_CHANNEL('s', 20, 1, 1), .time_spec =3D &ad4020_t_spec, + .max_rate_hz =3D 1800 * KILO, }; =20 static const struct ad4000_chip_info ad4021_chip_info =3D { .dev_name =3D "ad4021", .chan_spec =3D AD4000_DIFF_CHANNELS('s', 20, 0), .reg_access_chan_spec =3D AD4000_DIFF_CHANNELS('s', 20, 1), + .offload_chan_spec =3D AD4000_DIFF_CHANNEL('s', 20, 0, 1), + .reg_access_offload_chan_spec =3D AD4000_DIFF_CHANNEL('s', 20, 1, 1), .time_spec =3D &ad4020_t_spec, + .max_rate_hz =3D 1 * MEGA, }; =20 static const struct ad4000_chip_info ad4022_chip_info =3D { .dev_name =3D "ad4022", .chan_spec =3D AD4000_DIFF_CHANNELS('s', 20, 0), .reg_access_chan_spec =3D AD4000_DIFF_CHANNELS('s', 20, 1), + .offload_chan_spec =3D AD4000_DIFF_CHANNEL('s', 20, 0, 1), + .reg_access_offload_chan_spec =3D AD4000_DIFF_CHANNEL('s', 20, 1, 1), .time_spec =3D &ad4020_t_spec, + .max_rate_hz =3D 500 * KILO, }; =20 static const struct ad4000_chip_info adaq4001_chip_info =3D { .dev_name =3D "adaq4001", .chan_spec =3D AD4000_DIFF_CHANNELS('s', 16, 0), .reg_access_chan_spec =3D AD4000_DIFF_CHANNELS('s', 16, 1), + .offload_chan_spec =3D AD4000_DIFF_CHANNEL('s', 16, 0, 1), + .reg_access_offload_chan_spec =3D AD4000_DIFF_CHANNEL('s', 16, 1, 1), .time_spec =3D &ad4000_t_spec, .has_hardware_gain =3D true, + .max_rate_hz =3D 2 * MEGA, }; =20 static const struct ad4000_chip_info adaq4003_chip_info =3D { .dev_name =3D "adaq4003", .chan_spec =3D AD4000_DIFF_CHANNELS('s', 18, 0), .reg_access_chan_spec =3D AD4000_DIFF_CHANNELS('s', 18, 1), + .offload_chan_spec =3D AD4000_DIFF_CHANNEL('s', 18, 0, 1), + .reg_access_offload_chan_spec =3D AD4000_DIFF_CHANNEL('s', 18, 1, 1), .time_spec =3D &ad4000_t_spec, .has_hardware_gain =3D true, + .max_rate_hz =3D 2 * MEGA, }; =20 static const struct ad4000_chip_info ad7685_chip_info =3D { .dev_name =3D "ad7685", .chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 0), + .offload_chan_spec =3D AD4000_PSEUDO_DIFF_CHANNEL('u', 16, 0, 1), .time_spec =3D &ad7687_t_spec, + .max_rate_hz =3D 250 * KILO, }; =20 static const struct ad4000_chip_info ad7686_chip_info =3D { .dev_name =3D "ad7686", .chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 0), + .offload_chan_spec =3D AD4000_PSEUDO_DIFF_CHANNEL('u', 16, 0, 1), .time_spec =3D &ad7686_t_spec, + .max_rate_hz =3D 500 * KILO, }; =20 static const struct ad4000_chip_info ad7687_chip_info =3D { .dev_name =3D "ad7687", .chan_spec =3D AD4000_DIFF_CHANNELS('s', 16, 0), + .offload_chan_spec =3D AD4000_DIFF_CHANNEL('s', 16, 0, 1), .time_spec =3D &ad7687_t_spec, + .max_rate_hz =3D 250 * KILO, }; =20 static const struct ad4000_chip_info ad7688_chip_info =3D { .dev_name =3D "ad7688", .chan_spec =3D AD4000_DIFF_CHANNELS('s', 16, 0), + .offload_chan_spec =3D AD4000_DIFF_CHANNEL('s', 16, 0, 1), .time_spec =3D &ad7686_t_spec, + .max_rate_hz =3D 500 * KILO, }; =20 static const struct ad4000_chip_info ad7690_chip_info =3D { .dev_name =3D "ad7690", .chan_spec =3D AD4000_DIFF_CHANNELS('s', 18, 0), + .offload_chan_spec =3D AD4000_DIFF_CHANNEL('s', 18, 0, 1), .time_spec =3D &ad7690_t_spec, + .max_rate_hz =3D 400 * KILO, }; =20 static const struct ad4000_chip_info ad7691_chip_info =3D { .dev_name =3D "ad7691", .chan_spec =3D AD4000_DIFF_CHANNELS('s', 18, 0), + .offload_chan_spec =3D AD4000_DIFF_CHANNEL('s', 18, 0, 1), .time_spec =3D &ad7691_t_spec, + .max_rate_hz =3D 250 * KILO, }; =20 static const struct ad4000_chip_info ad7693_chip_info =3D { .dev_name =3D "ad7693", .chan_spec =3D AD4000_DIFF_CHANNELS('s', 16, 0), + .offload_chan_spec =3D AD4000_DIFF_CHANNEL('s', 16, 0, 1), .time_spec =3D &ad7686_t_spec, + .max_rate_hz =3D 500 * KILO, }; =20 static const struct ad4000_chip_info ad7942_chip_info =3D { .dev_name =3D "ad7942", .chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 14, 0), + .offload_chan_spec =3D AD4000_PSEUDO_DIFF_CHANNEL('u', 14, 0, 1), .time_spec =3D &ad7687_t_spec, + .max_rate_hz =3D 250 * KILO, }; =20 static const struct ad4000_chip_info ad7946_chip_info =3D { .dev_name =3D "ad7946", .chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 14, 0), + .offload_chan_spec =3D AD4000_PSEUDO_DIFF_CHANNEL('u', 14, 0, 1), .time_spec =3D &ad7686_t_spec, + .max_rate_hz =3D 500 * KILO, }; =20 static const struct ad4000_chip_info ad7980_chip_info =3D { .dev_name =3D "ad7980", .chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 0), + .offload_chan_spec =3D AD4000_PSEUDO_DIFF_CHANNEL('u', 16, 0, 1), .time_spec =3D &ad7980_t_spec, + .max_rate_hz =3D 1 * MEGA, }; =20 static const struct ad4000_chip_info ad7982_chip_info =3D { .dev_name =3D "ad7982", .chan_spec =3D AD4000_DIFF_CHANNELS('s', 18, 0), + .offload_chan_spec =3D AD4000_DIFF_CHANNEL('s', 18, 0, 1), .time_spec =3D &ad7980_t_spec, + .max_rate_hz =3D 1 * MEGA, }; =20 static const struct ad4000_chip_info ad7983_chip_info =3D { .dev_name =3D "ad7983", .chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 0), + .offload_chan_spec =3D AD4000_PSEUDO_DIFF_CHANNEL('u', 16, 0, 1), .time_spec =3D &ad7983_t_spec, + .max_rate_hz =3D 1 * MEGA + 333 * KILO + 333, + }; =20 static const struct ad4000_chip_info ad7984_chip_info =3D { .dev_name =3D "ad7984", .chan_spec =3D AD4000_DIFF_CHANNELS('s', 18, 0), + .offload_chan_spec =3D AD4000_DIFF_CHANNEL('s', 18, 0, 1), .time_spec =3D &ad7983_t_spec, + .max_rate_hz =3D 1 * MEGA + 333 * KILO + 333, }; =20 static const struct ad4000_chip_info ad7988_1_chip_info =3D { .dev_name =3D "ad7988-1", .chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 0), + .offload_chan_spec =3D AD4000_PSEUDO_DIFF_CHANNEL('u', 16, 0, 1), .time_spec =3D &ad7988_1_t_spec, + .max_rate_hz =3D 100 * KILO, }; =20 static const struct ad4000_chip_info ad7988_5_chip_info =3D { .dev_name =3D "ad7988-5", .chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 0), + .offload_chan_spec =3D AD4000_PSEUDO_DIFF_CHANNEL('u', 16, 0, 1), .time_spec =3D &ad7686_t_spec, + .max_rate_hz =3D 500 * KILO, +}; + +static const struct spi_offload_config ad4000_offload_config =3D { + .capability_flags =3D SPI_OFFLOAD_CAP_TRIGGER | + SPI_OFFLOAD_CAP_RX_STREAM_DMA, }; =20 struct ad4000_state { @@ -397,6 +508,13 @@ struct ad4000_state { struct gpio_desc *cnv_gpio; struct spi_transfer xfers[2]; struct spi_message msg; + struct spi_transfer offload_xfers[2]; + struct spi_message offload_msg; + struct spi_offload *offload; + struct spi_offload_trigger *offload_trigger; + bool using_offload; + unsigned long offload_trigger_hz; + int max_rate_hz; struct mutex lock; /* Protect read modify write cycle */ int vref_mv; enum ad4000_sdi sdi_pin; @@ -411,8 +529,10 @@ struct ad4000_state { */ struct { union { - __be16 sample_buf16; - __be32 sample_buf32; + __be16 sample_buf16_be; + __be32 sample_buf32_be; + u16 sample_buf16; + u32 sample_buf32; } data; aligned_s64 timestamp; } scan __aligned(IIO_DMA_MINALIGN); @@ -487,6 +607,25 @@ static int ad4000_read_reg(struct ad4000_state *st, un= signed int *val) return ret; } =20 +static int ad4000_set_sampling_freq(struct ad4000_state *st, int freq) +{ + struct spi_offload_trigger_config config =3D { + .type =3D SPI_OFFLOAD_TRIGGER_PERIODIC, + .periodic =3D { + .frequency_hz =3D freq, + }, + }; + int ret; + + ret =3D spi_offload_trigger_validate(st->offload_trigger, &config); + if (ret) + return ret; + + st->offload_trigger_hz =3D config.periodic.frequency_hz; + + return 0; +} + static int ad4000_convert_and_acquire(struct ad4000_state *st) { int ret; @@ -515,10 +654,17 @@ static int ad4000_single_conversion(struct iio_dev *i= ndio_dev, if (ret < 0) return ret; =20 - if (chan->scan_type.storagebits > 16) - sample =3D be32_to_cpu(st->scan.data.sample_buf32); - else - sample =3D be16_to_cpu(st->scan.data.sample_buf16); + if (chan->scan_type.endianness =3D=3D IIO_BE) { + if (chan->scan_type.realbits > 16) + sample =3D be32_to_cpu(st->scan.data.sample_buf32_be); + else + sample =3D be16_to_cpu(st->scan.data.sample_buf16_be); + } else { + if (chan->scan_type.realbits > 16) + sample =3D st->scan.data.sample_buf32; + else + sample =3D st->scan.data.sample_buf16; + } =20 sample >>=3D chan->scan_type.shift; =20 @@ -554,6 +700,9 @@ static int ad4000_read_raw(struct iio_dev *indio_dev, if (st->span_comp) *val =3D mult_frac(st->vref_mv, 1, 10); =20 + return IIO_VAL_INT; + case IIO_CHAN_INFO_SAMP_FREQ: + *val =3D st->offload_trigger_hz; return IIO_VAL_INT; default: return -EINVAL; @@ -620,6 +769,7 @@ static int ad4000_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int val, int val2, long mask) { + struct ad4000_state *st =3D iio_priv(indio_dev); int ret; =20 switch (mask) { @@ -629,6 +779,15 @@ static int ad4000_write_raw(struct iio_dev *indio_dev, ret =3D __ad4000_write_raw(indio_dev, chan, val2); iio_device_release_direct(indio_dev); return ret; + case IIO_CHAN_INFO_SAMP_FREQ: + if (val < 1 || val > st->max_rate_hz) + return -EINVAL; + + if (!iio_device_claim_direct(indio_dev)) + return -EBUSY; + ret =3D ad4000_set_sampling_freq(st, val); + iio_device_release_direct(indio_dev); + return ret; default: return -EINVAL; } @@ -659,10 +818,115 @@ static const struct iio_info ad4000_reg_access_info = =3D { .write_raw_get_fmt =3D &ad4000_write_raw_get_fmt, }; =20 +static const struct iio_info ad4000_offload_info =3D { + .read_raw =3D &ad4000_read_raw, + .write_raw =3D &ad4000_write_raw, + .write_raw_get_fmt =3D &ad4000_write_raw_get_fmt, +}; + static const struct iio_info ad4000_info =3D { .read_raw =3D &ad4000_read_raw, }; =20 +static int ad4000_offload_buffer_postenable(struct iio_dev *indio_dev) +{ + struct ad4000_state *st =3D iio_priv(indio_dev); + struct spi_offload_trigger_config config =3D { + .type =3D SPI_OFFLOAD_TRIGGER_PERIODIC, + .periodic =3D { + .frequency_hz =3D st->offload_trigger_hz, + }, + }; + + return spi_offload_trigger_enable(st->offload, st->offload_trigger, + &config); +} + +static int ad4000_offload_buffer_predisable(struct iio_dev *indio_dev) +{ + struct ad4000_state *st =3D iio_priv(indio_dev); + + spi_offload_trigger_disable(st->offload, st->offload_trigger); + + return 0; +} + +static const struct iio_buffer_setup_ops ad4000_offload_buffer_setup_ops = =3D { + .postenable =3D &ad4000_offload_buffer_postenable, + .predisable =3D &ad4000_offload_buffer_predisable, +}; + +static int ad4000_spi_offload_setup(struct iio_dev *indio_dev, + struct ad4000_state *st) +{ + struct spi_device *spi =3D st->spi; + struct device *dev =3D &spi->dev; + struct dma_chan *rx_dma; + int ret; + + st->offload_trigger =3D devm_spi_offload_trigger_get(dev, st->offload, + SPI_OFFLOAD_TRIGGER_PERIODIC); + if (IS_ERR(st->offload_trigger)) + return dev_err_probe(dev, PTR_ERR(st->offload_trigger), + "Failed to get offload trigger\n"); + + ret =3D ad4000_set_sampling_freq(st, st->max_rate_hz); + if (ret) + return dev_err_probe(dev, ret, + "Failed to set sampling frequency\n"); + + rx_dma =3D devm_spi_offload_rx_stream_request_dma_chan(dev, st->offload); + if (IS_ERR(rx_dma)) + return dev_err_probe(dev, PTR_ERR(rx_dma), + "Failed to get offload RX DMA\n"); + + ret =3D devm_iio_dmaengine_buffer_setup_with_handle(dev, indio_dev, rx_dm= a, + IIO_BUFFER_DIRECTION_IN); + if (ret) + return dev_err_probe(dev, ret, "Failed to setup DMA buffer\n"); + + return 0; +} + +/* + * This executes a data sample transfer when using SPI offloading for when= the + * device connections are in "3-wire" mode, selected when the adi,sdi-pin = device + * tree property is set to "high". In this connection mode, the ADC SDI pi= n is + * connected to VIO and ADC CNV pin is connected to a SPI controller CS (it + * can't be connected to a GPIO). + * + * In order to achieve the maximum sample rate, we only do one transfer per + * SPI offload trigger. Because the ADC output has a one sample latency (d= elay) + * when the device is wired in "3-wire" mode and only one transfer per sam= ple is + * being made in turbo mode, the first data sample is not valid because it + * contains the output of an earlier conversion result. We also set transf= er + * `bits_per_word` to achieve higher throughput by using the minimum numbe= r of + * SCLK cycles. Also, a delay is added to make sure we meet the minimum qu= iet + * time before releasing the CS line. + * + * Note that, with `bits_per_word` set to the number of ADC precision bits, + * transfers use larger word sizes that get stored in 'in-memory wordsizes= ' that + * are always in native CPU byte order. Because of that, IIO buffer elemen= ts + * ought to be read in CPU endianness which requires setting IIO scan_type + * endianness accordingly (i.e. IIO_CPU). + */ +static int ad4000_prepare_offload_message(struct ad4000_state *st, + const struct iio_chan_spec *chan) +{ + struct spi_transfer *xfers =3D st->offload_xfers; + + xfers[0].bits_per_word =3D chan->scan_type.realbits; + xfers[0].len =3D chan->scan_type.realbits > 16 ? 4 : 2; + xfers[0].delay.value =3D st->time_spec->t_quiet2_ns; + xfers[0].delay.unit =3D SPI_DELAY_UNIT_NSECS; + xfers[0].offload_flags =3D SPI_OFFLOAD_XFER_RX_STREAM; + + spi_message_init_with_transfers(&st->offload_msg, xfers, 1); + st->offload_msg.offload =3D st->offload; + + return devm_spi_optimize_message(&st->spi->dev, st->spi, &st->offload_msg= ); +} + /* * This executes a data sample transfer for when the device connections are * in "3-wire" mode, selected when the adi,sdi-pin device tree property is @@ -690,6 +954,15 @@ static int ad4000_prepare_3wire_mode_message(struct ad= 4000_state *st, =20 xfers[1].rx_buf =3D &st->scan.data; xfers[1].len =3D BITS_TO_BYTES(chan->scan_type.storagebits); + + /* + * If the device is set up for SPI offloading, IIO channel scan_type is + * set to IIO_CPU. When that is the case, use larger SPI word sizes for + * single-shot reads too. Thus, sample data can be correctly handled in + * ad4000_single_conversion() according to scan_type endianness. + */ + if (chan->scan_type.endianness !=3D IIO_BE) + xfers[1].bits_per_word =3D chan->scan_type.realbits; xfers[1].delay.value =3D st->time_spec->t_quiet2_ns; xfers[1].delay.unit =3D SPI_DELAY_UNIT_NSECS; =20 @@ -733,6 +1006,9 @@ static int ad4000_config(struct ad4000_state *st) if (device_property_present(&st->spi->dev, "adi,high-z-input")) reg_val |=3D FIELD_PREP(AD4000_CFG_HIGHZ, 1); =20 + if (st->using_offload) + reg_val |=3D FIELD_PREP(AD4000_CFG_TURBO, 1); + return ad4000_write_reg(st, reg_val); } =20 @@ -755,6 +1031,7 @@ static int ad4000_probe(struct spi_device *spi) st =3D iio_priv(indio_dev); st->spi =3D spi; st->time_spec =3D chip->time_spec; + st->max_rate_hz =3D chip->max_rate_hz; =20 ret =3D devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(ad4000_power_suppl= ies), ad4000_power_supplies); @@ -772,6 +1049,26 @@ static int ad4000_probe(struct spi_device *spi) return dev_err_probe(dev, PTR_ERR(st->cnv_gpio), "Failed to get CNV GPIO"); =20 + st->offload =3D devm_spi_offload_get(dev, spi, &ad4000_offload_config); + ret =3D PTR_ERR_OR_ZERO(st->offload); + if (ret && ret !=3D -ENODEV) + return dev_err_probe(dev, ret, "Failed to get offload\n"); + + st->using_offload =3D !IS_ERR(st->offload); + if (st->using_offload) { + indio_dev->setup_ops =3D &ad4000_offload_buffer_setup_ops; + ret =3D ad4000_spi_offload_setup(indio_dev, st); + if (ret) + return ret; + } else { + ret =3D devm_iio_triggered_buffer_setup(dev, indio_dev, + &iio_pollfunc_store_time, + &ad4000_trigger_handler, + NULL); + if (ret) + return ret; + } + ret =3D device_property_match_property_string(dev, "adi,sdi-pin", ad4000_sdi_pin, ARRAY_SIZE(ad4000_sdi_pin)); @@ -784,7 +1081,10 @@ static int ad4000_probe(struct spi_device *spi) switch (st->sdi_pin) { case AD4000_SDI_MOSI: indio_dev->info =3D &ad4000_reg_access_info; - indio_dev->channels =3D chip->reg_access_chan_spec; + + /* Set CNV/CS high time for when turbo mode is used */ + spi->cs_inactive.value =3D st->time_spec->t_quiet1_ns; + spi->cs_inactive.unit =3D SPI_DELAY_UNIT_NSECS; =20 /* * In "3-wire mode", the ADC SDI line must be kept high when @@ -796,9 +1096,26 @@ static int ad4000_probe(struct spi_device *spi) if (ret < 0) return ret; =20 + if (st->using_offload) { + indio_dev->channels =3D &chip->reg_access_offload_chan_spec; + indio_dev->num_channels =3D 1; + ret =3D ad4000_prepare_offload_message(st, indio_dev->channels); + if (ret) + return dev_err_probe(dev, ret, + "Failed to optimize SPI msg\n"); + } else { + indio_dev->channels =3D chip->reg_access_chan_spec; + indio_dev->num_channels =3D ARRAY_SIZE(chip->reg_access_chan_spec); + } + + /* + * Call ad4000_prepare_3wire_mode_message() so single-shot read + * SPI messages are always initialized. + */ ret =3D ad4000_prepare_3wire_mode_message(st, &indio_dev->channels[0]); if (ret) - return ret; + return dev_err_probe(dev, ret, + "Failed to optimize SPI msg\n"); =20 ret =3D ad4000_config(st); if (ret < 0) @@ -806,19 +1123,47 @@ static int ad4000_probe(struct spi_device *spi) =20 break; case AD4000_SDI_VIO: - indio_dev->info =3D &ad4000_info; - indio_dev->channels =3D chip->chan_spec; + if (st->using_offload) { + indio_dev->info =3D &ad4000_offload_info; + indio_dev->channels =3D &chip->offload_chan_spec; + indio_dev->num_channels =3D 1; + + /* Set CNV/CS high time for when turbo mode is not used */ + if (!st->cnv_gpio) { + spi->cs_inactive.value =3D st->time_spec->t_conv_ns; + spi->cs_inactive.unit =3D SPI_DELAY_UNIT_NSECS; + ret =3D spi_setup(spi); + if (ret < 0) + return ret; + } + + ret =3D ad4000_prepare_offload_message(st, indio_dev->channels); + if (ret) + return dev_err_probe(dev, ret, + "Failed to optimize SPI msg\n"); + } else { + indio_dev->info =3D &ad4000_info; + indio_dev->channels =3D chip->chan_spec; + indio_dev->num_channels =3D ARRAY_SIZE(chip->chan_spec); + } + ret =3D ad4000_prepare_3wire_mode_message(st, &indio_dev->channels[0]); if (ret) - return ret; + return dev_err_probe(dev, ret, + "Failed to optimize SPI msg\n"); =20 break; case AD4000_SDI_CS: + if (st->using_offload) + return dev_err_probe(dev, -EPROTONOSUPPORT, + "Unsupported sdi-pin + offload config\n"); indio_dev->info =3D &ad4000_info; indio_dev->channels =3D chip->chan_spec; + indio_dev->num_channels =3D ARRAY_SIZE(chip->chan_spec); ret =3D ad4000_prepare_4wire_mode_message(st, &indio_dev->channels[0]); if (ret) - return ret; + return dev_err_probe(dev, ret, + "Failed to optimize SPI msg\n"); =20 break; case AD4000_SDI_GND: @@ -830,7 +1175,6 @@ static int ad4000_probe(struct spi_device *spi) } =20 indio_dev->name =3D chip->dev_name; - indio_dev->num_channels =3D 2; =20 ret =3D devm_mutex_init(dev, &st->lock); if (ret) @@ -853,12 +1197,6 @@ static int ad4000_probe(struct spi_device *spi) =20 ad4000_fill_scale_tbl(st, &indio_dev->channels[0]); =20 - ret =3D devm_iio_triggered_buffer_setup(dev, indio_dev, - &iio_pollfunc_store_time, - &ad4000_trigger_handler, NULL); - if (ret) - return ret; - return devm_iio_device_register(dev, indio_dev); } =20 @@ -947,3 +1285,4 @@ module_spi_driver(ad4000_driver); MODULE_AUTHOR("Marcelo Schmitt "); MODULE_DESCRIPTION("Analog Devices AD4000 ADC driver"); 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charset="utf-8" Commit ("iio: adc: ad4000: Add support for PulSAR devices"), extended the ad4000 driver supports many single-channel PulSAR devices. Update IIO ad4000 documentation with the extra list of supported devices. Signed-off-by: Marcelo Schmitt Reviewed-by: David Lechner --- Documentation/iio/ad4000.rst | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/Documentation/iio/ad4000.rst b/Documentation/iio/ad4000.rst index de8fd3ae6e62..5578a9cfd9d5 100644 --- a/Documentation/iio/ad4000.rst +++ b/Documentation/iio/ad4000.rst @@ -4,7 +4,7 @@ AD4000 driver =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 -Device driver for Analog Devices Inc. AD4000 series of ADCs. +Device driver for Analog Devices Inc. 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charset="utf-8" Complement ad4000 IIO driver documentation with considerations about ``_scale_available`` attribute and table of typical channel attributes. Signed-off-by: Marcelo Schmitt Reviewed-by: David Lechner --- Documentation/iio/ad4000.rst | 47 ++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/Documentation/iio/ad4000.rst b/Documentation/iio/ad4000.rst index 5578a9cfd9d5..468d30dc9214 100644 --- a/Documentation/iio/ad4000.rst +++ b/Documentation/iio/ad4000.rst @@ -144,3 +144,50 @@ Set ``adi,sdi-pin`` to ``"cs"`` to select this mode. ^ | | +--------------------| SCLK | +-------------+ + +IIO Device characteristics +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D + +The AD4000 series driver supports differential and pseudo-differential ADC= s. + +The span compression feature available in AD4000 series devices can be +enabled/disabled by changing the ``_scale_available`` attribute of the vol= tage +channel. Note that span compression configuration requires writing to AD40= 00 +configuration register, which is only possible when the ADC is wired in 3-= wire +turbo mode, and the SPI controller is ``SPI_MOSI_IDLE_HIGH`` capable. If t= hose +conditions are not met, no ``_scale_available`` attribute is provided. + +Besides that, differential and pseudo-differential voltage channels present +slightly different sysfs interfaces. + +Pseudo-differential ADCs +------------------------ + +Typical voltage channel attributes of a pseudo-differential AD4000 series = device: + ++-------------------------------------------+-----------------------------= -------------+ +| Voltage Channel Attributes | Description = | ++=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+ +| ``in_voltage0_raw`` | Raw ADC output code. = | ++-------------------------------------------+-----------------------------= -------------+ +| ``in_voltage0_offset`` | Offset to convert raw value = to mV. | ++-------------------------------------------+-----------------------------= -------------+ +| ``in_voltage0_scale`` | Scale factor to convert raw = value to mV. | ++-------------------------------------------+-----------------------------= -------------+ +| ``in_voltage0_scale_available`` | Toggles input span compressi= on | ++-------------------------------------------+-----------------------------= -------------+ + +Differential ADCs +----------------- + +Typical voltage channel attributes of a differential AD4000 series device: + ++-------------------------------------------+-----------------------------= -------------+ +| Voltage Channel Attributes | Description = | ++=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+ +| ``in_voltage0-voltage1_raw`` | Raw ADC output code. = | ++-------------------------------------------+-----------------------------= -------------+ +| ``in_voltage0-voltage1_scale`` | Scale factor to convert raw = value to mV. | ++-------------------------------------------+-----------------------------= -------------+ +| ``in_voltage0-voltage1_scale_available`` | Toggles input span compressi= on | ++-------------------------------------------+-----------------------------= -------------+ --=20 2.47.2 From nobody Wed Dec 17 05:26:35 2025 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DF0981E1E0E; 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Wed, 26 Mar 2025 09:26:01 -0400 From: Marcelo Schmitt To: , , CC: , , , , , Subject: [PATCH v3 4/4] Documentation: iio: ad4000: Describe offload support Date: Wed, 26 Mar 2025 10:25:57 -0300 Message-ID: <92b7db8eddce5b11476352405ed7695107ba7745.1742992305.git.marcelo.schmitt@analog.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-GUID: MoW91kgA5apYGZGc_Wz7L-ZCjARooGXc X-Proofpoint-ORIG-GUID: MoW91kgA5apYGZGc_Wz7L-ZCjARooGXc X-Authority-Analysis: v=2.4 cv=IuAecK/g c=1 sm=1 tr=0 ts=67e40074 cx=c_pps a=PpDZqlmH/M8setHirZLBMw==:117 a=PpDZqlmH/M8setHirZLBMw==:17 a=Vs1iUdzkB0EA:10 a=wI1k2SEZAAAA:8 a=gAnH3GRIAAAA:8 a=zhJGIpXlanaEhhhmQREA:9 a=6HWbV-4b7c7AdzY24d_u:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-26_06,2025-03-26_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 malwarescore=0 impostorscore=0 clxscore=1015 lowpriorityscore=0 priorityscore=1501 phishscore=0 spamscore=0 adultscore=0 bulkscore=0 mlxlogscore=999 mlxscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2503260082 Content-Type: text/plain; charset="utf-8" When SPI offloading is supported, the IIO device provides different sysfs interfaces to allow using the adjusting the sample rate. Document SPI offload support for AD4000 and similar devices. Signed-off-by: Marcelo Schmitt Reviewed-by: David Lechner --- Documentation/iio/ad4000.rst | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/Documentation/iio/ad4000.rst b/Documentation/iio/ad4000.rst index 468d30dc9214..e490f9604b94 100644 --- a/Documentation/iio/ad4000.rst +++ b/Documentation/iio/ad4000.rst @@ -191,3 +191,25 @@ Typical voltage channel attributes of a differential A= D4000 series device: +-------------------------------------------+-----------------------------= -------------+ | ``in_voltage0-voltage1_scale_available`` | Toggles input span compressi= on | +-------------------------------------------+-----------------------------= -------------+ + +SPI offload support +------------------- + +To be able to achieve the maximum sample rate, the driver can be used with= the +`AXI SPI Engine`_ to provide SPI offload support. + +.. _AXI SPI Engine: http://analogdevicesinc.github.io/hdl/projects/pulsar_= adc/index.html + +When set for SPI offload support, the IIO device will provide different +interfaces. + +* Either ``in_voltage0_sampling_frequency`` or + ``in_voltage0-voltage1_sampling_frequency`` file is provided to allow se= tting + the sample rate. +* IIO trigger device is not provided (no ``trigger`` directory). +* ``timestamp`` channel is not provided. + +Also, because the ADC output has a one sample latency (delay) when the dev= ice is +wired in "3-wire" mode and only one transfer per sample is done when using= SPI +offloading, the first data sample in the buffer is not valid because it co= ntains +the output of an earlier conversion result. --=20 2.47.2