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Thu, 13 Mar 2025 04:41:03 -0700 (PDT) Received: from mva-rohm ([2a10:a5c0:800d:dd00:8fdf:935a:2c85:d703]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-549ba8a702asm182306e87.212.2025.03.13.04.41.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Mar 2025 04:41:01 -0700 (PDT) Date: Thu, 13 Mar 2025 13:40:57 +0200 From: Matti Vaittinen To: Matti Vaittinen , Matti Vaittinen Cc: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liam Girdwood , Mark Brown , Matti Vaittinen , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 01/14] dt-bindings: regulator: Add ROHM BD96802 PMIC Message-ID: <93b7b5ba885328301242b8ef708db92c24e50132.1741864404.git.mazziesaccount@gmail.com> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="OlLCymbnSnZA6bsA" Content-Disposition: inline In-Reply-To: --OlLCymbnSnZA6bsA Content-Disposition: inline Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" BD96802Qxx-C is an automotive grade configurable Power Management Integrated Circuit supporting Functional Safety features for application processors, SoCs and FPGAs. BD96802 is controlled via I2C, provides two interrupt lines and has two controllable buck regulators. The BD96802 belongs to the family of ROHM Scalable PMICs and is intended to be used as a companion PMIC for the BD96801. Signed-off-by: Matti Vaittinen --- .../regulator/rohm,bd96802-regulator.yaml | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 Documentation/devicetree/bindings/regulator/rohm,bd9680= 2-regulator.yaml diff --git a/Documentation/devicetree/bindings/regulator/rohm,bd96802-regul= ator.yaml b/Documentation/devicetree/bindings/regulator/rohm,bd96802-regula= tor.yaml new file mode 100644 index 000000000000..671eaf1096d3 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/rohm,bd96802-regulator.ya= ml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/rohm,bd96802-regulator.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ROHM BD96802 Power Management Integrated Circuit regulators + +maintainers: + - Matti Vaittinen + +description: + This module is part of the ROHM BD96802 MFD device. For more details + see Documentation/devicetree/bindings/mfd/rohm,bd96802-pmic.yaml. + + The regulator controller is represented as a sub-node of the PMIC node + on the device tree. + + Regulator nodes should be named to buck1 and buck2. + +patternProperties: + "^buck[1-2]$": + type: object + description: + Properties for single BUCK regulator. + $ref: regulator.yaml# + + properties: + rohm,initial-voltage-microvolt: + description: + Initial voltage for regulator. Voltage can be tuned +/-150 mV fr= om + this value. NOTE, This can be modified via I2C only when PMIC is= in + STBY state. + minimum: 500000 + maximum: 3300000 + + rohm,keep-on-stby: + description: + Keep the regulator powered when PMIC transitions to STBY state. + type: boolean + + unevaluatedProperties: false + +additionalProperties: false --=20 2.48.1 --OlLCymbnSnZA6bsA Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQEzBAEBCAAdFiEEIx+f8wZb28fLKEhTeFA3/03aocUFAmfSxEkACgkQeFA3/03a ocV9eAf/YTGOqr0nkHr0qsRRN434dd/2sFINmLhSvGMVVdZB01nhPsod1b6aYBJN kQb/p7xUWp60jitnFYmRExBdu8JJH4kZiLsST7PYD6Goin777QPEwZLMLH0LCZrp nOTHbA7aYlZE//fhrg2cMADGjSLaID6ySF+vYdKbq6hsj7YXKd+bjEtpHcG8dBQi 8k7XzCK6OqTNErbZNIfmt8H6+UtF4Yi1hzgBFd2NQD2fZpeFQKGk7Fp/UuHh7BNP GNK3E3mxUuAdziwKgpgFZ4rm+U2PwpAxblmPYIhKUqUbE4tXuzP11kYPEMCE9AUD 7wqWt7lNMZHwyPlDulzgFyxNJWzvYA== =+NW0 -----END PGP SIGNATURE----- --OlLCymbnSnZA6bsA-- From nobody Thu Dec 18 07:09:44 2025 Received: from mail-lf1-f45.google.com (mail-lf1-f45.google.com [209.85.167.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0DC3C267B93; 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charset="utf-8" BD96802Qxx-C is an automotive grade configurable Power Management Integrated Circuit supporting Functional Safety features for application processors, SoCs and FPGAs. BD96802 is controlled via I2C, provides two interrupt lines and has two controllable buck regulators. Signed-off-by: Matti Vaittinen --- .../bindings/mfd/rohm,bd96802-pmic.yaml | 100 ++++++++++++++++++ 1 file changed, 100 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/rohm,bd96802-pmic= .yaml diff --git a/Documentation/devicetree/bindings/mfd/rohm,bd96802-pmic.yaml b= /Documentation/devicetree/bindings/mfd/rohm,bd96802-pmic.yaml new file mode 100644 index 000000000000..d5d9e69dc0c2 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/rohm,bd96802-pmic.yaml @@ -0,0 +1,100 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/rohm,bd96802-pmic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ROHM BD96802 Scalable Power Management Integrated Circuit + +maintainers: + - Matti Vaittinen + +description: | + BD96802Qxx-C is an automotive grade configurable Power Management + Integrated Circuit supporting Functional Safety features for application + processors, SoCs and FPGAs + +properties: + compatible: + const: rohm,bd96802 + + reg: + description: + I2C slave address. + maxItems: 1 + + interrupts: + description: + The PMIC provides intb and errb IRQ lines. The errb IRQ line is used + for fatal IRQs which will cause the PMIC to shut down power outputs. + In many systems this will shut down the SoC contolling the PMIC and + connecting/handling the errb can be omitted. However, there are cases + where the SoC is not powered by the PMIC. In that case it may be + useful to connect the errb and handle errb events. + minItems: 1 + maxItems: 2 + + interrupt-names: + minItems: 1 + items: + - enum: [intb, errb] + - const: errb + + regulators: + $ref: ../regulator/rohm,bd96802-regulator.yaml + description: + List of child nodes that specify the regulators. + +required: + - compatible + - reg + - interrupts + - interrupt-names + - regulators + +additionalProperties: false + +examples: + - | + #include + #include + i2c { + #address-cells =3D <1>; + #size-cells =3D <0>; + pmic: pmic@62 { + reg =3D <0x62>; + compatible =3D "rohm,bd96802"; + interrupt-parent =3D <&gpio1>; + interrupts =3D <29 IRQ_TYPE_LEVEL_LOW>, <6 IRQ_TYPE_LEVEL_LOW>; + interrupt-names =3D "intb", "errb"; + + regulators { + buck1: BUCK1 { + regulator-name =3D "buck1"; + regulator-ramp-delay =3D <1250>; + /* 0.5V min INITIAL - 150 mV tune */ + regulator-min-microvolt =3D <350000>; + /* 3.3V + 150mV tune */ + regulator-max-microvolt =3D <3450000>; + + /* These can be set only when PMIC is in STBY */ + rohm,initial-voltage-microvolt =3D <500000>; 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Thu, 13 Mar 2025 04:41:29 -0700 (PDT) Received: from mva-rohm ([2a10:a5c0:800d:dd00:8fdf:935a:2c85:d703]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-30c3f10ab4bsm1824541fa.50.2025.03.13.04.41.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Mar 2025 04:41:28 -0700 (PDT) Date: Thu, 13 Mar 2025 13:41:23 +0200 From: Matti Vaittinen To: Matti Vaittinen , Matti Vaittinen Cc: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liam Girdwood , Mark Brown , Matti Vaittinen , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 03/14] dt-bindings: mfd: bd96801: Add ROHM BD96805 Message-ID: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="OkcJcVLHHY7swm7U" Content-Disposition: inline In-Reply-To: --OkcJcVLHHY7swm7U Content-Disposition: inline Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The ROHM BD96805 is very similar to the BD96801. The differences visible to the drivers is different tune voltage ranges. Add compatible for the ROHM BD96805 PMIC. Signed-off-by: Matti Vaittinen --- .../devicetree/bindings/mfd/rohm,bd96801-pmic.yaml | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/mfd/rohm,bd96801-pmic.yaml b= /Documentation/devicetree/bindings/mfd/rohm,bd96801-pmic.yaml index efee3de0d9ad..0e06570483ae 100644 --- a/Documentation/devicetree/bindings/mfd/rohm,bd96801-pmic.yaml +++ b/Documentation/devicetree/bindings/mfd/rohm,bd96801-pmic.yaml @@ -4,19 +4,21 @@ $id: http://devicetree.org/schemas/mfd/rohm,bd96801-pmic.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: ROHM BD96801 Scalable Power Management Integrated Circuit +title: ROHM BD96801/BD96805 Scalable Power Management Integrated Circuit =20 maintainers: - Matti Vaittinen =20 description: - BD96801 is an automotive grade single-chip power management IC. - It integrates 4 buck converters and 3 LDOs with safety features like + BD96801 and BD96805 are automotive grade, single-chip power management I= Cs. + They both integrate 4 buck converters and 3 LDOs with safety features li= ke over-/under voltage and over current detection and a watchdog. =20 properties: compatible: - const: rohm,bd96801 + enum: + - rohm,bd96801 + - rohm,bd96805 =20 reg: maxItems: 1 --=20 2.48.1 --OkcJcVLHHY7swm7U Content-Type: application/pgp-signature; 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Thu, 13 Mar 2025 04:41:40 -0700 (PDT) Received: from mva-rohm ([2a10:a5c0:800d:dd00:8fdf:935a:2c85:d703]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-549ba864e01sm187376e87.112.2025.03.13.04.41.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Mar 2025 04:41:39 -0700 (PDT) Date: Thu, 13 Mar 2025 13:41:35 +0200 From: Matti Vaittinen To: Matti Vaittinen , Matti Vaittinen Cc: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liam Girdwood , Mark Brown , Matti Vaittinen , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 04/14] dt-bindings: mfd: bd96802: Add ROHM BD96806 Message-ID: <40a47b9ab61e9092bc16747b8e92ba0ce44fb1ac.1741864404.git.mazziesaccount@gmail.com> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="lOj8NaVvEWD5XEyi" Content-Disposition: inline In-Reply-To: --lOj8NaVvEWD5XEyi Content-Disposition: inline Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The ROHM BD96806 is very similar to the BD96802. The differences visible to the drivers is different tune voltage ranges. Add compatible for the ROHM BD96805 PMIC. Signed-off-by: Matti Vaittinen --- .../bindings/mfd/rohm,bd96802-pmic.yaml | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/mfd/rohm,bd96802-pmic.yaml b= /Documentation/devicetree/bindings/mfd/rohm,bd96802-pmic.yaml index d5d9e69dc0c2..c6e6be4015b2 100644 --- a/Documentation/devicetree/bindings/mfd/rohm,bd96802-pmic.yaml +++ b/Documentation/devicetree/bindings/mfd/rohm,bd96802-pmic.yaml @@ -4,23 +4,23 @@ $id: http://devicetree.org/schemas/mfd/rohm,bd96802-pmic.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: ROHM BD96802 Scalable Power Management Integrated Circuit +title: ROHM BD96802 / BD96806Scalable Power Management Integrated Circuit =20 maintainers: - Matti Vaittinen =20 description: | - BD96802Qxx-C is an automotive grade configurable Power Management - Integrated Circuit supporting Functional Safety features for application + BD96802Qxx-C and BD96806 are automotive grade configurable Power Managem= ent + Integrated Circuits supporting Functional Safety features for application processors, SoCs and FPGAs =20 properties: compatible: - const: rohm,bd96802 + enum: + - rohm,bd96802 + - rohm,bd96806 =20 reg: - description: - I2C slave address. maxItems: 1 =20 interrupts: @@ -29,7 +29,8 @@ properties: for fatal IRQs which will cause the PMIC to shut down power outputs. In many systems this will shut down the SoC contolling the PMIC and connecting/handling the errb can be omitted. However, there are cases - where the SoC is not powered by the PMIC. In that case it may be + where the SoC is not powered by the PMIC or has a short time backup + energy to handle shutdown of critical hardware. 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Thu, 13 Mar 2025 04:41:52 -0700 (PDT) Received: from mva-rohm ([2a10:a5c0:800d:dd00:8fdf:935a:2c85:d703]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-30c3f100c39sm1855861fa.48.2025.03.13.04.41.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Mar 2025 04:41:50 -0700 (PDT) Date: Thu, 13 Mar 2025 13:41:47 +0200 From: Matti Vaittinen To: Matti Vaittinen , Matti Vaittinen Cc: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liam Girdwood , Mark Brown , Matti Vaittinen , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 05/14] mfd: rohm-bd96801: Add chip info Message-ID: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="Xni6nKO7BxNC7pNi" Content-Disposition: inline In-Reply-To: --Xni6nKO7BxNC7pNi Content-Disposition: inline Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Prepare for adding support for BD96802 which is very similar to BD96801. Separate chip specific data into own structure which can be picked to be used by the device-tree. Signed-off-by: Matti Vaittinen --- drivers/mfd/rohm-bd96801.c | 83 ++++++++++++++++++++++++++------------ 1 file changed, 57 insertions(+), 26 deletions(-) diff --git a/drivers/mfd/rohm-bd96801.c b/drivers/mfd/rohm-bd96801.c index 60ec8db790a7..1232f571e4b1 100644 --- a/drivers/mfd/rohm-bd96801.c +++ b/drivers/mfd/rohm-bd96801.c @@ -40,7 +40,21 @@ #include #include =20 -static const struct resource regulator_errb_irqs[] =3D { +struct bd968xx_chip_data { + const struct resource *errb_irqs; + const struct resource *intb_irqs; + int num_errb_irqs; + int num_intb_irqs; + const struct regmap_irq_chip *errb_irq_chip; + const struct regmap_irq_chip *intb_irq_chip; + const struct regmap_config *regmap_config; + struct mfd_cell *cells; + int num_cells; + int unlock_reg; + int unlock_val; +}; + +static const struct resource bd96801_reg_errb_irqs[] =3D { DEFINE_RES_IRQ_NAMED(BD96801_OTP_ERR_STAT, "bd96801-otp-err"), DEFINE_RES_IRQ_NAMED(BD96801_DBIST_ERR_STAT, "bd96801-dbist-err"), DEFINE_RES_IRQ_NAMED(BD96801_EEP_ERR_STAT, "bd96801-eep-err"), @@ -98,7 +112,7 @@ static const struct resource regulator_errb_irqs[] =3D { DEFINE_RES_IRQ_NAMED(BD96801_LDO7_SHDN_ERR_STAT, "bd96801-ldo7-shdn-err"), }; =20 -static const struct resource regulator_intb_irqs[] =3D { +static const struct resource bd96801_reg_intb_irqs[] =3D { DEFINE_RES_IRQ_NAMED(BD96801_TW_STAT, "bd96801-core-thermal"), =20 DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_OCPH_STAT, "bd96801-buck1-overcurr-h"), @@ -345,18 +359,37 @@ static const struct regmap_config bd96801_regmap_conf= ig =3D { .cache_type =3D REGCACHE_MAPLE, }; =20 +static const struct bd968xx_chip_data bd96801_chip_data =3D { + .errb_irqs =3D bd96801_reg_errb_irqs, + .intb_irqs =3D bd96801_reg_intb_irqs, + .num_errb_irqs =3D ARRAY_SIZE(bd96801_reg_errb_irqs), + .num_intb_irqs =3D ARRAY_SIZE(bd96801_reg_intb_irqs), + .errb_irq_chip =3D &bd96801_irq_chip_errb, + .intb_irq_chip =3D &bd96801_irq_chip_intb, + .regmap_config =3D &bd96801_regmap_config, + .cells =3D bd96801_cells, + .num_cells =3D ARRAY_SIZE(bd96801_cells), + .unlock_reg =3D BD96801_LOCK_REG, + .unlock_val =3D BD96801_UNLOCK, +}; + static int bd96801_i2c_probe(struct i2c_client *i2c) { struct regmap_irq_chip_data *intb_irq_data, *errb_irq_data; struct irq_domain *intb_domain, *errb_domain; + static const struct bd968xx_chip_data *cd; const struct fwnode_handle *fwnode; struct resource *regulator_res; struct resource wdg_irq; struct regmap *regmap; - int intb_irq, errb_irq, num_intb, num_errb =3D 0; + int intb_irq, errb_irq, num_errb =3D 0; int num_regu_irqs, wdg_irq_no; int i, ret; =20 + cd =3D device_get_match_data(&i2c->dev); + if (!cd) + return -ENODEV; + fwnode =3D dev_fwnode(&i2c->dev); if (!fwnode) return dev_err_probe(&i2c->dev, -EINVAL, "Failed to find fwnode\n"); @@ -365,34 +398,32 @@ static int bd96801_i2c_probe(struct i2c_client *i2c) if (intb_irq < 0) return dev_err_probe(&i2c->dev, intb_irq, "INTB IRQ not configured\n"); =20 - num_intb =3D ARRAY_SIZE(regulator_intb_irqs); - /* ERRB may be omitted if processor is powered by the PMIC */ errb_irq =3D fwnode_irq_get_byname(fwnode, "errb"); - if (errb_irq < 0) - errb_irq =3D 0; + if (errb_irq =3D=3D -EPROBE_DEFER) + return errb_irq; =20 - if (errb_irq) - num_errb =3D ARRAY_SIZE(regulator_errb_irqs); + if (errb_irq > 0) + num_errb =3D cd->num_errb_irqs; =20 - num_regu_irqs =3D num_intb + num_errb; + num_regu_irqs =3D cd->num_intb_irqs + num_errb; =20 regulator_res =3D devm_kcalloc(&i2c->dev, num_regu_irqs, sizeof(*regulator_res), GFP_KERNEL); if (!regulator_res) return -ENOMEM; =20 - regmap =3D devm_regmap_init_i2c(i2c, &bd96801_regmap_config); + regmap =3D devm_regmap_init_i2c(i2c, cd->regmap_config); if (IS_ERR(regmap)) return dev_err_probe(&i2c->dev, PTR_ERR(regmap), "Regmap initialization failed\n"); =20 - ret =3D regmap_write(regmap, BD96801_LOCK_REG, BD96801_UNLOCK); + ret =3D regmap_write(regmap, cd->unlock_reg, cd->unlock_val); if (ret) return dev_err_probe(&i2c->dev, ret, "Failed to unlock PMIC\n"); =20 ret =3D devm_regmap_add_irq_chip(&i2c->dev, regmap, intb_irq, - IRQF_ONESHOT, 0, &bd96801_irq_chip_intb, + IRQF_ONESHOT, 0, cd->intb_irq_chip, &intb_irq_data); if (ret) return dev_err_probe(&i2c->dev, ret, "Failed to add INTB IRQ chip\n"); @@ -404,24 +435,25 @@ static int bd96801_i2c_probe(struct i2c_client *i2c) * has two domains so we do IRQ mapping here and provide the * already mapped IRQ numbers to sub-devices. */ - for (i =3D 0; i < num_intb; i++) { + for (i =3D 0; i < cd->num_intb_irqs; i++) { struct resource *res =3D ®ulator_res[i]; =20 - *res =3D regulator_intb_irqs[i]; + *res =3D cd->intb_irqs[i]; res->start =3D res->end =3D irq_create_mapping(intb_domain, res->start); } =20 wdg_irq_no =3D irq_create_mapping(intb_domain, BD96801_WDT_ERR_STAT); wdg_irq =3D DEFINE_RES_IRQ_NAMED(wdg_irq_no, "bd96801-wdg"); - bd96801_cells[WDG_CELL].resources =3D &wdg_irq; - bd96801_cells[WDG_CELL].num_resources =3D 1; + + cd->cells[WDG_CELL].resources =3D &wdg_irq; + cd->cells[WDG_CELL].num_resources =3D 1; =20 if (!num_errb) goto skip_errb; =20 ret =3D devm_regmap_add_irq_chip(&i2c->dev, regmap, errb_irq, IRQF_ONESHO= T, - 0, &bd96801_irq_chip_errb, &errb_irq_data); + 0, cd->errb_irq_chip, &errb_irq_data); if (ret) return dev_err_probe(&i2c->dev, ret, "Failed to add ERRB IRQ chip\n"); @@ -429,18 +461,17 @@ static int bd96801_i2c_probe(struct i2c_client *i2c) errb_domain =3D regmap_irq_get_domain(errb_irq_data); =20 for (i =3D 0; i < num_errb; i++) { - struct resource *res =3D ®ulator_res[num_intb + i]; + struct resource *res =3D ®ulator_res[cd->num_intb_irqs + i]; =20 - *res =3D regulator_errb_irqs[i]; + *res =3D cd->errb_irqs[i]; res->start =3D res->end =3D irq_create_mapping(errb_domain, res->start); } =20 skip_errb: - bd96801_cells[REGULATOR_CELL].resources =3D regulator_res; - bd96801_cells[REGULATOR_CELL].num_resources =3D num_regu_irqs; - - ret =3D devm_mfd_add_devices(&i2c->dev, PLATFORM_DEVID_AUTO, bd96801_cell= s, - ARRAY_SIZE(bd96801_cells), NULL, 0, NULL); + cd->cells[REGULATOR_CELL].resources =3D regulator_res; + cd->cells[REGULATOR_CELL].num_resources =3D num_regu_irqs; + ret =3D devm_mfd_add_devices(&i2c->dev, PLATFORM_DEVID_AUTO, + cd->cells, cd->num_cells, NULL, 0, NULL); if (ret) dev_err_probe(&i2c->dev, ret, "Failed to create subdevices\n"); =20 @@ -448,7 +479,7 @@ static int bd96801_i2c_probe(struct i2c_client *i2c) } =20 static const struct of_device_id bd96801_of_match[] =3D { - { .compatible =3D "rohm,bd96801", }, + { .compatible =3D "rohm,bd96801", .data =3D &bd96801_chip_data, }, { } }; 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Thu, 13 Mar 2025 04:42:04 -0700 (PDT) Received: from mva-rohm ([2a10:a5c0:800d:dd00:8fdf:935a:2c85:d703]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-549ba8a79a9sm185233e87.221.2025.03.13.04.42.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Mar 2025 04:42:03 -0700 (PDT) Date: Thu, 13 Mar 2025 13:42:00 +0200 From: Matti Vaittinen To: Matti Vaittinen , Matti Vaittinen Cc: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liam Girdwood , Mark Brown , Matti Vaittinen , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 06/14] mfd: bd96801: Drop IC name from the regulator IRQ resources Message-ID: <2d21e86e713f93a67cdc739731bb4282ced9af8a.1741864404.git.mazziesaccount@gmail.com> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="oERGHLDhfVJOFnxb" Content-Disposition: inline In-Reply-To: --oERGHLDhfVJOFnxb Content-Disposition: inline Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The resources generated in the BD96801 MFD driver are only visible to the sub-drivers whose resource fields they are added. This makes abbreviating the resource name with the IC name pointless. It just adds confusion in those sub-drivers which do not really care the exact model that generates the IRQ but just want to know the purpose IRQ was generated for. This is a preparatory fix to simplify adding support for ROHM BD96802 PMIC. Signed-off-by: Matti Vaittinen --- NOTE: This commit shall break the bd96801-regulator driver unless a follow-up regulator commit is also included. Compilation should not be broken though so squashing should not be mandatory as long as both this MFD commit and the regulator commit will end up in same release. --- drivers/mfd/rohm-bd96801.c | 187 +++++++++++++++++++------------------ 1 file changed, 94 insertions(+), 93 deletions(-) diff --git a/drivers/mfd/rohm-bd96801.c b/drivers/mfd/rohm-bd96801.c index 1232f571e4b1..47c77ed3d343 100644 --- a/drivers/mfd/rohm-bd96801.c +++ b/drivers/mfd/rohm-bd96801.c @@ -55,105 +55,106 @@ struct bd968xx_chip_data { }; =20 static const struct resource bd96801_reg_errb_irqs[] =3D { - DEFINE_RES_IRQ_NAMED(BD96801_OTP_ERR_STAT, "bd96801-otp-err"), - DEFINE_RES_IRQ_NAMED(BD96801_DBIST_ERR_STAT, "bd96801-dbist-err"), - DEFINE_RES_IRQ_NAMED(BD96801_EEP_ERR_STAT, "bd96801-eep-err"), - DEFINE_RES_IRQ_NAMED(BD96801_ABIST_ERR_STAT, "bd96801-abist-err"), - DEFINE_RES_IRQ_NAMED(BD96801_PRSTB_ERR_STAT, "bd96801-prstb-err"), - DEFINE_RES_IRQ_NAMED(BD96801_DRMOS1_ERR_STAT, "bd96801-drmoserr1"), - DEFINE_RES_IRQ_NAMED(BD96801_DRMOS2_ERR_STAT, "bd96801-drmoserr2"), - DEFINE_RES_IRQ_NAMED(BD96801_SLAVE_ERR_STAT, "bd96801-slave-err"), - DEFINE_RES_IRQ_NAMED(BD96801_VREF_ERR_STAT, "bd96801-vref-err"), - DEFINE_RES_IRQ_NAMED(BD96801_TSD_ERR_STAT, "bd96801-tsd"), - DEFINE_RES_IRQ_NAMED(BD96801_UVLO_ERR_STAT, "bd96801-uvlo-err"), - DEFINE_RES_IRQ_NAMED(BD96801_OVLO_ERR_STAT, "bd96801-ovlo-err"), - DEFINE_RES_IRQ_NAMED(BD96801_OSC_ERR_STAT, "bd96801-osc-err"), - DEFINE_RES_IRQ_NAMED(BD96801_PON_ERR_STAT, "bd96801-pon-err"), - DEFINE_RES_IRQ_NAMED(BD96801_POFF_ERR_STAT, "bd96801-poff-err"), - DEFINE_RES_IRQ_NAMED(BD96801_CMD_SHDN_ERR_STAT, "bd96801-cmd-shdn-err"), + DEFINE_RES_IRQ_NAMED(BD96801_OTP_ERR_STAT, "otp-err"), + DEFINE_RES_IRQ_NAMED(BD96801_DBIST_ERR_STAT, "dbist-err"), + DEFINE_RES_IRQ_NAMED(BD96801_EEP_ERR_STAT, "eep-err"), + DEFINE_RES_IRQ_NAMED(BD96801_ABIST_ERR_STAT, "abist-err"), + DEFINE_RES_IRQ_NAMED(BD96801_PRSTB_ERR_STAT, "prstb-err"), + DEFINE_RES_IRQ_NAMED(BD96801_DRMOS1_ERR_STAT, "drmoserr1"), + DEFINE_RES_IRQ_NAMED(BD96801_DRMOS2_ERR_STAT, "drmoserr2"), + DEFINE_RES_IRQ_NAMED(BD96801_SLAVE_ERR_STAT, "slave-err"), + DEFINE_RES_IRQ_NAMED(BD96801_VREF_ERR_STAT, "vref-err"), + DEFINE_RES_IRQ_NAMED(BD96801_TSD_ERR_STAT, "tsd"), + DEFINE_RES_IRQ_NAMED(BD96801_UVLO_ERR_STAT, "uvlo-err"), + DEFINE_RES_IRQ_NAMED(BD96801_OVLO_ERR_STAT, "ovlo-err"), + DEFINE_RES_IRQ_NAMED(BD96801_OSC_ERR_STAT, "osc-err"), + DEFINE_RES_IRQ_NAMED(BD96801_PON_ERR_STAT, "pon-err"), + DEFINE_RES_IRQ_NAMED(BD96801_POFF_ERR_STAT, "poff-err"), + DEFINE_RES_IRQ_NAMED(BD96801_CMD_SHDN_ERR_STAT, "cmd-shdn-err"), =20 DEFINE_RES_IRQ_NAMED(BD96801_INT_PRSTB_WDT_ERR, "bd96801-prstb-wdt-err"), DEFINE_RES_IRQ_NAMED(BD96801_INT_CHIP_IF_ERR, "bd96801-chip-if-err"), - DEFINE_RES_IRQ_NAMED(BD96801_INT_SHDN_ERR_STAT, "bd96801-int-shdn-err"), - - DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_PVIN_ERR_STAT, "bd96801-buck1-pvin-err= "), - DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_OVP_ERR_STAT, "bd96801-buck1-ovp-err"), - DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_UVP_ERR_STAT, "bd96801-buck1-uvp-err"), - DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_SHDN_ERR_STAT, "bd96801-buck1-shdn-err= "), - - DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_PVIN_ERR_STAT, "bd96801-buck2-pvin-err= "), - DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_OVP_ERR_STAT, "bd96801-buck2-ovp-err"), - DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_UVP_ERR_STAT, "bd96801-buck2-uvp-err"), - DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_SHDN_ERR_STAT, "bd96801-buck2-shdn-err= "), - - DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_PVIN_ERR_STAT, "bd96801-buck3-pvin-err= "), - DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_OVP_ERR_STAT, "bd96801-buck3-ovp-err"), - DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_UVP_ERR_STAT, "bd96801-buck3-uvp-err"), - DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_SHDN_ERR_STAT, "bd96801-buck3-shdn-err= "), - - DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_PVIN_ERR_STAT, "bd96801-buck4-pvin-err= "), - DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_OVP_ERR_STAT, "bd96801-buck4-ovp-err"), - DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_UVP_ERR_STAT, "bd96801-buck4-uvp-err"), - DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_SHDN_ERR_STAT, "bd96801-buck4-shdn-err= "), - - DEFINE_RES_IRQ_NAMED(BD96801_LDO5_PVIN_ERR_STAT, "bd96801-ldo5-pvin-err"), - DEFINE_RES_IRQ_NAMED(BD96801_LDO5_OVP_ERR_STAT, "bd96801-ldo5-ovp-err"), - DEFINE_RES_IRQ_NAMED(BD96801_LDO5_UVP_ERR_STAT, "bd96801-ldo5-uvp-err"), - DEFINE_RES_IRQ_NAMED(BD96801_LDO5_SHDN_ERR_STAT, "bd96801-ldo5-shdn-err"), - - DEFINE_RES_IRQ_NAMED(BD96801_LDO6_PVIN_ERR_STAT, "bd96801-ldo6-pvin-err"), - DEFINE_RES_IRQ_NAMED(BD96801_LDO6_OVP_ERR_STAT, "bd96801-ldo6-ovp-err"), - DEFINE_RES_IRQ_NAMED(BD96801_LDO6_UVP_ERR_STAT, "bd96801-ldo6-uvp-err"), - DEFINE_RES_IRQ_NAMED(BD96801_LDO6_SHDN_ERR_STAT, "bd96801-ldo6-shdn-err"), - - DEFINE_RES_IRQ_NAMED(BD96801_LDO7_PVIN_ERR_STAT, "bd96801-ldo7-pvin-err"), - DEFINE_RES_IRQ_NAMED(BD96801_LDO7_OVP_ERR_STAT, "bd96801-ldo7-ovp-err"), - DEFINE_RES_IRQ_NAMED(BD96801_LDO7_UVP_ERR_STAT, "bd96801-ldo7-uvp-err"), - DEFINE_RES_IRQ_NAMED(BD96801_LDO7_SHDN_ERR_STAT, "bd96801-ldo7-shdn-err"), + + DEFINE_RES_IRQ_NAMED(BD96801_INT_SHDN_ERR_STAT, "int-shdn-err"), + + DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_PVIN_ERR_STAT, "buck1-pvin-err"), + DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_OVP_ERR_STAT, "buck1-ovp-err"), + DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_UVP_ERR_STAT, "buck1-uvp-err"), + DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_SHDN_ERR_STAT, "buck1-shdn-err"), + + DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_PVIN_ERR_STAT, "buck2-pvin-err"), + DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_OVP_ERR_STAT, "buck2-ovp-err"), + DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_UVP_ERR_STAT, "buck2-uvp-err"), + DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_SHDN_ERR_STAT, "buck2-shdn-err"), + + DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_PVIN_ERR_STAT, "buck3-pvin-err"), + DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_OVP_ERR_STAT, "buck3-ovp-err"), + DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_UVP_ERR_STAT, "buck3-uvp-err"), + DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_SHDN_ERR_STAT, "buck3-shdn-err"), + + DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_PVIN_ERR_STAT, "buck4-pvin-err"), + DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_OVP_ERR_STAT, "buck4-ovp-err"), + DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_UVP_ERR_STAT, "buck4-uvp-err"), + DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_SHDN_ERR_STAT, "buck4-shdn-err"), + + DEFINE_RES_IRQ_NAMED(BD96801_LDO5_PVIN_ERR_STAT, "ldo5-pvin-err"), + DEFINE_RES_IRQ_NAMED(BD96801_LDO5_OVP_ERR_STAT, "ldo5-ovp-err"), + DEFINE_RES_IRQ_NAMED(BD96801_LDO5_UVP_ERR_STAT, "ldo5-uvp-err"), + DEFINE_RES_IRQ_NAMED(BD96801_LDO5_SHDN_ERR_STAT, "ldo5-shdn-err"), + + DEFINE_RES_IRQ_NAMED(BD96801_LDO6_PVIN_ERR_STAT, "ldo6-pvin-err"), + DEFINE_RES_IRQ_NAMED(BD96801_LDO6_OVP_ERR_STAT, "ldo6-ovp-err"), + DEFINE_RES_IRQ_NAMED(BD96801_LDO6_UVP_ERR_STAT, "ldo6-uvp-err"), + DEFINE_RES_IRQ_NAMED(BD96801_LDO6_SHDN_ERR_STAT, "ldo6-shdn-err"), + + DEFINE_RES_IRQ_NAMED(BD96801_LDO7_PVIN_ERR_STAT, "ldo7-pvin-err"), + DEFINE_RES_IRQ_NAMED(BD96801_LDO7_OVP_ERR_STAT, "ldo7-ovp-err"), + DEFINE_RES_IRQ_NAMED(BD96801_LDO7_UVP_ERR_STAT, "ldo7-uvp-err"), + DEFINE_RES_IRQ_NAMED(BD96801_LDO7_SHDN_ERR_STAT, "ldo7-shdn-err"), }; =20 static const struct resource bd96801_reg_intb_irqs[] =3D { - DEFINE_RES_IRQ_NAMED(BD96801_TW_STAT, "bd96801-core-thermal"), - - DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_OCPH_STAT, "bd96801-buck1-overcurr-h"), - DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_OCPL_STAT, "bd96801-buck1-overcurr-l"), - DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_OCPN_STAT, "bd96801-buck1-overcurr-n"), - DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_OVD_STAT, "bd96801-buck1-overvolt"), - DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_UVD_STAT, "bd96801-buck1-undervolt"), - DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_TW_CH_STAT, "bd96801-buck1-thermal"), - - DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_OCPH_STAT, "bd96801-buck2-overcurr-h"), - DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_OCPL_STAT, "bd96801-buck2-overcurr-l"), - DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_OCPN_STAT, "bd96801-buck2-overcurr-n"), - DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_OVD_STAT, "bd96801-buck2-overvolt"), - DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_UVD_STAT, "bd96801-buck2-undervolt"), - DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_TW_CH_STAT, "bd96801-buck2-thermal"), - - DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_OCPH_STAT, "bd96801-buck3-overcurr-h"), - DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_OCPL_STAT, "bd96801-buck3-overcurr-l"), - DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_OCPN_STAT, "bd96801-buck3-overcurr-n"), - DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_OVD_STAT, "bd96801-buck3-overvolt"), - DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_UVD_STAT, "bd96801-buck3-undervolt"), - DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_TW_CH_STAT, "bd96801-buck3-thermal"), - - DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_OCPH_STAT, "bd96801-buck4-overcurr-h"), - DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_OCPL_STAT, "bd96801-buck4-overcurr-l"), - DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_OCPN_STAT, "bd96801-buck4-overcurr-n"), - DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_OVD_STAT, "bd96801-buck4-overvolt"), - DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_UVD_STAT, "bd96801-buck4-undervolt"), - DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_TW_CH_STAT, "bd96801-buck4-thermal"), - - DEFINE_RES_IRQ_NAMED(BD96801_LDO5_OCPH_STAT, "bd96801-ldo5-overcurr"), - DEFINE_RES_IRQ_NAMED(BD96801_LDO5_OVD_STAT, "bd96801-ldo5-overvolt"), - DEFINE_RES_IRQ_NAMED(BD96801_LDO5_UVD_STAT, "bd96801-ldo5-undervolt"), - - DEFINE_RES_IRQ_NAMED(BD96801_LDO6_OCPH_STAT, "bd96801-ldo6-overcurr"), - DEFINE_RES_IRQ_NAMED(BD96801_LDO6_OVD_STAT, "bd96801-ldo6-overvolt"), - DEFINE_RES_IRQ_NAMED(BD96801_LDO6_UVD_STAT, "bd96801-ldo6-undervolt"), - - DEFINE_RES_IRQ_NAMED(BD96801_LDO7_OCPH_STAT, "bd96801-ldo7-overcurr"), - DEFINE_RES_IRQ_NAMED(BD96801_LDO7_OVD_STAT, "bd96801-ldo7-overvolt"), - DEFINE_RES_IRQ_NAMED(BD96801_LDO7_UVD_STAT, "bd96801-ldo7-undervolt"), + DEFINE_RES_IRQ_NAMED(BD96801_TW_STAT, "core-thermal"), + + DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_OCPH_STAT, "buck1-overcurr-h"), + DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_OCPL_STAT, "buck1-overcurr-l"), + DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_OCPN_STAT, "buck1-overcurr-n"), + DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_OVD_STAT, "buck1-overvolt"), + DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_UVD_STAT, "buck1-undervolt"), + DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_TW_CH_STAT, "buck1-thermal"), + + DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_OCPH_STAT, "buck2-overcurr-h"), + DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_OCPL_STAT, "buck2-overcurr-l"), + DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_OCPN_STAT, "buck2-overcurr-n"), + DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_OVD_STAT, "buck2-overvolt"), + DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_UVD_STAT, "buck2-undervolt"), + DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_TW_CH_STAT, "buck2-thermal"), + + DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_OCPH_STAT, "buck3-overcurr-h"), + DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_OCPL_STAT, "buck3-overcurr-l"), + DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_OCPN_STAT, "buck3-overcurr-n"), + DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_OVD_STAT, "buck3-overvolt"), + DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_UVD_STAT, "buck3-undervolt"), + DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_TW_CH_STAT, "buck3-thermal"), + + DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_OCPH_STAT, "buck4-overcurr-h"), + DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_OCPL_STAT, "buck4-overcurr-l"), + DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_OCPN_STAT, "buck4-overcurr-n"), + DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_OVD_STAT, "buck4-overvolt"), + DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_UVD_STAT, "buck4-undervolt"), + DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_TW_CH_STAT, "buck4-thermal"), + + DEFINE_RES_IRQ_NAMED(BD96801_LDO5_OCPH_STAT, "ldo5-overcurr"), + DEFINE_RES_IRQ_NAMED(BD96801_LDO5_OVD_STAT, "ldo5-overvolt"), + DEFINE_RES_IRQ_NAMED(BD96801_LDO5_UVD_STAT, "ldo5-undervolt"), + + DEFINE_RES_IRQ_NAMED(BD96801_LDO6_OCPH_STAT, "ldo6-overcurr"), + DEFINE_RES_IRQ_NAMED(BD96801_LDO6_OVD_STAT, "ldo6-overvolt"), + DEFINE_RES_IRQ_NAMED(BD96801_LDO6_UVD_STAT, "ldo6-undervolt"), + + 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2adb3069b0e04-549ba440077mr911202e87.16.1741866137646; Thu, 13 Mar 2025 04:42:17 -0700 (PDT) Received: from mva-rohm ([2a10:a5c0:800d:dd00:8fdf:935a:2c85:d703]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-549ba864d24sm187807e87.108.2025.03.13.04.42.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Mar 2025 04:42:16 -0700 (PDT) Date: Thu, 13 Mar 2025 13:42:12 +0200 From: Matti Vaittinen To: Matti Vaittinen , Matti Vaittinen Cc: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liam Girdwood , Mark Brown , Matti Vaittinen , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 07/14] regulator: bd96801: Drop IC name from the IRQ resources Message-ID: <9af81632fb6100af25af729f19237965add05d68.1741864404.git.mazziesaccount@gmail.com> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="XzL+GtzC5s9Eqhlj" Content-Disposition: inline In-Reply-To: --XzL+GtzC5s9Eqhlj Content-Disposition: inline Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The resources generated in the BD96801 MFD driver are only visible to the sub-drivers whose resource fields they are added. This makes abbreviating the resource name with the IC name pointless. It just adds confusion in those sub-drivers which do not really care the exact model that generates the IRQ but just want to know the purpose IRQ was generated for. Thus, as a preparatory fix to simplify adding support for ROHM BD96802 PMIC the IC name "bd96801-" prefix was dropped from the IRQ resource names. Adapt the regulator driver to this change. Signed-off-by: Matti Vaittinen --- NOTE: This commit shall break the driver unless 5ba9557e5d41 ("mfd: bd96801: Drop IC name from the IRQ resources") is also included. Compilation should not be broken though so squashing should not be mandatory as long as both this regiulator commit and the MFD commit will end up in same release. --- drivers/regulator/bd96801-regulator.c | 83 +++++++++++++-------------- 1 file changed, 40 insertions(+), 43 deletions(-) diff --git a/drivers/regulator/bd96801-regulator.c b/drivers/regulator/bd96= 801-regulator.c index 3a9d772491a8..48cdd583e92d 100644 --- a/drivers/regulator/bd96801-regulator.c +++ b/drivers/regulator/bd96801-regulator.c @@ -198,89 +198,89 @@ struct bd96801_irqinfo { =20 static const struct bd96801_irqinfo buck1_irqinfo[] =3D { BD96801_IRQINFO(BD96801_PROT_OCP, "buck1-over-curr-h", 500, - "bd96801-buck1-overcurr-h"), + "buck1-overcurr-h"), BD96801_IRQINFO(BD96801_PROT_OCP, "buck1-over-curr-l", 500, - "bd96801-buck1-overcurr-l"), + "buck1-overcurr-l"), BD96801_IRQINFO(BD96801_PROT_OCP, "buck1-over-curr-n", 500, - "bd96801-buck1-overcurr-n"), + "buck1-overcurr-n"), BD96801_IRQINFO(BD96801_PROT_OVP, "buck1-over-voltage", 500, - "bd96801-buck1-overvolt"), + "buck1-overvolt"), BD96801_IRQINFO(BD96801_PROT_UVP, "buck1-under-voltage", 500, - "bd96801-buck1-undervolt"), + "buck1-undervolt"), BD96801_IRQINFO(BD96801_PROT_TEMP, "buck1-over-temp", 500, - "bd96801-buck1-thermal") + "buck1-thermal") }; =20 static const struct bd96801_irqinfo buck2_irqinfo[] =3D { BD96801_IRQINFO(BD96801_PROT_OCP, "buck2-over-curr-h", 500, - "bd96801-buck2-overcurr-h"), + "buck2-overcurr-h"), BD96801_IRQINFO(BD96801_PROT_OCP, "buck2-over-curr-l", 500, - "bd96801-buck2-overcurr-l"), + "buck2-overcurr-l"), BD96801_IRQINFO(BD96801_PROT_OCP, "buck2-over-curr-n", 500, - "bd96801-buck2-overcurr-n"), + "buck2-overcurr-n"), BD96801_IRQINFO(BD96801_PROT_OVP, "buck2-over-voltage", 500, - "bd96801-buck2-overvolt"), + "buck2-overvolt"), BD96801_IRQINFO(BD96801_PROT_UVP, "buck2-under-voltage", 500, - "bd96801-buck2-undervolt"), + "buck2-undervolt"), BD96801_IRQINFO(BD96801_PROT_TEMP, "buck2-over-temp", 500, - "bd96801-buck2-thermal") + "buck2-thermal") }; =20 static const struct bd96801_irqinfo buck3_irqinfo[] =3D { BD96801_IRQINFO(BD96801_PROT_OCP, "buck3-over-curr-h", 500, - "bd96801-buck3-overcurr-h"), + "buck3-overcurr-h"), BD96801_IRQINFO(BD96801_PROT_OCP, "buck3-over-curr-l", 500, - "bd96801-buck3-overcurr-l"), + "buck3-overcurr-l"), BD96801_IRQINFO(BD96801_PROT_OCP, "buck3-over-curr-n", 500, - "bd96801-buck3-overcurr-n"), + "buck3-overcurr-n"), BD96801_IRQINFO(BD96801_PROT_OVP, "buck3-over-voltage", 500, - "bd96801-buck3-overvolt"), + "buck3-overvolt"), BD96801_IRQINFO(BD96801_PROT_UVP, "buck3-under-voltage", 500, - "bd96801-buck3-undervolt"), + "buck3-undervolt"), BD96801_IRQINFO(BD96801_PROT_TEMP, "buck3-over-temp", 500, - "bd96801-buck3-thermal") + "buck3-thermal") }; =20 static const struct bd96801_irqinfo buck4_irqinfo[] =3D { BD96801_IRQINFO(BD96801_PROT_OCP, "buck4-over-curr-h", 500, - "bd96801-buck4-overcurr-h"), + "buck4-overcurr-h"), BD96801_IRQINFO(BD96801_PROT_OCP, "buck4-over-curr-l", 500, - "bd96801-buck4-overcurr-l"), + "buck4-overcurr-l"), BD96801_IRQINFO(BD96801_PROT_OCP, "buck4-over-curr-n", 500, - "bd96801-buck4-overcurr-n"), + "buck4-overcurr-n"), BD96801_IRQINFO(BD96801_PROT_OVP, "buck4-over-voltage", 500, - "bd96801-buck4-overvolt"), + "buck4-overvolt"), BD96801_IRQINFO(BD96801_PROT_UVP, "buck4-under-voltage", 500, - "bd96801-buck4-undervolt"), + "buck4-undervolt"), BD96801_IRQINFO(BD96801_PROT_TEMP, "buck4-over-temp", 500, - "bd96801-buck4-thermal") + "buck4-thermal") }; =20 static const struct bd96801_irqinfo ldo5_irqinfo[] =3D { BD96801_IRQINFO(BD96801_PROT_OCP, "ldo5-overcurr", 500, - "bd96801-ldo5-overcurr"), + "ldo5-overcurr"), BD96801_IRQINFO(BD96801_PROT_OVP, "ldo5-over-voltage", 500, - "bd96801-ldo5-overvolt"), + "ldo5-overvolt"), BD96801_IRQINFO(BD96801_PROT_UVP, "ldo5-under-voltage", 500, - "bd96801-ldo5-undervolt"), + "ldo5-undervolt"), }; =20 static const struct bd96801_irqinfo ldo6_irqinfo[] =3D { BD96801_IRQINFO(BD96801_PROT_OCP, "ldo6-overcurr", 500, - "bd96801-ldo6-overcurr"), + "ldo6-overcurr"), BD96801_IRQINFO(BD96801_PROT_OVP, "ldo6-over-voltage", 500, - "bd96801-ldo6-overvolt"), + "ldo6-overvolt"), BD96801_IRQINFO(BD96801_PROT_UVP, "ldo6-under-voltage", 500, - "bd96801-ldo6-undervolt"), + "ldo6-undervolt"), }; =20 static const struct bd96801_irqinfo ldo7_irqinfo[] =3D { BD96801_IRQINFO(BD96801_PROT_OCP, "ldo7-overcurr", 500, - "bd96801-ldo7-overcurr"), + "ldo7-overcurr"), BD96801_IRQINFO(BD96801_PROT_OVP, "ldo7-over-voltage", 500, - "bd96801-ldo7-overvolt"), + "ldo7-overvolt"), BD96801_IRQINFO(BD96801_PROT_UVP, "ldo7-under-voltage", 500, - "bd96801-ldo7-undervolt"), + "ldo7-undervolt"), }; =20 struct bd96801_irq_desc { @@ -741,8 +741,7 @@ static int bd96801_rdev_errb_irqs(struct platform_devic= e *pdev, int i; void *retp; static const char * const single_out_errb_irqs[] =3D { - "bd96801-%s-pvin-err", "bd96801-%s-ovp-err", - "bd96801-%s-uvp-err", "bd96801-%s-shdn-err", + "%s-pvin-err", "%s-ovp-err", "%s-uvp-err", "%s-shdn-err", }; =20 for (i =3D 0; i < ARRAY_SIZE(single_out_errb_irqs); i++) { @@ -779,12 +778,10 @@ static int bd96801_global_errb_irqs(struct platform_d= evice *pdev, int i, num_irqs; void *retp; static const char * const global_errb_irqs[] =3D { - "bd96801-otp-err", "bd96801-dbist-err", "bd96801-eep-err", - "bd96801-abist-err", "bd96801-prstb-err", "bd96801-drmoserr1", - "bd96801-drmoserr2", "bd96801-slave-err", "bd96801-vref-err", - "bd96801-tsd", "bd96801-uvlo-err", "bd96801-ovlo-err", - "bd96801-osc-err", "bd96801-pon-err", "bd96801-poff-err", - "bd96801-cmd-shdn-err", "bd96801-int-shdn-err" + "otp-err", "dbist-err", "eep-err", "abist-err", "prstb-err", + "drmoserr1", "drmoserr2", "slave-err", "vref-err", "tsd", + "uvlo-err", "ovlo-err", "osc-err", "pon-err", "poff-err", + "cmd-shdn-err", "int-shdn-err" }; =20 num_irqs =3D ARRAY_SIZE(global_errb_irqs); @@ -956,12 +953,12 @@ static int bd96801_probe(struct platform_device *pdev) if (temp_notif_ldos) { int irq; struct regulator_irq_desc tw_desc =3D { - .name =3D "bd96801-core-thermal", + .name =3D "core-thermal", .irq_off_ms =3D 500, .map_event =3D ldo_map_notif, }; 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Thu, 13 Mar 2025 04:42:30 -0700 (PDT) Received: from mva-rohm ([2a10:a5c0:800d:dd00:8fdf:935a:2c85:d703]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-30c3f1c217dsm1845351fa.65.2025.03.13.04.42.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Mar 2025 04:42:28 -0700 (PDT) Date: Thu, 13 Mar 2025 13:42:24 +0200 From: Matti Vaittinen To: Matti Vaittinen , Matti Vaittinen Cc: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liam Girdwood , Mark Brown , Matti Vaittinen , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 08/14] mfd: rohm-bd96801: Support ROHM BD96802 Message-ID: <7afe2699c382f1d9da2d8341f0c10733030d1164.1741864404.git.mazziesaccount@gmail.com> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="KhowQEei6lKDF70+" Content-Disposition: inline In-Reply-To: --KhowQEei6lKDF70+ Content-Disposition: inline Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The ROHM BD96802 PMIC looks from software point of view a lot like ROHM BD96801 PMIC. Just with reduced number of voltage rails. Both PMICs provide two physical IRQ lines referred as INTB and ERRB and contain blocks implementing regulator controls and a weatchdog. Hence it makes sense to use same MFD core for both PMICs. Add support for ROHM BD96802 scalable companion PMIC to the BD96801 core driver. Signed-off-by: Matti Vaittinen --- drivers/mfd/rohm-bd96801.c | 238 ++++++++++++++++++++++++++++++- include/linux/mfd/rohm-bd96801.h | 2 + include/linux/mfd/rohm-bd96802.h | 74 ++++++++++ 3 files changed, 309 insertions(+), 5 deletions(-) create mode 100644 include/linux/mfd/rohm-bd96802.h diff --git a/drivers/mfd/rohm-bd96801.c b/drivers/mfd/rohm-bd96801.c index 47c77ed3d343..2438cfdeecf9 100644 --- a/drivers/mfd/rohm-bd96801.c +++ b/drivers/mfd/rohm-bd96801.c @@ -38,6 +38,7 @@ #include =20 #include +#include #include =20 struct bd968xx_chip_data { @@ -113,6 +114,36 @@ static const struct resource bd96801_reg_errb_irqs[] = =3D { DEFINE_RES_IRQ_NAMED(BD96801_LDO7_SHDN_ERR_STAT, "ldo7-shdn-err"), }; =20 +static const struct resource bd96802_reg_errb_irqs[] =3D { + DEFINE_RES_IRQ_NAMED(BD96802_OTP_ERR_STAT, "otp-err"), + DEFINE_RES_IRQ_NAMED(BD96802_DBIST_ERR_STAT, "dbist-err"), + DEFINE_RES_IRQ_NAMED(BD96802_EEP_ERR_STAT, "eep-err"), + DEFINE_RES_IRQ_NAMED(BD96802_ABIST_ERR_STAT, "abist-err"), + DEFINE_RES_IRQ_NAMED(BD96802_PRSTB_ERR_STAT, "prstb-err"), + DEFINE_RES_IRQ_NAMED(BD96802_DRMOS1_ERR_STAT, "drmoserr1"), + DEFINE_RES_IRQ_NAMED(BD96802_DRMOS1_ERR_STAT, "drmoserr2"), + DEFINE_RES_IRQ_NAMED(BD96802_SLAVE_ERR_STAT, "slave-err"), + DEFINE_RES_IRQ_NAMED(BD96802_VREF_ERR_STAT, "vref-err"), + DEFINE_RES_IRQ_NAMED(BD96802_TSD_ERR_STAT, "tsd"), + DEFINE_RES_IRQ_NAMED(BD96802_UVLO_ERR_STAT, "uvlo-err"), + DEFINE_RES_IRQ_NAMED(BD96802_OVLO_ERR_STAT, "ovlo-err"), + DEFINE_RES_IRQ_NAMED(BD96802_OSC_ERR_STAT, "osc-err"), + DEFINE_RES_IRQ_NAMED(BD96802_PON_ERR_STAT, "pon-err"), + DEFINE_RES_IRQ_NAMED(BD96802_POFF_ERR_STAT, "poff-err"), + DEFINE_RES_IRQ_NAMED(BD96802_CMD_SHDN_ERR_STAT, "cmd-shdn-err"), + DEFINE_RES_IRQ_NAMED(BD96802_INT_SHDN_ERR_STAT, "int-shdn-err"), + + DEFINE_RES_IRQ_NAMED(BD96802_BUCK1_PVIN_ERR_STAT, "buck1-pvin-err"), + DEFINE_RES_IRQ_NAMED(BD96802_BUCK1_OVP_ERR_STAT, "buck1-ovp-err"), + DEFINE_RES_IRQ_NAMED(BD96802_BUCK1_UVP_ERR_STAT, "buck1-uvp-err"), + DEFINE_RES_IRQ_NAMED(BD96802_BUCK1_SHDN_ERR_STAT, "buck1-shdn-err"), + + DEFINE_RES_IRQ_NAMED(BD96802_BUCK2_PVIN_ERR_STAT, "buck2-pvin-err"), + DEFINE_RES_IRQ_NAMED(BD96802_BUCK2_OVP_ERR_STAT, "buck2-ovp-err"), + DEFINE_RES_IRQ_NAMED(BD96802_BUCK2_UVP_ERR_STAT, "buck2-uvp-err"), + DEFINE_RES_IRQ_NAMED(BD96802_BUCK2_SHDN_ERR_STAT, "buck2-shdn-err"), +}; + static const struct resource bd96801_reg_intb_irqs[] =3D { DEFINE_RES_IRQ_NAMED(BD96801_TW_STAT, "core-thermal"), =20 @@ -157,6 +188,24 @@ static const struct resource bd96801_reg_intb_irqs[] = =3D { DEFINE_RES_IRQ_NAMED(BD96801_LDO7_UVD_STAT, "ldo7-undervolt"), }; =20 +static const struct resource bd96802_reg_intb_irqs[] =3D { + DEFINE_RES_IRQ_NAMED(BD96802_TW_STAT, "core-thermal"), + + DEFINE_RES_IRQ_NAMED(BD96802_BUCK1_OCPH_STAT, "buck1-overcurr-h"), + DEFINE_RES_IRQ_NAMED(BD96802_BUCK1_OCPL_STAT, "buck1-overcurr-l"), + DEFINE_RES_IRQ_NAMED(BD96802_BUCK1_OCPN_STAT, "buck1-overcurr-n"), + DEFINE_RES_IRQ_NAMED(BD96802_BUCK1_OVD_STAT, "buck1-overvolt"), + DEFINE_RES_IRQ_NAMED(BD96802_BUCK1_UVD_STAT, "buck1-undervolt"), + DEFINE_RES_IRQ_NAMED(BD96802_BUCK1_TW_CH_STAT, "buck1-thermal"), + + DEFINE_RES_IRQ_NAMED(BD96802_BUCK2_OCPH_STAT, "buck2-overcurr-h"), + DEFINE_RES_IRQ_NAMED(BD96802_BUCK2_OCPL_STAT, "buck2-overcurr-l"), + DEFINE_RES_IRQ_NAMED(BD96802_BUCK2_OCPN_STAT, "buck2-overcurr-n"), + DEFINE_RES_IRQ_NAMED(BD96802_BUCK2_OVD_STAT, "buck2-overvolt"), + DEFINE_RES_IRQ_NAMED(BD96802_BUCK2_UVD_STAT, "buck2-undervolt"), + DEFINE_RES_IRQ_NAMED(BD96802_BUCK2_TW_CH_STAT, "buck2-thermal"), +}; + enum { WDG_CELL =3D 0, REGULATOR_CELL, @@ -167,6 +216,11 @@ static struct mfd_cell bd96801_cells[] =3D { [REGULATOR_CELL] =3D { .name =3D "bd96801-regulator", }, }; =20 +static struct mfd_cell bd96802_cells[] =3D { + [WDG_CELL] =3D { .name =3D "bd96801-wdt", }, + [REGULATOR_CELL] =3D { .name =3D "bd96802-regulator", }, +}; + static const struct regmap_range bd96801_volatile_ranges[] =3D { /* Status registers */ regmap_reg_range(BD96801_REG_WD_FEED, BD96801_REG_WD_FAILCOUNT), @@ -184,11 +238,28 @@ static const struct regmap_range bd96801_volatile_ran= ges[] =3D { regmap_reg_range(BD96801_LDO5_VOL_LVL_REG, BD96801_LDO7_VOL_LVL_REG), }; =20 -static const struct regmap_access_table volatile_regs =3D { +static const struct regmap_range bd96802_volatile_ranges[] =3D { + /* Status regs */ + regmap_reg_range(BD96801_REG_WD_FEED, BD96801_REG_WD_FAILCOUNT), + regmap_reg_range(BD96801_REG_WD_ASK, BD96801_REG_WD_ASK), + regmap_reg_range(BD96801_REG_WD_STATUS, BD96801_REG_WD_STATUS), + regmap_reg_range(BD96801_REG_PMIC_STATE, BD96801_REG_INT_BUCK2_ERRB), + regmap_reg_range(BD96801_REG_INT_SYS_INTB, BD96801_REG_INT_BUCK2_INTB), + /* Registers which do not update value unless PMIC is in STBY */ + regmap_reg_range(BD96801_REG_SSCG_CTRL, BD96801_REG_SHD_INTB), + regmap_reg_range(BD96801_REG_BUCK_OVP, BD96801_REG_BOOT_OVERTIME), +}; + +static const struct regmap_access_table bd96801_volatile_regs =3D { .yes_ranges =3D bd96801_volatile_ranges, .n_yes_ranges =3D ARRAY_SIZE(bd96801_volatile_ranges), }; =20 +static const struct regmap_access_table bd96802_volatile_regs =3D { + .yes_ranges =3D bd96802_volatile_ranges, + .n_yes_ranges =3D ARRAY_SIZE(bd96802_volatile_ranges), +}; + /* * For ERRB we need main register bit mapping as bit(0) indicates active I= RQ * in one of the first 3 sub IRQ registers, For INTB we can use default 1 = to 1 @@ -203,7 +274,7 @@ static unsigned int bit5_offsets[] =3D {7}; /* LDO 5 st= at */ static unsigned int bit6_offsets[] =3D {8}; /* LDO 6 stat */ static unsigned int bit7_offsets[] =3D {9}; /* LDO 7 stat */ =20 -static const struct regmap_irq_sub_irq_map errb_sub_irq_offsets[] =3D { +static const struct regmap_irq_sub_irq_map bd96801_errb_sub_irq_offsets[] = =3D { REGMAP_IRQ_MAIN_REG_OFFSET(bit0_offsets), REGMAP_IRQ_MAIN_REG_OFFSET(bit1_offsets), REGMAP_IRQ_MAIN_REG_OFFSET(bit2_offsets), @@ -214,6 +285,12 @@ static const struct regmap_irq_sub_irq_map errb_sub_ir= q_offsets[] =3D { REGMAP_IRQ_MAIN_REG_OFFSET(bit7_offsets), }; =20 +static const struct regmap_irq_sub_irq_map bd96802_errb_sub_irq_offsets[] = =3D { + REGMAP_IRQ_MAIN_REG_OFFSET(bit0_offsets), + REGMAP_IRQ_MAIN_REG_OFFSET(bit1_offsets), + REGMAP_IRQ_MAIN_REG_OFFSET(bit2_offsets), +}; + static const struct regmap_irq bd96801_errb_irqs[] =3D { /* Reg 0x52 Fatal ERRB1 */ REGMAP_IRQ_REG(BD96801_OTP_ERR_STAT, 0, BD96801_OTP_ERR_MASK), @@ -274,6 +351,39 @@ static const struct regmap_irq bd96801_errb_irqs[] =3D= { REGMAP_IRQ_REG(BD96801_LDO7_SHDN_ERR_STAT, 9, BD96801_OUT_SHDN_ERR_MASK), }; =20 +static const struct regmap_irq bd96802_errb_irqs[] =3D { + /* Reg 0x52 Fatal ERRB1 */ + REGMAP_IRQ_REG(BD96802_OTP_ERR_STAT, 0, BD96801_OTP_ERR_MASK), + REGMAP_IRQ_REG(BD96802_DBIST_ERR_STAT, 0, BD96801_DBIST_ERR_MASK), + REGMAP_IRQ_REG(BD96802_EEP_ERR_STAT, 0, BD96801_EEP_ERR_MASK), + REGMAP_IRQ_REG(BD96802_ABIST_ERR_STAT, 0, BD96801_ABIST_ERR_MASK), + REGMAP_IRQ_REG(BD96802_PRSTB_ERR_STAT, 0, BD96801_PRSTB_ERR_MASK), + REGMAP_IRQ_REG(BD96802_DRMOS1_ERR_STAT, 0, BD96801_DRMOS1_ERR_MASK), + REGMAP_IRQ_REG(BD96802_DRMOS2_ERR_STAT, 0, BD96801_DRMOS2_ERR_MASK), + REGMAP_IRQ_REG(BD96802_SLAVE_ERR_STAT, 0, BD96801_SLAVE_ERR_MASK), + /* 0x53 Fatal ERRB2 */ + REGMAP_IRQ_REG(BD96802_VREF_ERR_STAT, 1, BD96801_VREF_ERR_MASK), + REGMAP_IRQ_REG(BD96802_TSD_ERR_STAT, 1, BD96801_TSD_ERR_MASK), + REGMAP_IRQ_REG(BD96802_UVLO_ERR_STAT, 1, BD96801_UVLO_ERR_MASK), + REGMAP_IRQ_REG(BD96802_OVLO_ERR_STAT, 1, BD96801_OVLO_ERR_MASK), + REGMAP_IRQ_REG(BD96802_OSC_ERR_STAT, 1, BD96801_OSC_ERR_MASK), + REGMAP_IRQ_REG(BD96802_PON_ERR_STAT, 1, BD96801_PON_ERR_MASK), + REGMAP_IRQ_REG(BD96802_POFF_ERR_STAT, 1, BD96801_POFF_ERR_MASK), + REGMAP_IRQ_REG(BD96802_CMD_SHDN_ERR_STAT, 1, BD96801_CMD_SHDN_ERR_MASK), + /* 0x54 Fatal INTB shadowed to ERRB */ + REGMAP_IRQ_REG(BD96802_INT_SHDN_ERR_STAT, 2, BD96801_INT_SHDN_ERR_MASK), + /* Reg 0x55 BUCK1 ERR IRQs */ + REGMAP_IRQ_REG(BD96802_BUCK1_PVIN_ERR_STAT, 3, BD96801_OUT_PVIN_ERR_MASK), + REGMAP_IRQ_REG(BD96802_BUCK1_OVP_ERR_STAT, 3, BD96801_OUT_OVP_ERR_MASK), + REGMAP_IRQ_REG(BD96802_BUCK1_UVP_ERR_STAT, 3, BD96801_OUT_UVP_ERR_MASK), + REGMAP_IRQ_REG(BD96802_BUCK1_SHDN_ERR_STAT, 3, BD96801_OUT_SHDN_ERR_MASK), + /* Reg 0x56 BUCK2 ERR IRQs */ + REGMAP_IRQ_REG(BD96802_BUCK2_PVIN_ERR_STAT, 4, BD96801_OUT_PVIN_ERR_MASK), + REGMAP_IRQ_REG(BD96802_BUCK2_OVP_ERR_STAT, 4, BD96801_OUT_OVP_ERR_MASK), + REGMAP_IRQ_REG(BD96802_BUCK2_UVP_ERR_STAT, 4, BD96801_OUT_UVP_ERR_MASK), + REGMAP_IRQ_REG(BD96802_BUCK2_SHDN_ERR_STAT, 4, BD96801_OUT_SHDN_ERR_MASK), +}; + static const struct regmap_irq bd96801_intb_irqs[] =3D { /* STATUS SYSTEM INTB */ REGMAP_IRQ_REG(BD96801_TW_STAT, 0, BD96801_TW_STAT_MASK), @@ -322,6 +432,69 @@ static const struct regmap_irq bd96801_intb_irqs[] =3D= { REGMAP_IRQ_REG(BD96801_LDO7_UVD_STAT, 7, BD96801_LDO_UVD_STAT_MASK), }; =20 +static const struct regmap_irq bd96802_intb_irqs[] =3D { + /* STATUS SYSTEM INTB */ + REGMAP_IRQ_REG(BD96802_TW_STAT, 0, BD96801_TW_STAT_MASK), + REGMAP_IRQ_REG(BD96802_WDT_ERR_STAT, 0, BD96801_WDT_ERR_STAT_MASK), + REGMAP_IRQ_REG(BD96802_I2C_ERR_STAT, 0, BD96801_I2C_ERR_STAT_MASK), + REGMAP_IRQ_REG(BD96802_CHIP_IF_ERR_STAT, 0, BD96801_CHIP_IF_ERR_STAT_MASK= ), + /* STATUS BUCK1 INTB */ + REGMAP_IRQ_REG(BD96802_BUCK1_OCPH_STAT, 1, BD96801_BUCK_OCPH_STAT_MASK), + REGMAP_IRQ_REG(BD96802_BUCK1_OCPL_STAT, 1, BD96801_BUCK_OCPL_STAT_MASK), + REGMAP_IRQ_REG(BD96802_BUCK1_OCPN_STAT, 1, BD96801_BUCK_OCPN_STAT_MASK), + REGMAP_IRQ_REG(BD96802_BUCK1_OVD_STAT, 1, BD96801_BUCK_OVD_STAT_MASK), + REGMAP_IRQ_REG(BD96802_BUCK1_UVD_STAT, 1, BD96801_BUCK_UVD_STAT_MASK), + REGMAP_IRQ_REG(BD96802_BUCK1_TW_CH_STAT, 1, BD96801_BUCK_TW_CH_STAT_MASK), + /* BUCK 2 INTB */ + REGMAP_IRQ_REG(BD96802_BUCK2_OCPH_STAT, 2, BD96801_BUCK_OCPH_STAT_MASK), + REGMAP_IRQ_REG(BD96802_BUCK2_OCPL_STAT, 2, BD96801_BUCK_OCPL_STAT_MASK), + REGMAP_IRQ_REG(BD96802_BUCK2_OCPN_STAT, 2, BD96801_BUCK_OCPN_STAT_MASK), + REGMAP_IRQ_REG(BD96802_BUCK2_OVD_STAT, 2, BD96801_BUCK_OVD_STAT_MASK), + REGMAP_IRQ_REG(BD96802_BUCK2_UVD_STAT, 2, BD96801_BUCK_UVD_STAT_MASK), + REGMAP_IRQ_REG(BD96802_BUCK2_TW_CH_STAT, 2, BD96801_BUCK_TW_CH_STAT_MASK), +}; + +/* + * The IRQ stuff is a bit hairy. The BD96801 / BD96802 provide two physical + * IRQ lines called INTB and ERRB. They share the same main status registe= r. + * + * For ERRB, mapping from main status to sub-status is such that the + * 'global' faults are mapped to first 3 sub-status registers - and indica= ted + * by the first bit[0] in main status reg. + * + * Rest of the status registers are for indicating stuff for individual + * regulators, 1 sub register / regulator and 1 main status register bit / + * regulator, starting from bit[1]. + * + * Eg, regulator specific stuff has 1 to 1 mapping from main-status to sub + * registers but 'global' ERRB IRQs require mapping from main status bit[0= ] to + * 3 status registers. + * + * Furthermore, the BD96801 has 7 regulators where the BD96802 has only 2. + * + * INTB has only 1 sub status register for 'global' events and then own sub + * status register for each of the regulators. So, for INTB we have direct + * 1 to 1 mapping - BD96801 just having 5 register and 5 main status bits + * more than the BD96802. + * + * Sharing the main status bits could be a problem if we had both INTB and + * ERRB IRQs asserted but for different sub-status offsets. This might lead + * IRQ controller code to go read a sub status register which indicates no + * active IRQs. I assume this occurring repeteadly might lead the IRQ to be + * disabled by core as a result of repeteadly returned IRQ_NONEs. + * + * I don't consider this as a fatal problem for now because: + * a) Having ERRB asserted leads to PMIC fault state which will kill + * the SoC powered by the PMIC. (So, relevant only for potential + * case of not powering the processor with this PMIC). + * b) Having ERRB set without having respective INTB is unlikely + * (haven't actually verified this). + * + * So, let's proceed with main status enabled for both INTB and ERRB. We c= an + * later disable main-status usage on systems where this ever proves to be + * a problem. + */ + static const struct regmap_irq_chip bd96801_irq_chip_errb =3D { .name =3D "bd96801-irq-errb", .domain_suffix =3D "errb", @@ -335,7 +508,23 @@ static const struct regmap_irq_chip bd96801_irq_chip_e= rrb =3D { .init_ack_masked =3D true, .num_regs =3D 10, .irq_reg_stride =3D 1, - .sub_reg_offsets =3D &errb_sub_irq_offsets[0], + .sub_reg_offsets =3D &bd96801_errb_sub_irq_offsets[0], +}; + +static const struct regmap_irq_chip bd96802_irq_chip_errb =3D { + .name =3D "bd96802-irq-errb", + .domain_suffix =3D "errb", + .main_status =3D BD96801_REG_INT_MAIN, + .num_main_regs =3D 1, + .irqs =3D &bd96802_errb_irqs[0], + .num_irqs =3D ARRAY_SIZE(bd96802_errb_irqs), + .status_base =3D BD96801_REG_INT_SYS_ERRB1, + .mask_base =3D BD96801_REG_MASK_SYS_ERRB, + .ack_base =3D BD96801_REG_INT_SYS_ERRB1, + .init_ack_masked =3D true, + .num_regs =3D 5, + .irq_reg_stride =3D 1, + .sub_reg_offsets =3D &bd96802_errb_sub_irq_offsets[0], }; =20 static const struct regmap_irq_chip bd96801_irq_chip_intb =3D { @@ -353,10 +542,32 @@ static const struct regmap_irq_chip bd96801_irq_chip_= intb =3D { .irq_reg_stride =3D 1, }; =20 +static const struct regmap_irq_chip bd96802_irq_chip_intb =3D { + .name =3D "bd96802-irq-intb", + .domain_suffix =3D "intb", + .main_status =3D BD96801_REG_INT_MAIN, + .num_main_regs =3D 1, + .irqs =3D &bd96802_intb_irqs[0], + .num_irqs =3D ARRAY_SIZE(bd96802_intb_irqs), + .status_base =3D BD96801_REG_INT_SYS_INTB, + .mask_base =3D BD96801_REG_MASK_SYS_INTB, + .ack_base =3D BD96801_REG_INT_SYS_INTB, + .init_ack_masked =3D true, + .num_regs =3D 3, + .irq_reg_stride =3D 1, +}; + static const struct regmap_config bd96801_regmap_config =3D { .reg_bits =3D 8, .val_bits =3D 8, - .volatile_table =3D &volatile_regs, + .volatile_table =3D &bd96801_volatile_regs, + .cache_type =3D REGCACHE_MAPLE, +}; + +static const struct regmap_config bd96802_regmap_config =3D { + .reg_bits =3D 8, + .val_bits =3D 8, + .volatile_table =3D &bd96802_volatile_regs, .cache_type =3D REGCACHE_MAPLE, }; =20 @@ -374,6 +585,20 @@ static const struct bd968xx_chip_data bd96801_chip_dat= a =3D { .unlock_val =3D BD96801_UNLOCK, }; =20 +static struct bd968xx_chip_data bd96802_chip_data =3D { + .errb_irqs =3D bd96802_reg_errb_irqs, + .intb_irqs =3D bd96802_reg_intb_irqs, + .num_errb_irqs =3D ARRAY_SIZE(bd96802_reg_errb_irqs), + .num_intb_irqs =3D ARRAY_SIZE(bd96802_reg_intb_irqs), + .errb_irq_chip =3D &bd96802_irq_chip_errb, + .intb_irq_chip =3D &bd96802_irq_chip_intb, + .regmap_config =3D &bd96802_regmap_config, + .cells =3D bd96802_cells, + .num_cells =3D ARRAY_SIZE(bd96802_cells), + .unlock_reg =3D BD96801_LOCK_REG, + .unlock_val =3D BD96801_UNLOCK, +}; + static int bd96801_i2c_probe(struct i2c_client *i2c) { struct regmap_irq_chip_data *intb_irq_data, *errb_irq_data; @@ -388,8 +613,10 @@ static int bd96801_i2c_probe(struct i2c_client *i2c) int i, ret; =20 cd =3D device_get_match_data(&i2c->dev); - if (!cd) + if (!cd) { + dev_err(&i2c->dev, "No data\n"); return -ENODEV; + } =20 fwnode =3D dev_fwnode(&i2c->dev); if (!fwnode) @@ -481,6 +708,7 @@ static int bd96801_i2c_probe(struct i2c_client *i2c) =20 static const struct of_device_id bd96801_of_match[] =3D { { .compatible =3D "rohm,bd96801", .data =3D &bd96801_chip_data, }, + { .compatible =3D "rohm,bd96802", .data =3D &bd96802_chip_data, }, { } }; MODULE_DEVICE_TABLE(of, bd96801_of_match); diff --git a/include/linux/mfd/rohm-bd96801.h b/include/linux/mfd/rohm-bd96= 801.h index e2d9e10b6364..68c8ac8ad409 100644 --- a/include/linux/mfd/rohm-bd96801.h +++ b/include/linux/mfd/rohm-bd96801.h @@ -40,7 +40,9 @@ * INTB status registers are at range 0x5c ... 0x63 */ #define BD96801_REG_INT_SYS_ERRB1 0x52 +#define BD96801_REG_INT_BUCK2_ERRB 0x56 #define BD96801_REG_INT_SYS_INTB 0x5c +#define BD96801_REG_INT_BUCK2_INTB 0x5e #define BD96801_REG_INT_LDO7_INTB 0x63 =20 /* MASK registers */ diff --git a/include/linux/mfd/rohm-bd96802.h b/include/linux/mfd/rohm-bd96= 802.h new file mode 100644 index 000000000000..bf4b77944edf --- /dev/null +++ b/include/linux/mfd/rohm-bd96802.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2025 ROHM Semiconductors + * + * The digital interface of trhe BD96802 PMIC is a reduced version of the + * BD96801. Hence the BD96801 definitions are used for registers and masks + * while this header only holds the IRQ definitions - mainly to avoid gaps= in + * IRQ numbers caused by the lack of some BUCKs / LDOs and their respective + * IRQs. + */ + +#ifndef __LINUX_MFD_BD96802_H__ +#define __LINUX_MFD_BD96802_H__ + +/* ERRB IRQs */ +enum { + /* Reg 0x52, 0x53, 0x54 - ERRB system IRQs */ + BD96802_OTP_ERR_STAT, + BD96802_DBIST_ERR_STAT, + BD96802_EEP_ERR_STAT, + BD96802_ABIST_ERR_STAT, + BD96802_PRSTB_ERR_STAT, + BD96802_DRMOS1_ERR_STAT, + BD96802_DRMOS2_ERR_STAT, + BD96802_SLAVE_ERR_STAT, + BD96802_VREF_ERR_STAT, + BD96802_TSD_ERR_STAT, + BD96802_UVLO_ERR_STAT, + BD96802_OVLO_ERR_STAT, + BD96802_OSC_ERR_STAT, + BD96802_PON_ERR_STAT, + BD96802_POFF_ERR_STAT, + BD96802_CMD_SHDN_ERR_STAT, + BD96802_INT_SHDN_ERR_STAT, + + /* Reg 0x55 BUCK1 ERR IRQs */ + BD96802_BUCK1_PVIN_ERR_STAT, + BD96802_BUCK1_OVP_ERR_STAT, + BD96802_BUCK1_UVP_ERR_STAT, + BD96802_BUCK1_SHDN_ERR_STAT, + + /* Reg 0x56 BUCK2 ERR IRQs */ + BD96802_BUCK2_PVIN_ERR_STAT, + BD96802_BUCK2_OVP_ERR_STAT, + BD96802_BUCK2_UVP_ERR_STAT, + BD96802_BUCK2_SHDN_ERR_STAT, +}; + +/* INTB IRQs */ +enum { + /* Reg 0x5c (System INTB) */ + BD96802_TW_STAT, + BD96802_WDT_ERR_STAT, + BD96802_I2C_ERR_STAT, + BD96802_CHIP_IF_ERR_STAT, + + /* Reg 0x5d (BUCK1 INTB) */ + BD96802_BUCK1_OCPH_STAT, + BD96802_BUCK1_OCPL_STAT, + BD96802_BUCK1_OCPN_STAT, + BD96802_BUCK1_OVD_STAT, + BD96802_BUCK1_UVD_STAT, + BD96802_BUCK1_TW_CH_STAT, + + /* Reg 0x5e (BUCK2 INTB) */ + BD96802_BUCK2_OCPH_STAT, + BD96802_BUCK2_OCPL_STAT, + BD96802_BUCK2_OCPN_STAT, + BD96802_BUCK2_OVD_STAT, + BD96802_BUCK2_UVD_STAT, + BD96802_BUCK2_TW_CH_STAT, +}; + +#endif --=20 2.48.1 --KhowQEei6lKDF70+ Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQEzBAEBCAAdFiEEIx+f8wZb28fLKEhTeFA3/03aocUFAmfSxKAACgkQeFA3/03a ocWHIwf/a/FyGH9w3SbTExddgEDlMMFJZ3J5mTBIcQNYoEQ0BvKosJZPDq+TdL/O /fmIkAKMfZeViAgMe0psnWQX2ZoObWOtqLrKla5somGpzfUcdM8tufnZTDi8i/dc HFKv72RPI4SqqqDiqHwibaBP8bh/LnvMm+uKZvqX7m4PVQ/cec2sCN+Ge28FqFcF 35YCuhd3bDgUWup42GhpefIe/H9NQl1yZ8Szdl45DVJtqtvkq46lOtlHGC2ceJis P3cAnDK5WUDIqy52JC/nq7SIpCt45a6eRKxeLTtnSX3bdReaJNCaCpJ3cg8gGZ/6 8DL4vCBEeMfEhfiXZ52Roy92B00uLA== =KysR -----END PGP SIGNATURE----- --KhowQEei6lKDF70+-- From nobody Thu Dec 18 07:09:44 2025 Received: from mail-lj1-f177.google.com (mail-lj1-f177.google.com [209.85.208.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CE665266581; 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Thu, 13 Mar 2025 04:42:42 -0700 (PDT) Received: from mva-rohm ([2a10:a5c0:800d:dd00:8fdf:935a:2c85:d703]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-549ba864d7dsm183850e87.130.2025.03.13.04.42.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Mar 2025 04:42:41 -0700 (PDT) Date: Thu, 13 Mar 2025 13:42:37 +0200 From: Matti Vaittinen To: Matti Vaittinen , Matti Vaittinen Cc: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liam Girdwood , Mark Brown , Matti Vaittinen , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 09/14] regulator: bd96801: Support ROHM BD96802 Message-ID: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="DMYhEBtsz2RVNr/C" Content-Disposition: inline In-Reply-To: --DMYhEBtsz2RVNr/C Content-Disposition: inline Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The ROHM BD96802 PMIC is primarily intended to be used as a companion PMIC extending the capabilities of the BD96802 but it can be used on it's own as well. When used as a companion PMIC, the start-up and shut-down sequences are usually intitiated by the master PMIC using IF pins. The BD96802 looks from the digital interface point of view pretty much like a reduced version of BD96801. It includes only 2 BUCKs and provides the same error protection/detection mechanisms as the BD96801. Also, the voltage control logic is same up to the register addresses. Add support for controlling BD96802 using the BD96801 driver. Signed-off-by: Matti Vaittinen --- drivers/regulator/bd96801-regulator.c | 92 ++++++++++++++++++++++++--- 1 file changed, 83 insertions(+), 9 deletions(-) diff --git a/drivers/regulator/bd96801-regulator.c b/drivers/regulator/bd96= 801-regulator.c index 48cdd583e92d..893efdd92008 100644 --- a/drivers/regulator/bd96801-regulator.c +++ b/drivers/regulator/bd96801-regulator.c @@ -302,6 +302,7 @@ struct bd96801_pmic_data { struct bd96801_regulator_data regulator_data[BD96801_NUM_REGULATORS]; struct regmap *regmap; int fatal_ind; + int num_regulators; }; =20 static int ldo_map_notif(int irq, struct regulator_irq_data *rid, @@ -503,6 +504,70 @@ static int bd96801_walk_regulator_dt(struct device *de= v, struct regmap *regmap, * case later. What we can easly do for preparing is to not use static glo= bal * data for regulators though. */ +static const struct bd96801_pmic_data bd96802_data =3D { + .regulator_data =3D { + { + .desc =3D { + .name =3D "buck1", + .of_match =3D of_match_ptr("buck1"), + .regulators_node =3D of_match_ptr("regulators"), + .id =3D BD96801_BUCK1, + .ops =3D &bd96801_buck_ops, + .type =3D REGULATOR_VOLTAGE, + .linear_ranges =3D bd96801_tune_volts, + .n_linear_ranges =3D ARRAY_SIZE(bd96801_tune_volts), + .n_voltages =3D BD96801_BUCK_VOLTS, + .enable_reg =3D BD96801_REG_ENABLE, + .enable_mask =3D BD96801_BUCK1_EN_MASK, + .enable_is_inverted =3D true, + .vsel_reg =3D BD96801_BUCK1_VSEL_REG, + .vsel_mask =3D BD96801_BUCK_VSEL_MASK, + .ramp_reg =3D BD96801_BUCK1_VSEL_REG, + .ramp_mask =3D BD96801_MASK_RAMP_DELAY, + .ramp_delay_table =3D &buck_ramp_table[0], + .n_ramp_values =3D ARRAY_SIZE(buck_ramp_table), + .owner =3D THIS_MODULE, + }, + .init_ranges =3D bd96801_buck_init_volts, + .num_ranges =3D ARRAY_SIZE(bd96801_buck_init_volts), + .irq_desc =3D { + .irqinfo =3D (struct bd96801_irqinfo *)&buck1_irqinfo[0], + .num_irqs =3D ARRAY_SIZE(buck1_irqinfo), + }, + }, + { + .desc =3D { + .name =3D "buck2", + .of_match =3D of_match_ptr("buck2"), + .regulators_node =3D of_match_ptr("regulators"), + .id =3D BD96801_BUCK2, + .ops =3D &bd96801_buck_ops, + .type =3D REGULATOR_VOLTAGE, + .linear_ranges =3D bd96801_tune_volts, + .n_linear_ranges =3D ARRAY_SIZE(bd96801_tune_volts), + .n_voltages =3D BD96801_BUCK_VOLTS, + .enable_reg =3D BD96801_REG_ENABLE, + .enable_mask =3D BD96801_BUCK2_EN_MASK, + .enable_is_inverted =3D true, + .vsel_reg =3D BD96801_BUCK2_VSEL_REG, + .vsel_mask =3D BD96801_BUCK_VSEL_MASK, + .ramp_reg =3D BD96801_BUCK2_VSEL_REG, + .ramp_mask =3D BD96801_MASK_RAMP_DELAY, + .ramp_delay_table =3D &buck_ramp_table[0], + .n_ramp_values =3D ARRAY_SIZE(buck_ramp_table), + .owner =3D THIS_MODULE, + }, + .irq_desc =3D { + .irqinfo =3D (struct bd96801_irqinfo *)&buck2_irqinfo[0], + .num_irqs =3D ARRAY_SIZE(buck2_irqinfo), + }, + .init_ranges =3D bd96801_buck_init_volts, + .num_ranges =3D ARRAY_SIZE(bd96801_buck_init_volts), + }, + }, + .num_regulators =3D 2, +}; + static const struct bd96801_pmic_data bd96801_data =3D { .regulator_data =3D { { @@ -688,11 +753,13 @@ static const struct bd96801_pmic_data bd96801_data = =3D { .ldo_vol_lvl =3D BD96801_LDO7_VOL_LVL_REG, }, }, + .num_regulators =3D 7, }; =20 -static int initialize_pmic_data(struct device *dev, +static int initialize_pmic_data(struct platform_device *pdev, struct bd96801_pmic_data *pdata) { + struct device *dev =3D &pdev->dev; int r, i; =20 /* @@ -700,7 +767,7 @@ static int initialize_pmic_data(struct device *dev, * wish to modify IRQ information independently for each driver * instance. */ - for (r =3D 0; r < BD96801_NUM_REGULATORS; r++) { + for (r =3D 0; r < pdata->num_regulators; r++) { const struct bd96801_irqinfo *template; struct bd96801_irqinfo *new; int num_infos; @@ -866,6 +933,7 @@ static int bd96801_probe(struct platform_device *pdev) { struct regulator_dev *ldo_errs_rdev_arr[BD96801_NUM_LDOS]; struct regulator_dev *all_rdevs[BD96801_NUM_REGULATORS]; + struct bd96801_pmic_data *pdata_template; struct bd96801_regulator_data *rdesc; struct regulator_config config =3D {}; int ldo_errs_arr[BD96801_NUM_LDOS]; @@ -878,12 +946,16 @@ static int bd96801_probe(struct platform_device *pdev) =20 parent =3D pdev->dev.parent; =20 - pdata =3D devm_kmemdup(&pdev->dev, &bd96801_data, sizeof(bd96801_data), + pdata_template =3D (struct bd96801_pmic_data *)platform_get_device_id(pde= v)->driver_data; + if (!pdata_template) + return -ENODEV; + + pdata =3D devm_kmemdup(&pdev->dev, pdata_template, sizeof(bd96801_data), GFP_KERNEL); if (!pdata) return -ENOMEM; =20 - if (initialize_pmic_data(&pdev->dev, pdata)) + if (initialize_pmic_data(pdev, pdata)) return -ENOMEM; =20 pdata->regmap =3D dev_get_regmap(parent, NULL); @@ -906,11 +978,11 @@ static int bd96801_probe(struct platform_device *pdev) use_errb =3D true; =20 ret =3D bd96801_walk_regulator_dt(&pdev->dev, pdata->regmap, rdesc, - BD96801_NUM_REGULATORS); + pdata->num_regulators); if (ret) return ret; =20 - for (i =3D 0; i < ARRAY_SIZE(pdata->regulator_data); i++) { + for (i =3D 0; i < pdata->num_regulators; i++) { struct regulator_dev *rdev; struct bd96801_irq_desc *idesc =3D &rdesc[i].irq_desc; int j; @@ -923,6 +995,7 @@ static int bd96801_probe(struct platform_device *pdev) rdesc[i].desc.name); return PTR_ERR(rdev); } + all_rdevs[i] =3D rdev; /* * LDOs don't have own temperature monitoring. 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Thu, 13 Mar 2025 04:42:56 -0700 (PDT) Received: from mva-rohm ([2a10:a5c0:800d:dd00:8fdf:935a:2c85:d703]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-549ba879ed0sm184418e87.163.2025.03.13.04.42.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Mar 2025 04:42:55 -0700 (PDT) Date: Thu, 13 Mar 2025 13:42:51 +0200 From: Matti Vaittinen To: Matti Vaittinen , Matti Vaittinen Cc: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liam Girdwood , Mark Brown , Matti Vaittinen , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 10/14] mfd: bd96801: Support ROHM BD96805 Message-ID: <125b495859e00d16dd59046fcb117bd8cbca5f14.1741864404.git.mazziesaccount@gmail.com> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="I+I55vHc4zvWt2vm" Content-Disposition: inline In-Reply-To: --I+I55vHc4zvWt2vm Content-Disposition: inline Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The ROHM BD96805 is from the software perspective almost identical to the ROHM BD96801. The main difference is different voltage tuning ranges. Add support differentiating these PMICs based on the compatible, and invoking the regulator driver with correct IC type. Signed-off-by: Matti Vaittinen --- drivers/mfd/rohm-bd96801.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/mfd/rohm-bd96801.c b/drivers/mfd/rohm-bd96801.c index 2438cfdeecf9..2ab4e1c0f9b8 100644 --- a/drivers/mfd/rohm-bd96801.c +++ b/drivers/mfd/rohm-bd96801.c @@ -220,6 +220,10 @@ static struct mfd_cell bd96802_cells[] =3D { [WDG_CELL] =3D { .name =3D "bd96801-wdt", }, [REGULATOR_CELL] =3D { .name =3D "bd96802-regulator", }, }; +static struct mfd_cell bd96805_cells[] =3D { + [WDG_CELL] =3D { .name =3D "bd96801-wdt", }, + [REGULATOR_CELL] =3D { .name =3D "bd96805-regulator", }, +}; =20 static const struct regmap_range bd96801_volatile_ranges[] =3D { /* Status registers */ @@ -599,6 +603,20 @@ static struct bd968xx_chip_data bd96802_chip_data =3D { .unlock_val =3D BD96801_UNLOCK, }; =20 +static const struct bd968xx_chip_data bd96805_chip_data =3D { + .errb_irqs =3D bd96801_reg_errb_irqs, + .intb_irqs =3D bd96801_reg_intb_irqs, + .num_errb_irqs =3D ARRAY_SIZE(bd96801_reg_errb_irqs), + .num_intb_irqs =3D ARRAY_SIZE(bd96801_reg_intb_irqs), + .errb_irq_chip =3D &bd96801_irq_chip_errb, + .intb_irq_chip =3D &bd96801_irq_chip_intb, + .regmap_config =3D &bd96801_regmap_config, + .cells =3D bd96805_cells, + .num_cells =3D ARRAY_SIZE(bd96805_cells), + .unlock_reg =3D BD96801_LOCK_REG, + .unlock_val =3D BD96801_UNLOCK, +}; + static int bd96801_i2c_probe(struct i2c_client *i2c) { struct regmap_irq_chip_data *intb_irq_data, *errb_irq_data; @@ -709,6 +727,7 @@ static int bd96801_i2c_probe(struct i2c_client *i2c) static const struct of_device_id bd96801_of_match[] =3D { { .compatible =3D "rohm,bd96801", .data =3D &bd96801_chip_data, }, { .compatible =3D "rohm,bd96802", .data =3D &bd96802_chip_data, }, + { .compatible =3D "rohm,bd96805", .data =3D &bd96805_chip_data, }, { } }; MODULE_DEVICE_TABLE(of, bd96801_of_match); --=20 2.48.1 --I+I55vHc4zvWt2vm Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQEzBAEBCAAdFiEEIx+f8wZb28fLKEhTeFA3/03aocUFAmfSxLsACgkQeFA3/03a ocWD1QgAuGDLk8yYF1cpx4h5ns7p9Dd4egX613GQKFeFZbSVUiMWfPaD/pJbjd06 u/XAxlDalxiiF5U/TQ/QACvYr8/Op0Uumhpdko+ik+c62J/hwd88GRBp9pc17Vlk KtcCyBforIrcm9K4scbT6FhNn1TDwCpTn1idLSdNpKbCSHQqUqBYK7lMGMlcNDFr mSTFFjdZhc+xVT3qatOiVUmt2HQohfFZmdm31mt75SGfmQKtA5H22rPAf0MFSIPf gUgsYYattmXlysIgmkdzNrIEg83jXr9BOndFIhauKdGGCx4JEFBhSjPe+Jt4SKku pyWrroZZXkjIDyjxCAw3DQQKlVA7JA== =SOv0 -----END PGP SIGNATURE----- --I+I55vHc4zvWt2vm-- From nobody Thu Dec 18 07:09:44 2025 Received: from mail-lf1-f46.google.com (mail-lf1-f46.google.com [209.85.167.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DDEED2661A9; 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Thu, 13 Mar 2025 04:43:11 -0700 (PDT) Received: from mva-rohm ([2a10:a5c0:800d:dd00:8fdf:935a:2c85:d703]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-549ba7a8b11sm187664e87.30.2025.03.13.04.43.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Mar 2025 04:43:10 -0700 (PDT) Date: Thu, 13 Mar 2025 13:43:06 +0200 From: Matti Vaittinen To: Matti Vaittinen , Matti Vaittinen Cc: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liam Girdwood , Mark Brown , Matti Vaittinen , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 11/14] regulator: bd96801: Support ROHM BD96805 PMIC Message-ID: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="UTMpQQMjCORDX4ye" Content-Disposition: inline In-Reply-To: --UTMpQQMjCORDX4ye Content-Disposition: inline Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The ROHM BD96805 is from the software perspective almost identical to the ROHM BD96801. The main difference is different voltage tuning ranges. Add support differentiating these PMICs and provide correct voltages for both models. Signed-off-by: Matti Vaittinen --- drivers/regulator/bd96801-regulator.c | 207 ++++++++++++++++++++++++++ 1 file changed, 207 insertions(+) diff --git a/drivers/regulator/bd96801-regulator.c b/drivers/regulator/bd96= 801-regulator.c index 893efdd92008..d829289942f9 100644 --- a/drivers/regulator/bd96801-regulator.c +++ b/drivers/regulator/bd96801-regulator.c @@ -83,6 +83,7 @@ enum { #define BD96801_LDO6_VSEL_REG 0x26 #define BD96801_LDO7_VSEL_REG 0x27 #define BD96801_BUCK_VSEL_MASK 0x1F +#define BD96805_BUCK_VSEL_MASK 0x3f #define BD96801_LDO_VSEL_MASK 0xff =20 #define BD96801_MASK_RAMP_DELAY 0xc0 @@ -90,6 +91,7 @@ enum { #define BD96801_BUCK_INT_VOUT_MASK 0xff =20 #define BD96801_BUCK_VOLTS 256 +#define BD96805_BUCK_VOLTS 64 #define BD96801_LDO_VOLTS 256 =20 #define BD96801_OVP_MASK 0x03 @@ -160,6 +162,22 @@ static const struct linear_range bd96801_buck_init_vol= ts[] =3D { REGULATOR_LINEAR_RANGE(3300000 - 150000, 0xed, 0xff, 0), }; =20 +/* + * On BD96805 we have similar "negative tuning range" as on BD96801, except + * that the max tuning is -310 ... +310 mV (instead of the 150mV). We use = same + * approach as with the BD96801 ranges. + */ +static const struct linear_range bd96805_tune_volts[] =3D { + REGULATOR_LINEAR_RANGE(310000, 0x00, 0x1F, 10000), + REGULATOR_LINEAR_RANGE(0, 0x20, 0x3F, 10000), +}; + +static const struct linear_range bd96805_buck_init_volts[] =3D { + REGULATOR_LINEAR_RANGE(500000 - 310000, 0x00, 0xc8, 5000), + REGULATOR_LINEAR_RANGE(1550000 - 310000, 0xc9, 0xec, 50000), + REGULATOR_LINEAR_RANGE(3300000 - 310000, 0xed, 0xff, 0), +}; + static const struct linear_range bd96801_ldo_int_volts[] =3D { REGULATOR_LINEAR_RANGE(300000, 0x00, 0x78, 25000), REGULATOR_LINEAR_RANGE(3300000, 0x79, 0xff, 0), @@ -756,6 +774,194 @@ static const struct bd96801_pmic_data bd96801_data = =3D { .num_regulators =3D 7, }; =20 +static const struct bd96801_pmic_data bd96805_data =3D { + .regulator_data =3D { + { + .desc =3D { + .name =3D "buck1", + .of_match =3D of_match_ptr("buck1"), + .regulators_node =3D of_match_ptr("regulators"), + .id =3D BD96801_BUCK1, + .ops =3D &bd96801_buck_ops, + .type =3D REGULATOR_VOLTAGE, + .linear_ranges =3D bd96805_tune_volts, + .n_linear_ranges =3D ARRAY_SIZE(bd96805_tune_volts), + .n_voltages =3D BD96805_BUCK_VOLTS, + .enable_reg =3D BD96801_REG_ENABLE, + .enable_mask =3D BD96801_BUCK1_EN_MASK, + .enable_is_inverted =3D true, + .vsel_reg =3D BD96801_BUCK1_VSEL_REG, + .vsel_mask =3D BD96805_BUCK_VSEL_MASK, + .ramp_reg =3D BD96801_BUCK1_VSEL_REG, + .ramp_mask =3D BD96801_MASK_RAMP_DELAY, + .ramp_delay_table =3D &buck_ramp_table[0], + .n_ramp_values =3D ARRAY_SIZE(buck_ramp_table), + .owner =3D THIS_MODULE, + }, + .init_ranges =3D bd96805_buck_init_volts, + .num_ranges =3D ARRAY_SIZE(bd96805_buck_init_volts), + .irq_desc =3D { + .irqinfo =3D (struct bd96801_irqinfo *)&buck1_irqinfo[0], + .num_irqs =3D ARRAY_SIZE(buck1_irqinfo), + }, + }, { + .desc =3D { + .name =3D "buck2", + .of_match =3D of_match_ptr("buck2"), + .regulators_node =3D of_match_ptr("regulators"), + .id =3D BD96801_BUCK2, + .ops =3D &bd96801_buck_ops, + .type =3D REGULATOR_VOLTAGE, + .linear_ranges =3D bd96805_tune_volts, + .n_linear_ranges =3D ARRAY_SIZE(bd96805_tune_volts), + .n_voltages =3D BD96805_BUCK_VOLTS, + .enable_reg =3D BD96801_REG_ENABLE, + .enable_mask =3D BD96801_BUCK2_EN_MASK, + .enable_is_inverted =3D true, + .vsel_reg =3D BD96801_BUCK2_VSEL_REG, + .vsel_mask =3D BD96805_BUCK_VSEL_MASK, + .ramp_reg =3D BD96801_BUCK2_VSEL_REG, + .ramp_mask =3D BD96801_MASK_RAMP_DELAY, + .ramp_delay_table =3D &buck_ramp_table[0], + .n_ramp_values =3D ARRAY_SIZE(buck_ramp_table), + .owner =3D THIS_MODULE, + }, + .irq_desc =3D { + .irqinfo =3D (struct bd96801_irqinfo *)&buck2_irqinfo[0], + .num_irqs =3D ARRAY_SIZE(buck2_irqinfo), + }, + .init_ranges =3D bd96805_buck_init_volts, + .num_ranges =3D ARRAY_SIZE(bd96805_buck_init_volts), + }, { + .desc =3D { + .name =3D "buck3", + .of_match =3D of_match_ptr("buck3"), + .regulators_node =3D of_match_ptr("regulators"), + .id =3D BD96801_BUCK3, + .ops =3D &bd96801_buck_ops, + .type =3D REGULATOR_VOLTAGE, + .linear_ranges =3D bd96805_tune_volts, + .n_linear_ranges =3D ARRAY_SIZE(bd96805_tune_volts), + .n_voltages =3D BD96805_BUCK_VOLTS, + .enable_reg =3D BD96801_REG_ENABLE, + .enable_mask =3D BD96801_BUCK3_EN_MASK, + .enable_is_inverted =3D true, + .vsel_reg =3D BD96801_BUCK3_VSEL_REG, + .vsel_mask =3D BD96805_BUCK_VSEL_MASK, + .ramp_reg =3D BD96801_BUCK3_VSEL_REG, + .ramp_mask =3D BD96801_MASK_RAMP_DELAY, + .ramp_delay_table =3D &buck_ramp_table[0], + .n_ramp_values =3D ARRAY_SIZE(buck_ramp_table), + .owner =3D THIS_MODULE, + }, + .irq_desc =3D { + .irqinfo =3D (struct bd96801_irqinfo *)&buck3_irqinfo[0], + .num_irqs =3D ARRAY_SIZE(buck3_irqinfo), + }, + .init_ranges =3D bd96805_buck_init_volts, + .num_ranges =3D ARRAY_SIZE(bd96805_buck_init_volts), + }, { + .desc =3D { + .name =3D "buck4", + .of_match =3D of_match_ptr("buck4"), + .regulators_node =3D of_match_ptr("regulators"), + .id =3D BD96801_BUCK4, + .ops =3D &bd96801_buck_ops, + .type =3D REGULATOR_VOLTAGE, + .linear_ranges =3D bd96805_tune_volts, + .n_linear_ranges =3D ARRAY_SIZE(bd96805_tune_volts), + .n_voltages =3D BD96805_BUCK_VOLTS, + .enable_reg =3D BD96801_REG_ENABLE, + .enable_mask =3D BD96801_BUCK4_EN_MASK, + .enable_is_inverted =3D true, + .vsel_reg =3D BD96801_BUCK4_VSEL_REG, + .vsel_mask =3D BD96805_BUCK_VSEL_MASK, + .ramp_reg =3D BD96801_BUCK4_VSEL_REG, + .ramp_mask =3D BD96801_MASK_RAMP_DELAY, + .ramp_delay_table =3D &buck_ramp_table[0], + .n_ramp_values =3D ARRAY_SIZE(buck_ramp_table), + .owner =3D THIS_MODULE, + }, + .irq_desc =3D { + .irqinfo =3D (struct bd96801_irqinfo *)&buck4_irqinfo[0], + .num_irqs =3D ARRAY_SIZE(buck4_irqinfo), + }, + .init_ranges =3D bd96805_buck_init_volts, + .num_ranges =3D ARRAY_SIZE(bd96805_buck_init_volts), + }, { + .desc =3D { + .name =3D "ldo5", + .of_match =3D of_match_ptr("ldo5"), + .regulators_node =3D of_match_ptr("regulators"), + .id =3D BD96801_LDO5, + .ops =3D &bd96801_ldo_ops, + .type =3D REGULATOR_VOLTAGE, + .linear_ranges =3D bd96801_ldo_int_volts, + .n_linear_ranges =3D ARRAY_SIZE(bd96801_ldo_int_volts), + .n_voltages =3D BD96801_LDO_VOLTS, + .enable_reg =3D BD96801_REG_ENABLE, + .enable_mask =3D BD96801_LDO5_EN_MASK, + .enable_is_inverted =3D true, + .vsel_reg =3D BD96801_LDO5_VSEL_REG, + .vsel_mask =3D BD96801_LDO_VSEL_MASK, + .owner =3D THIS_MODULE, + }, + .irq_desc =3D { + .irqinfo =3D (struct bd96801_irqinfo *)&ldo5_irqinfo[0], + .num_irqs =3D ARRAY_SIZE(ldo5_irqinfo), + }, + .ldo_vol_lvl =3D BD96801_LDO5_VOL_LVL_REG, + }, { + .desc =3D { + .name =3D "ldo6", + .of_match =3D of_match_ptr("ldo6"), + .regulators_node =3D of_match_ptr("regulators"), + .id =3D BD96801_LDO6, + .ops =3D &bd96801_ldo_ops, + .type =3D REGULATOR_VOLTAGE, + .linear_ranges =3D bd96801_ldo_int_volts, + .n_linear_ranges =3D ARRAY_SIZE(bd96801_ldo_int_volts), + .n_voltages =3D BD96801_LDO_VOLTS, + .enable_reg =3D BD96801_REG_ENABLE, + .enable_mask =3D BD96801_LDO6_EN_MASK, + .enable_is_inverted =3D true, + .vsel_reg =3D BD96801_LDO6_VSEL_REG, + .vsel_mask =3D BD96801_LDO_VSEL_MASK, + .owner =3D THIS_MODULE, + }, + .irq_desc =3D { + .irqinfo =3D (struct bd96801_irqinfo *)&ldo6_irqinfo[0], + .num_irqs =3D ARRAY_SIZE(ldo6_irqinfo), + }, + .ldo_vol_lvl =3D BD96801_LDO6_VOL_LVL_REG, + }, { + .desc =3D { + .name =3D "ldo7", + .of_match =3D of_match_ptr("ldo7"), + .regulators_node =3D of_match_ptr("regulators"), + .id =3D BD96801_LDO7, + .ops =3D &bd96801_ldo_ops, + .type =3D REGULATOR_VOLTAGE, + .linear_ranges =3D bd96801_ldo_int_volts, + .n_linear_ranges =3D ARRAY_SIZE(bd96801_ldo_int_volts), + .n_voltages =3D BD96801_LDO_VOLTS, + .enable_reg =3D BD96801_REG_ENABLE, + .enable_mask =3D BD96801_LDO7_EN_MASK, + .enable_is_inverted =3D true, + .vsel_reg =3D BD96801_LDO7_VSEL_REG, + .vsel_mask =3D BD96801_LDO_VSEL_MASK, + .owner =3D THIS_MODULE, + }, + .irq_desc =3D { + .irqinfo =3D (struct bd96801_irqinfo *)&ldo7_irqinfo[0], + .num_irqs =3D ARRAY_SIZE(ldo7_irqinfo), + }, + .ldo_vol_lvl =3D BD96801_LDO7_VOL_LVL_REG, + }, + }, + .num_regulators =3D 7, +}; + static int initialize_pmic_data(struct platform_device *pdev, struct bd96801_pmic_data *pdata) { @@ -1053,6 +1259,7 @@ static int bd96801_probe(struct platform_device *pdev) static const struct platform_device_id bd96801_pmic_id[] =3D { { "bd96801-regulator", (kernel_ulong_t)&bd96801_data }, { "bd96802-regulator", (kernel_ulong_t)&bd96802_data }, + { "bd96805-regulator", (kernel_ulong_t)&bd96805_data }, { }, }; MODULE_DEVICE_TABLE(platform, bd96801_pmic_id); --=20 2.48.1 --UTMpQQMjCORDX4ye Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQEzBAEBCAAdFiEEIx+f8wZb28fLKEhTeFA3/03aocUFAmfSxMoACgkQeFA3/03a ocW0Ogf/WkmZu/JAHSDI8Bj50WDT0UKToQMGNRtEEmzQgP0SSSVpijl5fgjsRr0e QFmVtObOvrgDtuAS0aGV7QdBSGVviJ21VFlXpvhrVurfV7w6TOE+BExQ4LFUs/Ab 3Z9L+yLGjjzOon9U5lYi4y+e8xvQbeYxE3zdBoeTgfLAGZ57bO/tCfe+BHL+9N8h ykSmct4ke1AFg7LHJ63cmECtPKATvnxANqTbyRFGAsbySFePGsdKDEjV9zoQ2jRU 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<8fd61949bdd3a85f19c86fc3e2e768a990803586.1741864404.git.mazziesaccount@gmail.com> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="twVtW0S7FqJP+3Is" Content-Disposition: inline In-Reply-To: --twVtW0S7FqJP+3Is Content-Disposition: inline Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The ROHM BD96806 is from the software perspective almost identical to the ROHM BD96802. The main difference is different voltage tuning ranges. Add support differentiating these PMICs based on the compatible, and invoking the regulator driver with correct IC type. Signed-off-by: Matti Vaittinen --- drivers/mfd/rohm-bd96801.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/mfd/rohm-bd96801.c b/drivers/mfd/rohm-bd96801.c index 2ab4e1c0f9b8..3b85aaa27f54 100644 --- a/drivers/mfd/rohm-bd96801.c +++ b/drivers/mfd/rohm-bd96801.c @@ -225,6 +225,11 @@ static struct mfd_cell bd96805_cells[] =3D { [REGULATOR_CELL] =3D { .name =3D "bd96805-regulator", }, }; =20 +static struct mfd_cell bd96806_cells[] =3D { + [WDG_CELL] =3D { .name =3D "bd96806-wdt", }, + [REGULATOR_CELL] =3D { .name =3D "bd96806-regulator", }, +}; + static const struct regmap_range bd96801_volatile_ranges[] =3D { /* Status registers */ regmap_reg_range(BD96801_REG_WD_FEED, BD96801_REG_WD_FAILCOUNT), @@ -617,6 +622,20 @@ static const struct bd968xx_chip_data bd96805_chip_dat= a =3D { .unlock_val =3D BD96801_UNLOCK, }; =20 +static struct bd968xx_chip_data bd96806_chip_data =3D { + .errb_irqs =3D bd96802_reg_errb_irqs, + .intb_irqs =3D bd96802_reg_intb_irqs, + .num_errb_irqs =3D ARRAY_SIZE(bd96802_reg_errb_irqs), + .num_intb_irqs =3D ARRAY_SIZE(bd96802_reg_intb_irqs), + .errb_irq_chip =3D &bd96802_irq_chip_errb, + .intb_irq_chip =3D &bd96802_irq_chip_intb, + .regmap_config =3D &bd96802_regmap_config, + .cells =3D bd96806_cells, + .num_cells =3D ARRAY_SIZE(bd96806_cells), + .unlock_reg =3D BD96801_LOCK_REG, + .unlock_val =3D BD96801_UNLOCK, +}; + static int bd96801_i2c_probe(struct i2c_client *i2c) { struct regmap_irq_chip_data *intb_irq_data, *errb_irq_data; @@ -728,6 +747,7 @@ static const struct of_device_id bd96801_of_match[] =3D= { { .compatible =3D "rohm,bd96801", .data =3D &bd96801_chip_data, }, { .compatible =3D "rohm,bd96802", .data =3D &bd96802_chip_data, }, { .compatible =3D "rohm,bd96805", .data =3D &bd96805_chip_data, }, + { .compatible =3D "rohm,bd96806", .data =3D &bd96806_chip_data, }, { } }; MODULE_DEVICE_TABLE(of, bd96801_of_match); --=20 2.48.1 --twVtW0S7FqJP+3Is Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQEzBAEBCAAdFiEEIx+f8wZb28fLKEhTeFA3/03aocUFAmfSxNYACgkQeFA3/03a ocXT6Qf9GHv4kVj0p+kl+w7jKhDKmM5R2io6m/uS5RFMCUjfv18ZimvDuirZcfL+ ZVsW6ig8EerNjyeD+mxJpAF32SR+KtAk1/KdvWCcjzpAqK2K9PRdIrNLCbngwaW5 +ajPLifPQxqbO/SEMMJQsjPav6EgRBRWd/3uf5n5688QlHubrgmjhjAN4yQaD2yz TLsejfSimGMaaN9b8UKboeCMIY28N0dgGlNKdcXAggdTw7lvgmN7EvgHOO5zH7PA uPxf+k182dk/nlrku5QXjXqfAT57H8VJbZTK0y1rTQPahfY2PD58e20hR9P6AbYt 9+5I8rZizupdr/5DG9zWuQq64oazog== =CU5T -----END PGP SIGNATURE----- --twVtW0S7FqJP+3Is-- From nobody Thu Dec 18 07:09:44 2025 Received: from mail-lj1-f170.google.com (mail-lj1-f170.google.com [209.85.208.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9998C266B68; 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Thu, 13 Mar 2025 04:43:35 -0700 (PDT) Received: from mva-rohm ([2a10:a5c0:800d:dd00:8fdf:935a:2c85:d703]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-549ba7ce9e3sm186339e87.106.2025.03.13.04.43.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Mar 2025 04:43:34 -0700 (PDT) Date: Thu, 13 Mar 2025 13:43:31 +0200 From: Matti Vaittinen To: Matti Vaittinen , Matti Vaittinen Cc: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liam Girdwood , Mark Brown , Matti Vaittinen , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 13/14] regulator: bd96801: Support ROHM BD96806 PMIC Message-ID: <1cd9265e4396296d05db100d74f334e7f95c7907.1741864404.git.mazziesaccount@gmail.com> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="nuj5i02+lN0dO3xp" Content-Disposition: inline In-Reply-To: --nuj5i02+lN0dO3xp Content-Disposition: inline Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The ROHM BD96806 is from the software perspective almost identical to the ROHM BD96802. The main difference is different voltage tuning ranges. Add support differentiating these PMICs and provide correct voltages for both models. Signed-off-by: Matti Vaittinen --- drivers/regulator/bd96801-regulator.c | 65 +++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/drivers/regulator/bd96801-regulator.c b/drivers/regulator/bd96= 801-regulator.c index d829289942f9..fb9e7c3314a3 100644 --- a/drivers/regulator/bd96801-regulator.c +++ b/drivers/regulator/bd96801-regulator.c @@ -962,6 +962,70 @@ static const struct bd96801_pmic_data bd96805_data =3D= { .num_regulators =3D 7, }; =20 +static const struct bd96801_pmic_data bd96806_data =3D { + .regulator_data =3D { + { + .desc =3D { + .name =3D "buck1", + .of_match =3D of_match_ptr("buck1"), + .regulators_node =3D of_match_ptr("regulators"), + .id =3D BD96801_BUCK1, + .ops =3D &bd96801_buck_ops, + .type =3D REGULATOR_VOLTAGE, + .linear_ranges =3D bd96805_tune_volts, + .n_linear_ranges =3D ARRAY_SIZE(bd96805_tune_volts), + .n_voltages =3D BD96805_BUCK_VOLTS, + .enable_reg =3D BD96801_REG_ENABLE, + .enable_mask =3D BD96801_BUCK1_EN_MASK, + .enable_is_inverted =3D true, + .vsel_reg =3D BD96801_BUCK1_VSEL_REG, + .vsel_mask =3D BD96805_BUCK_VSEL_MASK, + .ramp_reg =3D BD96801_BUCK1_VSEL_REG, + .ramp_mask =3D BD96801_MASK_RAMP_DELAY, + .ramp_delay_table =3D &buck_ramp_table[0], + .n_ramp_values =3D ARRAY_SIZE(buck_ramp_table), + .owner =3D THIS_MODULE, + }, + .init_ranges =3D bd96801_buck_init_volts, + .num_ranges =3D ARRAY_SIZE(bd96801_buck_init_volts), + .irq_desc =3D { + .irqinfo =3D (struct bd96801_irqinfo *)&buck1_irqinfo[0], + .num_irqs =3D ARRAY_SIZE(buck1_irqinfo), + }, + }, + { + .desc =3D { + .name =3D "buck2", + .of_match =3D of_match_ptr("buck2"), + .regulators_node =3D of_match_ptr("regulators"), + .id =3D BD96801_BUCK2, + .ops =3D &bd96801_buck_ops, + .type =3D REGULATOR_VOLTAGE, + .linear_ranges =3D bd96805_tune_volts, + .n_linear_ranges =3D ARRAY_SIZE(bd96805_tune_volts), + .n_voltages =3D BD96805_BUCK_VOLTS, + .enable_reg =3D BD96801_REG_ENABLE, + .enable_mask =3D BD96801_BUCK2_EN_MASK, + .enable_is_inverted =3D true, + .vsel_reg =3D BD96801_BUCK2_VSEL_REG, + .vsel_mask =3D BD96805_BUCK_VSEL_MASK, + .ramp_reg =3D BD96801_BUCK2_VSEL_REG, + .ramp_mask =3D BD96801_MASK_RAMP_DELAY, + .ramp_delay_table =3D &buck_ramp_table[0], + .n_ramp_values =3D ARRAY_SIZE(buck_ramp_table), + .owner =3D THIS_MODULE, + }, + .irq_desc =3D { + .irqinfo =3D (struct bd96801_irqinfo *)&buck2_irqinfo[0], + .num_irqs =3D ARRAY_SIZE(buck2_irqinfo), + }, + .init_ranges =3D bd96801_buck_init_volts, + .num_ranges =3D ARRAY_SIZE(bd96801_buck_init_volts), + }, + }, + .num_regulators =3D 2, +}; + static int initialize_pmic_data(struct platform_device *pdev, struct bd96801_pmic_data *pdata) { @@ -1260,6 +1324,7 @@ static const struct platform_device_id bd96801_pmic_i= d[] =3D { { "bd96801-regulator", (kernel_ulong_t)&bd96801_data }, { "bd96802-regulator", (kernel_ulong_t)&bd96802_data }, { "bd96805-regulator", (kernel_ulong_t)&bd96805_data }, + { "bd96806-regulator", (kernel_ulong_t)&bd96806_data }, { }, }; MODULE_DEVICE_TABLE(platform, bd96801_pmic_id); --=20 2.48.1 --nuj5i02+lN0dO3xp Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQEzBAEBCAAdFiEEIx+f8wZb28fLKEhTeFA3/03aocUFAmfSxOMACgkQeFA3/03a ocUD6AgAqOEi2FLJFEU8mmru9URPSLjoFj6MJ3fe+Z3ZfJv5n1VJCXtATIwXu+Ic ieSfREA8+dluWdAMPRwMiElLQ+81a+bxQkUTmNcs2iLvVOnDuOghtNfbEUpdlXeI xYF026zjpbCPevAYOf59JJvYPe2Si/Gp0/tolc/fw1HhvIE2F2gCiB5uUv6nsgRt QRU5TF0//WUBktivi/dSW8urxFYU2EvmJP5adkzf7h1ZtCQSJKc2eh82ZwCIIOq5 zvu04ZId+eRO5hC/yV0D4yPil33IfeFCMsNTrNnkjnpktnaVtx1yc9DVHe2M4tLQ Lk9+PiFDEI9SvWvUPqLYMxwfMxOtEQ== =mEk8 -----END PGP SIGNATURE----- --nuj5i02+lN0dO3xp-- From nobody Thu Dec 18 07:09:44 2025 Received: from mail-lf1-f51.google.com (mail-lf1-f51.google.com [209.85.167.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 10685266B68; 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Thu, 13 Mar 2025 04:43:47 -0700 (PDT) Received: from mva-rohm ([2a10:a5c0:800d:dd00:8fdf:935a:2c85:d703]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-549ba7a81afsm189440e87.24.2025.03.13.04.43.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Mar 2025 04:43:47 -0700 (PDT) Date: Thu, 13 Mar 2025 13:43:43 +0200 From: Matti Vaittinen To: Matti Vaittinen , Matti Vaittinen Cc: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liam Girdwood , Mark Brown , Matti Vaittinen , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 14/14] MAINTAINERS: Add BD96802 specific header Message-ID: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="zUuIGOnMsVdPAjjC" Content-Disposition: inline In-Reply-To: --zUuIGOnMsVdPAjjC Content-Disposition: inline Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add the include/linux/mfd/rohm-bd96802.h to the list of the ROHM PMIC specific files maintained by the undersigned. Signed-off-by: Matti Vaittinen --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 8e0736dc2ee0..973f0e06b2a2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20599,6 +20599,7 @@ F: include/linux/mfd/rohm-bd71828.h F: include/linux/mfd/rohm-bd718x7.h F: include/linux/mfd/rohm-bd957x.h F: include/linux/mfd/rohm-bd96801.h +F: include/linux/mfd/rohm-bd96802.h F: include/linux/mfd/rohm-generic.h F: include/linux/mfd/rohm-shared.h =20 --=20 2.48.1 --zUuIGOnMsVdPAjjC Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQEzBAEBCAAdFiEEIx+f8wZb28fLKEhTeFA3/03aocUFAmfSxO8ACgkQeFA3/03a ocURBwgAkj3dFZmJd2ZcP//BK+LRtwLqsF0IPSjWhqShDei/H658nfs2nIPLIFVl dhx3nEFecntFIMWlmkSQb4aVrHbcyuPIUDPrhXyAp8zeVZZ0oj2aQfULOMrRt0RC bMvyvWL+r3Fm5zN4AUsfURpewlpjK0HzW2/Go9HOIYU94/BCZPUFeTDAgPhf1YXA W4S2jhnVbzkeRLWMj4i905S5zoP8/5YQDvBoX5uC8zExhepNzxuZh6+qjC50xCg2 LPcwVcdUDLkPht+REZpsOh7xj7dUYpkP6VLvfp1WCp2WwG0PeP6dsBujcA+zSa9N s/bdAEtUQNbgpaP6mE0WVZrWxvEvRQ== =W6Me -----END PGP SIGNATURE----- --zUuIGOnMsVdPAjjC--