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Tue, 4 Mar 2025 21:05:08 -0800 From: Nicolin Chen To: , , CC: , , , , Subject: [PATCH v1 1/4] iommu/arm-smmu-v3: Pass in vmid to arm_smmu_make_s2_domain_ste() Date: Tue, 4 Mar 2025 21:04:00 -0800 Message-ID: <214b10db02f1046efdc70e2c4803111357f60070.1741150594.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044AB:EE_|PH7PR12MB6610:EE_ X-MS-Office365-Filtering-Correlation-Id: ad65fe9e-ac1c-4603-7ef6-08dd5ba35536 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|36860700013|1800799024|30052699003; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?LKOubk2EL9+5UC3BGh7HjYEdM2RAs/HaNVIMT5RiLeY+VBtrel42J1Pc+6q9?= =?us-ascii?Q?+Rf/vcryYRzTT9OOgtUbSg1Ig6vOutVyrF+QOlzAIGWIoDzxuv/kxjq7GuqR?= =?us-ascii?Q?2Ilu6STD1MNbU/QsBDWyOPZ3cQ83lwB5GLv9AHnME3qxyDtLvE/VOmuaOSyf?= =?us-ascii?Q?o5+9Hq+1YseLkYsEmRNOXtMprS+rHNz6KLJNhUcb8g8bJo/V4FIau5UABq4k?= =?us-ascii?Q?bs4yqU8cLIGckU8Qr0wHONXslx6n8xOZKrUCTeynb9+ciPsw5FFuc3XC1jos?= =?us-ascii?Q?7kvwzhnrgc6+VQSXXK6cHFWdy/pLTnMf9APsbrI5O3zfD7XkpXD0Ul2KD3bR?= =?us-ascii?Q?Du6mJ4qEt745ZnQuk4RMDjW5a+tLFddccODJNfnIsoG+e94znx5sWshqEeKj?= =?us-ascii?Q?GqPBoOhZKUKnbZVQjg4VkPH0+Wt+3VUr0dKRqB3GGAh+A5oV5Y5/6o4WOYM6?= =?us-ascii?Q?PHFK3OLQ7ZnjevuGkcOkRQYfRfFd/BtXdCeNMt5+ZgvqXQ2eMF80VSwmL1Xq?= =?us-ascii?Q?fsMCObv9PsOmemvezPFJFWMtR+g9E1D6iLF1u1WcwvH7KhtdIBe0NseLvdDq?= =?us-ascii?Q?9f46GE+yAWDB/U99/I2IUqlI6llMaHLCPsrUrky3VNZw5ubb96vMeU+clhFq?= =?us-ascii?Q?ub3oZpifKVnY8PaPRN9xZXt4pVZerLRr4o5Z4keEofhCJRi9D7FKimu4SqhN?= =?us-ascii?Q?fFXoW/o3AbnS4hWxjlxG7ufuA+KDcjxj1vWG8shALkZhY4Lc2zv4rGa4whAl?= =?us-ascii?Q?qs06tpF3ekLhErEyOlqw2sRF3NiI80rum8hgdOSU+2d11Clo1pyqUJSyo4aE?= =?us-ascii?Q?R6zyw4c0H/04sA9Bb2xGL52tfmr8bQZbAQN1l13usdYUWLalS8SX/pe4AYFx?= =?us-ascii?Q?6orB9uOv1kKFPon0SyORZtHybz3q//C5zmWDPl5iGJ3Sr8xOHW4NhIqwp5xw?= =?us-ascii?Q?YF/mFdZrratYw0rhAW0xRx9DxDnWrjqSHZMHZ0e3DR8Zur537KB2smEXWplX?= =?us-ascii?Q?LpiJnKnm+YoCK11samMx0I55sKoNu5Q3vuHoVxcLsn5yvKFZ0qlhn/wqf2Ys?= =?us-ascii?Q?LbV71JbwYG7Rat0I1cNFpdA/bTOEWAsMRxavYjml8N//r2GtA7POVPb7ekoS?= =?us-ascii?Q?vsghdSlJXIZz5RSL9yZxVULSBKgRtFve0PaisUJCMFufdYS+5cr3AIs8LTZd?= =?us-ascii?Q?if0xgjaqF1g4yiSNjss5knDgRwvxVl2/kHW42zRjbfhAXzko78QotZb5Kfik?= =?us-ascii?Q?w8xNW+ht+j0i2fAUz/0QjN35okn20Dc+7RqMRQzJIQ2hh9MjUe2Ni70uR76H?= =?us-ascii?Q?nPMza1foOMUgAJmrIl86Rp5HqDoGNB0Hg5bufVSPm9sPhs6eLXy2ftSD4YE/?= =?us-ascii?Q?TZnzOA11ZqoI1zYpmKnNKsBZOTI5d91jGwF499mHbKGCnjWCNT2I8cGkqFnQ?= =?us-ascii?Q?h1MvEOy7P1Brz1kxZO0UoFUKouA5dmsJO2syBnob0j2TPdQNBca5iTqiHD7X?= =?us-ascii?Q?f7GMkVI3nx7+XwQ=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(376014)(36860700013)(1800799024)(30052699003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Mar 2025 05:05:22.1878 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ad65fe9e-ac1c-4603-7ef6-08dd5ba35536 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044AB.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6610 Content-Type: text/plain; charset="utf-8" An stage-2 STE requires a vmid that has been so far allocated per domain, so arm_smmu_make_s2_domain_ste() has been extracting the vmid from the S2 domain. To share an S2 parent domain across vSMMUs in the same VM, a vmid will be no longer allocated for nor stored in the S2 domain, but per vSMMU, which means the arm_smmu_make_s2_domain_ste() can get a vmid either from an S2 domain (non nesting parent) or a vSMMU. Allow to pass in vmid explicitly to arm_smmu_make_s2_domain_ste(), giving its callers a chance to pick the vmid between a domain or a vSMMU. Signed-off-by: Nicolin Chen Reviewed-by: Jason Gunthorpe Reviewed-by: Pranjal Shrivastava --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 +- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 6 ++++-- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c | 3 ++- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 6 +++--- 4 files changed, 10 insertions(+), 7 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index bd9d7c85576a..e08c4ede4b2d 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -887,7 +887,7 @@ struct arm_smmu_entry_writer_ops { void arm_smmu_make_abort_ste(struct arm_smmu_ste *target); void arm_smmu_make_s2_domain_ste(struct arm_smmu_ste *target, struct arm_smmu_master *master, - struct arm_smmu_domain *smmu_domain, + struct arm_smmu_domain *smmu_domain, u16 vmid, bool ats_enabled); =20 #if IS_ENABLED(CONFIG_KUNIT) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c b/drivers/= iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c index 5aa2e7af58b4..ff8b550159f2 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c @@ -34,8 +34,9 @@ static void arm_smmu_make_nested_cd_table_ste( struct arm_smmu_ste *target, struct arm_smmu_master *master, struct arm_smmu_nested_domain *nested_domain, bool ats_enabled) { - arm_smmu_make_s2_domain_ste( - target, master, nested_domain->vsmmu->s2_parent, ats_enabled); + arm_smmu_make_s2_domain_ste(target, master, + nested_domain->vsmmu->s2_parent, + nested_domain->vsmmu->vmid, ats_enabled); =20 target->data[0] =3D cpu_to_le64(STRTAB_STE_0_V | FIELD_PREP(STRTAB_STE_0_CFG, @@ -76,6 +77,7 @@ static void arm_smmu_make_nested_domain_ste( case STRTAB_STE_0_CFG_BYPASS: arm_smmu_make_s2_domain_ste(target, master, nested_domain->vsmmu->s2_parent, + nested_domain->vsmmu->vmid, ats_enabled); break; case STRTAB_STE_0_CFG_ABORT: diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c b/drivers/iom= mu/arm/arm-smmu-v3/arm-smmu-v3-test.c index d2671bfd3798..7fac5a112c5c 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c @@ -316,7 +316,8 @@ static void arm_smmu_test_make_s2_ste(struct arm_smmu_s= te *ste, io_pgtable.cfg.arm_lpae_s2_cfg.vtcr.sl =3D 3; io_pgtable.cfg.arm_lpae_s2_cfg.vtcr.tsz =3D 4; =20 - arm_smmu_make_s2_domain_ste(ste, &master, &smmu_domain, ats_enabled); + arm_smmu_make_s2_domain_ste(ste, &master, &smmu_domain, + smmu_domain.s2_cfg.vmid, ats_enabled); } =20 static void arm_smmu_v3_write_ste_test_s2_to_abort(struct kunit *test) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 358072b4e293..310bb4109ec9 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1656,10 +1656,9 @@ EXPORT_SYMBOL_IF_KUNIT(arm_smmu_make_cdtable_ste); =20 void arm_smmu_make_s2_domain_ste(struct arm_smmu_ste *target, struct arm_smmu_master *master, - struct arm_smmu_domain *smmu_domain, + struct arm_smmu_domain *smmu_domain, u16 vmid, bool ats_enabled) { - struct arm_smmu_s2_cfg *s2_cfg =3D &smmu_domain->s2_cfg; const struct io_pgtable_cfg *pgtbl_cfg =3D &io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops)->cfg; typeof(&pgtbl_cfg->arm_lpae_s2_cfg.vtcr) vtcr =3D @@ -1690,7 +1689,7 @@ void arm_smmu_make_s2_domain_ste(struct arm_smmu_ste = *target, FIELD_PREP(STRTAB_STE_2_VTCR_S2TG, vtcr->tg) | FIELD_PREP(STRTAB_STE_2_VTCR_S2PS, vtcr->ps); target->data[2] =3D cpu_to_le64( - FIELD_PREP(STRTAB_STE_2_S2VMID, s2_cfg->vmid) | + FIELD_PREP(STRTAB_STE_2_S2VMID, vmid) | FIELD_PREP(STRTAB_STE_2_VTCR, vtcr_val) | STRTAB_STE_2_S2AA64 | #ifdef __BIG_ENDIAN @@ -2969,6 +2968,7 @@ static int arm_smmu_attach_dev(struct iommu_domain *d= omain, struct device *dev) } case ARM_SMMU_DOMAIN_S2: arm_smmu_make_s2_domain_ste(&target, master, smmu_domain, + smmu_domain->s2_cfg.vmid, state.ats_enabled); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Mar 2025 05:05:25.4957 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cd5177a2-7231-420f-1514-08dd5ba35728 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000147.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8070 Content-Type: text/plain; charset="utf-8" Allow arm-smmu-v3-iommufd to call it for S2 cache invalidations. Signed-off-by: Nicolin Chen Reviewed-by: Pranjal Shrivastava --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 ++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 4 ++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index e08c4ede4b2d..3336d196062c 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -984,6 +984,8 @@ void arm_smmu_install_ste_for_dev(struct arm_smmu_maste= r *master, int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu, struct arm_smmu_cmdq *cmdq, u64 *cmds, int n, bool sync); +int arm_smmu_cmdq_issue_cmd_with_sync(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq_ent *ent); =20 #ifdef CONFIG_ARM_SMMU_V3_SVA bool arm_smmu_sva_supported(struct arm_smmu_device *smmu); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 310bb4109ec9..0462eb1b2912 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -929,8 +929,8 @@ static int arm_smmu_cmdq_issue_cmd(struct arm_smmu_devi= ce *smmu, return __arm_smmu_cmdq_issue_cmd(smmu, ent, false); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Mar 2025 05:05:26.2024 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fdb02c97-c2c9-4a86-ec22-08dd5ba35793 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000144.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB9042 Content-Type: text/plain; charset="utf-8" An S2 nest_parent domain can be shared across vSMMUs in the same VM, since the S2 domain is basically the IPA mappings for the entire RAM of the VM. Meanwhile, each vSMMU can have its own VMID, so the VMID allocation should be done per vSMMU instance v.s. per S2 nest_parent domain. However, an S2 domain can be also allocated when a physical SMMU instance doesn't support S1. So, the structure has to retain the s2_cfg and vmid. Allocate a vmid for a vSMMU instance in arm_vsmmu_alloc() and add a proper arm_vsmmu_destroy() to clean it up. Add a per-domain "vsmmus" list pairing with a spinlock, maintaining a list on the S2 parent domain, to iterate S2 invalidations over the vmids across the vSMMU instances created for the same VM. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 10 +++- .../arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 35 ++++++++++++-- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 47 +++++++++++++++---- 3 files changed, 79 insertions(+), 13 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 3336d196062c..1f6696bc4f6c 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -849,8 +849,12 @@ struct arm_smmu_domain { =20 enum arm_smmu_domain_stage stage; union { - struct arm_smmu_ctx_desc cd; - struct arm_smmu_s2_cfg s2_cfg; + struct arm_smmu_ctx_desc cd; /* S1 */ + struct arm_smmu_s2_cfg s2_cfg; /* S2 && !nest_parent */ + struct { /* S2 && nest_parent */ + struct list_head list; + spinlock_t lock; + } vsmmus; }; =20 struct iommu_domain domain; @@ -1049,6 +1053,8 @@ struct arm_vsmmu { struct arm_smmu_device *smmu; struct arm_smmu_domain *s2_parent; u16 vmid; + + struct list_head vsmmus_elm; /* arm_smmu_domain::vsmmus::list */ }; =20 #if IS_ENABLED(CONFIG_ARM_SMMU_V3_IOMMUFD) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c b/drivers/= iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c index ff8b550159f2..2c5a9d0abed5 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c @@ -30,6 +30,23 @@ void *arm_smmu_hw_info(struct device *dev, u32 *length, = u32 *type) return info; } =20 +static void arm_vsmmu_destroy(struct iommufd_viommu *viommu) +{ + struct arm_vsmmu *vsmmu =3D container_of(viommu, struct arm_vsmmu, core); + struct arm_smmu_device *smmu =3D vsmmu->smmu; + struct arm_smmu_cmdq_ent cmd =3D { + .opcode =3D CMDQ_OP_TLBI_S12_VMALL, + .tlbi.vmid =3D vsmmu->vmid, + }; + unsigned long flags; + + spin_lock_irqsave(&vsmmu->s2_parent->vsmmus.lock, flags); + list_del(&vsmmu->vsmmus_elm); + spin_unlock_irqrestore(&vsmmu->s2_parent->vsmmus.lock, flags); + arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); + ida_free(&smmu->vmid_map, vsmmu->vmid); +} + static void arm_smmu_make_nested_cd_table_ste( struct arm_smmu_ste *target, struct arm_smmu_master *master, struct arm_smmu_nested_domain *nested_domain, bool ats_enabled) @@ -337,6 +354,7 @@ static int arm_vsmmu_cache_invalidate(struct iommufd_vi= ommu *viommu, } =20 static const struct iommufd_viommu_ops arm_vsmmu_ops =3D { + .destroy =3D arm_vsmmu_destroy, .alloc_domain_nested =3D arm_vsmmu_alloc_domain_nested, .cache_invalidate =3D arm_vsmmu_cache_invalidate, }; @@ -351,6 +369,8 @@ struct iommufd_viommu *arm_vsmmu_alloc(struct device *d= ev, struct arm_smmu_master *master =3D dev_iommu_priv_get(dev); struct arm_smmu_domain *s2_parent =3D to_smmu_domain(parent); struct arm_vsmmu *vsmmu; + unsigned long flags; + int vmid; =20 if (viommu_type !=3D IOMMU_VIOMMU_TYPE_ARM_SMMUV3) return ERR_PTR(-EOPNOTSUPP); @@ -381,15 +401,24 @@ struct iommufd_viommu *arm_vsmmu_alloc(struct device = *dev, !(smmu->features & ARM_SMMU_FEAT_S2FWB)) return ERR_PTR(-EOPNOTSUPP); =20 + vmid =3D ida_alloc_range(&smmu->vmid_map, 1, (1 << smmu->vmid_bits) - 1, + GFP_KERNEL); + if (vmid < 0) + return ERR_PTR(vmid); + vsmmu =3D iommufd_viommu_alloc(ictx, struct arm_vsmmu, core, &arm_vsmmu_ops); - if (IS_ERR(vsmmu)) + if (IS_ERR(vsmmu)) { + ida_free(&smmu->vmid_map, vmid); return ERR_CAST(vsmmu); + } =20 vsmmu->smmu =3D smmu; + vsmmu->vmid =3D (u16)vmid; vsmmu->s2_parent =3D s2_parent; - /* FIXME Move VMID allocation from the S2 domain allocation to here */ - vsmmu->vmid =3D s2_parent->s2_cfg.vmid; + spin_lock_irqsave(&s2_parent->vsmmus.lock, flags); + list_add_tail(&vsmmu->vsmmus_elm, &s2_parent->vsmmus.list); + spin_unlock_irqrestore(&s2_parent->vsmmus.lock, flags); =20 return &vsmmu->core; } diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 0462eb1b2912..addc6308742b 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2249,10 +2249,22 @@ static void arm_smmu_tlb_inv_context(void *cookie) */ if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1) { arm_smmu_tlb_inv_asid(smmu, smmu_domain->cd.asid); - } else { + } else if (!smmu_domain->nest_parent) { cmd.opcode =3D CMDQ_OP_TLBI_S12_VMALL; cmd.tlbi.vmid =3D smmu_domain->s2_cfg.vmid; arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); + } else { + struct arm_vsmmu *vsmmu, *next; + unsigned long flags; + + cmd.opcode =3D CMDQ_OP_TLBI_S12_VMALL; + spin_lock_irqsave(&smmu_domain->vsmmus.lock, flags); + list_for_each_entry_safe(vsmmu, next, &smmu_domain->vsmmus.list, + vsmmus_elm) { + cmd.tlbi.vmid =3D vsmmu->vmid; + arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); + } + spin_unlock_irqrestore(&smmu_domain->vsmmus.lock, flags); } arm_smmu_atc_inv_domain(smmu_domain, 0, 0); } @@ -2342,19 +2354,33 @@ static void arm_smmu_tlb_inv_range_domain(unsigned = long iova, size_t size, cmd.opcode =3D smmu_domain->smmu->features & ARM_SMMU_FEAT_E2H ? CMDQ_OP_TLBI_EL2_VA : CMDQ_OP_TLBI_NH_VA; cmd.tlbi.asid =3D smmu_domain->cd.asid; - } else { + __arm_smmu_tlb_inv_range(&cmd, iova, size, granule, + smmu_domain); + } else if (!smmu_domain->nest_parent) { cmd.opcode =3D CMDQ_OP_TLBI_S2_IPA; cmd.tlbi.vmid =3D smmu_domain->s2_cfg.vmid; - } - __arm_smmu_tlb_inv_range(&cmd, iova, size, granule, smmu_domain); + __arm_smmu_tlb_inv_range(&cmd, iova, size, granule, + smmu_domain); + } else { + struct arm_vsmmu *vsmmu, *next; + unsigned long flags; =20 - if (smmu_domain->nest_parent) { /* * When the S2 domain changes all the nested S1 ASIDs have to be * flushed too. */ cmd.opcode =3D CMDQ_OP_TLBI_NH_ALL; arm_smmu_cmdq_issue_cmd_with_sync(smmu_domain->smmu, &cmd); + + cmd.opcode =3D CMDQ_OP_TLBI_S2_IPA; + spin_lock_irqsave(&smmu_domain->vsmmus.lock, flags); + list_for_each_entry_safe(vsmmu, next, &smmu_domain->vsmmus.list, + vsmmus_elm) { + cmd.tlbi.vmid =3D vsmmu->vmid; + __arm_smmu_tlb_inv_range(&cmd, iova, size, granule, + smmu_domain); + } + spin_unlock_irqrestore(&smmu_domain->vsmmus.lock, flags); } =20 /* @@ -2477,7 +2503,7 @@ static void arm_smmu_domain_free_paging(struct iommu_= domain *domain) mutex_lock(&arm_smmu_asid_lock); xa_erase(&arm_smmu_asid_xa, smmu_domain->cd.asid); mutex_unlock(&arm_smmu_asid_lock); - } else { + } else if (!smmu_domain->nest_parent) { struct arm_smmu_s2_cfg *cfg =3D &smmu_domain->s2_cfg; if (cfg->vmid) ida_free(&smmu->vmid_map, cfg->vmid); @@ -2506,7 +2532,10 @@ static int arm_smmu_domain_finalise_s2(struct arm_sm= mu_device *smmu, struct arm_smmu_domain *smmu_domain) { int vmid; - struct arm_smmu_s2_cfg *cfg =3D &smmu_domain->s2_cfg; + + /* nest_parent stores vmid in vSMMU instead of a shared S2 domain */ + if (smmu_domain->nest_parent) + return 0; =20 /* Reserve VMID 0 for stage-2 bypass STEs */ vmid =3D ida_alloc_range(&smmu->vmid_map, 1, (1 << smmu->vmid_bits) - 1, @@ -2514,7 +2543,7 @@ static int arm_smmu_domain_finalise_s2(struct arm_smm= u_device *smmu, if (vmid < 0) return vmid; =20 - cfg->vmid =3D (u16)vmid; + smmu_domain->s2_cfg.vmid =3D (u16)vmid; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Mar 2025 05:05:25.6163 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4d8dd552-195d-413f-a3a5-08dd5ba35741 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A9.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7654 Content-Type: text/plain; charset="utf-8" Now, vmids are stored in vSMMU objects. So all vSMMUs assigned to the same VM can share a s2_parent domain. This means a vIOMMU allocation per device behind one SMMU can be given with a s2_parent domain that's allocated per another device behind another SMMU, i.e. s2_parent->smmu !=3D master->smmu. Remove the validation line to allow this use case. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c b/drivers/= iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c index 2c5a9d0abed5..9bfa5fa5bafa 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c @@ -378,9 +378,6 @@ struct iommufd_viommu *arm_vsmmu_alloc(struct device *d= ev, if (!(smmu->features & ARM_SMMU_FEAT_NESTING)) return ERR_PTR(-EOPNOTSUPP); =20 - if (s2_parent->smmu !=3D master->smmu) - return ERR_PTR(-EINVAL); - /* * FORCE_SYNC is not set with FEAT_NESTING. Some study of the exact HW * defect is needed to determine if arm_vsmmu_cache_invalidate() needs --=20 2.43.0