From nobody Mon Dec 15 21:41:51 2025 Received: from mail-ot1-f43.google.com (mail-ot1-f43.google.com [209.85.210.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 929FC216618; Wed, 26 Feb 2025 02:15:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740536113; cv=none; b=eS7e4/1rjigsVvOYB8qz91WNhsb50PAK5DX/L1/ecRVnOEC+8eC1wU8EwHE/aOx52FNWDHchVLCN/hKDOJvK/chWziYHh85Te9zyOPDJdx8bPJuKtcp2O+lDdiVnrcVLcFmgQAG33oCB6+3WdQyhbselHpueIK33WxQQTls6guo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740536113; c=relaxed/simple; bh=sWYsoy1AYKSOnbYc4dyUR2ZMRQ0Z/zhcfav6WfQD1cQ=; h=From:To:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Z3z4qGO+uPV3rnlGOgQ3+n1xZGFm/snVsIUyciIoC+VyrMIQUYxrBunfS+zZhP0Vj+whDH+90Ie8Jy3oms/4hsZgvTtCCDLWVq7y2qDNDuk4iKAtciVJ5w/haOMipapnoMgKokwqk3rcJbO31ldRjt9XCcOHKnXmQwkENMYusmA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=M54MdYpp; arc=none smtp.client-ip=209.85.210.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="M54MdYpp" Received: by mail-ot1-f43.google.com with SMTP id 46e09a7af769-71e10e6a1ceso1665928a34.0; Tue, 25 Feb 2025 18:15:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1740536109; x=1741140909; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=TSwGNN0SIOhmXf5jKWogh0gmEP1MjDJlYVwfiVZRhNw=; b=M54MdYppat5W58eXf6byUgZpabsJEo1uC+eAvDkos99BxbEavu3YfbbpFeR9QtnJrR aAFz0feGHpHeeytfbgmncceyl+sZZkI1goEO11jqCOGGBhjz1cjtH1gKpkyXETX3zdsd YZ36lEyFKPxw+qlMmfbHriXyxxE1K3l9q62evJw8BGlz+CHhe4Sa2oVRmw1R058iuzWO EZidOOcIXHw1/3ucTmbI44x3ENZVGNd5THT3toaYKDs4e1LcmCia1PfeYWmQztMXDGZx 3hy1DdEiTUffEC6rOFplK4Ji4NR2S61WZlRktrq8ZCds2KZgi+YHroq9ZMu5yYzZEOK9 xTQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740536109; x=1741140909; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TSwGNN0SIOhmXf5jKWogh0gmEP1MjDJlYVwfiVZRhNw=; b=w77b3bdgB/17BlMfXhitHXZlnH067sdYLJsr+9WtkFYFHn40mxEdrcac9BV7O/OfrE 5bDF2kylOF8BFW/4vHfl6wQOyC76JIh6KjanqWt/NA2OdjWrQ8ZvgLiBlLmV9MGM4jLd Tnz/URJrmfU5S0+6hJnjDzT7df3GVZ2Y+Z9s8Tsmqkn41gKBFVM/MbhHeIlQNA70iWxH pf5v5ZX5gKEqoUF0YTXtJhmkU3s0LUaFZZJm/Xv1TWnf8hMd0WwbscC6lmivYdCxbB1P xGv4S6T62k/J78XbkqQuZ21kClPd0EImnNk2geUal5L6foyQKj+OrHs8iLekCaW2+XaN XyMw== X-Forwarded-Encrypted: i=1; AJvYcCXN3YOdTAS8/bpQWTZVokGonD94/AyMnnJLrFvKJDxCq79Mv+1N0+LitKy5bHpkN1sO6HwYhz3FzhyC@vger.kernel.org, AJvYcCXUpMdqaS4nwOuwr8gEAuAwWY2tDYba3aReBKlz8otyB3N8Ni8WhdtSi4qvKuSoKO5Z20iRfhNoVqZKH/0q@vger.kernel.org X-Gm-Message-State: AOJu0Ywqn5XdQ5Ew1I8EJ0B3mp3jQuZQphGacbDZGHHxD+ZTLern4KD/ 1yZ1CwcdfNnwZk4NB0/IgGlfGswpFEPCDymGGgbTUDJk0Sn5emdL X-Gm-Gg: ASbGncs1rYSTfQjHAHuqpQaBzKhPLK3usrXozXfA69YJzkAyHaacI/ys6XdQoCE9V8z Hm8xu4BIzIZfAvYVgH3O5o1MAHfcaahAEHTnHAfCj6pklPR+80VyDPPH68kbmgdDZiHVELNU4mf TBVTdTg8Nj94Kcn5FHVwng6YCXpb6QM4Ww74slK9M2KdHSX7C136g0COpU2oKeciN7LqQKPXmak 86S2KmerHIfCFX2yjyO3njp1wiipH2Ronxy9plsZuL3WDdEEjDCNhTHcxYfX5RGVvAw6GUPVpxG ccGp4u5BtFM5TuYDOfyya1mNzjFSkWrsI6vj X-Google-Smtp-Source: AGHT+IHm1jbA3PRpFiPlRgdyJBzf/dyx+1/asA4Sg0xYUoO4ugWiSAPfuJPn+/X752gLUM1QYWGjFw== X-Received: by 2002:a05:6830:6a90:b0:727:3380:66ce with SMTP id 46e09a7af769-7274c568347mr14173878a34.25.1740536109482; Tue, 25 Feb 2025 18:15:09 -0800 (PST) Received: from localhost.localdomain ([122.8.183.87]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7289df4ec4fsm532272a34.46.2025.02.25.18.15.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Feb 2025 18:15:08 -0800 (PST) From: Chen Wang To: u.kleine-koenig@baylibre.com, aou@eecs.berkeley.edu, arnd@arndb.de, unicorn_wang@outlook.com, conor+dt@kernel.org, guoren@kernel.org, inochiama@outlook.com, krzk+dt@kernel.org, palmer@dabbelt.com, paul.walmsley@sifive.com, robh@kernel.org, tglx@linutronix.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, chao.wei@sophgo.com, xiaoguang.xing@sophgo.com, fengchun.li@sophgo.com Subject: [PATCH v5 1/3] dt-bindings: interrupt-controller: Add Sophgo SG2042 MSI Date: Wed, 26 Feb 2025 10:15:01 +0800 Message-Id: <44de02977624be334ba6328acfdbb2a375f2071f.1740535748.git.unicorn_wang@outlook.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen Wang Add binding for Sophgo SG2042 MSI controller. Reviewed-by: Rob Herring (Arm) Signed-off-by: Chen Wang --- .../sophgo,sg2042-msi.yaml | 61 +++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/= sophgo,sg2042-msi.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/sophgo,= sg2042-msi.yaml b/Documentation/devicetree/bindings/interrupt-controller/so= phgo,sg2042-msi.yaml new file mode 100644 index 000000000000..e1ffd55fa7bf --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-= msi.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/sophgo,sg2042-msi.= yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo SG2042 MSI Controller + +maintainers: + - Chen Wang + +description: + This interrupt controller is in Sophgo SG2042 for transforming interrupt= s from + PCIe MSI to PLIC interrupts. + +allOf: + - $ref: /schemas/interrupt-controller/msi-controller.yaml# + +properties: + compatible: + const: sophgo,sg2042-msi + + reg: + items: + - description: clear register + - description: msi doorbell address + + reg-names: + items: + - const: clr + - const: doorbell + + msi-controller: true + + msi-ranges: + maxItems: 1 + + "#msi-cells": + const: 0 + +required: + - compatible + - reg + - reg-names + - msi-controller + - msi-ranges + - "#msi-cells" + +unevaluatedProperties: false + +examples: + - | + #include + msi-controller@30000000 { + compatible =3D "sophgo,sg2042-msi"; + reg =3D <0x30000000 0x4>, <0x30000008 0x4>; + reg-names =3D "clr", "doorbell"; + msi-controller; + #msi-cells =3D <0>; + msi-ranges =3D <&plic 64 IRQ_TYPE_LEVEL_HIGH 32>; + }; --=20 2.34.1 From nobody Mon Dec 15 21:41:51 2025 Received: from mail-ot1-f44.google.com (mail-ot1-f44.google.com [209.85.210.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 106E0219A79; Wed, 26 Feb 2025 02:15:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740536131; cv=none; b=swY9x3RU8KZmko/ahKUrGVVCdVg77fkZ8rTg1VYC2kquFEzoQTlLKcye7iYtYpj061IiiVDQUfBLhhIN44ub7Yxb6jNmb7gsNbtPZDIHe99zm5vFhu3bAstKxJBkW5a7I0q/YQ2w1WsUjphq7i5pgKtgcuL/G36XbJdWs8thQm4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740536131; c=relaxed/simple; bh=R4NGN1mLxfJOfVOq2/PvkJAPjtmRo1siCKgn2kgU6ic=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=VaosSMoSyezN9LfPTiayJOJjEJXnQSSw5UAurrgH5ZpVWH+BhvE2nxl3TmipYENJEShOCH8pEEol1HdbySlNwigZB0qO1uv4kekky1S6fanNUTkACwTx+cY97w/Vyc3VDIuirrXDf7gMXFR/WaDRR2dk+qfONX5v/Z2zXC6F77g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=BCQdCtWT; arc=none smtp.client-ip=209.85.210.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="BCQdCtWT" Received: by mail-ot1-f44.google.com with SMTP id 46e09a7af769-7272f3477e9so1930225a34.3; Tue, 25 Feb 2025 18:15:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1740536129; x=1741140929; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IUmZvnb1tRiSqbV2BrYwnOfVYe6ZV5LXNUg2BqKjz48=; b=BCQdCtWTJpDbTZz61bC05XrwbULohTaA1gS+oaeOeM+IXY0WmXpMTE6SUgFAb/uMnO xY2EC5QhQgqr5YiXnIkaecOL0+Veh5cPfd1ONwljFYKSERp/O/A02p0be+36ULw3xibi ZXTzGpWWWJVjKeMl0prXujJBhcaVkNDj52h/EoXECtAdkvS6R+zV4gUShSAR1ic8gPLV qs78tWzq9XwBqKZwArGpmWREOtzmQZTJ1jHD+bE5KfIKjWDFFKTkmz1cZ3PeqU3jz7Ic qHiKsvrqWyVfrAC/0i3my+GNi4EoQkJhE5NV8Gkf+Otyc3E0mMEwh9zTlRlpwixYGHAK DBfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740536129; x=1741140929; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IUmZvnb1tRiSqbV2BrYwnOfVYe6ZV5LXNUg2BqKjz48=; b=cvEZ9pqqPBOfeKWssf9e0wBd3eieWZqareDymND08FTA2JQYQGD42saQu+B8V6fXgi JuQ4xXlQeZ1a/7xzHAZPL1WCpJDvkog/Y5IRGvj3JGF581uaTt2xxnS/4Cg7dhrzqbd+ ZaYUdc63AalHKQVlMmzxaJkH0DoMtCAJiVtV04lvDp1+R5KHV1HFf/8O5JjTwkmI6fZQ fo893hskGGfDWBMGTB2w+L6OCB8IdA21j+ZlfMoERyX/3/5E5vjYCafuIXsGIWoyjN8n 7hKo/McUsOJMuvZn8weiCMj0OPKKVEkaCwYb4ZM9ab7EL1k1Y0R4xGqK4LHEhD67CLB8 mODw== X-Forwarded-Encrypted: i=1; AJvYcCWQ76QixuPTIic2vghEAQr8atY2O1ydQZGu0Lg00mPlE768Mnsb2dJRSclr8TQNVkk+9iMJkGMhJnUegOQr@vger.kernel.org, AJvYcCWbHg9kEbzPbEFr7OQHNXMlKTp0gy7g41Hjb642sxl+5vLqhSflYUgLChR0CUk5quwYjYsEXDxOOer+@vger.kernel.org X-Gm-Message-State: AOJu0YwFKGJblIr86pEML38Z6c01QsDZQ5QjXZ4VqiKjYwmewSHR059I y6xJZ51JlCWjbF0UYTA0r8id1xowPEAGjkZC0OhZ38jMnyH8VhP6 X-Gm-Gg: ASbGncuh527RxZJ6T5WqpPPFWSfgYEYHYKp4d2GnAJOgj0pao2W6CiKa+AaMFxVp5fb vtuFzjJefVFRlEDFKROHtETRnyVbjYgkR2GiMLIGC6Lvt/Cba11uDf6HIW858O3GTud/IFy+QoL +KzCVSMpdYCTYKyjk8eG+I0EPRTUF4xZk+UFFvklMPLpl29OWYnqOCyYoOL9yS4OWTHts0WHam0 TQXFj/mfXYc+/yybbt+qymbpeXglunwzfBgCPFB69GD0HRiqG2OnZWSIltAm59zBt/nXL4tJV1v 39ux+Hrk39PY4CB2bOqETA8VeZRL1FDRDzzB X-Google-Smtp-Source: AGHT+IE+BOCYfr9QO3EfVjOBLzsZKPPxYogSm+kRRkFUHbnyJZsjyeWiwA417ugAXi8l2mp7JA54JQ== X-Received: by 2002:a05:6830:3883:b0:727:4144:2bbb with SMTP id 46e09a7af769-7289d0facc8mr4486493a34.8.1740536128887; Tue, 25 Feb 2025 18:15:28 -0800 (PST) Received: from localhost.localdomain ([122.8.183.87]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-2c11128723csm661569fac.18.2025.02.25.18.15.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Feb 2025 18:15:27 -0800 (PST) From: Chen Wang To: u.kleine-koenig@baylibre.com, aou@eecs.berkeley.edu, arnd@arndb.de, unicorn_wang@outlook.com, conor+dt@kernel.org, guoren@kernel.org, inochiama@outlook.com, krzk+dt@kernel.org, palmer@dabbelt.com, paul.walmsley@sifive.com, robh@kernel.org, tglx@linutronix.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, chao.wei@sophgo.com, xiaoguang.xing@sophgo.com, fengchun.li@sophgo.com Cc: Inochi Amaoto Subject: [PATCH v5 2/3] irqchip: Add the Sophgo SG2042 MSI interrupt controller Date: Wed, 26 Feb 2025 10:15:19 +0800 Message-Id: <3104216ca90a5f532bafb676c1c5b1efb19e94d1.1740535748.git.unicorn_wang@outlook.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen Wang Add driver for Sophgo SG2042 MSI interrupt controller. Reviewed-by: Inochi Amaoto Signed-off-by: Chen Wang --- drivers/irqchip/Kconfig | 12 ++ drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-sg2042-msi.c | 258 +++++++++++++++++++++++++++++++ 3 files changed, 271 insertions(+) create mode 100644 drivers/irqchip/irq-sg2042-msi.c diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index c11b9965c4ad..078ed8b55b34 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -752,6 +752,18 @@ config MCHP_EIC help Support for Microchip External Interrupt Controller. =20 +config SOPHGO_SG2042_MSI + bool "Sophgo SG2042 MSI Controller" + depends on ARCH_SOPHGO || COMPILE_TEST + depends on PCI + select IRQ_DOMAIN_HIERARCHY + select IRQ_MSI_LIB + select PCI_MSI + help + Support for the Sophgo SG2042 MSI Controller. + This on-chip interrupt controller enables MSI sources to be + routed to the primary PLIC controller on SoC. + config SUNPLUS_SP7021_INTC bool "Sunplus SP7021 interrupt controller" if COMPILE_TEST default SOC_SP7021 diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 25e9ad29b8c4..dd60e597491d 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -128,4 +128,5 @@ obj-$(CONFIG_WPCM450_AIC) +=3D irq-wpcm450-aic.o obj-$(CONFIG_IRQ_IDT3243X) +=3D irq-idt3243x.o obj-$(CONFIG_APPLE_AIC) +=3D irq-apple-aic.o obj-$(CONFIG_MCHP_EIC) +=3D irq-mchp-eic.o +obj-$(CONFIG_SOPHGO_SG2042_MSI) +=3D irq-sg2042-msi.o obj-$(CONFIG_SUNPLUS_SP7021_INTC) +=3D irq-sp7021-intc.o diff --git a/drivers/irqchip/irq-sg2042-msi.c b/drivers/irqchip/irq-sg2042-= msi.c new file mode 100644 index 000000000000..9c0a5f2777a4 --- /dev/null +++ b/drivers/irqchip/irq-sg2042-msi.c @@ -0,0 +1,258 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SG2042 MSI Controller + * + * Copyright (C) 2024 Sophgo Technology Inc. + * Copyright (C) 2024 Chen Wang + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "irq-msi-lib.h" + +#define SG2042_MAX_MSI_VECTOR 32 + +struct sg2042_msi_chipdata { + void __iomem *reg_clr; // clear reg, see TRM, 10.1.33, GP_INTR0_CLR + + phys_addr_t doorbell_addr; // see TRM, 10.1.32, GP_INTR0_SET + + u32 irq_first; // The vector number that MSIs starts + u32 num_irqs; // The number of vectors for MSIs + + DECLARE_BITMAP(msi_map, SG2042_MAX_MSI_VECTOR); + struct mutex msi_map_lock; // lock for msi_map +}; + +static int sg2042_msi_allocate_hwirq(struct sg2042_msi_chipdata *data, int= num_req) +{ + int first; + + guard(mutex)(&data->msi_map_lock); + first =3D bitmap_find_free_region(data->msi_map, data->num_irqs, + get_count_order(num_req)); + return first >=3D 0 ? first : -ENOSPC; +} + +static void sg2042_msi_free_hwirq(struct sg2042_msi_chipdata *data, + int hwirq, int num_req) +{ + guard(mutex)(&data->msi_map_lock); + bitmap_release_region(data->msi_map, hwirq, get_count_order(num_req)); +} + +static void sg2042_msi_irq_ack(struct irq_data *d) +{ + struct sg2042_msi_chipdata *data =3D irq_data_get_irq_chip_data(d); + int bit_off =3D d->hwirq; + + writel(1 << bit_off, data->reg_clr); + + irq_chip_ack_parent(d); +} + +static void sg2042_msi_irq_compose_msi_msg(struct irq_data *d, + struct msi_msg *msg) +{ + struct sg2042_msi_chipdata *data =3D irq_data_get_irq_chip_data(d); + + msg->address_hi =3D upper_32_bits(data->doorbell_addr); + msg->address_lo =3D lower_32_bits(data->doorbell_addr); + msg->data =3D 1 << d->hwirq; +} + +static const struct irq_chip sg2042_msi_middle_irq_chip =3D { + .name =3D "SG2042 MSI", + .irq_ack =3D sg2042_msi_irq_ack, + .irq_mask =3D irq_chip_mask_parent, + .irq_unmask =3D irq_chip_unmask_parent, +#ifdef CONFIG_SMP + .irq_set_affinity =3D irq_chip_set_affinity_parent, +#endif + .irq_compose_msi_msg =3D sg2042_msi_irq_compose_msi_msg, +}; + +static int sg2042_msi_parent_domain_alloc(struct irq_domain *domain, + unsigned int virq, int hwirq) +{ + struct sg2042_msi_chipdata *data =3D domain->host_data; + struct irq_fwspec fwspec; + struct irq_data *d; + int ret; + + fwspec.fwnode =3D domain->parent->fwnode; + fwspec.param_count =3D 2; + fwspec.param[0] =3D data->irq_first + hwirq; + fwspec.param[1] =3D IRQ_TYPE_EDGE_RISING; + + ret =3D irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec); + if (ret) + return ret; + + d =3D irq_domain_get_irq_data(domain->parent, virq); + return d->chip->irq_set_type(d, IRQ_TYPE_EDGE_RISING); +} + +static int sg2042_msi_middle_domain_alloc(struct irq_domain *domain, + unsigned int virq, + unsigned int nr_irqs, void *args) +{ + struct sg2042_msi_chipdata *data =3D domain->host_data; + int hwirq, err, i; + + hwirq =3D sg2042_msi_allocate_hwirq(data, nr_irqs); + if (hwirq < 0) + return hwirq; + + for (i =3D 0; i < nr_irqs; i++) { + err =3D sg2042_msi_parent_domain_alloc(domain, virq + i, hwirq + i); + if (err) + goto err_hwirq; + + irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i, + &sg2042_msi_middle_irq_chip, data); + } + + return 0; + +err_hwirq: + sg2042_msi_free_hwirq(data, hwirq, nr_irqs); + irq_domain_free_irqs_parent(domain, virq, i); + + return err; +} + +static void sg2042_msi_middle_domain_free(struct irq_domain *domain, + unsigned int virq, + unsigned int nr_irqs) +{ + struct irq_data *d =3D irq_domain_get_irq_data(domain, virq); + struct sg2042_msi_chipdata *data =3D irq_data_get_irq_chip_data(d); + + irq_domain_free_irqs_parent(domain, virq, nr_irqs); + sg2042_msi_free_hwirq(data, d->hwirq, nr_irqs); +} + +static const struct irq_domain_ops sg2042_msi_middle_domain_ops =3D { + .alloc =3D sg2042_msi_middle_domain_alloc, + .free =3D sg2042_msi_middle_domain_free, + .select =3D msi_lib_irq_domain_select, +}; + +#define SG2042_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \ + MSI_FLAG_USE_DEF_CHIP_OPS) + +#define SG2042_MSI_FLAGS_SUPPORTED MSI_GENERIC_FLAGS_MASK + +static const struct msi_parent_ops sg2042_msi_parent_ops =3D { + .required_flags =3D SG2042_MSI_FLAGS_REQUIRED, + .supported_flags =3D SG2042_MSI_FLAGS_SUPPORTED, + .bus_select_mask =3D MATCH_PCI_MSI, + .bus_select_token =3D DOMAIN_BUS_NEXUS, + .prefix =3D "SG2042-", + .init_dev_msi_info =3D msi_lib_init_dev_msi_info, +}; + +static int sg2042_msi_init_domains(struct sg2042_msi_chipdata *data, + struct irq_domain *plic_domain, + struct device *dev) +{ + struct fwnode_handle *fwnode =3D dev_fwnode(dev); + struct irq_domain *middle_domain; + + middle_domain =3D irq_domain_create_hierarchy(plic_domain, 0, data->num_i= rqs, + fwnode, + &sg2042_msi_middle_domain_ops, + data); + if (!middle_domain) { + pr_err("Failed to create the MSI middle domain\n"); + return -ENOMEM; + } + + irq_domain_update_bus_token(middle_domain, DOMAIN_BUS_NEXUS); + + middle_domain->flags |=3D IRQ_DOMAIN_FLAG_MSI_PARENT; + middle_domain->msi_parent_ops =3D &sg2042_msi_parent_ops; + + return 0; +} + +static int sg2042_msi_probe(struct platform_device *pdev) +{ + struct fwnode_reference_args args =3D {}; + struct sg2042_msi_chipdata *data; + struct device *dev =3D &pdev->dev; + struct irq_domain *plic_domain; + struct resource *res; + int ret; + + data =3D devm_kzalloc(dev, sizeof(struct sg2042_msi_chipdata), GFP_KERNEL= ); + if (!data) + return -ENOMEM; + + data->reg_clr =3D devm_platform_ioremap_resource_byname(pdev, "clr"); + if (IS_ERR(data->reg_clr)) { + dev_err(dev, "Failed to map clear register\n"); + return PTR_ERR(data->reg_clr); + } + + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "doorbell"); + if (!res) { + dev_err(dev, "Failed get resource from set\n"); + return -EINVAL; + } + data->doorbell_addr =3D res->start; + + ret =3D fwnode_property_get_reference_args(dev_fwnode(dev), "msi-ranges", + "#interrupt-cells", 0, 0, &args); + if (ret) { + dev_err(dev, "Unable to parse MSI vec base\n"); + return ret; + } + fwnode_handle_put(args.fwnode); + + ret =3D fwnode_property_get_reference_args(dev_fwnode(dev), "msi-ranges", + NULL, args.nargs + 1, + 0, &args); + if (ret) { + dev_err(dev, "Unable to parse MSI vec number\n"); + return ret; + } + + plic_domain =3D irq_find_matching_fwnode(args.fwnode, DOMAIN_BUS_ANY); + fwnode_handle_put(args.fwnode); + if (!plic_domain) { + pr_err("Failed to find the PLIC domain\n"); + return -ENXIO; + } + + data->irq_first =3D (u32)args.args[0]; + data->num_irqs =3D (u32)args.args[args.nargs - 1]; + + mutex_init(&data->msi_map_lock); + + return sg2042_msi_init_domains(data, plic_domain, dev); +} + +static const struct of_device_id sg2042_msi_of_match[] =3D { + { .compatible =3D "sophgo,sg2042-msi" }, + {} +}; + +static struct platform_driver sg2042_msi_driver =3D { + .driver =3D { + .name =3D "sg2042-msi", + .of_match_table =3D sg2042_msi_of_match, + }, + .probe =3D sg2042_msi_probe, +}; +builtin_platform_driver(sg2042_msi_driver); --=20 2.34.1 From nobody Mon Dec 15 21:41:51 2025 Received: from mail-oo1-f46.google.com (mail-oo1-f46.google.com [209.85.161.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B2DD4218AAF; Wed, 26 Feb 2025 02:15:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.161.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740536150; cv=none; b=bFq8NRYezN7Fru4xJOWDZ21hiKMT3+zFoB4FNX7Gwh21sYT8SdZgo9m6Lcl8RCs0EF+tn/+vRpKBMekTdSA/O62x84qBLh1TUoSTGUAJSR3YcK3N6G3dtK0wGdBDrB+e3XhtU4JnprUT4XrVYlW2pQvB96YJxituMSY09S9+4Zo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740536150; c=relaxed/simple; bh=/r37Uw7CkBPVUgHSzBMXiIbx/pc5+LM6KKEWlFa1wcA=; h=From:To:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Y6BfMLMHisFtkv4O7gstYkSX3CWv4Pge7c0Y28N2/7v2LP71ec0IUjg3lY82ZSUDmph6uJghEwocQOSLFBAIas5RpbGbwPgpd6CyTa9b86J+ilprGCz9Oz3SQv4W5LNyEtChVoihhgEDxGhCs2hN3aXjmSLMHp7Twjuz2fXL2ns= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=FTcx8rXo; arc=none smtp.client-ip=209.85.161.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="FTcx8rXo" Received: by mail-oo1-f46.google.com with SMTP id 006d021491bc7-5fcd509468eso3043066eaf.2; Tue, 25 Feb 2025 18:15:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1740536148; x=1741140948; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=KHGavz6z1XAW16p7P/7q7QGD5LUvtpVWO2vRaC4bQT4=; b=FTcx8rXojkKKHryAKa9gqn6vI0aHYfe3zVRbY3N32RDp1njWR2OZfptEB/aBPZQV2t LtrJagGRZB3fPiEesW2ZODsmebAaW/U2nA3svbQ0TkdOvG3TOVs+dl+HxnR1LHlHCafo Rc8OgEfpDsn7GcVHhnnYjiysb8oczdWXBewVh5pIXK6eUvxOE1NeC4hWEwVryKlUoWfz ItPOJ4iziaFmnOGl2tEiePuo0CHcnmzVUN3+YvlC6t13m5O9PKFkCnm/uCo6M9oP/dzA IzIJ2TdmdDSLWOWRR1GV62dkgWtyCWOlrf2nXx6k7xHLrVVeRxYPBeKgAAtzlOrJ7Qhl aOOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740536148; x=1741140948; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KHGavz6z1XAW16p7P/7q7QGD5LUvtpVWO2vRaC4bQT4=; b=NZh86OgFL/FDnC2vKm4p6yQFg3wNRhtFVX9XfDBupGrCN1L0aDU70RBAjifVhyG/yJ ClvgQes3blsu75dtSrYXuinfhFjzO3c5TJSF2Vb1U7K1eooVW7zA63T1ZFgkeybxjERi PAvhu+Ytx3dKjXtfwrhUFGEw5QmIo4g2LYDQhG1gVz/dvOwFZ3mN5QcWoqoGjMmvORCo Zan80DcBKWGNVvcw+hmcZ+D74LHAkFFM1QspaEA3k3r5/zy0nVzwPsU5aNbCEt4ah/AB DWNpi3mL3ADtqs7LDVoZcPNgeEKda8G7NEnh3Ls/vB2+il//lFH7+YO4Si1Y1SfUDE+n MqWA== X-Forwarded-Encrypted: i=1; AJvYcCUDannqm0qg/2QjlT4GDRQug6e8N0cXFbdX8bD7v/XOsJEij6E47BZc5QXY4f280QRJLJB+Jmtds5Iq@vger.kernel.org, AJvYcCWYrv0sbU0H7qGVSB+g1q6vy9CBufJbNfuhIlVwH5lCFjKS1qaMqLYhrbQX3vE9xGE6YAuDmGknlWE91k0j@vger.kernel.org X-Gm-Message-State: AOJu0YxOi0ZoWrwhVrMgKpj0aiv06j3L402doFji1sRaeyPpmiNorWva bEJkG1Vj9a4lJJ8sUZMBiiA7pwpYTA20lu2esAkgsEmXsb1/76dJ X-Gm-Gg: ASbGncthcEVYG+Y1muEl1sju+a0TYVSfM6vlbSZ5rGvcRLguN1JtX2UKYRKzDe56lID oxEkXZY1QhGk/0G1jchgUPQVJXJdcSp/t8KZ2F7IibbVeP6rPb3JFX+Fi7p11jmcBuheY0WSQPI vEx4LDDr0Iaq1DPQsGI6EjOCjUFXKQeX4cXt3z7EgC0QZzZtLR79y7JPHRt4E+qpRBEljHuk1Ky 9/M8PbO/UPXMhikVlPLnQskkoz5JbBIgOeMqnjxtE80fmVgnoTUxRN/atckteQ/BoSOAB197bn8 hYq8iw76qAmDIc9mKdO4/7ktO4A0cFiCRjPQ X-Google-Smtp-Source: AGHT+IGLYc8zwdtfmLaEsvbdDcjtt1ROPr3PJkWV4l0eqsn4p4lu2DNAkyhTkGMvz1D3nRQo2igqow== X-Received: by 2002:a05:6820:1b92:b0:5fd:f8d:3870 with SMTP id 006d021491bc7-5fd1a77973bmr11258701eaf.4.1740536147732; Tue, 25 Feb 2025 18:15:47 -0800 (PST) Received: from localhost.localdomain ([122.8.183.87]) by smtp.gmail.com with ESMTPSA id 006d021491bc7-5fe9410df0dsm523864eaf.3.2025.02.25.18.15.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Feb 2025 18:15:46 -0800 (PST) From: Chen Wang To: u.kleine-koenig@baylibre.com, aou@eecs.berkeley.edu, arnd@arndb.de, unicorn_wang@outlook.com, conor+dt@kernel.org, guoren@kernel.org, inochiama@outlook.com, krzk+dt@kernel.org, palmer@dabbelt.com, paul.walmsley@sifive.com, robh@kernel.org, tglx@linutronix.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, chao.wei@sophgo.com, xiaoguang.xing@sophgo.com, fengchun.li@sophgo.com Subject: [PATCH v5 3/3] riscv: sophgo: dts: add msi controller for SG2042 Date: Wed, 26 Feb 2025 10:15:37 +0800 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen Wang Add msi-controller node to dts for SG2042. Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/sg2042.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/s= ophgo/sg2042.dtsi index e62ac51ac55a..fef2a0e0f7a3 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi @@ -173,6 +173,16 @@ pllclk: clock-controller@70300100c0 { #clock-cells =3D <1>; }; =20 + msi: msi-controller@7030010304 { + compatible =3D "sophgo,sg2042-msi"; + reg =3D <0x70 0x30010304 0x0 0x4>, + <0x70 0x30010300 0x0 0x4>; + reg-names =3D "clr", "doorbell"; + msi-controller; + #msi-cells =3D <0>; + msi-ranges =3D <&intc 64 IRQ_TYPE_LEVEL_HIGH 32>; + }; + rpgate: clock-controller@7030010368 { compatible =3D "sophgo,sg2042-rpgate"; reg =3D <0x70 0x30010368 0x0 0x98>; --=20 2.34.1