From nobody Sun Dec 14 21:36:25 2025 Received: from mail-oo1-f52.google.com (mail-oo1-f52.google.com [209.85.161.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D1BF025A647; Wed, 5 Feb 2025 07:00:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.161.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738738860; cv=none; b=tyHzGkzpveDGHqkTC6yOwnXZJHrYZJbJfcCegSnsznn6BHzwbFinKgIqOgOvH/u+NTuFw1irDxqB+BhV0gsKEYsUJI1gfnq7xtqnGiNAKUE2+B/roSoLwAMNwazH0ZPmMsb34CGbdaQnIlJb/Tc3MpMMVhnrqsubuHASE211dAo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738738860; c=relaxed/simple; bh=7WjeZz4TO/UuK5w9UlH8RWVjZ0WWQQw3zyv05GSNR6k=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=pMqy3THPJpKfgHCzbqEbQufcK8/xqpzfp8Coyus3ng1mmQ/ScgXsRTY//IAkv2gW3tcy+JStGqUfzJcQbBmppuI6vAV1tlp4HiqDXpnbCs9JfDIDx3nMkG6Gm3qB3tUCKDsMEpNumGlDatZC15+sxUdIlhUdgqPNvvvQJG3uIRY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=XZKMrglM; arc=none smtp.client-ip=209.85.161.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="XZKMrglM" Received: by mail-oo1-f52.google.com with SMTP id 006d021491bc7-5fa2685c5c0so2512470eaf.3; Tue, 04 Feb 2025 23:00:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1738738857; x=1739343657; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FVz8hdajmeQn+sLRJ3LfLAYPYY16G3b35wwKMJMKlco=; b=XZKMrglMrIcKZ92aUDgXEA6zo1F/ZElB5gE6U0vs0qnpxHzSakFhCIMbX+gV9QLme9 bjf7qCwTVVTkf4agtiFKTbuD/p6UArod18B+cxehLAUtBBvMyRXbJKsKV26oZs6Tlprw PKo6zcNStD+rD75lp/1mUT9vw5boKFMVQPwWV1NVsCEzEhyZylu3EySfC4rrbtITNL9g TvyiNwoTlvj9lM/IcQe/g05E5zQGRNgYAx40iWWw33wMJmuwk3W53n+Fondmo3mPYRJP eftDO5MJIV4RsL89AnZC9TePPRX3zeJ+uKYv+6Uo/N0Y9SaCgIojjLXHU/RuOvCLZIok 6LaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738738857; x=1739343657; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FVz8hdajmeQn+sLRJ3LfLAYPYY16G3b35wwKMJMKlco=; b=LlfCleuqyc88cjfF1CKfkUjPw3DfGdlNc/+es1w/6vUL8N+YHwaZzi1Wnvh0zEEY9/ XIkhvpnuSGoVmzoTQyHhvcImKe2fYSsIqlS43kgSCG4QyPFUeWPpZ0udnqUBJvuEb7I8 F5V7K+j3l+y9dnUdwbQydW9UPBMoZverRVfLsQiFP+f+5k6Ep07M3lGrb6gSusRaRFKM Dtm/DyUrWbxKPJjYFnSSNoF9crIsq631vH+VKr+y9fPwLyPBYLUvu4lwAKybrkp/M+UW K/chsdq7JFSErBUdys1xGt8r1azedGo2R69b+Nt68BxUKb7iyAczHKfT7Hq9yGiX9lII rLeA== X-Forwarded-Encrypted: i=1; AJvYcCVYJN2hgW6mFFGf+I1PW7QI/6aVlE0dyfewMFqz2EG8d6n1FGlt1Bg4JzZ281rc9czUSLtQpwHt2i3hM6O+@vger.kernel.org, AJvYcCVwGiX1cjp3v80q2KCljj2wNif3u0IPQ1XJwTtrpCZJAsWdTfjF8Um9xGZFf0b3jXMiFIZ3XKQ2vNy3@vger.kernel.org, AJvYcCW1Kt0J2KnaVOi5DxwkX7xN6ZsIXcwdfuLNkFRreIKrUp0eT9r9iFRj8mWkMB89QcuDkCGCgNilWBE+@vger.kernel.org X-Gm-Message-State: AOJu0YwuyH8WovshNAaQUjPhPHZxG/NQe+frbzqjqqMcYbSM1zMKXEwh QKGZcOnQVsd7gCo0WHBXwMvMcNIUV57Cv+DIXPYZTEsnGJ8O7nT6fozSb4Shwl4= X-Gm-Gg: ASbGncs8xo69JHguIS2+K+js3E67v8wWmA/NzWCHlSjUZMsaZ28aQxTyNRvfYHugNYl WYfTNsmiI7FYKYLdSI16pmu7FgE/oXv260Q0w1YMS/2ibpVxQLhOwnwoMng0EhXeWdybgRBxq2U jDGLqC4CrVG0lh1VNBKMLY5kgKOC/+expCclCCPVFrPLFk3W7Y4JFuk5CE6a2mh5bI68iKXBxbF msJd+f7ib6S998sUndua3Ma260dqrrGwplxeg2iedpym/Bu+7VG8WfEIvJ2x7glC9mvYJ6acUWN xiU0XLmtnK4z7Hzqu8evmtCdmg== X-Google-Smtp-Source: AGHT+IFsHiem+4btGG99h0d6BwMEp2mzewnRG8Nfz6GBsGDnx1ZgDacLy7O2/NhwKDNQhLK60akjwA== X-Received: by 2002:a05:6820:1992:b0:5fa:73ed:de8 with SMTP id 006d021491bc7-5fc479ce7demr1475362eaf.6.1738738856694; Tue, 04 Feb 2025 23:00:56 -0800 (PST) Received: from localhost.localdomain ([122.8.183.87]) by smtp.gmail.com with ESMTPSA id 006d021491bc7-5fc104e29b7sm3598247eaf.17.2025.02.04.23.00.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Feb 2025 23:00:55 -0800 (PST) From: Chen Wang To: ukleinek@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, unicorn_wang@outlook.com, inochiama@outlook.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, linux-riscv@lists.infradead.org, chao.wei@sophgo.com, haijiao.liu@sophgo.com, xiaoguang.xing@sophgo.com, chunzhi.lin@sophgo.com Cc: Krzysztof Kozlowski Subject: [PATCH v7 1/3] dt-bindings: pwm: sophgo: add PWM controller for SG2042 Date: Wed, 5 Feb 2025 15:00:47 +0800 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen Wang Sophgo SG2042 contains a PWM controller, which has 4 channels and can generate PWM waveforms output. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Chen Wang --- .../bindings/pwm/sophgo,sg2042-pwm.yaml | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/sophgo,sg2042-pwm= .yaml diff --git a/Documentation/devicetree/bindings/pwm/sophgo,sg2042-pwm.yaml b= /Documentation/devicetree/bindings/pwm/sophgo,sg2042-pwm.yaml new file mode 100644 index 000000000000..bbb6326d47d7 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/sophgo,sg2042-pwm.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/sophgo,sg2042-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo SG2042 PWM controller + +maintainers: + - Chen Wang + +description: + This controller contains 4 channels which can generate PWM waveforms. + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + const: sophgo,sg2042-pwm + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: apb + + resets: + maxItems: 1 + + "#pwm-cells": + const: 3 + +required: + - compatible + - reg + - clocks + - clock-names + - resets + +unevaluatedProperties: false + +examples: + - | + #include + + pwm@7f006000 { + compatible =3D "sophgo,sg2042-pwm"; + reg =3D <0x7f006000 0x1000>; + #pwm-cells =3D <3>; + clocks =3D <&clock 67>; + clock-names =3D "apb"; + resets =3D <&rstgen RST_PWM>; + }; --=20 2.34.1 From nobody Sun Dec 14 21:36:25 2025 Received: from mail-oi1-f178.google.com (mail-oi1-f178.google.com [209.85.167.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7AEEC227BA5; Wed, 5 Feb 2025 07:01:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.178 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738738887; cv=none; b=o9w43qu135f5IO6Xev4vUg36NUa7Sj7YrdJiWH3/CAoT5cSolEaeW69DbZkxC3YQ1/NGu1ZkNp1ZslhOdmPBFfOMUXlNXfnwlC1XatfZXY+jWAjNiqGQSUrEq2MGXHRsTlwhVYWd3LlfQaUwuZyCJZkhJVcAUA7BUIbzD2MX2iA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738738887; c=relaxed/simple; bh=GGqBP1IfPzVWXKWgqaKxM1VSdxfOao9IJ4hydXG6cKE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=tPNo8GeUR48lAlU+278UVDNt7wyRpGpxY/M/Rjsda025Zsv0fZs20bVJcWTpzdmpu+xiIcp2SvmChIi3wX0YSeMptfnXWf1jbfGOc/S5xzX9N/IRg1LwcXVQHHKJF12j7H4a0amhnPFdHnXSnMj7lmKEBHt2TlF2dB1gwL86Pf8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=UkEvmT/Y; arc=none smtp.client-ip=209.85.167.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="UkEvmT/Y" Received: by mail-oi1-f178.google.com with SMTP id 5614622812f47-3eb98b3b63dso1694868b6e.1; Tue, 04 Feb 2025 23:01:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1738738884; x=1739343684; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SwBabY2Dif2qU+HHNZ8N8GiCs/b5gFtvrv0DgcVk+kU=; b=UkEvmT/Y+CPT7BGATUkUFNUjGBp/xi22s1hhrx4fJK3wgpItu6CZlpUQ52hrUQnOBG NfPnqg4nIdpdis8d2N5wtGSBkEvRb4XrBsU6sHzVWid85woWMYfOHsNv/GUOabFi7gpl oCFxfLnW6jAtuVFHdr6b0OutTdHG2sjrnx6o968AaywOkv1wWPTj7uPOL4t7lJxIzA9n Rn0Bw4aVtVaBobcZCicFz1VtLlM6f9aEQ2KN//AZ9pkbfvDPHVT6iVcg7V2kA7ougMWN TallryA/xOWZF/NdRrwYV0cOnsA9nDr8QL5uJPze5Pkv640qz73LO5xmZa0YB4qemFKt CHrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738738884; x=1739343684; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SwBabY2Dif2qU+HHNZ8N8GiCs/b5gFtvrv0DgcVk+kU=; b=uDyJuxqxCqPZAfLSHTGC542eUzrFUWlLPdCR3+r0w4S7cGp1t1Gl/qIdMOkYawgjzb STb13Yrqpwol8mB9eIopRJiQwOGvBNbLXLfx/gvu/byXZSzuhPUpKKZ9gp2cjK381SWn 8jYmU0F1K3rqeHZjCXzXbQ5g4C0No55NRCBDu1Nc8AqHIDwY2qq0H1HNVXTYir9yQ1DE iPkg8fRGkfb2KwbxP5bh0cX3wYLTZIVllu2Rori2YArlcuL0SrSehwK036gaUKt9kws9 7H80P7m2OmtGiCazKQJyAY6oqp/5FPwir3G/rkY4iEL3lmIlmGau2sYiSj3ZcmwK3Hii a6mA== X-Forwarded-Encrypted: i=1; AJvYcCVt11k1EmeWnMu5rwbHrYAjWcVVL5XrWIaWEAvyvEl/H2kFFuHPq1Zq8Vc9Qwr4tQEFq6vSAOObhWJ4jQl1@vger.kernel.org, AJvYcCX//SxXF2Nlq393Esa0fYkDbzCPD3vB6h4O9+gZKRLWNvokSvUrhgNGXbihGzmA78dungHtBI9ZYwYA@vger.kernel.org, AJvYcCXnyukYCIg4+/oGAU+ys4bh2c0eVrSALHeqtYDjrVrPlWKnASENZlCg6V7yz97WH/k7kSbi1N+TEB07@vger.kernel.org X-Gm-Message-State: AOJu0Yy8uy22fCi7HEtHgl0PmRKmvh7TpKtW2ySrYdVx5o9mfVefmgX9 aZ87cp/ud8OkWveDpC7KNJV4Bxgcq6gcIx2LIg9c/WZ620sbChWR X-Gm-Gg: ASbGncu37fvRJ8OfVrZfYaRVMQE2Im0MUZhuP6F5iUV8KT1aftGird/Ilh1DCgG9P9G 9zhk53X2luW97qBGserPvgWAZHMfDkWQZhUfcG4K/RFMfe6rZUV9p7/ZssSayfFFuq9PT0VPeJC 09jd5ltemUpCCvzD5tA2V10V8kA9OjNt/NrJxyn4HvXhjYTtE5dH28bQIBQahrLseqSEFNyJFSh wsr0Dc/6lES3vrovwj75DbimfBoh3Z8cI9iLciuV/lhv2euuCiR24z/vuVWIoWEdjaIaQfFtPVH dYIMb7i3lJNS1WdXtxH9Cy2QfQ== X-Google-Smtp-Source: AGHT+IFOKv7NvEPObj+ABlljhF58GKcG3uAwtk/8J4W/YhXzERpVBCwZPgxh2nYVVtiLK17dNr+teQ== X-Received: by 2002:a05:6808:3204:b0:3e6:5761:af3 with SMTP id 5614622812f47-3f37c10d334mr1158689b6e.9.1738738882752; Tue, 04 Feb 2025 23:01:22 -0800 (PST) Received: from localhost.localdomain ([122.8.183.87]) by smtp.gmail.com with ESMTPSA id 5614622812f47-3f33367f6c6sm3441203b6e.42.2025.02.04.23.01.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Feb 2025 23:01:21 -0800 (PST) From: Chen Wang To: ukleinek@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, unicorn_wang@outlook.com, inochiama@outlook.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, linux-riscv@lists.infradead.org, chao.wei@sophgo.com, haijiao.liu@sophgo.com, xiaoguang.xing@sophgo.com, chunzhi.lin@sophgo.com Cc: Sean Young Subject: [PATCH v7 2/3] pwm: sophgo: add driver for Sophgo SG2042 PWM Date: Wed, 5 Feb 2025 15:01:13 +0800 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen Wang Add a PWM driver for PWM controller in Sophgo SG2042 SoC. Signed-off-by: Sean Young Signed-off-by: Chen Wang --- drivers/pwm/Kconfig | 10 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-sophgo-sg2042.c | 196 ++++++++++++++++++++++++++++++++ 3 files changed, 207 insertions(+) create mode 100644 drivers/pwm/pwm-sophgo-sg2042.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 0915c1e7df16..ec85f3895936 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -584,6 +584,16 @@ config PWM_SL28CPLD To compile this driver as a module, choose M here: the module will be called pwm-sl28cpld. =20 +config PWM_SOPHGO_SG2042 + tristate "Sophgo SG2042 PWM support" + depends on ARCH_SOPHGO || COMPILE_TEST + help + PWM driver for the PWM controller on Sophgo SG2042 SoC. The PWM + controller supports outputing 4 channels of PWM waveforms. + + To compile this driver as a module, choose M here: the module + will be called pwm_sophgo_sg2042. + config PWM_SPEAR tristate "STMicroelectronics SPEAr PWM support" depends on PLAT_SPEAR || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 9081e0c0e9e0..539e0def3f82 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -53,6 +53,7 @@ obj-$(CONFIG_PWM_RZ_MTU3) +=3D pwm-rz-mtu3.o obj-$(CONFIG_PWM_SAMSUNG) +=3D pwm-samsung.o obj-$(CONFIG_PWM_SIFIVE) +=3D pwm-sifive.o obj-$(CONFIG_PWM_SL28CPLD) +=3D pwm-sl28cpld.o +obj-$(CONFIG_PWM_SOPHGO_SG2042) +=3D pwm-sophgo-sg2042.o obj-$(CONFIG_PWM_SPEAR) +=3D pwm-spear.o obj-$(CONFIG_PWM_SPRD) +=3D pwm-sprd.o obj-$(CONFIG_PWM_STI) +=3D pwm-sti.o diff --git a/drivers/pwm/pwm-sophgo-sg2042.c b/drivers/pwm/pwm-sophgo-sg204= 2.c new file mode 100644 index 000000000000..ce8cf8af3402 --- /dev/null +++ b/drivers/pwm/pwm-sophgo-sg2042.c @@ -0,0 +1,196 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Sophgo SG2042 PWM Controller Driver + * + * Copyright (C) 2024 Sophgo Technology Inc. + * Copyright (C) 2024 Chen Wang + * + * Limitations: + * - After reset, the output of the PWM channel is always high. + * The value of HLPERIOD/PERIOD is 0. + * - When HLPERIOD or PERIOD is reconfigured, PWM will start to + * output waveforms with the new configuration after completing + * the running period. + * - When PERIOD and HLPERIOD is set to 0, the PWM wave output will + * be stopped and the output is pulled to high. + * See the datasheet [1] for more details. + * [1]:https://github.com/sophgo/sophgo-doc/tree/main/SG2042/TRM + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Offset RegisterName + * 0x0000 HLPERIOD0 + * 0x0004 PERIOD0 + * 0x0008 HLPERIOD1 + * 0x000C PERIOD1 + * 0x0010 HLPERIOD2 + * 0x0014 PERIOD2 + * 0x0018 HLPERIOD3 + * 0x001C PERIOD3 + * Four groups and every group is composed of HLPERIOD & PERIOD + */ +#define SG2042_PWM_HLPERIOD(chan) ((chan) * 8 + 0) +#define SG2042_PWM_PERIOD(chan) ((chan) * 8 + 4) + +#define SG2042_PWM_CHANNELNUM 4 + +/** + * struct sg2042_pwm_ddata - private driver data + * @base: base address of mapped PWM registers + * @clk_rate_hz: rate of base clock in HZ + */ +struct sg2042_pwm_ddata { + void __iomem *base; + unsigned long clk_rate_hz; +}; + +/* + * period_ticks: PERIOD + * hlperiod_ticks: HLPERIOD + */ +static void pwm_sg2042_config(struct sg2042_pwm_ddata *ddata, unsigned int= chan, + u32 period_ticks, u32 hlperiod_ticks) +{ + void __iomem *base =3D ddata->base; + + writel(period_ticks, base + SG2042_PWM_PERIOD(chan)); + writel(hlperiod_ticks, base + SG2042_PWM_HLPERIOD(chan)); +} + +static int pwm_sg2042_apply(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) +{ + struct sg2042_pwm_ddata *ddata =3D pwmchip_get_drvdata(chip); + u32 hlperiod_ticks; + u32 period_ticks; + + if (state->polarity =3D=3D PWM_POLARITY_INVERSED) + return -EINVAL; + + if (!state->enabled) { + pwm_sg2042_config(ddata, pwm->hwpwm, 0, 0); + return 0; + } + + /* + * Duration of High level (duty_cycle) =3D HLPERIOD x Period_of_input_clk + * Duration of One Cycle (period) =3D PERIOD x Period_of_input_clk + */ + period_ticks =3D min(mul_u64_u64_div_u64(ddata->clk_rate_hz, state->perio= d, NSEC_PER_SEC), U32_MAX); + hlperiod_ticks =3D min(mul_u64_u64_div_u64(ddata->clk_rate_hz, state->dut= y_cycle, NSEC_PER_SEC), U32_MAX); + + dev_dbg(pwmchip_parent(chip), "chan[%u]: PERIOD=3D%u, HLPERIOD=3D%u\n", + pwm->hwpwm, period_ticks, hlperiod_ticks); + + pwm_sg2042_config(ddata, pwm->hwpwm, period_ticks, hlperiod_ticks); + + return 0; +} + +static int pwm_sg2042_get_state(struct pwm_chip *chip, struct pwm_device *= pwm, + struct pwm_state *state) +{ + struct sg2042_pwm_ddata *ddata =3D pwmchip_get_drvdata(chip); + unsigned int chan =3D pwm->hwpwm; + u32 hlperiod_ticks; + u32 period_ticks; + + period_ticks =3D readl(ddata->base + SG2042_PWM_PERIOD(chan)); + hlperiod_ticks =3D readl(ddata->base + SG2042_PWM_HLPERIOD(chan)); + + if (!period_ticks) { + state->enabled =3D false; + return 0; + } + + if (hlperiod_ticks > period_ticks) + hlperiod_ticks =3D period_ticks; + + state->enabled =3D true; + state->period =3D DIV_ROUND_UP_ULL((u64)period_ticks * NSEC_PER_SEC, ddat= a->clk_rate_hz); + state->duty_cycle =3D DIV_ROUND_UP_ULL((u64)hlperiod_ticks * NSEC_PER_SEC= , ddata->clk_rate_hz); + state->polarity =3D PWM_POLARITY_NORMAL; + + return 0; +} + +static const struct pwm_ops pwm_sg2042_ops =3D { + .apply =3D pwm_sg2042_apply, + .get_state =3D pwm_sg2042_get_state, +}; + +static const struct of_device_id sg2042_pwm_ids[] =3D { + { .compatible =3D "sophgo,sg2042-pwm" }, + { } +}; +MODULE_DEVICE_TABLE(of, sg2042_pwm_ids); + +static int pwm_sg2042_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct sg2042_pwm_ddata *ddata; + struct reset_control *rst; + struct pwm_chip *chip; + struct clk *clk; + int ret; + + chip =3D devm_pwmchip_alloc(dev, SG2042_PWM_CHANNELNUM, sizeof(*ddata)); + if (IS_ERR(chip)) + return PTR_ERR(chip); + ddata =3D pwmchip_get_drvdata(chip); + + ddata->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(ddata->base)) + return PTR_ERR(ddata->base); + + clk =3D devm_clk_get_enabled(dev, "apb"); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), "Failed to get base clk\n"); + + ret =3D devm_clk_rate_exclusive_get(dev, clk); + if (ret) + return dev_err_probe(dev, ret, "Failed to get exclusive rate\n"); + + ddata->clk_rate_hz =3D clk_get_rate(clk); + /* period =3D PERIOD * NSEC_PER_SEC / clk_rate_hz */ + if (!ddata->clk_rate_hz || ddata->clk_rate_hz > NSEC_PER_SEC) + return dev_err_probe(dev, -EINVAL, + "Invalid clock rate: %lu\n", ddata->clk_rate_hz); + + rst =3D devm_reset_control_get_optional_shared_deasserted(dev, NULL); + if (IS_ERR(rst)) + return dev_err_probe(dev, PTR_ERR(rst), "Failed to get reset\n"); + + chip->ops =3D &pwm_sg2042_ops; + chip->atomic =3D true; + + ret =3D devm_pwmchip_add(dev, chip); + if (ret < 0) { + reset_control_assert(rst); + return dev_err_probe(dev, ret, "Failed to register PWM chip\n"); + } + + return 0; +} + +static struct platform_driver pwm_sg2042_driver =3D { + .driver =3D { + .name =3D "sg2042-pwm", + .of_match_table =3D sg2042_pwm_ids, + }, + .probe =3D pwm_sg2042_probe, +}; +module_platform_driver(pwm_sg2042_driver); + +MODULE_AUTHOR("Chen Wang"); +MODULE_DESCRIPTION("Sophgo SG2042 PWM driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1 From nobody Sun Dec 14 21:36:26 2025 Received: from mail-oi1-f175.google.com (mail-oi1-f175.google.com [209.85.167.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5514721773E; Wed, 5 Feb 2025 07:01:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.175 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738738905; cv=none; b=bw4V4Ysgg4C1EiAAODA30wgPeuZiVcTJCJJ7HMA0JnwI1b1Vh5MOJ8p/7DdcsH9DCWHVwt9x7MZ/j8MibtDSW6ui+0fM8fuXsA6VUpQwU1hYAspvs8LKVnevhQRAifQIDTLRlnudUadnOqytcec7cdbb0gcCScayV6DgR1mgaPU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738738905; c=relaxed/simple; bh=yxW7QMaAB0nuL2yZCjk4W1zhHXFyqyCXjnl61MZJ/hI=; h=From:To:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=tPtaqyhNqXeygQzXUUn7uO4cSv+8en7PVVXxNziuCG9mNfYs3LxQ7Cmron7jd0Qw5xuszutk1w2a8AEyPSrXdJv0iS657YwRNdTW24EkqHvjilJb6lQprVrtCa8m6CklEcHYLOcS/jZkR/OfArD++WO7Qro+TTev+QcACoSGDNI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=jeAsW1p1; arc=none smtp.client-ip=209.85.167.175 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="jeAsW1p1" Received: by mail-oi1-f175.google.com with SMTP id 5614622812f47-3eb9a0a2089so4126212b6e.1; Tue, 04 Feb 2025 23:01:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1738738903; x=1739343703; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=VetlIju5pkNjg/WmtiNabYY/80QVE5zZqTlQOK48sTE=; b=jeAsW1p1tUzTybDtLaLpfcBriUdjO2oP24xtG1DmSLiXPJu9Ss8CuUHjPXNwYnF1kx LwRCvOHg076FoL5ipfzYYOSeNayn12snRLKuy895LxtD8eYOe7KP+GHPhd63SMyYQTMU cVb2LLUhSFYU/gOx2yYri75xmEFqegChkEgrh1DyAqF33mjCiAzKACncS/AdJdTuSJ0D DkzcAqfrjxN7dbwz6ydeXetWj5qSnVfrhYEuckVHZQn8KxgQn+Bjp8EkSt76kRHepDmS XOfVKZOR723Ym9M+3GknmNdNA1lZNt98V5GZdmSy7su7VBSykC5J1dtcCGgEWJ8YEhKa cH4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738738903; x=1739343703; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VetlIju5pkNjg/WmtiNabYY/80QVE5zZqTlQOK48sTE=; b=wjb1RA1joZNPKqzZ/4WKDXU6jjYxWht4N6rCwPShPxFybnKRHwf4KZtv+LpSWmZt60 su5x0GKJiI6NGDa0+ub9KyqDyeAMXZHxqWYvgwAL1TxNneSTTQ1TdJ0hWgYd+0ol3BbP jw+sHJ+hLJxqn2kTWD7NdsBLfTpLtbS1N2iH6TivGSsDG007T4Otw5Sbm7Ut+1aUqfrv TEAvHrxsyjpHQbVE0phK70h7Mz/nbqc23p/1Md8r66S4JF61GCqkaFM5CuDW2IU58pnx jBP9PC3+45lbImZrRg8o11diIRFz9ya+r/xPENUyfCbqGckqKtvqLySasbOZZbdBfwmg PmYg== X-Forwarded-Encrypted: i=1; AJvYcCWXb8zJeuyBb/DqMGOCWmE05uSUlBAhx0vh0VvPH1JS+Q3ScLrjn+JKtW8AVaBIzj19JIIN/3PMEFvv@vger.kernel.org, AJvYcCX2YdqQ0vcTkmpdquh2iHDXI6FU28w3GVOczGeySmJFU29MZTuEtEvkZrMA966dDS7b/e26HSEYvBA5O+F0@vger.kernel.org, AJvYcCXHcMQM/wU4i9/F4DzN6S7czu7AoqIsM7m2K+CJQumQyvQkkGZ4AmDK4oIJKAZSMB3n0HYSKFC7LxoU@vger.kernel.org X-Gm-Message-State: AOJu0YzWJnH9/Lj/NIrSeb15ikwkuyKgNrueGSgog/qIG2+ErIbk2qew tWKVr2C6SXTvQGDVXtuPhJ6+cUMxuhAeX0GofVNsjdGD8B64QKVt X-Gm-Gg: ASbGncvrHFyC+IHCGDmsgCi+Q+spNaVHwPun+n3PwWqKNlSTl5HOXdY24XZgk0yAHFR QJKGUqgZgitY1TcUTCdPuQZcvMXlFU4D5iBKlH8yM8hW8NQMYvEJEI5Qd8tWb+P8FdHSLHFRlFo 2IoPfDS0RcUyRfdy8NCR1xgjNDs+c88pDzxcga2DByX3tg/jMS2m1Lnm5hO5Gs4nsJ2WOigEm8s yHgNZGh0Jbr3iVOGyHR/K0KElBSyrUlo14YPU7o+MfV/xbsAGZXKn15tGInk+bHSnyGoxU+iBLr jE8w48sl3TZLAys83gGJbYtlvQ== X-Google-Smtp-Source: AGHT+IHsN/LcSCw5m80/mGufauWzvwto1G8RpGC+M5RvbFWxlmw2NwUKjbpX1R3EQj/I7XUX3H7gJw== X-Received: by 2002:a05:6808:3c8a:b0:3eb:638d:5e28 with SMTP id 5614622812f47-3f37c0e5a0bmr1104846b6e.4.1738738903247; Tue, 04 Feb 2025 23:01:43 -0800 (PST) Received: from localhost.localdomain ([122.8.183.87]) by smtp.gmail.com with ESMTPSA id 5614622812f47-3f33367f6c6sm3441313b6e.42.2025.02.04.23.01.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Feb 2025 23:01:42 -0800 (PST) From: Chen Wang To: ukleinek@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, unicorn_wang@outlook.com, inochiama@outlook.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, linux-riscv@lists.infradead.org, chao.wei@sophgo.com, haijiao.liu@sophgo.com, xiaoguang.xing@sophgo.com, chunzhi.lin@sophgo.com Subject: [PATCH v7 3/3] riscv: sophgo: dts: add pwm controller for SG2042 SoC Date: Wed, 5 Feb 2025 15:01:34 +0800 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen Wang SG2042 has one PWM controller, which has 4 pwm output channels. Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/sg2042.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/s= ophgo/sg2042.dtsi index e62ac51ac55a..4449c762d663 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi @@ -165,6 +165,15 @@ port2a: gpio-controller@0 { }; }; =20 + pwm: pwm@703000c000 { + compatible =3D "sophgo,sg2042-pwm"; + reg =3D <0x70 0x3000c000 0x0 0x20>; + #pwm-cells =3D <3>; + clocks =3D <&clkgen GATE_CLK_APB_PWM>; + clock-names =3D "apb"; + resets =3D <&rstgen RST_PWM>; + }; + pllclk: clock-controller@70300100c0 { compatible =3D "sophgo,sg2042-pll"; reg =3D <0x70 0x300100c0 0x0 0x40>; --=20 2.34.1