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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Feb 2025 16:39:21.4462 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5b7b9b51-c951-417c-8216-08dd44714fad X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF00036F3C.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7361 Content-Type: text/plain; charset="utf-8" Firmware contants do not fit the purpose of bindings because they are not independent IDs for abstractions. They are more or less just contants which better to wire via header with DT which is using it. That's why copy header to platform folder (align macro) and use it locally. Signed-off-by: Michal Simek Acked-by: Conor Dooley --- arch/arm64/boot/dts/xilinx/xlnx-zynqmp-clk.h | 126 ++++++++++++++++++ .../arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 2 +- 2 files changed, 127 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/xilinx/xlnx-zynqmp-clk.h diff --git a/arch/arm64/boot/dts/xilinx/xlnx-zynqmp-clk.h b/arch/arm64/boot= /dts/xilinx/xlnx-zynqmp-clk.h new file mode 100644 index 000000000000..0aa17f2a2818 --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/xlnx-zynqmp-clk.h @@ -0,0 +1,126 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Xilinx Zynq MPSoC Firmware layer + * + * Copyright (C) 2014-2018 Xilinx, Inc. + * + */ + +#ifndef _XLNX_ZYNQMP_CLK_H +#define _XLNX_ZYNQMP_CLK_H + +#define IOPLL 0 +#define RPLL 1 +#define APLL 2 +#define DPLL 3 +#define VPLL 4 +#define IOPLL_TO_FPD 5 +#define RPLL_TO_FPD 6 +#define APLL_TO_LPD 7 +#define DPLL_TO_LPD 8 +#define VPLL_TO_LPD 9 +#define ACPU 10 +#define ACPU_HALF 11 +#define DBF_FPD 12 +#define DBF_LPD 13 +#define DBG_TRACE 14 +#define DBG_TSTMP 15 +#define DP_VIDEO_REF 16 +#define DP_AUDIO_REF 17 +#define DP_STC_REF 18 +#define GDMA_REF 19 +#define DPDMA_REF 20 +#define DDR_REF 21 +#define SATA_REF 22 +#define PCIE_REF 23 +#define GPU_REF 24 +#define GPU_PP0_REF 25 +#define GPU_PP1_REF 26 +#define TOPSW_MAIN 27 +#define TOPSW_LSBUS 28 +#define GTGREF0_REF 29 +#define LPD_SWITCH 30 +#define LPD_LSBUS 31 +#define USB0_BUS_REF 32 +#define USB1_BUS_REF 33 +#define USB3_DUAL_REF 34 +#define USB0 35 +#define USB1 36 +#define CPU_R5 37 +#define CPU_R5_CORE 38 +#define CSU_SPB 39 +#define CSU_PLL 40 +#define PCAP 41 +#define IOU_SWITCH 42 +#define GEM_TSU_REF 43 +#define GEM_TSU 44 +#define GEM0_TX 45 +#define GEM1_TX 46 +#define GEM2_TX 47 +#define GEM3_TX 48 +#define GEM0_RX 49 +#define GEM1_RX 50 +#define GEM2_RX 51 +#define GEM3_RX 52 +#define QSPI_REF 53 +#define SDIO0_REF 54 +#define SDIO1_REF 55 +#define UART0_REF 56 +#define UART1_REF 57 +#define SPI0_REF 58 +#define SPI1_REF 59 +#define NAND_REF 60 +#define I2C0_REF 61 +#define I2C1_REF 62 +#define CAN0_REF 63 +#define CAN1_REF 64 +#define CAN0 65 +#define CAN1 66 +#define DLL_REF 67 +#define ADMA_REF 68 +#define TIMESTAMP_REF 69 +#define AMS_REF 70 +#define PL0_REF 71 +#define PL1_REF 72 +#define PL2_REF 73 +#define PL3_REF 74 +#define WDT 75 +#define IOPLL_INT 76 +#define IOPLL_PRE_SRC 77 +#define IOPLL_HALF 78 +#define IOPLL_INT_MUX 79 +#define IOPLL_POST_SRC 80 +#define RPLL_INT 81 +#define RPLL_PRE_SRC 82 +#define RPLL_HALF 83 +#define RPLL_INT_MUX 84 +#define RPLL_POST_SRC 85 +#define APLL_INT 86 +#define APLL_PRE_SRC 87 +#define APLL_HALF 88 +#define APLL_INT_MUX 89 +#define APLL_POST_SRC 90 +#define DPLL_INT 91 +#define DPLL_PRE_SRC 92 +#define DPLL_HALF 93 +#define DPLL_INT_MUX 94 +#define DPLL_POST_SRC 95 +#define VPLL_INT 96 +#define VPLL_PRE_SRC 97 +#define VPLL_HALF 98 +#define VPLL_INT_MUX 99 +#define VPLL_POST_SRC 100 +#define CAN0_MIO 101 +#define CAN1_MIO 102 +#define ACPU_FULL 103 +#define GEM0_REF 104 +#define GEM1_REF 105 +#define GEM2_REF 106 +#define GEM3_REF 107 +#define GEM0_REF_UNG 108 +#define GEM1_REF_UNG 109 +#define GEM2_REF_UNG 110 +#define GEM3_REF_UNG 111 +#define LPD_WDT 112 + +#endif /* _XLNX_ZYNQMP_CLK_H */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/bo= ot/dts/xilinx/zynqmp-clk-ccf.dtsi index 385fed8a852a..52e122fc7c9e 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi @@ -8,7 +8,7 @@ * Michal Simek */ =20 -#include +#include "xlnx-zynqmp-clk.h" / { pss_ref_clk: pss-ref-clk { bootph-all; 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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SN1PEPF00036F41.mail.protection.outlook.com (10.167.248.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8398.14 via Frontend Transport; Mon, 3 Feb 2025 16:39:25 +0000 Received: from localhost (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 3 Feb 2025 10:39:23 -0600 From: Michal Simek To: , , , CC: Anand Ashok Dumbre , Andrew Lunn , Claudiu Beznea , "Conor Dooley" , Damien Le Moal , "David S. Miller" , Eric Dumazet , "Greg Kroah-Hartman" , Harini Katakam , Jakub Kicinski , Jonathan Cameron , Krzysztof Kozlowski , "Lars-Peter Clausen" , Mark Brown , Michael Tretter , Michael Turquette , Mubin Sayyed , Nicolas Ferre , Niklas Cassel , Paolo Abeni , Rob Herring , Shyam Pandey , Stephen Boyd , Vinod Koul , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "open list:DMA GENERIC OFFLOAD ENGINE SUBSYSTEM" , "moderated list:ARM/ZYNQ ARCHITECTURE" , "open list:COMMON CLK FRAMEWORK" , "open list:LIBATA SUBSYSTEM (Serial and Parallel ATA drivers)" , "open list:XILINX AMS DRIVER" , "open list:SPI SUBSYSTEM" , "open list:USB SUBSYSTEM" , "open list:NETWORKING DRIVERS" Subject: [PATCH 2/2] dt-bindings: xilinx: Deprecate header with firmware constants Date: Mon, 3 Feb 2025 17:39:11 +0100 Message-ID: <2a6f0229522327939e6893565e540b75f854a37b.1738600745.git.michal.simek@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Feb 2025 16:39:25.6570 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3be94396-7605-45b6-08ec-08dd44715230 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF00036F41.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7334 Content-Type: text/plain; charset="utf-8" Firmware contants do not fit the purpose of bindings because they are not independent IDs for abstractions. They are more or less just contants which better to wire via header with DT which is using it. That's why add deprecated message to dt binding header and also update existing dt bindings not to use macros from the header and replace them by it's value. Actually value is not relevant because it is only example. The similar changes have been done by commit 9d9292576810 ("dt-bindings: pinctrl: samsung: deprecate header with register constants"). Signed-off-by: Michal Simek Acked-by: Conor Dooley Acked-by: Jonathan Cameron Acked-by: Vinod Koul --- Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml | 4 +--- .../bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml | 3 +-- .../devicetree/bindings/iio/adc/xlnx,zynqmp-ams.yaml | 3 +-- Documentation/devicetree/bindings/net/cdns,macb.yaml | 7 +++---- Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml | 3 +-- Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml | 3 +-- include/dt-bindings/clock/xlnx-zynqmp-clk.h | 7 +++++++ 7 files changed, 15 insertions(+), 15 deletions(-) diff --git a/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml b/Do= cumentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml index 9952e0ef7767..6ad78429dc74 100644 --- a/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml +++ b/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml @@ -163,11 +163,9 @@ additionalProperties: false =20 examples: - | - #include #include #include #include - #include #include =20 sata: ahci@fd0c0000 { @@ -175,7 +173,7 @@ examples: reg =3D <0xfd0c0000 0x200>; interrupt-parent =3D <&gic>; interrupts =3D <0 133 IRQ_TYPE_LEVEL_HIGH>; - clocks =3D <&zynqmp_clk SATA_REF>; + clocks =3D <&zynqmp_clk 22>; ceva,p0-cominit-params =3D /bits/ 8 <0x0F 0x25 0x18 0x29>; ceva,p0-comwake-params =3D /bits/ 8 <0x04 0x0B 0x08 0x0F>; ceva,p0-burst-params =3D /bits/ 8 <0x0A 0x08 0x4A 0x06>; diff --git a/Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dma-1= .0.yaml b/Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.= yaml index ac3198953b8e..b5399c65a731 100644 --- a/Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml +++ b/Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml @@ -75,7 +75,6 @@ additionalProperties: false =20 examples: - | - #include =20 fpd_dma_chan1: dma-controller@fd500000 { compatible =3D "xlnx,zynqmp-dma-1.0"; @@ -84,7 +83,7 @@ examples: interrupts =3D <0 117 0x4>; #dma-cells =3D <1>; clock-names =3D "clk_main", "clk_apb"; - clocks =3D <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; + clocks =3D <&zynqmp_clk 19>, <&zynqmp_clk 31>; xlnx,bus-width =3D <128>; dma-coherent; }; diff --git a/Documentation/devicetree/bindings/iio/adc/xlnx,zynqmp-ams.yaml= b/Documentation/devicetree/bindings/iio/adc/xlnx,zynqmp-ams.yaml index 8cbad7e792b6..a403392fb263 100644 --- a/Documentation/devicetree/bindings/iio/adc/xlnx,zynqmp-ams.yaml +++ b/Documentation/devicetree/bindings/iio/adc/xlnx,zynqmp-ams.yaml @@ -193,7 +193,6 @@ additionalProperties: false =20 examples: - | - #include =20 bus { #address-cells =3D <2>; @@ -204,7 +203,7 @@ examples: interrupt-parent =3D <&gic>; interrupts =3D <0 56 4>; reg =3D <0x0 0xffa50000 0x0 0x800>; - clocks =3D <&zynqmp_clk AMS_REF>; + clocks =3D <&zynqmp_clk 70>; #address-cells =3D <1>; #size-cells =3D <1>; #io-channel-cells =3D <1>; diff --git a/Documentation/devicetree/bindings/net/cdns,macb.yaml b/Documen= tation/devicetree/bindings/net/cdns,macb.yaml index 3c30dd23cd4e..8d69846b2e09 100644 --- a/Documentation/devicetree/bindings/net/cdns,macb.yaml +++ b/Documentation/devicetree/bindings/net/cdns,macb.yaml @@ -197,7 +197,6 @@ examples: }; =20 - | - #include #include #include #include @@ -210,9 +209,9 @@ examples: interrupt-parent =3D <&gic>; interrupts =3D <0 59 4>, <0 59 4>; reg =3D <0x0 0xff0c0000 0x0 0x1000>; - clocks =3D <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_= REF>, - <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>, - <&zynqmp_clk GEM_TSU>; + clocks =3D <&zynqmp_clk 31>, <&zynqmp_clk 105>, + <&zynqmp_clk 51>, <&zynqmp_clk 50>, + <&zynqmp_clk 44>; clock-names =3D "pclk", "hclk", "tx_clk", "rx_clk", "t= su_clk"; #address-cells =3D <1>; #size-cells =3D <0>; diff --git a/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml b/D= ocumentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml index 04d4d3b4916d..02cf1314367b 100644 --- a/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml +++ b/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml @@ -65,14 +65,13 @@ allOf: =20 examples: - | - #include soc { #address-cells =3D <2>; #size-cells =3D <2>; =20 qspi: spi@ff0f0000 { compatible =3D "xlnx,zynqmp-qspi-1.0"; - clocks =3D <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>; + clocks =3D <&zynqmp_clk 53>, <&zynqmp_clk 82>; clock-names =3D "ref_clk", "pclk"; interrupts =3D <0 15 4>; interrupt-parent =3D <&gic>; diff --git a/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml b/Docum= entation/devicetree/bindings/usb/dwc3-xilinx.yaml index 00f87a558c7d..b5843f4d17d8 100644 --- a/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml +++ b/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml @@ -101,7 +101,6 @@ examples: #include #include #include - #include #include #include axi { @@ -113,7 +112,7 @@ examples: #size-cells =3D <0x2>; compatible =3D "xlnx,zynqmp-dwc3"; reg =3D <0x0 0xff9d0000 0x0 0x100>; - clocks =3D <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_= REF>; + clocks =3D <&zynqmp_clk 32>, <&zynqmp_clk 34>; clock-names =3D "bus_clk", "ref_clk"; power-domains =3D <&zynqmp_firmware PD_USB_0>; resets =3D <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>, diff --git a/include/dt-bindings/clock/xlnx-zynqmp-clk.h b/include/dt-bindi= ngs/clock/xlnx-zynqmp-clk.h index cdc4c0b9a374..f0f7ddd3dcbd 100644 --- a/include/dt-bindings/clock/xlnx-zynqmp-clk.h +++ b/include/dt-bindings/clock/xlnx-zynqmp-clk.h @@ -9,6 +9,13 @@ #ifndef _DT_BINDINGS_CLK_ZYNQMP_H #define _DT_BINDINGS_CLK_ZYNQMP_H =20 +/* + * These bindings are deprecated, because they do not match the actual + * concept of bindings but rather contain pure firmware values. + * Instead include the header in the DTS source directory. + */ +#warning "These bindings are deprecated. Instead use the header in the DTS= source directory." + #define IOPLL 0 #define RPLL 1 #define APLL 2 --=20 2.43.0