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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jan 2025 21:20:53.6468 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fde89e3f-5c43-4222-c8e9-08dd4173fa8f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397AE.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6318 Content-Type: text/plain; charset="utf-8" Smart Data Cache Injection (SDCI) is a mechanism that enables direct insertion of data from I/O devices into the L3 cache. By directly caching data from I/O devices rather than first storing the I/O data in DRAM, SDCI reduces demands on DRAM bandwidth and reduces latency to the processor consuming the I/O data. The SDCIAE (SDCI Allocation Enforcement) PQE feature allows system software to control the portion of the L3 cache used for SDCI. When enabled, SDCIAE forces all SDCI lines to be placed into the L3 cache partitions identified by the highest-supported L3_MASK_n register, where n is the maximum supported CLOSID. Add CPUID feature bit that can be used to configure SDCIAE. The feature details are documented in APM listed below [1]. [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming Publication # 24593 Revision 3.41 section 19.4.7 L3 Smart Data Cache Injection Allocation Enforcement (SDCIAE) Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537 Signed-off-by: Babu Moger --- v3: No changes. v2: Added dependancy on X86_FEATURE_CAT_L3 Removed the "" in CPU feature definition. Minor text changes. --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/cpuid-deps.c | 1 + arch/x86/kernel/cpu/scattered.c | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index 508c0dad116b..a738617b1910 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -483,6 +483,7 @@ #define X86_FEATURE_AMD_FAST_CPPC (21*32 + 5) /* Fast CPPC */ #define X86_FEATURE_AMD_HETEROGENEOUS_CORES (21*32 + 6) /* Heterogeneous C= ore Topology */ #define X86_FEATURE_AMD_WORKLOAD_CLASS (21*32 + 7) /* Workload Classificat= ion */ +#define X86_FEATURE_SDCIAE (21*32 + 8) /* L3 Smart Data Cache Injection A= llocation Enforcement */ =20 /* * BUG word(s) diff --git a/arch/x86/kernel/cpu/cpuid-deps.c b/arch/x86/kernel/cpu/cpuid-d= eps.c index 8bd84114c2d9..8185521ce854 100644 --- a/arch/x86/kernel/cpu/cpuid-deps.c +++ b/arch/x86/kernel/cpu/cpuid-deps.c @@ -70,6 +70,7 @@ static const struct cpuid_dep cpuid_deps[] =3D { { X86_FEATURE_CQM_MBM_LOCAL, X86_FEATURE_CQM_LLC }, { X86_FEATURE_BMEC, X86_FEATURE_CQM_MBM_TOTAL }, { X86_FEATURE_BMEC, X86_FEATURE_CQM_MBM_LOCAL }, + { X86_FEATURE_SDCIAE, X86_FEATURE_CAT_L3 }, { X86_FEATURE_AVX512_BF16, X86_FEATURE_AVX512VL }, { X86_FEATURE_AVX512_FP16, X86_FEATURE_AVX512BW }, { X86_FEATURE_ENQCMD, X86_FEATURE_XSAVES }, diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattere= d.c index 16f3ca30626a..d18a7ce16388 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -49,6 +49,7 @@ static const struct cpuid_bit cpuid_bits[] =3D { { X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 }, { X86_FEATURE_SMBA, CPUID_EBX, 2, 0x80000020, 0 }, { X86_FEATURE_BMEC, CPUID_EBX, 3, 0x80000020, 0 }, + { X86_FEATURE_SDCIAE, CPUID_EBX, 6, 0x80000020, 0 }, { X86_FEATURE_AMD_WORKLOAD_CLASS, CPUID_EAX, 22, 0x80000021, 0 }, { X86_FEATURE_PERFMON_V2, CPUID_EAX, 0, 0x80000022, 0 }, { X86_FEATURE_AMD_LBR_V2, CPUID_EAX, 1, 0x80000022, 0 }, --=20 2.34.1 From nobody Mon Feb 9 07:19:36 2026 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2079.outbound.protection.outlook.com [40.107.243.79]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A9711F0E36; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jan 2025 21:21:01.5344 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 81d64d0e-d3b1-4519-b923-08dd4173ff45 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397B1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB8065 Content-Type: text/plain; charset="utf-8" Add the command line options to enable or disable the new resctrl feature L3 Smart Data Cache Injection Allocation Enforcement (SDCIAE). Signed-off-by: Babu Moger --- v3: No changes. v2: No changes. --- Documentation/admin-guide/kernel-parameters.txt | 2 +- arch/x86/kernel/cpu/resctrl/core.c | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentatio= n/admin-guide/kernel-parameters.txt index d0f6c055dfcc..0077c4340d10 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -5942,7 +5942,7 @@ rdt=3D [HW,X86,RDT] Turn on/off individual RDT features. List is: cmt, mbmtotal, mbmlocal, l3cat, l3cdp, l2cat, l2cdp, - mba, smba, bmec. + mba, smba, bmec, sdciae. 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jan 2025 21:21:09.6283 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: eaf5be74-1809-40c6-5e54-08dd41740416 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397B1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4125 Content-Type: text/plain; charset="utf-8" "io_alloc" feature is a mechanism that enables direct insertion of data from I/O devices into the L3 cache. By directly caching data from I/O devices rather than first storing the I/O data in DRAM, feature reduces the demands on DRAM bandwidth and reduces latency to the processor consuming the I/O data. Signed-off-by: Babu Moger --- v3: Rewrote commit log. Changed the text to bit generic than the AMD specif= ic. Renamed the rdt_get_sdciae_alloc_cfg() to rdt_set_io_alloc_capable(). Removed leftover comment from v2. v2: Changed sdciae_capable to io_alloc_capable to make it generic feature. Also moved the io_alloc_capable in struct resctrl_cache. --- arch/x86/kernel/cpu/resctrl/core.c | 7 +++++++ include/linux/resctrl.h | 3 +++ 2 files changed, 10 insertions(+) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index c2450cd52511..1ebdb2dcc009 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -306,6 +306,11 @@ static void rdt_get_cdp_config(int level) rdt_resources_all[level].r_resctrl.cdp_capable =3D true; } =20 +static void rdt_set_io_alloc_capable(struct rdt_resource *r) +{ + r->cache.io_alloc_capable =3D true; +} + static void rdt_get_cdp_l3_config(void) { rdt_get_cdp_config(RDT_RESOURCE_L3); @@ -931,6 +936,8 @@ static __init bool get_rdt_alloc_resources(void) rdt_get_cache_alloc_cfg(1, r); if (rdt_cpu_has(X86_FEATURE_CDP_L3)) rdt_get_cdp_l3_config(); + if (rdt_cpu_has(X86_FEATURE_SDCIAE)) + rdt_set_io_alloc_capable(r); ret =3D true; } if (rdt_cpu_has(X86_FEATURE_CAT_L2)) { diff --git a/include/linux/resctrl.h b/include/linux/resctrl.h index d94abba1c716..dbe6461f3fbc 100644 --- a/include/linux/resctrl.h +++ b/include/linux/resctrl.h @@ -129,6 +129,8 @@ struct rdt_mon_domain { * @arch_has_sparse_bitmasks: True if a bitmask like f00f is valid. * @arch_has_per_cpu_cfg: True if QOS_CFG register for this cache * level has CPU scope. + * @io_alloc_capable: True if portion of the L3 cache can be allocated + * for I/O traffic. */ struct resctrl_cache { unsigned int cbm_len; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jan 2025 21:21:17.6943 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 17de3caf-3984-4654-85a7-08dd417408e7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397B3.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4261 Content-Type: text/plain; charset="utf-8" "io_alloc" feature that enables direct insertion of data from I/O devices into the L3 cache. On AMD, 'io_alloc" feature is backed by L3 Smart Data Cache Injection Allocation Enforcement (SDCIAE). SDCIAE feature can be enabled by setting bit 1 in MSR L3_QOS_EXT_CFG. Apply the updated SDCIAE value across all logical processors within the QOS domain when modifying its state. Introduce architecture-specific handlers to manage the detection and enabling/disabling of 'io_alloc" feature. The SDCIAE feature details are available in APM listed below [1]. [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming Publication # 24593 Revision 3.41 section 19.4.7 L3 Smart Data Cache Injection Allocation Enforcement (SDCIAE) Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537 Signed-off-by: Babu Moger --- v3: Passed the struct rdt_resource to resctrl_arch_get_io_alloc_enabled() i= nstead of resource id. Renamed the _resctrl_io_alloc_enable() to _resctrl_sdciae_enable() as i= t is arch specific. Changed the return to void in _resctrl_sdciae_enable() instead of int. Added more context in commit log and fixed few typos. v2: Renamed the functions to simplify the code. Renamed sdciae_capable to io_alloc_capable. Changed the name of few arch functions similar to ABMC series. resctrl_arch_get_io_alloc_enabled() resctrl_arch_io_alloc_enable() --- arch/x86/include/asm/msr-index.h | 1 + arch/x86/kernel/cpu/resctrl/internal.h | 10 ++++++++ arch/x86/kernel/cpu/resctrl/rdtgroup.c | 32 ++++++++++++++++++++++++++ include/linux/resctrl.h | 9 ++++++++ 4 files changed, 52 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-in= dex.h index 9a71880eec07..fea1f3afe197 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -1197,6 +1197,7 @@ /* - AMD: */ #define MSR_IA32_MBA_BW_BASE 0xc0000200 #define MSR_IA32_SMBA_BW_BASE 0xc0000280 +#define MSR_IA32_L3_QOS_EXT_CFG 0xc00003ff #define MSR_IA32_EVT_CFG_BASE 0xc0000400 =20 /* AMD-V MSRs */ diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index 20c898f09b7e..61bc609e932b 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -56,6 +56,9 @@ /* Max event bits supported */ #define MAX_EVT_CONFIG_BITS GENMASK(6, 0) =20 +/* Setting bit 1 in L3_QOS_EXT_CFG enables the SDCIAE feature. */ +#define SDCIAE_ENABLE_BIT 1 + /** * cpumask_any_housekeeping() - Choose any CPU in @mask, preferring those = that * aren't marked nohz_full @@ -479,6 +482,7 @@ struct rdt_parse_data { * @mbm_cfg_mask: Bandwidth sources that can be tracked when Bandwidth * Monitoring Event Configuration (BMEC) is supported. * @cdp_enabled: CDP state of this resource + * @sdciae_enabled: SDCIAE feature is enabled * * Members of this structure are either private to the architecture * e.g. mbm_width, or accessed via helpers that provide abstraction. e.g. @@ -493,6 +497,7 @@ struct rdt_hw_resource { unsigned int mbm_width; unsigned int mbm_cfg_mask; bool cdp_enabled; + bool sdciae_enabled; }; =20 static inline struct rdt_hw_resource *resctrl_to_arch_res(struct rdt_resou= rce *r) @@ -539,6 +544,11 @@ int resctrl_arch_set_cdp_enabled(enum resctrl_res_leve= l l, bool enable); =20 void arch_mon_domain_online(struct rdt_resource *r, struct rdt_mon_domain = *d); =20 +static inline bool resctrl_arch_get_io_alloc_enabled(struct rdt_resource *= r) +{ + return resctrl_to_arch_res(r)->sdciae_enabled; +} + /* * To return the common struct rdt_resource, which is contained in struct * rdt_hw_resource, walk the resctrl member of struct rdt_hw_resource. diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 6419e04d8a7b..c5a0a31c3a85 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1798,6 +1798,38 @@ static ssize_t mbm_local_bytes_config_write(struct k= ernfs_open_file *of, return ret ?: nbytes; } =20 +static void resctrl_sdciae_set_one_amd(void *arg) +{ + bool *enable =3D arg; + + if (*enable) + msr_set_bit(MSR_IA32_L3_QOS_EXT_CFG, SDCIAE_ENABLE_BIT); + else + msr_clear_bit(MSR_IA32_L3_QOS_EXT_CFG, SDCIAE_ENABLE_BIT); +} + +static void _resctrl_sdciae_enable(struct rdt_resource *r, bool enable) +{ + struct rdt_ctrl_domain *d; + + /* Update L3_QOS_EXT_CFG MSR on all the CPUs in all domains*/ + list_for_each_entry(d, &r->ctrl_domains, hdr.list) + on_each_cpu_mask(&d->hdr.cpu_mask, resctrl_sdciae_set_one_amd, &enable, = 1); +} + +int resctrl_arch_io_alloc_enable(struct rdt_resource *r, bool enable) +{ + struct rdt_hw_resource *hw_res =3D resctrl_to_arch_res(r); + + if (hw_res->r_resctrl.cache.io_alloc_capable && + hw_res->sdciae_enabled !=3D enable) { + _resctrl_sdciae_enable(r, enable); + hw_res->sdciae_enabled =3D enable; + } + + return 0; +} + /* rdtgroup information files for one cache resource. */ static struct rftype res_common_files[] =3D { { diff --git a/include/linux/resctrl.h b/include/linux/resctrl.h index dbe6461f3fbc..e77c3b37bad4 100644 --- a/include/linux/resctrl.h +++ b/include/linux/resctrl.h @@ -343,6 +343,15 @@ void resctrl_arch_reset_rmid(struct rdt_resource *r, s= truct rdt_mon_domain *d, */ void resctrl_arch_reset_rmid_all(struct rdt_resource *r, struct rdt_mon_do= main *d); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jan 2025 21:21:25.6902 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: da32f153-d695-4242-3853-08dd41740da9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397B2.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB6911 Content-Type: text/plain; charset="utf-8" The io_alloc feature in resctrl is a mechanism that enables direct insertion of data from I/O devices into the L3 cache. On AMD systems, io_alloc feature is backed by SDCIAE (L3 Smart Data Cache Injection Allocation Enforcement). When enabled, SDCIAE forces all SDCI lines to be placed into the L3 cache partitions identified by the highest-supported L3_MASK_n register as reported by CPUID Fn0000_0010_EDX_x1.MAX_COS. For example, if MAX_COS=3D15, SDCI lines will be allocated into the L3 cache partitions determined by the bitmask in the L3_MASK_15 register. When CDP is enabled, io_alloc routes I/O traffic using the highest CLOSID allocated for the instruction cache. Introduce interface to enable/disable "io_alloc" feature on user input. Signed-off-by: Babu Moger --- v3: Rewrote the change to make it generic. Rewrote the documentation in resctrl.rst to be generic and added AMD feature details in the end. Added the check to verify if MAX CLOSID availability on the system. Added CDP check to make sure io_alloc is configured in CDP_CODE. Added resctrl_io_alloc_closid_free() to free the io_alloc CLOSID. Added errors in few cases when CLOSID allocation fails. Fixes splat reported when info/L3/bit_usage is accesed when io_alloc is enabled. https://lore.kernel.org/lkml/SJ1PR11MB60837B532254E7B23BC27E84FC052@SJ1= PR11MB6083.namprd11.prod.outlook.com/ v2: Renamed the feature to "io_alloc". Added generic texts for the feature in commit log and resctrl.rst doc. Added resctrl_io_alloc_init_cat() to initialize io_alloc to default values when enabled. Fixed io_alloc show functinality to display only on L3 resource. --- Documentation/arch/x86/resctrl.rst | 34 ++++++ arch/x86/kernel/cpu/resctrl/core.c | 2 + arch/x86/kernel/cpu/resctrl/rdtgroup.c | 144 +++++++++++++++++++++++++ 3 files changed, 180 insertions(+) diff --git a/Documentation/arch/x86/resctrl.rst b/Documentation/arch/x86/re= sctrl.rst index 6768fc1fad16..1b67e31d626c 100644 --- a/Documentation/arch/x86/resctrl.rst +++ b/Documentation/arch/x86/resctrl.rst @@ -135,6 +135,40 @@ related to allocation: "1": Non-contiguous 1s value in CBM is supported. =20 +"io_alloc": + The "io_alloc" feature in resctrl enables system software to + configure the portion of the L3 cache allocated for I/O traffic. + By directly caching data from I/O devices rather than first storing + the I/O data in DRAM, reduces the demands on DRAM bandwidth and + reduces latency to the processor consuming the I/O data. + + The feature routes the I/O traffic via specific CLOSID reserved + for io_alloc feature. By configuring the CBM (Capacity Bit Mask) + for the CLOSID users can control the L3 portions available for + I/O traffic. When enabled, CLOSID reserved for the io_alloc will + not be available to the resctrl group. + :: + + # cat /sys/fs/resctrl/info/L3/io_alloc + 0 + + "0": + io_alloc feature is not enabled. + "1": + io_alloc feature is enabled, allowing users to manage + the portions of the L3 cache allocated for the I/O device. + + Feature can be enabled/disabled by writing to the interface. + Example:: + + # echo 1 > /sys/fs/resctrl/info/L3/io_alloc + + On AMD systems, the io_alloc feature is supported by the L3 Smart + Data Cache Injection Allocation Enforcement (SDCIAE). The CLOSID for + io_alloc is determined by the highest CLOSID supported by the resource. + When CDP is enabled, io_alloc routes I/O traffic using the highest + CLOSID allocated for the instruction cache. + Memory bandwidth(MB) subdirectory contains the following files with respect to allocation: =20 diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index 1ebdb2dcc009..88bc95c14ea8 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -309,6 +309,8 @@ static void rdt_get_cdp_config(int level) static void rdt_set_io_alloc_capable(struct rdt_resource *r) { r->cache.io_alloc_capable =3D true; + resctrl_file_fflags_init("io_alloc", + RFTYPE_CTRL_INFO | RFTYPE_RES_CACHE); } =20 static void rdt_get_cdp_l3_config(void) diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index c5a0a31c3a85..37295dd14abe 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -62,6 +62,7 @@ static char last_cmd_status_buf[512]; =20 static int rdtgroup_setup_root(struct rdt_fs_context *ctx); static void rdtgroup_destroy_root(void); +static int rdtgroup_init_cat(struct resctrl_schema *s, u32 closid); =20 struct dentry *debugfs_resctrl; =20 @@ -180,6 +181,19 @@ void closid_free(int closid) __set_bit(closid, &closid_free_map); } =20 +static int resctrl_io_alloc_closid_alloc(u32 io_alloc_closid) +{ + if (__test_and_clear_bit(io_alloc_closid, &closid_free_map)) + return io_alloc_closid; + else + return -ENOSPC; +} + +static void resctrl_io_alloc_closid_free(u32 io_alloc_closid) +{ + closid_free(io_alloc_closid); +} + /** * closid_allocated - test if provided closid is in use * @closid: closid to be tested @@ -995,6 +1009,33 @@ static int rdt_shareable_bits_show(struct kernfs_open= _file *of, return 0; } =20 +/* + * io_alloc feature uses max CLOSID to route the IO traffic. + * Get the max CLOSID and verify if the CLOSID is available. + */ +static int resctrl_io_alloc_closid_get(struct rdt_resource *r, + struct resctrl_schema *s) +{ + int num_closids =3D resctrl_arch_get_num_closid(r); + + /* + * The number of CLOSIDs is determined based on the minimum + * supported across all resources (in closid_init). It is stored + * in s->num_closids. Also, if CDP is enabled number of CLOSIDs + * are halved. To enable io_alloc feature, the number of CLOSIDs + * must match the maximum CLOSID supported by the resource. + */ + if (resctrl_arch_get_cdp_enabled(r->rid)) + num_closids /=3D 2; + + if (s->num_closid !=3D num_closids) { + rdt_last_cmd_puts("Max CLOSID to support io_alloc is not available\n"); + return -ENOSPC; + } + + return num_closids - 1; +} + /* * rdt_bit_usage_show - Display current usage of resources * @@ -1038,6 +1079,14 @@ static int rdt_bit_usage_show(struct kernfs_open_fil= e *of, for (i =3D 0; i < closids_supported(); i++) { if (!closid_allocated(i)) continue; + /* + * If io_alloc is enabled, the CLOSID will be + * allocated but will not be associated with any + * groups. Skip in that case. + */ + if (i =3D=3D resctrl_io_alloc_closid_get(r, s) && + resctrl_arch_get_io_alloc_enabled(r)) + continue; ctrl_val =3D resctrl_arch_get_config(r, dom, i, s->conf_type); mode =3D rdtgroup_mode_by_closid(i); @@ -1830,6 +1879,94 @@ int resctrl_arch_io_alloc_enable(struct rdt_resource= *r, bool enable) return 0; } =20 +static int resctrl_io_alloc_show(struct kernfs_open_file *of, + struct seq_file *seq, void *v) +{ + struct resctrl_schema *s =3D of->kn->parent->priv; + struct rdt_resource *r =3D s->res; + + seq_printf(seq, "%x\n", resctrl_arch_get_io_alloc_enabled(r)); + return 0; +} + +/* + * Initialize io_alloc CLOSID cache resource with default CBM values. + */ +static int resctrl_io_alloc_init_cat(struct rdt_resource *r, + struct resctrl_schema *s, u32 closid) +{ + int ret; + + rdt_staged_configs_clear(); + + ret =3D rdtgroup_init_cat(s, closid); + if (ret < 0) + goto out_init_cat; + + ret =3D resctrl_arch_update_domains(r, closid); + +out_init_cat: + rdt_staged_configs_clear(); + return ret; +} + +static ssize_t resctrl_io_alloc_write(struct kernfs_open_file *of, char *b= uf, + size_t nbytes, loff_t off) +{ + struct resctrl_schema *s =3D of->kn->parent->priv; + struct rdt_resource *r =3D s->res; + u32 io_alloc_closid; + bool enable; + int ret; + + if (!r->cache.io_alloc_capable || s->conf_type =3D=3D CDP_DATA) { + rdt_last_cmd_puts("io_alloc feature is not supported on the resource\n"); + return -EINVAL; + } + + ret =3D kstrtobool(buf, &enable); + if (ret) + return ret; + + cpus_read_lock(); + mutex_lock(&rdtgroup_mutex); + + rdt_last_cmd_clear(); + + io_alloc_closid =3D resctrl_io_alloc_closid_get(r, s); + if (io_alloc_closid < 0) { + ret =3D -EINVAL; + goto out_io_alloc; + } + + if (resctrl_arch_get_io_alloc_enabled(r) !=3D enable) { + if (enable) { + ret =3D resctrl_io_alloc_closid_alloc(io_alloc_closid); + if (ret < 0) { + rdt_last_cmd_puts("CLOSID for io_alloc is not available\n"); + goto out_io_alloc; + } + ret =3D resctrl_io_alloc_init_cat(r, s, io_alloc_closid); + if (ret) { + rdt_last_cmd_puts("Failed to initialize io_alloc allocations\n"); + resctrl_io_alloc_closid_free(io_alloc_closid); + goto out_io_alloc; + } + + } else { + resctrl_io_alloc_closid_free(io_alloc_closid); + } + + ret =3D resctrl_arch_io_alloc_enable(r, enable); + } + +out_io_alloc: + mutex_unlock(&rdtgroup_mutex); + cpus_read_unlock(); + + return ret ?: nbytes; +} + /* rdtgroup information files for one cache resource. */ static struct rftype res_common_files[] =3D { { @@ -1982,6 +2119,13 @@ static struct rftype res_common_files[] =3D { .seq_show =3D rdtgroup_schemata_show, .fflags =3D RFTYPE_CTRL_BASE, }, + { + .name =3D "io_alloc", + .mode =3D 0644, + .kf_ops =3D &rdtgroup_kf_single_ops, + .seq_show =3D resctrl_io_alloc_show, + .write =3D resctrl_io_alloc_write, + }, { .name =3D "mba_MBps_event", .mode =3D 0644, --=20 2.34.1 From nobody Mon Feb 9 07:19:36 2026 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2075.outbound.protection.outlook.com [40.107.244.75]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F6341F0E36; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jan 2025 21:21:33.7459 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: deac3b9b-9c38-4d30-6b76-08dd41741276 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397B5.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB7462 Content-Type: text/plain; charset="utf-8" The io_alloc feature in resctrl enables system software to configure the portion of the L3 cache allocated for I/O traffic. Add the interface to display CBMs (Capacity Bit Mask) of io_alloc feature. When CDP is enabled, io_alloc routes traffic using the highest CLOSID which corresponds to CDP_CODE. Add a check for the CDP resource type. Signed-off-by: Babu Moger --- v3: Minor changes due to changes in resctrl_arch_get_io_alloc_enabled() and resctrl_io_alloc_closid_get(). Added the check to verify CDP resource type. Updated the commit log. v2: Fixed to display only on L3 resources. Added the locks while processing. Rename the displat to io_alloc_cbm (from sdciae_cmd). --- arch/x86/kernel/cpu/resctrl/core.c | 2 ++ arch/x86/kernel/cpu/resctrl/ctrlmondata.c | 2 +- arch/x86/kernel/cpu/resctrl/internal.h | 1 + arch/x86/kernel/cpu/resctrl/rdtgroup.c | 38 +++++++++++++++++++++++ 4 files changed, 42 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index 88bc95c14ea8..030f738dea8d 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -311,6 +311,8 @@ static void rdt_set_io_alloc_capable(struct rdt_resourc= e *r) r->cache.io_alloc_capable =3D true; resctrl_file_fflags_init("io_alloc", RFTYPE_CTRL_INFO | RFTYPE_RES_CACHE); + resctrl_file_fflags_init("io_alloc_cbm", + RFTYPE_CTRL_INFO | RFTYPE_RES_CACHE); } =20 static void rdt_get_cdp_l3_config(void) diff --git a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c b/arch/x86/kernel/cp= u/resctrl/ctrlmondata.c index 536351159cc2..d272dea43924 100644 --- a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c +++ b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c @@ -444,7 +444,7 @@ u32 resctrl_arch_get_config(struct rdt_resource *r, str= uct rdt_ctrl_domain *d, return hw_dom->ctrl_val[idx]; } =20 -static void show_doms(struct seq_file *s, struct resctrl_schema *schema, i= nt closid) +void show_doms(struct seq_file *s, struct resctrl_schema *schema, int clos= id) { struct rdt_resource *r =3D schema->res; struct rdt_ctrl_domain *dom; diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index 61bc609e932b..07cf8409174d 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -668,4 +668,5 @@ void resctrl_file_fflags_init(const char *config, unsig= ned long fflags); void rdt_staged_configs_clear(void); bool closid_allocated(unsigned int closid); int resctrl_find_cleanest_closid(void); +void show_doms(struct seq_file *s, struct resctrl_schema *schema, int clos= id); #endif /* _ASM_X86_RESCTRL_INTERNAL_H */ diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 37295dd14abe..81b9d8c5dabf 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1967,6 +1967,38 @@ static ssize_t resctrl_io_alloc_write(struct kernfs_= open_file *of, char *buf, return ret ?: nbytes; } =20 +static int resctrl_io_alloc_cbm_show(struct kernfs_open_file *of, + struct seq_file *seq, void *v) +{ + struct resctrl_schema *s =3D of->kn->parent->priv; + struct rdt_resource *r =3D s->res; + u32 io_alloc_closid; + int ret =3D 0; + + if (!r->cache.io_alloc_capable || s->conf_type =3D=3D CDP_DATA) { + rdt_last_cmd_puts("io_alloc feature is not supported on the resource\n"); + return -EINVAL; + } + + cpus_read_lock(); + mutex_lock(&rdtgroup_mutex); + + if (!resctrl_arch_get_io_alloc_enabled(r)) { + rdt_last_cmd_puts("io_alloc feature is not enabled\n"); + ret =3D -EINVAL; + goto cbm_show_out; + } + + io_alloc_closid =3D resctrl_io_alloc_closid_get(r, s); + + show_doms(seq, s, io_alloc_closid); + +cbm_show_out: + mutex_unlock(&rdtgroup_mutex); + cpus_read_unlock(); + return ret; +} + /* rdtgroup information files for one cache resource. */ static struct rftype res_common_files[] =3D { { @@ -2126,6 +2158,12 @@ static struct rftype res_common_files[] =3D { .seq_show =3D resctrl_io_alloc_show, .write =3D resctrl_io_alloc_write, }, + { + .name =3D "io_alloc_cbm", + .mode =3D 0444, + .kf_ops =3D &rdtgroup_kf_single_ops, + .seq_show =3D resctrl_io_alloc_cbm_show, + }, { .name =3D "mba_MBps_event", .mode =3D 0644, --=20 2.34.1 From nobody Mon Feb 9 07:19:36 2026 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2056.outbound.protection.outlook.com [40.107.244.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B4C5C1F150B; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jan 2025 21:21:41.8620 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 22408b9b-34b6-47c1-d574-08dd4174174c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397B2.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6082 Content-Type: text/plain; charset="utf-8" "io_alloc" feature is a mechanism that enables direct insertion of data from I/O devices into the L3 cache. By directly caching data from I/O devices rather than first storing the I/O data in DRAM, it reduces the demands on DRAM bandwidth and reduces latency to the processor consuming the I/O data. io_alloc feature uses the highest CLOSID to route the traffic from I/O devices. Provide the interface to modify io_alloc CBMs (Capacity Bit Mask) when feature is enabled. Signed-off-by: Babu Moger --- v3: Minor changes due to changes in resctrl_arch_get_io_alloc_enabled() and resctrl_io_alloc_closid_get(). Taken care of handling the CBM update when CDP is enabled. Updated the commit log to make it generic. v2: Added more generic text in documentation. --- Documentation/arch/x86/resctrl.rst | 12 ++ arch/x86/kernel/cpu/resctrl/ctrlmondata.c | 2 +- arch/x86/kernel/cpu/resctrl/internal.h | 1 + arch/x86/kernel/cpu/resctrl/rdtgroup.c | 134 +++++++++++++++++++++- 4 files changed, 147 insertions(+), 2 deletions(-) diff --git a/Documentation/arch/x86/resctrl.rst b/Documentation/arch/x86/re= sctrl.rst index 1b67e31d626c..29c8851bcc7f 100644 --- a/Documentation/arch/x86/resctrl.rst +++ b/Documentation/arch/x86/resctrl.rst @@ -169,6 +169,18 @@ related to allocation: When CDP is enabled, io_alloc routes I/O traffic using the highest CLOSID allocated for the instruction cache. =20 +"io_alloc_cbm": + Capacity Bit Masks (CBMs) available to supported IO devices which + can directly insert cache lines in L3 which can help to reduce the + latency. CBM can be configured by writing to the interface in the + following format:: + + L3:=3D;=3D;... + + When CDP is enabled, L3 control is divided into two separate resources: + L3CODE and L3DATA. However, the CBM can only be updated on the L3CODE + resource. + Memory bandwidth(MB) subdirectory contains the following files with respect to allocation: =20 diff --git a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c b/arch/x86/kernel/cp= u/resctrl/ctrlmondata.c index d272dea43924..4dfee0436c1c 100644 --- a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c +++ b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c @@ -102,7 +102,7 @@ int parse_bw(struct rdt_parse_data *data, struct resctr= l_schema *s, * requires at least two bits set. * AMD allows non-contiguous bitmasks. */ -static bool cbm_validate(char *buf, u32 *data, struct rdt_resource *r) +bool cbm_validate(char *buf, u32 *data, struct rdt_resource *r) { unsigned long first_bit, zero_bit, val; unsigned int cbm_len =3D r->cache.cbm_len; diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index 07cf8409174d..702f6926bbdf 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -669,4 +669,5 @@ void rdt_staged_configs_clear(void); bool closid_allocated(unsigned int closid); int resctrl_find_cleanest_closid(void); void show_doms(struct seq_file *s, struct resctrl_schema *schema, int clos= id); +bool cbm_validate(char *buf, u32 *data, struct rdt_resource *r); #endif /* _ASM_X86_RESCTRL_INTERNAL_H */ diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 81b9d8c5dabf..9997cbfc1c19 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1999,6 +1999,137 @@ static int resctrl_io_alloc_cbm_show(struct kernfs_= open_file *of, return ret; } =20 +/* + * Read the CBM and check the validity. Make sure CBM is not shared + * with any other exclusive resctrl groups. + */ +static int resctrl_io_alloc_parse_cbm(char *buf, struct resctrl_schema *s, + struct rdt_ctrl_domain *d) +{ + struct resctrl_staged_config *cfg; + struct rdt_resource *r =3D s->res; + u32 io_alloc_closid; + u32 cbm_val; + + cfg =3D &d->staged_config[s->conf_type]; + if (cfg->have_new_ctrl) { + rdt_last_cmd_printf("Duplicate domain %d\n", d->hdr.id); + return -EINVAL; + } + + if (!cbm_validate(buf, &cbm_val, r)) + return -EINVAL; + + /* + * The CBM may not overlap with other exclusive group. + */ + io_alloc_closid =3D resctrl_io_alloc_closid_get(r, s); + if (rdtgroup_cbm_overlaps(s, d, cbm_val, io_alloc_closid, true)) { + rdt_last_cmd_puts("Overlaps with exclusive group\n"); + return -EINVAL; + } + + cfg->new_ctrl =3D cbm_val; + cfg->have_new_ctrl =3D true; + + return 0; +} + +static int resctrl_io_alloc_parse_line(char *line, struct rdt_resource *r, + struct resctrl_schema *s) +{ + struct rdt_ctrl_domain *d; + char *dom =3D NULL, *id; + unsigned long dom_id; + +next: + if (!line || line[0] =3D=3D '\0') + return 0; + + dom =3D strsep(&line, ";"); + id =3D strsep(&dom, "=3D"); + if (!dom || kstrtoul(id, 10, &dom_id)) { + rdt_last_cmd_puts("Missing '=3D' or non-numeric domain\n"); + return -EINVAL; + } + + dom =3D strim(dom); + list_for_each_entry(d, &r->ctrl_domains, hdr.list) { + if (d->hdr.id =3D=3D dom_id) { + if (resctrl_io_alloc_parse_cbm(dom, s, d)) + return -EINVAL; + goto next; + } + } + return -EINVAL; +} + +static ssize_t resctrl_io_alloc_cbm_write(struct kernfs_open_file *of, + char *buf, size_t nbytes, loff_t off) +{ + struct resctrl_schema *s =3D of->kn->parent->priv; + struct rdt_resource *r =3D s->res; + u32 io_alloc_closid; + char *resname; + int ret =3D 0; + + /* Valid input requires a trailing newline */ + if (nbytes =3D=3D 0 || buf[nbytes - 1] !=3D '\n') + return -EINVAL; + + buf[nbytes - 1] =3D '\0'; + + if (!r->cache.io_alloc_capable || s->conf_type =3D=3D CDP_DATA) { + rdt_last_cmd_puts("io_alloc feature is not supported on the resource\n"); + return -EINVAL; + } + + cpus_read_lock(); + mutex_lock(&rdtgroup_mutex); + + rdt_last_cmd_clear(); + rdt_staged_configs_clear(); + + if (!resctrl_arch_get_io_alloc_enabled(r)) { + rdt_last_cmd_puts("io_alloc feature is not enabled\n"); + ret =3D -EINVAL; + goto cbm_write_out; + } + + resname =3D strim(strsep(&buf, ":")); + if (!buf) { + rdt_last_cmd_puts("Missing ':'\n"); + ret =3D -EINVAL; + goto cbm_write_out; + } + + if (strcmp(resname, s->name)) { + rdt_last_cmd_printf("Unsupported resource name '%s'\n", resname); + ret =3D -EINVAL; + goto cbm_write_out; + } + + if (buf[0] =3D=3D '\0') { + rdt_last_cmd_printf("Missing '%s' value\n", resname); + ret =3D -EINVAL; + goto cbm_write_out; + } + + ret =3D resctrl_io_alloc_parse_line(buf, r, s); + if (ret) + goto cbm_write_out; + + io_alloc_closid =3D resctrl_io_alloc_closid_get(r, s); + ret =3D resctrl_arch_update_domains(r, io_alloc_closid); + +cbm_write_out: + rdt_staged_configs_clear(); + mutex_unlock(&rdtgroup_mutex); + cpus_read_unlock(); + + return ret ?: nbytes; +} + /* rdtgroup information files for one cache resource. */ static struct rftype res_common_files[] =3D { { @@ -2160,9 +2291,10 @@ static struct rftype res_common_files[] =3D { }, { .name =3D "io_alloc_cbm", - .mode =3D 0444, + .mode =3D 0644, .kf_ops =3D &rdtgroup_kf_single_ops, .seq_show =3D resctrl_io_alloc_cbm_show, + .write =3D resctrl_io_alloc_cbm_write, }, { .name =3D "mba_MBps_event", --=20 2.34.1