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charset="utf-8" From: Ryan Wanner Add SAMA7D65 DDR3phy compatible to DT bindings documentation Signed-off-by: Ryan Wanner Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/mfd/syscon.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentat= ion/devicetree/bindings/mfd/syscon.yaml index b414de4fa779b..54a6d5957e13a 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -188,6 +188,7 @@ properties: - microchip,lan966x-cpu-syscon - microchip,mpfs-sysreg-scb - microchip,sam9x60-sfr + - microchip,sama7d65-ddr3phy - microchip,sama7g5-ddr3phy - mscc,ocelot-cpu-syscon - mstar,msc313-pmsleep --=20 2.43.0 From nobody Tue Feb 10 03:00:38 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C5E091F1302; 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charset="utf-8" From: Ryan Wanner Add SAMA7D65 SFRBU compatible string to DT bindings documentation Signed-off-by: Ryan Wanner --- Documentation/devicetree/bindings/mfd/syscon.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentat= ion/devicetree/bindings/mfd/syscon.yaml index 54a6d5957e13a..25c4ed6cbf5d1 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -90,6 +90,7 @@ select: - microchip,lan966x-cpu-syscon - microchip,mpfs-sysreg-scb - microchip,sam9x60-sfr + - microchip,sama7d65-sfrbu - microchip,sama7g5-ddr3phy - mscc,ocelot-cpu-syscon - mstar,msc313-pmsleep @@ -188,6 +189,7 @@ properties: - microchip,lan966x-cpu-syscon - microchip,mpfs-sysreg-scb - microchip,sam9x60-sfr + - microchip,sama7d65-sfrbu - microchip,sama7d65-ddr3phy - microchip,sama7g5-ddr3phy - mscc,ocelot-cpu-syscon --=20 2.43.0 From nobody Tue Feb 10 03:00:38 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0E7F21F0E27; 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charset="utf-8" From: Ryan Wanner Add microchip,sama7d65-sram compatibility to DT binding documentation. Signed-off-by: Ryan Wanner Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/sram/sram.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/sram/sram.yaml b/Documentati= on/devicetree/bindings/sram/sram.yaml index 7c1337e159f23..3071c5075ee48 100644 --- a/Documentation/devicetree/bindings/sram/sram.yaml +++ b/Documentation/devicetree/bindings/sram/sram.yaml @@ -31,6 +31,7 @@ properties: - amlogic,meson-gxbb-sram - arm,juno-sram-ns - atmel,sama5d2-securam + - microchip,sama7d65-securam - nvidia,tegra186-sysram - nvidia,tegra194-sysram - nvidia,tegra234-sysram --=20 2.43.0 From nobody Tue Feb 10 03:00:38 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C58B71F1504; Thu, 30 Jan 2025 17:36:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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d="scan'208";a="204623010" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 30 Jan 2025 10:36:21 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 30 Jan 2025 10:35:40 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Thu, 30 Jan 2025 10:35:40 -0700 From: To: , , , , , , , , , CC: , , , , , Ryan Wanner Subject: [PATCH 04/16] dt-bindings: power: reset: atmel,sama5d2-shdwc: Add microchip,sama7d65-shdwc Date: Thu, 30 Jan 2025 10:33:44 -0700 Message-ID: <1e04bd9b667d2831be3c7f6dc6f3d23f07a7d8e6.1738257860.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Ryan Wanner Add SAMA7D65 SHDWC compatible to DT bindings documentation Signed-off-by: Ryan Wanner Acked-by: Rob Herring (Arm) --- .../devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-sh= dwc.yaml b/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdw= c.yaml index 8c58e12cdb600..2930607480ea2 100644 --- a/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml +++ b/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml @@ -16,6 +16,11 @@ description: | properties: compatible: oneOf: + - items: + - enum: + - microchip,sama7d65-shdwc + - const: microchip,sama7g5-shdwc + - const: syscon - items: - const: microchip,sama7g5-shdwc - const: syscon --=20 2.43.0 From nobody Tue Feb 10 03:00:38 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8BEA21F1521; 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X-CSE-ConnectionGUID: Qux6TnwtQkq+U6Cg6JCAlA== X-CSE-MsgGUID: 3YdoWKTPTdWqkkI7huaAyw== X-IronPort-AV: E=Sophos;i="6.13,246,1732604400"; d="scan'208";a="204623011" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 30 Jan 2025 10:36:21 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 30 Jan 2025 10:35:40 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Thu, 30 Jan 2025 10:35:40 -0700 From: To: , , , , , , , , , CC: , , , , , Ryan Wanner Subject: [PATCH 05/16] dt-bindings: reset: atmel,at91sam9260-reset: add microchip,sama7d65-rstc Date: Thu, 30 Jan 2025 10:33:45 -0700 Message-ID: <2350540fd22b181875d3cce272fba87fff924670.1738257860.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Ryan Wanner Add SAMA7D65 RSTC compatible to DT bindings documentation. The sama7g54-rstc is compatible with the sama7g5-rstc. Signed-off-by: Ryan Wanner --- .../devicetree/bindings/reset/atmel,at91sam9260-reset.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/reset/atmel,at91sam9260-rese= t.yaml b/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.ya= ml index 98465d26949ee..a1c21c3880f9d 100644 --- a/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml +++ b/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml @@ -23,6 +23,11 @@ properties: - atmel,sama5d3-rstc - microchip,sam9x60-rstc - microchip,sama7g5-rstc + + - items: + - const: microchip,sama7d65-rstc + - const: microchip,sama7g5-rstc + - items: - const: atmel,sama5d3-rstc - const: atmel,at91sam9g45-rstc --=20 2.43.0 From nobody Tue Feb 10 03:00:38 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CF87F1F1535; Thu, 30 Jan 2025 17:36:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738258586; cv=none; b=U3RSW0u0HBwMq3uEa8lbY+Sa3MMw8hAKRT5g7DxnLemVp376eHbVE/aa7t1pzDOZFho5tWt8kfa5cBiFVez0Q+0xdviESe794jF2O4dbx0ZWhZ+6GelgZCao2t6EzhIomEW7PMR1vFsAyZsbxiWy9GzZVuMYviG+zjuu/Sgj+IE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738258586; c=relaxed/simple; bh=zrbbMTlcUWrm93EkCQYP4a8+4Ji/9a+FhVO9sECvsBQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Sj3IN7vlu5uHzk7Hr+vhtWgZc5sgjcy7D9X7L8a9EeTEoWMKZwzWUNY4p5g/Z3YrflZ2A4iOS+VsFk0Kvx58UBVk/2evH7XF2CtUAwxwWOH1UTbJaKKSc7bE0pZIJVj0ZLDeu8G+wAbEFH5mpF0kZBjAOzl7GZsw0ORJSJlNQ8I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=MqUKuyI0; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="MqUKuyI0" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1738258584; x=1769794584; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=zrbbMTlcUWrm93EkCQYP4a8+4Ji/9a+FhVO9sECvsBQ=; b=MqUKuyI0JSiifVcQEsRBkYRJ98fAgaKSIRwXkmKs4l4AS1/kQjFVJzpu eQZPgdfG0ZZNufE2bcizlKMx9bTk0uTX92ljj/XKxGGFhN1j+0dEl0hKz Uh/18M67/FqCPbPgxdoSnJDSdB4ZD0RGHwgSh7pR9bJYq0O7HtKNAuVGT qmGdevmULCE7wVjNYYZSPnVQg7nNt83FZ0m9jcCpggM01uf+Mmepb2fJ1 6jIRhZe+XDkW/8T9GYvBA+cJ6HuE/NWOuI13g0aWLCGA9KCPM8l67qGv5 tIH27No/B3L8URb/ZVfxRtAoxZlZbh9fa0sk3+x25JDYPKyxPHhKyDceC A==; X-CSE-ConnectionGUID: Qux6TnwtQkq+U6Cg6JCAlA== X-CSE-MsgGUID: 8djFspQTSKygg97mneOtTg== X-IronPort-AV: E=Sophos;i="6.13,246,1732604400"; d="scan'208";a="204623013" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 30 Jan 2025 10:36:21 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 30 Jan 2025 10:35:40 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Thu, 30 Jan 2025 10:35:40 -0700 From: To: , , , , , , , , , CC: , , , , , Ryan Wanner Subject: [PATCH 06/16] dt-bindings: rtc: at91rm9200: Reorganize compatible items Date: Thu, 30 Jan 2025 10:33:46 -0700 Message-ID: <2846391c5ffab332ad7a4b65aa60aac9c49a3496.1738257860.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Ryan Wanner Reorganize compatible to allow more devices to be added to this enum. Signed-off-by: Ryan Wanner --- .../devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.yam= l b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml index c8bb2eef442dd..30d87b74c51dc 100644 --- a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml @@ -21,9 +21,10 @@ properties: - atmel,sama5d4-rtc - atmel,sama5d2-rtc - microchip,sam9x60-rtc - - microchip,sama7g5-rtc - items: - - const: microchip,sam9x7-rtc + - enum: + - microchip,sama7g5-rtc + - microchip,sam9x7-rtc - const: microchip,sam9x60-rtc =20 reg: --=20 2.43.0 From nobody Tue Feb 10 03:00:38 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9E06E1F1929; Thu, 30 Jan 2025 17:36:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738258587; cv=none; b=RnZD3zeiJTGp0jTBSPR0AaC8pZjwpZe5dKKuKwJx8wBXby+moE8DtcO1RISFUzejx6rYvrs0XQpbwl4jGT9CFXol2iLywkn/Cg0YsTux6NvlxQwnARhphHnBqethMQHXKHVKsC7lGj3n73+QogwK6ur7cJHUv1KbI342pbzSm54= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738258587; c=relaxed/simple; bh=3DIUaseaLPdLuHuizOpT4HlTIidRdrZDDni3saHEVio=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=a4Zu8ESCzLUOMI455JxcilW8cQMbh7jvb/hcROKjq6y542zkan/DNZY5vPITLR6RKo1A2ChUc/6VP8hiR+9Nlw6D7ImXLYdNjF7o3WOQpNsEwqlmB//92umpPF30SNTr2t+Lpwof4wHhj2qJhn215HtdV5PWWymEuZCqA0OmnYs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=LoGV0VyJ; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="LoGV0VyJ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1738258585; x=1769794585; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3DIUaseaLPdLuHuizOpT4HlTIidRdrZDDni3saHEVio=; b=LoGV0VyJ7dnf3RIqo0l64qZjDJqo+OETHNZgl5IDq0RLXN4/bstRB06g VmoiVbU1JFARdzi8uX9L2rsOhM4DciSjo3DU8pXyNun+kOGXTYGIR3XiR nh8H2JOplhyxzfzv1Gm0PQHZ9ilwyF1RwRZ4coCHGCl9F3DIw/KZMCCli BlP+psxJEPQN40WN5u/5Jj9J/y1CJ5zd8AemSFmr+PyoMnYFVXK+KYSrE iANpCWqwAz7g4re55BQqUDytf15kpEA1OXCWBcY5yjzVTkHqI/F9vnxZx i3n+xi6lQHh47kF9bh3r29PL4XqUUzfIAl3opNI8DzhEFY6Ef/R2K4iZ9 w==; X-CSE-ConnectionGUID: Qux6TnwtQkq+U6Cg6JCAlA== X-CSE-MsgGUID: EcLVourmTqyK7csd0aL7tA== X-IronPort-AV: E=Sophos;i="6.13,246,1732604400"; d="scan'208";a="204623014" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 30 Jan 2025 10:36:22 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 30 Jan 2025 10:35:40 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Thu, 30 Jan 2025 10:35:40 -0700 From: To: , , , , , , , , , CC: , , , , , Ryan Wanner Subject: [PATCH 07/16] dt-bindings: rtc: at91rm9200: add microchip,sama7d65-rtc Date: Thu, 30 Jan 2025 10:33:47 -0700 Message-ID: <18618f9afd74be84d446608257c37d7bc8271ff8.1738257860.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Ryan Wanner Add SAMA7D65 RTC compatible to DT bindings documentation. Signed-off-by: Ryan Wanner --- Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.yam= l b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml index 30d87b74c51dc..d248cd49dbe23 100644 --- a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.yaml @@ -23,6 +23,7 @@ properties: - microchip,sam9x60-rtc - items: - enum: + - microchip,sama7d65-rtc - microchip,sama7g5-rtc - microchip,sam9x7-rtc - const: microchip,sam9x60-rtc --=20 2.43.0 From nobody Tue Feb 10 03:00:38 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B8B281F238E; Thu, 30 Jan 2025 17:36:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738258588; cv=none; b=nKoSkQ/dB5MUVU04pNbSvTPZH/bOiPATJX63kDMDqnDEnhTHs8O92cLeNdfEbJ9VMgrhgeYcXaTzM9X7iUJ/40eCR6PPH79rdoUgtvqIulKcwFI8bJc0KCXKjKJjh0yQ0pzkOHc8+1jQxdZgQ5ad/Mzk2HmbMVprHUDRkNQfQbk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738258588; c=relaxed/simple; bh=py/yqNx13hsIQ9lYRrDtu9qmIYc+M8dbM6qysRjVXU0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=SmuHUIv4HBDyruWI+HcUzVOM3vxATG+K2rX19RJ7HpmZ6BeYY2QkTPGAxtYxtw/esfoYNm5Hbwjx4w9UiI1SdPS9VC9tdZXvgJQdyz3swBB/ziur5NWkx7C9Wth2jeg8rn/P71eqUrSqWjCZ+jj7iw58Bcy4V7z3kWwiEmgZYvU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=L5hJ6r+O; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="L5hJ6r+O" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1738258586; x=1769794586; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=py/yqNx13hsIQ9lYRrDtu9qmIYc+M8dbM6qysRjVXU0=; b=L5hJ6r+OqbHfOBnaef+WWaH47YTwrI6J3SoXbt7M+zu4xClGu/fL1t7+ 0hPOeH11SmqgWffqykbethg/gJFd1/9bbD7kyCFF99JnWpLOIfC7bMFk3 /sGgnkjmJ0pTxaBsOgPHunawmhQCMdrIhKiRoILWdiH9q57qQIr8iNp0a qPj0trqE5atJV1eEpLy7L88ixhjH7rGIJs9AFl7cZbi6FunREldV6DmQ2 PGlLSMI5bOw3lW2hNU7hXDV3F0ODo9cgVgbsRuEeZ8Is5m8hmRzS+I/zc voiB+5JK/ia2EA8YPW0F5wFrfcGuOdjjrdfX+n6zX3Sr68FRQweyeL9vr w==; X-CSE-ConnectionGUID: Qux6TnwtQkq+U6Cg6JCAlA== X-CSE-MsgGUID: 9Uc2kZpQTSKP4t4SzjONhA== X-IronPort-AV: E=Sophos;i="6.13,246,1732604400"; d="scan'208";a="204623016" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 30 Jan 2025 10:36:22 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 30 Jan 2025 10:35:40 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Thu, 30 Jan 2025 10:35:40 -0700 From: To: , , , , , , , , , CC: , , , , , Ryan Wanner Subject: [PATCH 08/16] dt-bindings: at91rm9260-rtt: add microchip,sama7d65-rtt Date: Thu, 30 Jan 2025 10:33:48 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Ryan Wanner Add SAMA7D65 RTT compatible to DT bindings documentation. Signed-off-by: Ryan Wanner --- .../devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.ya= ml b/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml index a7f6c1d1a08ab..078b753f453b4 100644 --- a/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml +++ b/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml @@ -23,6 +23,11 @@ properties: - microchip,sam9x60-rtt - microchip,sam9x7-rtt - const: atmel,at91sam9260-rtt + - items: + - enum: + - microchip,sama7d65-rtt + - const: microchip,sama7g5-rtt + - const: atmel,at91sam9260-rtt - items: - const: microchip,sama7g5-rtt - const: microchip,sam9x60-rtt --=20 2.43.0 From nobody Tue Feb 10 03:00:38 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7FD351F2C3D; Thu, 30 Jan 2025 17:36:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738258589; cv=none; b=kdoA2r78UHKIl7GzaTDwq7m1lhU218yIkdQK9ScgKPBgvp8sGZRJqK5nE1PT5/3ZjdK8WWh9EemT2pxhmYGLIoN9ku7qhQ1HnUlvLmfxVpRbkSnKchn50X7Km6OgYJV2BQCNGj2hdNI0CIS/J7giI/kQv50PbC9G5lEVFWPQn78= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738258589; c=relaxed/simple; bh=tr+5ctybWd1qXbabAXHiNSfhGJo/z7RoiOi9HQGyK+g=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=BRjTcOl8tUxuNkbshcVX3FG6D3EY3W+G1m9H6wXmU/Bh/NcNEOJQIl/ouZfBFlQpSgR/j3acB0zAY8J9taqtT6OBjTHdx5V5M6jmB8gtuRuSi32pD7nO1n9fgO13K5iD2Nwp3MgLGgpdwvvpTLeuoea4sMG1HQwwgR3Rrrd+mug= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=Ab3k73GA; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="Ab3k73GA" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1738258587; x=1769794587; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tr+5ctybWd1qXbabAXHiNSfhGJo/z7RoiOi9HQGyK+g=; b=Ab3k73GAQTThsKIIdQ1Hjmmtvu0j+KRSw2LNusR8VwaJF7RFeq80ne48 XTzt1efMKLKOo3PPbLnCYCxg78zv78Gx7xavCsk8iFRGkiv+BVQWB/PBr bArLxvx8OTFagzyXlxYA67ZjJauiC88UoY4ttRCDLkbuFZEyPLLxVR2Xq NyhMhP/u2SmWU0d42BmzYrOs7kViZNBFNzDzP7c0ZRBez5qh8C3+Nq06n hZkO7uygFyi5EG7YEvK9CMO3QznEaibm6UgFxYQztgaNGVar24kfLenOr w+FvBwO8a9y9ASxX96Cdd4FRz28yFMHMcqyqjoo8CHAFEkil3hBFf7Wox g==; X-CSE-ConnectionGUID: Qux6TnwtQkq+U6Cg6JCAlA== X-CSE-MsgGUID: QG7KiDv0SXmpwDdFB//Xow== X-IronPort-AV: E=Sophos;i="6.13,246,1732604400"; d="scan'208";a="204623018" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 30 Jan 2025 10:36:22 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 30 Jan 2025 10:35:41 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Thu, 30 Jan 2025 10:35:41 -0700 From: To: , , , , , , , , , CC: , , , , , Ryan Wanner Subject: [PATCH 09/16] ARM: at91: Add PM support to sama7d65 Date: Thu, 30 Jan 2025 10:33:49 -0700 Message-ID: <9a57da4b20f5fa7ec84af7353cfcdb43efbff29c.1738257860.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Ryan Wanner Add PM support to SAMA7D65 SoC. Signed-off-by: Ryan Wanner --- arch/arm/mach-at91/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 04bd91c72521c..f3ff1220c0fb0 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -65,6 +65,7 @@ config SOC_SAMA7D65 select HAVE_AT91_SAM9X60_PLL select HAVE_AT91_USB_CLK select HAVE_AT91_UTMI + select PM_OPP select SOC_SAMA7 help Select this if you are using one of Microchip's SAMA7D65 family SoC. --=20 2.43.0 From nobody Tue Feb 10 03:00:38 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A6BD11EF0B6; Thu, 30 Jan 2025 17:36:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738258574; cv=none; b=CySHyPPn4gomg8y8OdwjRtmCsXdp0YzD2WMZ4f0HT8QfdzTNje02xlXwqtooUcogfg12cCGLejuiOSaeA+613DeSyiv20xl7CxGQfQShm7jbCKhOs6mlb9bd9a59V60F+8jOdEmClWpRUwMl9nkpZTrtmfVpIJAwDDX3/XaUkjY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738258574; c=relaxed/simple; bh=EWDYRLDJNCSj8RgMr4ncDCesuiq7qtH/1S45Wc/TEoI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=hXTjvJnkfXkXzKOyLpc0XiOzGVqOd9KnrI0XDNgiroAASPyYTwANXK0oM+tFikH9TWw/f8ngveAoKtPk8VrB5C2RZAAIh1JFXdYkTxjYWcwsVJNTAkbO/g7cpUizCzAQBLuH3ZjIEUFJ6ekU+MvXpR5SQX8f7VsGBzeNnRBBXvU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=DMSULMaL; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="DMSULMaL" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1738258572; x=1769794572; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=EWDYRLDJNCSj8RgMr4ncDCesuiq7qtH/1S45Wc/TEoI=; b=DMSULMaLlJLVE5S40NpXK+0sZITsBpMxxekHFNMETBp0z7gKuMJKwy3X edyjDxMjV7KPeh7US/3V6vfFqRAQI/aAEnz/TJsqt+St3ONoG2cD0XQun LD83IbW4o3Jd8BNm20Evy9oA190a/3EBw+4uvq/OaOh1lhVA14ImVO30b Bb2MEHBI3b0doxFbRFnSzgiU7x4Y0ni2cm1b7I10W0wj+uaVl95TU39Hf fsS9ng1Q13LrbhB1vAYocDZPd9ojVTJH4yiB+dfZ85O+y+ykaChrwyBYE njQM1c/JR5sga8sEJrwwMWYkKsHsbNEfv8xr43k64II+XPWYk7objsS2X g==; X-CSE-ConnectionGUID: 7iQ0c/B2QHylE8DKLR4q+g== X-CSE-MsgGUID: R4Kkehl8R8mgFbR+LWh4IA== X-IronPort-AV: E=Sophos;i="6.13,246,1732604400"; d="scan'208";a="41090047" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 30 Jan 2025 10:36:11 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 30 Jan 2025 10:35:41 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Thu, 30 Jan 2025 10:35:41 -0700 From: To: , , , , , , , , , CC: , , , , , Li Bin , Ryan Wanner , Durai Manickam KR , Andrei Simion Subject: [PATCH 10/16] ARM: at91: pm: fix at91_suspend_finish for ZQ calibration Date: Thu, 30 Jan 2025 10:33:50 -0700 Message-ID: <862773938ff0b1265cf1e7a5b11ae0eb5b03cb2f.1738257860.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Li Bin For sama7g5 and sama7d65 backup mode, we encountered a "ZQ calibrate error" during recalibrating the impedance in BootStrap. We found that the impedance value saved in at91_suspend_finish() before the DDR entered self-refresh mode did not match the resistor values. The ZDATA field in the DDR3PHY_ZQ0CR0 register uses a modified gray code to select the different impedance setting. But these gray code are incorrect, a workaournd from design team fixed the bug in the calibration logic. The ZDATA contains four independent impedance elements, but the algorithm combined the four elements into one. The elemen= ts were fixed using properly shifted offsets. Signed-off-by: Li Bin [nicolas.ferre@microchip.com: fix indentation and combine 2 patches] Signed-off-by: Nicolas Ferre Tested-by: Ryan Wanner Tested-by: Durai Manickam KR Tested-by: Andrei Simion --- arch/arm/mach-at91/pm.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 05a1547642b60..32b8354738752 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -545,11 +545,12 @@ extern u32 at91_pm_suspend_in_sram_sz; =20 static int at91_suspend_finish(unsigned long val) { - unsigned char modified_gray_code[] =3D { - 0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05, 0x0c, 0x0d, - 0x0e, 0x0f, 0x0a, 0x0b, 0x08, 0x09, 0x18, 0x19, 0x1a, 0x1b, - 0x1e, 0x1f, 0x1c, 0x1d, 0x14, 0x15, 0x16, 0x17, 0x12, 0x13, - 0x10, 0x11, + /* SYNOPSYS workaround to fix a bug in the calibration logic (SYNOPSYS Ca= se Number 01331341) */ + unsigned char modified_fix_code[] =3D { + 0x00, 0x01, 0x01, 0x06, 0x07, 0x0c, 0x06, 0x07, 0x0b, 0x18, + 0x0a, 0x0b, 0x0c, 0x0d, 0x0d, 0x0a, 0x13, 0x13, 0x12, 0x13, + 0x14, 0x15, 0x15, 0x12, 0x18, 0x19, 0x19, 0x1e, 0x1f, 0x14, + 0x1e, 0x1f, }; unsigned int tmp, index; int i; @@ -560,25 +561,25 @@ static int at91_suspend_finish(unsigned long val) * restore the ZQ0SR0 with the value saved here. But the * calibration is buggy and restoring some values from ZQ0SR0 * is forbidden and risky thus we need to provide processed - * values for these (modified gray code values). + * values for these. */ tmp =3D readl(soc_pm.data.ramc_phy + DDR3PHY_ZQ0SR0); =20 /* Store pull-down output impedance select. */ index =3D (tmp >> DDR3PHY_ZQ0SR0_PDO_OFF) & 0x1f; - soc_pm.bu->ddr_phy_calibration[0] =3D modified_gray_code[index]; + soc_pm.bu->ddr_phy_calibration[0] =3D modified_fix_code[index] << DDR3PH= Y_ZQ0SR0_PDO_OFF; =20 /* Store pull-up output impedance select. */ index =3D (tmp >> DDR3PHY_ZQ0SR0_PUO_OFF) & 0x1f; - soc_pm.bu->ddr_phy_calibration[0] |=3D modified_gray_code[index]; + soc_pm.bu->ddr_phy_calibration[0] |=3D modified_fix_code[index] << DDR3P= HY_ZQ0SR0_PUO_OFF; =20 /* Store pull-down on-die termination impedance select. */ index =3D (tmp >> DDR3PHY_ZQ0SR0_PDODT_OFF) & 0x1f; - soc_pm.bu->ddr_phy_calibration[0] |=3D modified_gray_code[index]; + soc_pm.bu->ddr_phy_calibration[0] |=3D modified_fix_code[index] << DDR3P= HY_ZQ0SR0_PDODT_OFF; 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Thu, 30 Jan 2025 10:35:41 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Thu, 30 Jan 2025 10:35:41 -0700 From: To: , , , , , , , , , CC: , , , , , Ryan Wanner Subject: [PATCH 11/16] ARM: at91: pm: add DT compatible support for sama7d65 Date: Thu, 30 Jan 2025 10:33:51 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Ryan Wanner Add support for SAMA7D65 new compatible strings in pm.c file for wakeup sou= rce IDs and PMC. This is the first bits of PM for this new SoC. PM depends on other patches. Signed-off-by: Ryan Wanner [nicolas.ferre@microchip.com: split patch and address only the pm.c changes] Signed-off-by: Nicolas Ferre --- arch/arm/mach-at91/pm.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 32b8354738752..a8cd1300a8f33 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -222,12 +222,14 @@ static const struct of_device_id sam9x60_ws_ids[] =3D= { { /* sentinel */ } }; =20 -static const struct of_device_id sama7g5_ws_ids[] =3D { - { .compatible =3D "microchip,sama7g5-rtc", .data =3D &ws_info[1] }, +static const struct of_device_id sama7_ws_ids[] =3D { + { .compatible =3D "microchip,sama7d65-rtc", .data =3D &ws_info[1] }, + { .compatible =3D "microchip,sama7g5-rtc", .data =3D &ws_info[1] }, { .compatible =3D "microchip,sama7g5-ohci", .data =3D &ws_info[2] }, { .compatible =3D "usb-ohci", .data =3D &ws_info[2] }, { .compatible =3D "atmel,at91sam9g45-ehci", .data =3D &ws_info[2] }, { .compatible =3D "usb-ehci", .data =3D &ws_info[2] }, + { .compatible =3D "microchip,sama7d65-sdhci", .data =3D &ws_info[3] }, { .compatible =3D "microchip,sama7g5-sdhci", .data =3D &ws_info[3] }, { .compatible =3D "microchip,sama7g5-rtt", .data =3D &ws_info[4] }, { /* sentinel */ } @@ -1379,6 +1381,7 @@ static const struct of_device_id atmel_pmc_ids[] __in= itconst =3D { { .compatible =3D "atmel,sama5d2-pmc", .data =3D &pmc_infos[1] }, { .compatible =3D "microchip,sam9x60-pmc", .data =3D &pmc_infos[4] }, { .compatible =3D "microchip,sam9x7-pmc", .data =3D &pmc_infos[4] }, + { .compatible =3D "microchip,sama7d65-pmc", .data =3D &pmc_infos[4] }, { .compatible =3D "microchip,sama7g5-pmc", .data =3D &pmc_infos[5] }, { /* sentinel */ }, }; @@ -1672,7 +1675,7 @@ void __init sama7_pm_init(void) at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps)); at91_pm_init(NULL); =20 - soc_pm.ws_ids =3D sama7g5_ws_ids; + soc_pm.ws_ids =3D sama7_ws_ids; soc_pm.config_pmc_ws =3D at91_sam9x60_config_pmc_ws; =20 soc_pm.sfrbu_regs.pswbu.key =3D (0x4BD20C << 8); --=20 2.43.0 From nobody Tue Feb 10 03:00:38 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7F4B51F03CB; Thu, 30 Jan 2025 17:36:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738258576; cv=none; b=YPZovOyTnMmmizJn+JTfkZAIu99bkKzcANrY6SE1GvN9PwWiwRrrdtyrxpeOIrBU4n/KULy08lraOCLBpuFxSaqGIjo5NAhfjyyIbMgzmNsMy7DjipfZeJisrNcqcfr/DFzntcIoUqC7kfVfLFfQ9JkWVc+E92CUGa4WyEM98mY= ARC-Message-Signature: i=1; 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Thu, 30 Jan 2025 10:35:41 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Thu, 30 Jan 2025 10:35:41 -0700 From: To: , , , , , , , , , CC: , , , , , Ryan Wanner Subject: [PATCH 12/16] ARM: at91: PM: Add Backup mode for SAMA7D65 Date: Thu, 30 Jan 2025 10:33:52 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Ryan Wanner Add config check that enables Backup mode for SAMA7D65 SoC. Add SHDWC_SR read to clear the status bits once finished exiting low power modes. This is only for SAMA7D65 SoCs. Signed-off-by: Ryan Wanner --- arch/arm/mach-at91/pm.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index a8cd1300a8f33..5e458254e1f1c 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -706,6 +706,9 @@ static int at91_pm_enter(suspend_state_t state) static void at91_pm_end(void) { at91_pm_config_ws(soc_pm.data.mode, false); + + if (IS_ENABLED(CONFIG_SOC_SAMA7D65)) + readl(soc_pm.data.shdwc + 0x08); } =20 =20 @@ -1064,7 +1067,8 @@ static int __init at91_pm_backup_init(void) int ret =3D -ENODEV, located =3D 0; =20 if (!IS_ENABLED(CONFIG_SOC_SAMA5D2) && - !IS_ENABLED(CONFIG_SOC_SAMA7G5)) + !IS_ENABLED(CONFIG_SOC_SAMA7G5) && + !IS_ENABLED(CONFIG_SOC_SAMA7D65)) return -EPERM; =20 if (!at91_is_pm_mode_active(AT91_PM_BACKUP)) --=20 2.43.0 From nobody Tue Feb 10 03:00:38 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A37421EEA3D; Thu, 30 Jan 2025 17:35:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738258553; cv=none; b=hkuufYAw3OiHqSAxzLcoReKtqRUTklSbnDIhfr+l1sDr1rzYg8OghYfFAk6SFd52RrU0rOV3ZvOawYpUIE1j8gS1ixJMKka6LYIcgZ/PZu0x9FHk2OrnoL5NWtYcU/IEQ+WCDNq/7SQroJn+N+ULdO3HsifzAI+EHZ8Kj+G+qLs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738258553; c=relaxed/simple; bh=nZid29reqDR3++ddySt2KOHWm8tGT444s+OSw8Gjkok=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=sjxlWHQ7GgMvcWycAoDU98mnRlW5L2T9kbFcc5pB0Ht3zgFbsHKgDIjjJm/P1l+AEFF4bZnzPmaprjxzkXKt4nq7EvJr2HIUmG4IRljEXflRZFOBf4+/Y+3aZ3HUNlyq7KAIk7J/GPJGOmP+A9lljaX0N8AJfy+DoUY0Tn44UzM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=oBoSQjtt; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="oBoSQjtt" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1738258551; x=1769794551; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=nZid29reqDR3++ddySt2KOHWm8tGT444s+OSw8Gjkok=; b=oBoSQjttMXFoeoZJnmZbhAkkN+G7D5jBQi4UxRnXqBhhVcTCXD5gjFZW uazlzcg2h/8sTB1MeTyqdW+x7QU1DWsw99avgUsS2DJ/A8/CYKe74tcAY a7m4qMwtn0Jc7g6LsZYz2hS5ejwCoJQjQznIDPQjRBARQkQt9cF7zSuHW B/fdPAqsZisZjN1Lmigt/lVnz117hqO7QgJj8hnGXFhIPb38eDB1GeWYk hGs0dLJfgeiot6Qhil+P1zv4SFmMrp3Wp/o615FcSbLX9zxepslaaP0d4 l3sL23LXJ6EG4pWk4j3jLUvUc/7Q/Rd4OOiQNomNrV0Dale9Q+m3XcgWQ g==; X-CSE-ConnectionGUID: X8noN3xrSZmPEckyVo5bzw== X-CSE-MsgGUID: exe2a/zgRGuLm6QIj8jwtA== X-IronPort-AV: E=Sophos;i="6.13,246,1732604400"; d="scan'208";a="204622972" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 30 Jan 2025 10:35:45 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 30 Jan 2025 10:35:41 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Thu, 30 Jan 2025 10:35:41 -0700 From: To: , , , , , , , , , CC: , , , , , Ryan Wanner Subject: [PATCH 13/16] ARM: at91: pm: Enable ULP0 for SAMA7D65 Date: Thu, 30 Jan 2025 10:33:53 -0700 Message-ID: <24544d75175c47e23eb0a89ab4c1783e191747cc.1738257860.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Ryan Wanner New clocks are saved to enable ULP0 for SAMA7D65 because this SoC has a total of 10 main clocks that need to be saved for ULP0 mode. Add mck_count member to at91_pm_data, this will be used to determine how many mcks need to be saved. In the mck_count member will also make sure that no unnecessary clock settings are written during mck_ps_restore. Add SHDWC to ULP0 mapping to clear the SHDWC status after exiting low power modes. Signed-off-by: Ryan Wanner Acked-by: Nicolas Ferre --- arch/arm/mach-at91/pm.c | 19 +++++- arch/arm/mach-at91/pm.h | 1 + arch/arm/mach-at91/pm_data-offsets.c | 2 + arch/arm/mach-at91/pm_suspend.S | 97 ++++++++++++++++++++++++++-- 4 files changed, 110 insertions(+), 9 deletions(-) diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 5e458254e1f1c..e29c44924ac22 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -1336,6 +1336,7 @@ struct pmc_info { unsigned long uhp_udp_mask; unsigned long mckr; unsigned long version; + unsigned long mck_count; }; =20 static const struct pmc_info pmc_infos[] __initconst =3D { @@ -1343,30 +1344,42 @@ static const struct pmc_info pmc_infos[] __initcons= t =3D { .uhp_udp_mask =3D AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP, .mckr =3D 0x30, .version =3D AT91_PMC_V1, + .mck_count =3D 1, }, =20 { .uhp_udp_mask =3D AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP, .mckr =3D 0x30, .version =3D AT91_PMC_V1, + .mck_count =3D 1, }, { .uhp_udp_mask =3D AT91SAM926x_PMC_UHP, .mckr =3D 0x30, .version =3D AT91_PMC_V1, + .mck_count =3D 1, }, { .uhp_udp_mask =3D 0, .mckr =3D 0x30, .version =3D AT91_PMC_V1, + .mck_count =3D 1, }, { .uhp_udp_mask =3D AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP, .mckr =3D 0x28, .version =3D AT91_PMC_V2, + .mck_count =3D 1, }, { .mckr =3D 0x28, .version =3D AT91_PMC_V2, + .mck_count =3D 5, + }, + { + .uhp_udp_mask =3D AT91SAM926x_PMC_UHP, + .mckr =3D 0x28, + .version =3D AT91_PMC_V2, + .mck_count =3D 10, }, =20 }; @@ -1385,7 +1398,7 @@ static const struct of_device_id atmel_pmc_ids[] __in= itconst =3D { { .compatible =3D "atmel,sama5d2-pmc", .data =3D &pmc_infos[1] }, { .compatible =3D "microchip,sam9x60-pmc", .data =3D &pmc_infos[4] }, { .compatible =3D "microchip,sam9x7-pmc", .data =3D &pmc_infos[4] }, - { .compatible =3D "microchip,sama7d65-pmc", .data =3D &pmc_infos[4] }, + { .compatible =3D "microchip,sama7d65-pmc", .data =3D &pmc_infos[6] }, { .compatible =3D "microchip,sama7g5-pmc", .data =3D &pmc_infos[5] }, { /* sentinel */ }, }; @@ -1456,6 +1469,7 @@ static void __init at91_pm_init(void (*pm_idle)(void)) soc_pm.data.uhp_udp_mask =3D pmc->uhp_udp_mask; soc_pm.data.pmc_mckr_offset =3D pmc->mckr; soc_pm.data.pmc_version =3D pmc->version; + soc_pm.data.pmc_mck_count =3D pmc->mck_count; =20 if (pm_idle) arm_pm_idle =3D pm_idle; @@ -1658,7 +1672,8 @@ void __init sama7_pm_init(void) AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP1, AT91_PM_BACKUP, }; static const u32 iomaps[] __initconst =3D { - [AT91_PM_ULP0] =3D AT91_PM_IOMAP(SFRBU), + [AT91_PM_ULP0] =3D AT91_PM_IOMAP(SFRBU) | + AT91_PM_IOMAP(SHDWC), [AT91_PM_ULP1] =3D AT91_PM_IOMAP(SFRBU) | AT91_PM_IOMAP(SHDWC) | AT91_PM_IOMAP(ETHC), diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h index 53bdc9000e447..ccde9c8728c27 100644 --- a/arch/arm/mach-at91/pm.h +++ b/arch/arm/mach-at91/pm.h @@ -39,6 +39,7 @@ struct at91_pm_data { unsigned int suspend_mode; unsigned int pmc_mckr_offset; unsigned int pmc_version; + unsigned int pmc_mck_count; }; #endif =20 diff --git a/arch/arm/mach-at91/pm_data-offsets.c b/arch/arm/mach-at91/pm_d= ata-offsets.c index 40bd4e8fe40a5..59a4838038381 100644 --- a/arch/arm/mach-at91/pm_data-offsets.c +++ b/arch/arm/mach-at91/pm_data-offsets.c @@ -18,6 +18,8 @@ int main(void) pmc_mckr_offset)); DEFINE(PM_DATA_PMC_VERSION, offsetof(struct at91_pm_data, pmc_version)); + DEFINE(PM_DATA_PMC_MCK_COUNT, offsetof(struct at91_pm_data, + pmc_mck_count)); =20 return 0; } diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspen= d.S index e5869cca5e791..2bbcbb26adb28 100644 --- a/arch/arm/mach-at91/pm_suspend.S +++ b/arch/arm/mach-at91/pm_suspend.S @@ -814,17 +814,19 @@ sr_dis_exit: .endm =20 /** - * at91_mckx_ps_enable: save MCK1..4 settings and switch it to main clock + * at91_mckx_ps_enable: save MCK settings and switch it to main clock * - * Side effects: overwrites tmp1, tmp2 + * Side effects: overwrites tmp1, tmp2, tmp3 */ .macro at91_mckx_ps_enable #ifdef CONFIG_SOC_SAMA7 ldr pmc, .pmc_base + ldr tmp3, .mck_count =20 - /* There are 4 MCKs we need to handle: MCK1..4 */ + /* Start at MCK1 and go until MCK_count */ mov tmp1, #1 -e_loop: cmp tmp1, #5 +e_loop: + cmp tmp1, tmp3 beq e_done =20 /* Write MCK ID to retrieve the settings. */ @@ -850,7 +852,37 @@ e_save_mck3: b e_ps =20 e_save_mck4: + cmp tmp1, #4 + bne e_save_mck5 str tmp2, .saved_mck4 + b e_ps + +e_save_mck5: + cmp tmp1, #5 + bne e_save_mck6 + str tmp2, .saved_mck5 + b e_ps + +e_save_mck6: + cmp tmp1, #6 + bne e_save_mck7 + str tmp2, .saved_mck6 + b e_ps + +e_save_mck7: + cmp tmp1, #7 + bne e_save_mck8 + str tmp2, .saved_mck7 + b e_ps + +e_save_mck8: + cmp tmp1, #8 + bne e_save_mck9 + str tmp2, .saved_mck8 + b e_ps + +e_save_mck9: + str tmp2, .saved_mck9 =20 e_ps: /* Use CSS=3DMAINCK and DIV=3D1. */ @@ -870,17 +902,19 @@ e_done: .endm =20 /** - * at91_mckx_ps_restore: restore MCK1..4 settings + * at91_mckx_ps_restore: restore MCKx settings * * Side effects: overwrites tmp1, tmp2 */ .macro at91_mckx_ps_restore #ifdef CONFIG_SOC_SAMA7 ldr pmc, .pmc_base + ldr tmp2, .mck_count =20 - /* There are 4 MCKs we need to handle: MCK1..4 */ + /* Start from MCK1 and go up to MCK_count */ mov tmp1, #1 -r_loop: cmp tmp1, #5 +r_loop: + cmp tmp1, tmp2 beq r_done =20 r_save_mck1: @@ -902,7 +936,37 @@ r_save_mck3: b r_ps =20 r_save_mck4: + cmp tmp1, #4 + bne r_save_mck5 ldr tmp2, .saved_mck4 + b r_ps + +r_save_mck5: + cmp tmp1, #5 + bne r_save_mck6 + ldr tmp2, .saved_mck5 + b r_ps + +r_save_mck6: + cmp tmp1, #6 + bne r_save_mck7 + ldr tmp2, .saved_mck6 + b r_ps + +r_save_mck7: + cmp tmp1, #7 + bne r_save_mck8 + ldr tmp2, .saved_mck7 + b r_ps + +r_save_mck8: + cmp tmp1, #8 + bne r_save_mck9 + ldr tmp2, .saved_mck8 + b r_ps + +r_save_mck9: + ldr tmp2, .saved_mck9 =20 r_ps: /* Write MCK ID to retrieve the settings. */ @@ -921,6 +985,7 @@ r_ps: wait_mckrdy tmp1 =20 add tmp1, tmp1, #1 + ldr tmp2, .mck_count b r_loop r_done: #endif @@ -1045,6 +1110,10 @@ ENTRY(at91_pm_suspend_in_sram) str tmp1, .memtype ldr tmp1, [r0, #PM_DATA_MODE] str tmp1, .pm_mode +#ifdef CONFIG_SOC_SAMA7 + ldr tmp1, [r0, #PM_DATA_PMC_MCK_COUNT] + str tmp1, .mck_count +#endif =20 /* * ldrne below are here to preload their address in the TLB as access @@ -1132,6 +1201,10 @@ ENDPROC(at91_pm_suspend_in_sram) .word 0 .pmc_version: .word 0 +#ifdef CONFIG_SOC_SAMA7 +.mck_count: + .word 0 +#endif .saved_mckr: .word 0 .saved_pllar: @@ -1155,6 +1228,16 @@ ENDPROC(at91_pm_suspend_in_sram) .word 0 .saved_mck4: .word 0 +.saved_mck5: + .word 0 +.saved_mck6: + .word 0 +.saved_mck7: + .word 0 +.saved_mck8: + .word 0 +.saved_mck9: + .word 0 #endif =20 ENTRY(at91_pm_suspend_in_sram_sz) --=20 2.43.0 From nobody Tue Feb 10 03:00:38 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C517D1EF0AB; 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charset="utf-8" From: Ryan Wanner Add sama7d65-pmc compatible string to the list of valid PMC IDs. Signed-off-by: Ryan Wanner --- drivers/power/reset/at91-sama5d2_shdwc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/power/reset/at91-sama5d2_shdwc.c b/drivers/power/reset= /at91-sama5d2_shdwc.c index edb0df86aff45..0cb7fe9f25a07 100644 --- a/drivers/power/reset/at91-sama5d2_shdwc.c +++ b/drivers/power/reset/at91-sama5d2_shdwc.c @@ -326,6 +326,7 @@ static const struct of_device_id at91_pmc_ids[] =3D { { .compatible =3D "atmel,sama5d2-pmc" }, { .compatible =3D "microchip,sam9x60-pmc" }, { .compatible =3D "microchip,sama7g5-pmc" }, + { .compatible =3D "microchip,sama7d65-pmc" }, { /* Sentinel. */ } }; =20 --=20 2.43.0 From nobody Tue Feb 10 03:00:38 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6D0021EF0BE; Thu, 30 Jan 2025 17:35:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738258556; cv=none; b=PEGvxFMEjfG9DDtKiXS0BNpdsYvrl0MKGARSAC0NA3qKXR7yAML/EUm0xjsUYeHccv+E8h8aW7ZIzDYMSEPLSD/K0sYXlgiNeV3JV6a5GA2PPMlVJLpbaHZ0f99XxVDv9xhbYHqejOXjhdPFGM7qYa6MK74GPB9HZi37TQNd3UI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738258556; c=relaxed/simple; bh=wan1Nd3Bl14Mogpslj9rCJupKOyLIC//emvKCJOzmww=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=BEVrlOkmrXZZKmO4Vy4oNkZL+Su32818nC20U+v3KS9Xltjvr17ECGeI0H9t50lJRN+Gi/Ct2fmiTvUDlxgF/LVMU+4DWgUotjLJj1j0mvPvPV6sztwo5z0HtIZ/aZpDl8GTAoEZ0RMVVlk9tQ72id6KfdfJuCf5oFbRGKCFmfc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=U4NkV5kv; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="U4NkV5kv" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1738258554; x=1769794554; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wan1Nd3Bl14Mogpslj9rCJupKOyLIC//emvKCJOzmww=; b=U4NkV5kv9LSmq5WpBSTHcnvP6yIQg556UtbVyUloZNX+C7hNwtXJmr6i Db8H1meqN4FsoSrlnfdtJRGDaaYg5WY7vyQE9poarVN319i3J/yPWBUm0 xLIxlPeahHHv/OSE/rmdnhNQfeLkp8O64UairTtEF/Hpo/xzulixjIi73 Tg/zje3y0c5A4Qm/7T9m1nS+4nrSQYnsnHTLyQbZbTpNLJ5MdgCeMtlsa LEkUFzUEmZh6vNmycYqxCe88Gkc32f9VM9Vgd1vlzTD2QySu2S38A8sSr 8kCIVtqDy8Ahoc+A3jGRuELdwniRh6lZcO42XvEjKVFtNG3D0F2KmlPyQ A==; X-CSE-ConnectionGUID: X8noN3xrSZmPEckyVo5bzw== X-CSE-MsgGUID: UJXhY5GLRvWt9YKMkDMqRA== X-IronPort-AV: E=Sophos;i="6.13,246,1732604400"; d="scan'208";a="204622974" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 30 Jan 2025 10:35:45 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 30 Jan 2025 10:35:42 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Thu, 30 Jan 2025 10:35:42 -0700 From: To: , , , , , , , , , CC: , , , , , Ryan Wanner Subject: [PATCH 15/16] ARM: dts: microchip: sama7d65: Add Reset and Shutdown and PM support Date: Thu, 30 Jan 2025 10:33:55 -0700 Message-ID: <4c7226eb6e70ebd8fcc3e1afd0dbdf3d5a16f2a6.1738257860.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Ryan Wanner Add support for reset controller, wake up alarm timers, and shutdown controller. Add SRAM, SFR, secumod, UDDRC, and DDR3phy to enable support for low power = modes. Signed-off-by: Ryan Wanner --- arch/arm/boot/dts/microchip/sama7d65.dtsi | 77 +++++++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/= microchip/sama7d65.dtsi index 854b30d15dcd4..8e117586e5902 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -46,12 +46,42 @@ slow_xtal: clock-slowxtal { }; }; =20 + ns_sram: sram@100000 { + compatible =3D "mmio-sram"; + #address-cells =3D <1>; + #size-cells =3D <1>; + reg =3D <0x100000 0x20000>; + ranges; + }; + soc { compatible =3D "simple-bus"; ranges; #address-cells =3D <1>; #size-cells =3D <1>; =20 + securam: sram@e0000800 { + compatible =3D "microchip,sama7d65-securam", "atmel,sama5d2-securam", "= mmio-sram"; + reg =3D <0xe0000800 0x4000>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 17>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0 0xe0000800 0x4000>; + no-memory-wc; + }; + + secumod: secumod@e0004000 { + compatible =3D "microchip,sama7d65-secumod", "atmel,sama5d2-secumod", "= syscon"; + reg =3D <0xe0004000 0x4000>; + gpio-controller; + #gpio-cells =3D <2>; + }; + + sfrbu: sfr@e0008000 { + compatible =3D"microchip,sama7d65-sfrbu", "atmel,sama5d2-sfrbu", "sysco= n"; + reg =3D <0xe0008000 0x20>; + }; + pioa: pinctrl@e0014000 { compatible =3D "microchip,sama7d65-pinctrl", "microchip,sama7g5-pinctrl= "; reg =3D <0xe0014000 0x800>; @@ -76,6 +106,31 @@ pmc: clock-controller@e0018000 { clock-names =3D "td_slck", "md_slck", "main_xtal"; }; =20 + reset_controller: reset-controller@e001d100 { + compatible =3D "microchip,sama7d65-rstc", "microchip,sama7g5-rstc"; + reg =3D <0xe001d100 0xc>, <0xe001d1e4 0x4>; + #reset-cells =3D <1>; + clocks =3D <&clk32k 0>; + }; + + shdwc: poweroff@e001d200 { + compatible =3D "microchip,sama7d65-shdwc", "microchip,sama7g5-shdwc", "= syscon"; + reg =3D <0xe001d200 0x20>; + clocks =3D <&clk32k 0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + atmel,wakeup-rtc-timer; + atmel,wakeup-rtt-timer; + status =3D "disabled"; + }; + + rtt: rtc@e001d300 { + compatible =3D "microchip,sama7d65-rtt", "microchip,sama7g5-rtt", "atme= l,at91sam9260-rtt"; + reg =3D <0xe001d300 0x30>; + interrupts =3D ; + clocks =3D <&clk32k 0>; + }; + clk32k: clock-controller@e001d500 { compatible =3D "microchip,sama7d65-sckc", "microchip,sam9x60-sckc"; reg =3D <0xe001d500 0x4>; @@ -83,6 +138,18 @@ clk32k: clock-controller@e001d500 { #clock-cells =3D <1>; }; =20 + gpbr: gpbr@e001d700 { + compatible =3D "microchip,sama7d65-gpbr", "syscon"; + reg =3D <0xe001d700 0x48>; + }; + + rtc: rtc@e001d800 { + compatible =3D "microchip,sama7d65-rtc", "microchip,sam9x60-rtc"; + reg =3D <0xe001d800 0x30>; + interrupts =3D ; + clocks =3D <&clk32k 1>; + }; + sdmmc1: mmc@e1208000 { compatible =3D "microchip,sama7d65-sdhci", "microchip,sam9x60-sdhci"; reg =3D <0xe1208000 0x400>; @@ -132,6 +199,16 @@ uart6: serial@200 { }; }; =20 + uddrc: uddrc@e3800000 { + compatible =3D "microchip,sama7d65-uddrc", "microchip,sama7g5-uddrc"; + reg =3D <0xe3800000 0x4000>; + }; + + ddr3phy: ddr3phy@e3804000 { + compatible =3D "microchip,sama7d65-ddr3phy", "microchip,sama7g5-ddr3phy= "; + reg =3D <0xe3804000 0x1000>; + }; + gic: interrupt-controller@e8c11000 { compatible =3D "arm,cortex-a7-gic"; reg =3D <0xe8c11000 0x1000>, --=20 2.43.0 From nobody Tue Feb 10 03:00:38 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 77EE51F03D0; Thu, 30 Jan 2025 17:35:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738258557; cv=none; b=Rg+gLaLODN+fIrJsFHDaCCsaiBgn2GKA7y8ySv2C7LW4QOCBd7RVf0Q52eMrTX93hEEKKsv0mIdr4u0k8EPgMKpKP56bn0Jm6S0g4TLixTFqttAMLiarkKdA23ANzrAJn3ziPg6EdrNc7VWkqgUBLdY5mvWsnHJmapoZoXuCb6E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738258557; c=relaxed/simple; bh=unETEqL21PPGjcJ+5ThZ5Xx9TlKma2kepF5jLOEMdPY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; 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Thu, 30 Jan 2025 10:35:42 -0700 From: To: , , , , , , , , , CC: , , , , , Ryan Wanner Subject: [PATCH 16/16] ARM: dts: microchip: add shutdown controller and rtt timer Date: Thu, 30 Jan 2025 10:33:56 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Ryan Wanner Add shutdown controller and rtt timer to support shutdown and wake up. Signed-off-by: Ryan Wanner --- .../boot/dts/microchip/at91-sama7d65_curiosity.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts b/arch= /arm/boot/dts/microchip/at91-sama7d65_curiosity.dts index 0f86360fb733a..d1d0b06fbfc43 100644 --- a/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts +++ b/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts @@ -77,6 +77,11 @@ pinctrl_uart6_default: uart6-default { }; }; =20 +&rtt { + atmel,rtt-rtc-time-reg =3D <&gpbr 0x0>; + status =3D "disabled"; +}; + &sdmmc1 { bus-width =3D <4>; pinctrl-names =3D "default"; @@ -84,6 +89,15 @@ &sdmmc1 { status =3D "okay"; }; =20 +&shdwc { + debounce-delay-us =3D <976>; + status =3D "okay"; + + input@0 { + reg =3D <0>; + }; +}; + &slow_xtal { clock-frequency =3D <32768>; }; --=20 2.43.0