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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Dec 2024 21:38:19.1807 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4d197d87-b8fe-4849-a6fb-08dd1fac4a0a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE37.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB7831 Content-Type: text/plain; charset="utf-8" Smart Data Cache Injection (SDCI) is a mechanism that enables direct insertion of data from I/O devices into the L3 cache. By directly caching data from I/O devices rather than first storing the I/O data in DRAM, SDCI reduces demands on DRAM bandwidth and reduces latency to the processor consuming the I/O data. The SDCIAE (SDCI Allocation Enforcement) PQE feature allows system software to control the portion of the L3 cache used for SDCI. When enabled, SDCIAE forces all SDCI lines to be placed into the L3 cache partitions identified by the highest-supported L3_MASK_n register, where n is the maximum supported CLOSID. Add CPUID feature bit that can be used to configure SDCIAE. The feature details are documented in APM listed below [1]. [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming Publication # 24593 Revision 3.41 section 19.4.7 L3 Smart Data Cache Injection Allocation Enforcement (SDCIAE) Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537 Signed-off-by: Babu Moger --- v2: Added dependancy on X86_FEATURE_CAT_L3 Removed the "" in CPU feature definition. Minor text changes. --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/cpuid-deps.c | 1 + arch/x86/kernel/cpu/scattered.c | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index 935d44cc4db8..57aa3c26fe4b 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -481,6 +481,7 @@ #define X86_FEATURE_AMD_FAST_CPPC (21*32 + 5) /* Fast CPPC */ #define X86_FEATURE_AMD_HETEROGENEOUS_CORES (21*32 + 6) /* Heterogeneous C= ore Topology */ #define X86_FEATURE_AMD_WORKLOAD_CLASS (21*32 + 7) /* Workload Classificat= ion */ +#define X86_FEATURE_SDCIAE (21*32 + 8) /* L3 Smart Data Cache Injection A= llocation Enforcement */ =20 /* * BUG word(s) diff --git a/arch/x86/kernel/cpu/cpuid-deps.c b/arch/x86/kernel/cpu/cpuid-d= eps.c index 8bd84114c2d9..8185521ce854 100644 --- a/arch/x86/kernel/cpu/cpuid-deps.c +++ b/arch/x86/kernel/cpu/cpuid-deps.c @@ -70,6 +70,7 @@ static const struct cpuid_dep cpuid_deps[] =3D { { X86_FEATURE_CQM_MBM_LOCAL, X86_FEATURE_CQM_LLC }, { X86_FEATURE_BMEC, X86_FEATURE_CQM_MBM_TOTAL }, { X86_FEATURE_BMEC, X86_FEATURE_CQM_MBM_LOCAL }, + { X86_FEATURE_SDCIAE, X86_FEATURE_CAT_L3 }, { X86_FEATURE_AVX512_BF16, X86_FEATURE_AVX512VL }, { X86_FEATURE_AVX512_FP16, X86_FEATURE_AVX512BW }, { X86_FEATURE_ENQCMD, X86_FEATURE_XSAVES }, diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattere= d.c index 16f3ca30626a..d18a7ce16388 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -49,6 +49,7 @@ static const struct cpuid_bit cpuid_bits[] =3D { { X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 }, { X86_FEATURE_SMBA, CPUID_EBX, 2, 0x80000020, 0 }, { X86_FEATURE_BMEC, CPUID_EBX, 3, 0x80000020, 0 }, + { X86_FEATURE_SDCIAE, CPUID_EBX, 6, 0x80000020, 0 }, { X86_FEATURE_AMD_WORKLOAD_CLASS, CPUID_EAX, 22, 0x80000021, 0 }, { X86_FEATURE_PERFMON_V2, CPUID_EAX, 0, 0x80000022, 0 }, { X86_FEATURE_AMD_LBR_V2, CPUID_EAX, 1, 0x80000022, 0 }, --=20 2.34.1 From nobody Thu Dec 18 20:25:30 2025 Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2049.outbound.protection.outlook.com [40.107.236.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 21FFB1991AA; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Dec 2024 21:38:26.8793 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d8e24bbd-18d1-400c-fae7-08dd1fac4e9e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE32.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW6PR12MB8736 Content-Type: text/plain; charset="utf-8" Add the command line options to enable or disable the new resctrl feature L3 Smart Data Cache Injection Allocation Enforcement (SDCIAE). Signed-off-by: Babu Moger --- v2: No changes. --- Documentation/admin-guide/kernel-parameters.txt | 2 +- arch/x86/kernel/cpu/resctrl/core.c | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentatio= n/admin-guide/kernel-parameters.txt index 7d427d0a4a1a..8e8efccc1d0a 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -5854,7 +5854,7 @@ rdt=3D [HW,X86,RDT] Turn on/off individual RDT features. List is: cmt, mbmtotal, mbmlocal, l3cat, l3cdp, l2cat, l2cdp, - mba, smba, bmec. + mba, smba, bmec, sdciae. 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Dec 2024 21:38:35.7367 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 858bf4d1-4cbc-48f8-e4af-08dd1fac53e8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE34.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4274 Content-Type: text/plain; charset="utf-8" Introduce io_alloc_capable in struct resctrl_cache to detect SDCIAE (L3 Smart Data Cache Injection Allocation Enforcement) feature. Signed-off-by: Babu Moger --- v2: Changed sdciae_capable to io_alloc_capable to make it generic feature. Also moved the io_alloc_capable in struct resctrl_cache. --- arch/x86/kernel/cpu/resctrl/core.c | 7 +++++++ include/linux/resctrl.h | 4 ++++ 2 files changed, 11 insertions(+) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index c2450cd52511..39e110033d96 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -306,6 +306,11 @@ static void rdt_get_cdp_config(int level) rdt_resources_all[level].r_resctrl.cdp_capable =3D true; } =20 +static void rdt_get_sdciae_alloc_cfg(struct rdt_resource *r) +{ + r->cache.io_alloc_capable =3D true; +} + static void rdt_get_cdp_l3_config(void) { rdt_get_cdp_config(RDT_RESOURCE_L3); @@ -931,6 +936,8 @@ static __init bool get_rdt_alloc_resources(void) rdt_get_cache_alloc_cfg(1, r); if (rdt_cpu_has(X86_FEATURE_CDP_L3)) rdt_get_cdp_l3_config(); + if (rdt_cpu_has(X86_FEATURE_SDCIAE)) + rdt_get_sdciae_alloc_cfg(r); ret =3D true; } if (rdt_cpu_has(X86_FEATURE_CAT_L2)) { diff --git a/include/linux/resctrl.h b/include/linux/resctrl.h index d94abba1c716..5837acff7442 100644 --- a/include/linux/resctrl.h +++ b/include/linux/resctrl.h @@ -129,6 +129,8 @@ struct rdt_mon_domain { * @arch_has_sparse_bitmasks: True if a bitmask like f00f is valid. * @arch_has_per_cpu_cfg: True if QOS_CFG register for this cache * level has CPU scope. + * @io_alloc_capable: Smart Data Cache Injection Allocation Enforcement + * capable (SDCIAE). */ struct resctrl_cache { unsigned int cbm_len; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Dec 2024 21:38:42.4306 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 560d2344-418b-49f6-9e98-08dd1fac57f4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE37.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5749 Content-Type: text/plain; charset="utf-8" Introduce architecture-specific2yy handlers to manage the detection and enabling/disabling of this feature. SDCIAE feature can be enabled by setting bit 1 in MSR L3_QOS_EXT_CFG. When the state of SDCIAE is modified, the updated value must be applied across all logical processors within the QOS Domain. By default, the io_alloc feature is turned off. The SDCIAE feature details are available in APM listed below [1]. [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming Publication # 24593 Revision 3.41 section 19.4.7 L3 Smart Data Cache Injection Allocation Enforcement (SDCIAE) Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537 Signed-off-by: Babu Moger --- v2: Renamed the functions to simplify the code. Renamed sdciae_capable to io_alloc_capable. Changed the name of few arch functions similar to ABMC series. resctrl_arch_get_io_alloc_enabled() resctrl_arch_io_alloc_enable() --- arch/x86/include/asm/msr-index.h | 1 + arch/x86/kernel/cpu/resctrl/internal.h | 10 ++++++++ arch/x86/kernel/cpu/resctrl/rdtgroup.c | 34 ++++++++++++++++++++++++++ include/linux/resctrl.h | 9 +++++++ 4 files changed, 54 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-in= dex.h index 3f3e2bc99162..360c52a62da9 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -1196,6 +1196,7 @@ /* - AMD: */ #define MSR_IA32_MBA_BW_BASE 0xc0000200 #define MSR_IA32_SMBA_BW_BASE 0xc0000280 +#define MSR_IA32_L3_QOS_EXT_CFG 0xc00003ff #define MSR_IA32_EVT_CFG_BASE 0xc0000400 =20 /* AMD-V MSRs */ diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index 20c898f09b7e..dff3354c2282 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -56,6 +56,9 @@ /* Max event bits supported */ #define MAX_EVT_CONFIG_BITS GENMASK(6, 0) =20 +/* Setting bit 1 in L3_QOS_EXT_CFG enables the SDCIAE feature. */ +#define SDCIAE_ENABLE_BIT 1 + /** * cpumask_any_housekeeping() - Choose any CPU in @mask, preferring those = that * aren't marked nohz_full @@ -479,6 +482,7 @@ struct rdt_parse_data { * @mbm_cfg_mask: Bandwidth sources that can be tracked when Bandwidth * Monitoring Event Configuration (BMEC) is supported. * @cdp_enabled: CDP state of this resource + * @sdciae_enabled: SDCIAE feature is enabled * * Members of this structure are either private to the architecture * e.g. mbm_width, or accessed via helpers that provide abstraction. e.g. @@ -493,6 +497,7 @@ struct rdt_hw_resource { unsigned int mbm_width; unsigned int mbm_cfg_mask; bool cdp_enabled; + bool sdciae_enabled; }; =20 static inline struct rdt_hw_resource *resctrl_to_arch_res(struct rdt_resou= rce *r) @@ -539,6 +544,11 @@ int resctrl_arch_set_cdp_enabled(enum resctrl_res_leve= l l, bool enable); =20 void arch_mon_domain_online(struct rdt_resource *r, struct rdt_mon_domain = *d); =20 +static inline bool resctrl_arch_get_io_alloc_enabled(enum resctrl_res_leve= l l) +{ + return rdt_resources_all[l].sdciae_enabled; +} + /* * To return the common struct rdt_resource, which is contained in struct * rdt_hw_resource, walk the resctrl member of struct rdt_hw_resource. diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 6419e04d8a7b..398f241b65d5 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1798,6 +1798,40 @@ static ssize_t mbm_local_bytes_config_write(struct k= ernfs_open_file *of, return ret ?: nbytes; } =20 +static void resctrl_sdciae_set_one_amd(void *arg) +{ + bool *enable =3D arg; + + if (*enable) + msr_set_bit(MSR_IA32_L3_QOS_EXT_CFG, SDCIAE_ENABLE_BIT); + else + msr_clear_bit(MSR_IA32_L3_QOS_EXT_CFG, SDCIAE_ENABLE_BIT); +} + +static int _resctrl_io_alloc_enable(struct rdt_resource *r, bool enable) +{ + struct rdt_ctrl_domain *d; + + /* Update L3_QOS_EXT_CFG MSR on all the CPUs in all domains*/ + list_for_each_entry(d, &r->ctrl_domains, hdr.list) + on_each_cpu_mask(&d->hdr.cpu_mask, resctrl_sdciae_set_one_amd, &enable, = 1); + + return 0; +} + +int resctrl_arch_io_alloc_enable(struct rdt_resource *r, bool enable) +{ + struct rdt_hw_resource *hw_res =3D resctrl_to_arch_res(r); + + if (hw_res->r_resctrl.cache.io_alloc_capable && + hw_res->sdciae_enabled !=3D enable) { + _resctrl_io_alloc_enable(r, enable); + hw_res->sdciae_enabled =3D enable; + } + + return 0; +} + /* rdtgroup information files for one cache resource. */ static struct rftype res_common_files[] =3D { { diff --git a/include/linux/resctrl.h b/include/linux/resctrl.h index 5837acff7442..8c66aeac4768 100644 --- a/include/linux/resctrl.h +++ b/include/linux/resctrl.h @@ -344,6 +344,15 @@ void resctrl_arch_reset_rmid(struct rdt_resource *r, s= truct rdt_mon_domain *d, */ void resctrl_arch_reset_rmid_all(struct rdt_resource *r, struct rdt_mon_do= main *d); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Dec 2024 21:38:50.2220 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fab48523-c913-4568-cb3d-08dd1fac5c88 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE31.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7357 Content-Type: text/plain; charset="utf-8" The io_alloc feature in resctrl enables system software to configure the portion of the L3 cache allocated for I/O traffic. Smart Data Cache Injection (SDCI) is a mechanism that allows direct insertion of data from I/O devices into the L3 cache. By caching I/O data directly in the L3 cache, instead of writing it to DRAM first, SDCI reduces DRAM bandwidth usage and lowers latency for the processor consuming the I/O data. When enabled, SDCIAE forces all SDCI lines to be placed into the L3 cache partitions identified by the highest-supported L3_MASK_n register as reported by CPUID Fn0000_0010_EDX_x1.MAX_COS. For example, if MAX_COS=3D15, SDCI lines will be allocated into the L3 cache partitions determined by the bitmask in the L3_MASK_15 register. Introduce interface to enable/disable "io_alloc" feature on user input. Signed-off-by: Babu Moger --- v2: Renamed the feature to "io_alloc". Added generic texts for the feature in commit log and resctrl.rst doc. Added resctrl_io_alloc_init_cat() to initialize io_alloc to default values when enabled. Fixed io_alloc show functinality to display only on L3 resource. --- Documentation/arch/x86/resctrl.rst | 27 ++++++ arch/x86/kernel/cpu/resctrl/core.c | 2 + arch/x86/kernel/cpu/resctrl/rdtgroup.c | 118 +++++++++++++++++++++++++ 3 files changed, 147 insertions(+) diff --git a/Documentation/arch/x86/resctrl.rst b/Documentation/arch/x86/re= sctrl.rst index 6768fc1fad16..52679175ee14 100644 --- a/Documentation/arch/x86/resctrl.rst +++ b/Documentation/arch/x86/resctrl.rst @@ -135,6 +135,33 @@ related to allocation: "1": Non-contiguous 1s value in CBM is supported. =20 +"io_alloc": + The "io_alloc" feature in resctrl enables system software to + configure the portion of the L3 cache allocated for I/O traffic. + + Smart Data Cache Injection (SDCI) is a mechanism that allows + direct insertion of data from I/O devices into the L3 cache. + By caching I/O data directly in the L3 cache, instead of writing + it to DRAM first, SDCI reduces DRAM bandwidth usage and lowers + latency for the processor consuming the I/O data. + + When enabled the feature forces all SDCI lines to be placed + into the L3 cache partitions identified by the highest-supported + CLOSID (num_closids-1). This CLOSID will not be available to the + resctrl group. + + "0": + I/O device L3 cache control is not enabled. + "1": + I/O device L3 cache control is enabled, allowing users + to manage the portions of the L3 cache allocated for + the I/O device. + + Feature can be enabled/disabled by writing to the interface. + Example:: + + # echo 1 > /sys/fs/resctrl/info/L3/io_alloc + Memory bandwidth(MB) subdirectory contains the following files with respect to allocation: =20 diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index 39e110033d96..066a7997eaf1 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -309,6 +309,8 @@ static void rdt_get_cdp_config(int level) static void rdt_get_sdciae_alloc_cfg(struct rdt_resource *r) { r->cache.io_alloc_capable =3D true; + resctrl_file_fflags_init("io_alloc", + RFTYPE_CTRL_INFO | RFTYPE_RES_CACHE); } =20 static void rdt_get_cdp_l3_config(void) diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 398f241b65d5..e30731ce9335 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -62,6 +62,7 @@ static char last_cmd_status_buf[512]; =20 static int rdtgroup_setup_root(struct rdt_fs_context *ctx); static void rdtgroup_destroy_root(void); +static int rdtgroup_init_cat(struct resctrl_schema *s, u32 closid); =20 struct dentry *debugfs_resctrl; =20 @@ -180,6 +181,25 @@ void closid_free(int closid) __set_bit(closid, &closid_free_map); } =20 +/* + * io_alloc (SDCIAE) feature uses max CLOSID to route the SDCI traffic. + * Get the max CLOSID number + */ +static u32 resctrl_io_alloc_closid_get(struct rdt_resource *r) +{ + return resctrl_arch_get_num_closid(r) - 1; +} + +static int resctrl_io_alloc_closid_alloc(struct rdt_resource *r) +{ + u32 io_alloc_closid =3D resctrl_io_alloc_closid_get(r); + + if (__test_and_clear_bit(io_alloc_closid, &closid_free_map)) + return io_alloc_closid; + else + return -ENOSPC; +} + /** * closid_allocated - test if provided closid is in use * @closid: closid to be tested @@ -1832,6 +1852,97 @@ int resctrl_arch_io_alloc_enable(struct rdt_resource= *r, bool enable) return 0; } =20 +static int resctrl_io_alloc_show(struct kernfs_open_file *of, + struct seq_file *seq, void *v) +{ + struct resctrl_schema *s =3D of->kn->parent->priv; + struct rdt_resource *r =3D s->res; + + seq_printf(seq, "%x\n", resctrl_arch_get_io_alloc_enabled(r->rid)); + return 0; +} + +/* + * Initialize the io_alloc feature default when enabled + */ +static int resctrl_io_alloc_init_cat(struct rdt_resource *r, u32 closid) +{ + struct resctrl_schema *s; + int ret =3D 0; + + rdt_staged_configs_clear(); + + list_for_each_entry(s, &resctrl_schema_all, list) { + r =3D s->res; + if (r->rid =3D=3D RDT_RESOURCE_L3) { + ret =3D rdtgroup_init_cat(s, closid); + if (ret < 0) + goto out_init_cat; + + ret =3D resctrl_arch_update_domains(r, closid); + if (ret < 0) + goto out_init_cat; + } + } + +out_init_cat: + if (ret) + rdt_last_cmd_puts("Failed to initialize io_alloc allocations\n"); + + rdt_staged_configs_clear(); + return ret; +} + +static ssize_t resctrl_io_alloc_write(struct kernfs_open_file *of, char *b= uf, + size_t nbytes, loff_t off) +{ + struct resctrl_schema *s =3D of->kn->parent->priv; + struct rdt_resource *r =3D s->res; + u32 io_alloc_closid; + bool enable; + int ret; + + if (!r->cache.io_alloc_capable) + return -EINVAL; + + ret =3D kstrtobool(buf, &enable); + if (ret) + return ret; + + cpus_read_lock(); + mutex_lock(&rdtgroup_mutex); + + rdt_last_cmd_clear(); + + io_alloc_closid =3D resctrl_io_alloc_closid_get(r); + + if (resctrl_arch_get_io_alloc_enabled(r->rid) !=3D enable) { + if (enable) { + ret =3D resctrl_io_alloc_closid_alloc(r); + if (ret < 0) { + rdt_last_cmd_puts("io_alloc CLOSID is not available\n"); + goto out_io_alloc; + } + ret =3D resctrl_io_alloc_init_cat(r, io_alloc_closid); + if (ret) { + closid_free(io_alloc_closid); + goto out_io_alloc; + } + + } else { + closid_free(io_alloc_closid); + } + + ret =3D resctrl_arch_io_alloc_enable(r, enable); + } + +out_io_alloc: + mutex_unlock(&rdtgroup_mutex); + cpus_read_unlock(); + + return ret ?: nbytes; +} + /* rdtgroup information files for one cache resource. */ static struct rftype res_common_files[] =3D { { @@ -1984,6 +2095,13 @@ static struct rftype res_common_files[] =3D { .seq_show =3D rdtgroup_schemata_show, .fflags =3D RFTYPE_CTRL_BASE, }, + { + .name =3D "io_alloc", + .mode =3D 0644, + .kf_ops =3D &rdtgroup_kf_single_ops, + .seq_show =3D resctrl_io_alloc_show, + .write =3D resctrl_io_alloc_write, + }, { .name =3D "mba_MBps_event", .mode =3D 0644, --=20 2.34.1 From nobody Thu Dec 18 20:25:30 2025 Received: from NAM02-SN1-obe.outbound.protection.outlook.com (mail-sn1nam02on2056.outbound.protection.outlook.com [40.107.96.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DE17C1FC7DF; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Dec 2024 21:38:57.6990 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fa407b26-9be3-4fde-4f37-08dd1fac60fb X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE36.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7137 Content-Type: text/plain; charset="utf-8" The io_alloc feature in resctrl enables system software to configure the portion of the L3 cache allocated for I/O traffic. Add the interface to display CBMs (Capacity Bit Mask) of io_alloc feature. Signed-off-by: Babu Moger --- v2: Fixed to display only on L3 resources. Added the locks while processing. Rename the displat to io_alloc_cbm (from sdciae_cmd). --- arch/x86/kernel/cpu/resctrl/core.c | 2 ++ arch/x86/kernel/cpu/resctrl/ctrlmondata.c | 2 +- arch/x86/kernel/cpu/resctrl/internal.h | 1 + arch/x86/kernel/cpu/resctrl/rdtgroup.c | 33 +++++++++++++++++++++++ 4 files changed, 37 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index 066a7997eaf1..f1ac7af7b366 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -311,6 +311,8 @@ static void rdt_get_sdciae_alloc_cfg(struct rdt_resourc= e *r) r->cache.io_alloc_capable =3D true; resctrl_file_fflags_init("io_alloc", RFTYPE_CTRL_INFO | RFTYPE_RES_CACHE); + resctrl_file_fflags_init("io_alloc_cbm", + RFTYPE_CTRL_INFO | RFTYPE_RES_CACHE); } =20 static void rdt_get_cdp_l3_config(void) diff --git a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c b/arch/x86/kernel/cp= u/resctrl/ctrlmondata.c index 536351159cc2..d272dea43924 100644 --- a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c +++ b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c @@ -444,7 +444,7 @@ u32 resctrl_arch_get_config(struct rdt_resource *r, str= uct rdt_ctrl_domain *d, return hw_dom->ctrl_val[idx]; } =20 -static void show_doms(struct seq_file *s, struct resctrl_schema *schema, i= nt closid) +void show_doms(struct seq_file *s, struct resctrl_schema *schema, int clos= id) { struct rdt_resource *r =3D schema->res; struct rdt_ctrl_domain *dom; diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index dff3354c2282..1550cb468b8e 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -668,4 +668,5 @@ void resctrl_file_fflags_init(const char *config, unsig= ned long fflags); void rdt_staged_configs_clear(void); bool closid_allocated(unsigned int closid); int resctrl_find_cleanest_closid(void); +void show_doms(struct seq_file *s, struct resctrl_schema *schema, int clos= id); #endif /* _ASM_X86_RESCTRL_INTERNAL_H */ diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index e30731ce9335..4d6b83d18790 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1943,6 +1943,33 @@ static ssize_t resctrl_io_alloc_write(struct kernfs_= open_file *of, char *buf, return ret ?: nbytes; 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Wed, 18 Dec 2024 15:39:03 -0600 From: Babu Moger To: , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v2 7/7] x86/resctrl: Introduce interface to modify io_alloc Capacity Bit Masks Date: Wed, 18 Dec 2024 15:38:03 -0600 Message-ID: <2bb9ce3e4ac57c6709f1cd37d8571373c6e3c024.1734556832.git.babu.moger@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE37:EE_|DS0PR12MB7772:EE_ X-MS-Office365-Filtering-Correlation-Id: b2d69d2e-9933-41e3-915a-08dd1fac65fd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|7416014|376014|36860700013; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Dec 2024 21:39:06.0868 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b2d69d2e-9933-41e3-915a-08dd1fac65fd X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE37.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7772 Content-Type: text/plain; charset="utf-8" "io_alloc" feature is a mechanism that enables direct insertion of data from I/O devices into the L3 cache. By directly caching data from I/O devices rather than first storing the I/O data in DRAM, SDCI reduces demands on DRAM bandwidth and reduces latency to the processor consuming the I/O data. The SDCIAE (SDCI Allocation Enforcement) PQE feature allows system software to limit the portion of the L3 cache used for SDCI. Provide the interface to modify io_alloc CBMs (Capacity Bit Masks). Signed-off-by: Babu Moger --- v2: Added more generic text in documentation. --- Documentation/arch/x86/resctrl.rst | 8 ++ arch/x86/kernel/cpu/resctrl/ctrlmondata.c | 2 +- arch/x86/kernel/cpu/resctrl/internal.h | 1 + arch/x86/kernel/cpu/resctrl/rdtgroup.c | 128 +++++++++++++++++++++- 4 files changed, 137 insertions(+), 2 deletions(-) diff --git a/Documentation/arch/x86/resctrl.rst b/Documentation/arch/x86/re= sctrl.rst index 52679175ee14..da74356adcc2 100644 --- a/Documentation/arch/x86/resctrl.rst +++ b/Documentation/arch/x86/resctrl.rst @@ -162,6 +162,14 @@ related to allocation: =20 # echo 1 > /sys/fs/resctrl/info/L3/io_alloc =20 +"io_alloc_cbm": + Capacity Bit Masks (CBMs) available to supported IO devices which + can directly insert cache lines in L3 which can help to reduce the + latency. CBM can be configured by writing to the interface in the + following format:: + + L3:=3D;=3D;... + Memory bandwidth(MB) subdirectory contains the following files with respect to allocation: =20 diff --git a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c b/arch/x86/kernel/cp= u/resctrl/ctrlmondata.c index d272dea43924..4dfee0436c1c 100644 --- a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c +++ b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c @@ -102,7 +102,7 @@ int parse_bw(struct rdt_parse_data *data, struct resctr= l_schema *s, * requires at least two bits set. * AMD allows non-contiguous bitmasks. */ -static bool cbm_validate(char *buf, u32 *data, struct rdt_resource *r) +bool cbm_validate(char *buf, u32 *data, struct rdt_resource *r) { unsigned long first_bit, zero_bit, val; unsigned int cbm_len =3D r->cache.cbm_len; diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index 1550cb468b8e..5f7236437cb5 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -669,4 +669,5 @@ void rdt_staged_configs_clear(void); bool closid_allocated(unsigned int closid); int resctrl_find_cleanest_closid(void); void show_doms(struct seq_file *s, struct resctrl_schema *schema, int clos= id); +bool cbm_validate(char *buf, u32 *data, struct rdt_resource *r); #endif /* _ASM_X86_RESCTRL_INTERNAL_H */ diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 4d6b83d18790..c2b4221ea469 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1970,6 +1970,131 @@ static int resctrl_io_alloc_cbm_show(struct kernfs_= open_file *of, return ret; } =20 +/* + * Read the CBM and check the validity. Make sure CBM is not shared + * with any other exclusive resctrl groups. + */ +static int resctrl_io_alloc_parse_cbm(char *buf, struct resctrl_schema *s, + struct rdt_ctrl_domain *d) +{ + struct resctrl_staged_config *cfg; + struct rdt_resource *r =3D s->res; + u32 io_alloc_closid; + u32 cbm_val; + + cfg =3D &d->staged_config[s->conf_type]; + if (cfg->have_new_ctrl) { + rdt_last_cmd_printf("Duplicate domain %d\n", d->hdr.id); + return -EINVAL; + } + + if (!cbm_validate(buf, &cbm_val, r)) + return -EINVAL; + + /* + * The CBM may not overlap with other exclusive group. + */ + io_alloc_closid =3D resctrl_io_alloc_closid_get(r); + if (rdtgroup_cbm_overlaps(s, d, cbm_val, io_alloc_closid, true)) { + rdt_last_cmd_puts("Overlaps with exclusive group\n"); + return -EINVAL; + } + + cfg->new_ctrl =3D cbm_val; + cfg->have_new_ctrl =3D true; + + return 0; +} + +static int resctrl_io_alloc_parse_line(char *line, struct rdt_resource *r, + struct resctrl_schema *s) +{ + struct rdt_ctrl_domain *d; + char *dom =3D NULL, *id; + unsigned long dom_id; + +next: + if (!line || line[0] =3D=3D '\0') + return 0; + + dom =3D strsep(&line, ";"); + id =3D strsep(&dom, "=3D"); + if (!dom || kstrtoul(id, 10, &dom_id)) { + rdt_last_cmd_puts("Missing '=3D' or non-numeric domain\n"); + return -EINVAL; + } + + dom =3D strim(dom); + list_for_each_entry(d, &r->ctrl_domains, hdr.list) { + if (d->hdr.id =3D=3D dom_id) { + if (resctrl_io_alloc_parse_cbm(dom, s, d)) + return -EINVAL; + goto next; + } + } + return -EINVAL; +} + +static ssize_t resctrl_io_alloc_cbm_write(struct kernfs_open_file *of, + char *buf, size_t nbytes, loff_t off) +{ + struct resctrl_schema *s =3D of->kn->parent->priv; + struct rdt_resource *r =3D s->res; + u32 io_alloc_closid; + char *resname; + int ret =3D 0; + + /* Valid input requires a trailing newline */ + if (nbytes =3D=3D 0 || buf[nbytes - 1] !=3D '\n') + return -EINVAL; + + buf[nbytes - 1] =3D '\0'; + + cpus_read_lock(); + mutex_lock(&rdtgroup_mutex); + + rdt_last_cmd_clear(); + rdt_staged_configs_clear(); + + if (!resctrl_arch_get_io_alloc_enabled(r->rid)) { + rdt_last_cmd_puts("io_alloc feature is not enabled\n"); + ret =3D -EINVAL; + goto cbm_write_out; + } + + resname =3D strim(strsep(&buf, ":")); + if (!buf) { + rdt_last_cmd_puts("Missing ':'\n"); + ret =3D -EINVAL; + goto cbm_write_out; + } + + if (strcmp(resname, "L3")) { + rdt_last_cmd_printf("Unsupported resource name '%s'\n", resname); + ret =3D -EINVAL; + goto cbm_write_out; + } + + if (buf[0] =3D=3D '\0') { + rdt_last_cmd_printf("Missing '%s' value\n", resname); + ret =3D -EINVAL; + goto cbm_write_out; + } + + ret =3D resctrl_io_alloc_parse_line(buf, r, s); + if (ret) + goto cbm_write_out; + + io_alloc_closid =3D resctrl_io_alloc_closid_get(r); + ret =3D resctrl_arch_update_domains(r, io_alloc_closid); + +cbm_write_out: + mutex_unlock(&rdtgroup_mutex); + cpus_read_unlock(); + + return ret ?: nbytes; +} + /* rdtgroup information files for one cache resource. */ static struct rftype res_common_files[] =3D { { @@ -2131,9 +2256,10 @@ static struct rftype res_common_files[] =3D { }, { .name =3D "io_alloc_cbm", - .mode =3D 0444, + .mode =3D 0644, .kf_ops =3D &rdtgroup_kf_single_ops, .seq_show =3D resctrl_io_alloc_cbm_show, + .write =3D resctrl_io_alloc_cbm_write, }, { .name =3D "mba_MBps_event", --=20 2.34.1