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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Dec 2024 20:16:14.4486 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 686963bc-05b7-4724-fb53-08dd1ae9d420 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B075.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4433 Content-Type: text/plain; charset="utf-8" resctrl_late_init() has the __init attribute, but some of the functions called from it do not have the __init attribute. Add the __init attribute to all the functions in the call sequences to maintain consistency throughout. Fixes: 6a445edce657 ("x86/intel_rdt/cqm: Add RDT monitoring initialization") Fixes: def10853930a ("x86/intel_rdt: Add two new resources for L2 Code and = Data Prioritization (CDP)") Fixes: bd334c86b5d7 ("x86/resctrl: Add __init attribute to rdt_get_mon_l3_c= onfig()") Suggested-by: Reinette Chatre Signed-off-by: Babu Moger --- v10: Text changes. Added __init attribute to cache_alloc_hsw_probe() Followed function prototype rules (preferred order is storage class before return type). v9: Moved the patch to the begining of the series. Fixed all the call sequences. Added additional Fixed tags. v8: New patch. --- arch/x86/kernel/cpu/resctrl/core.c | 10 +++++----- arch/x86/kernel/cpu/resctrl/internal.h | 2 +- arch/x86/kernel/cpu/resctrl/monitor.c | 4 ++-- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index b681c2e07dbf..62f2c5bbe2c6 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -145,7 +145,7 @@ u32 resctrl_arch_system_num_rmid_idx(void) * is always 20 on hsw server parts. The minimum cache bitmask length * allowed for HSW server is always 2 bits. Hardcode all of them. */ -static inline void cache_alloc_hsw_probe(void) +static inline __init void cache_alloc_hsw_probe(void) { struct rdt_hw_resource *hw_res =3D &rdt_resources_all[RDT_RESOURCE_L3]; struct rdt_resource *r =3D &hw_res->r_resctrl; @@ -275,7 +275,7 @@ static __init bool __rdt_get_mem_config_amd(struct rdt_= resource *r) return true; } =20 -static void rdt_get_cache_alloc_cfg(int idx, struct rdt_resource *r) +static __init void rdt_get_cache_alloc_cfg(int idx, struct rdt_resource *r) { struct rdt_hw_resource *hw_res =3D resctrl_to_arch_res(r); union cpuid_0x10_1_eax eax; @@ -294,7 +294,7 @@ static void rdt_get_cache_alloc_cfg(int idx, struct rdt= _resource *r) r->alloc_capable =3D true; } =20 -static void rdt_get_cdp_config(int level) +static __init void rdt_get_cdp_config(int level) { /* * By default, CDP is disabled. CDP can be enabled by mount parameter @@ -304,12 +304,12 @@ static void rdt_get_cdp_config(int level) rdt_resources_all[level].r_resctrl.cdp_capable =3D true; } =20 -static void rdt_get_cdp_l3_config(void) +static __init void rdt_get_cdp_l3_config(void) { rdt_get_cdp_config(RDT_RESOURCE_L3); } =20 -static void rdt_get_cdp_l2_config(void) +static __init void rdt_get_cdp_l2_config(void) { rdt_get_cdp_config(RDT_RESOURCE_L2); } diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index 955999aecfca..16181b90159a 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -627,7 +627,7 @@ int closids_supported(void); void closid_free(int closid); int alloc_rmid(u32 closid); void free_rmid(u32 closid, u32 rmid); -int rdt_get_mon_l3_config(struct rdt_resource *r); +int __init rdt_get_mon_l3_config(struct rdt_resource *r); void __exit rdt_put_mon_l3_config(void); bool __init rdt_cpu_has(int flag); void mon_event_count(void *info); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Dec 2024 20:16:22.2628 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0ba41eaf-c029-4523-b80b-08dd1ae9d8cb X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B076.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB9173 Content-Type: text/plain; charset="utf-8" Users can create as many monitor groups as RMIDs supported by the hardware. However, bandwidth monitoring feature on AMD system only guarantees that RMIDs currently assigned to a processor will be tracked by hardware. The counters of any other RMIDs which are no longer being tracked will be reset to zero. The MBM event counters return "Unavailable" for the RMIDs that are not tracked by hardware. So, there can be only limited number of groups that can give guaranteed monitoring numbers. With ever changing configurations there is no way to definitely know which of these groups are being tracked for certain point of time. Users do not have the option to monitor a group or set of groups for certain period of time without worrying about RMID being reset in between. The ABMC feature provides an option to the user to assign a hardware counter to an RMID, event pair and monitor the bandwidth as long as it is assigned. The assigned RMID will be tracked by the hardware until the user unassigns it manually. There is no need to worry about counters being reset during this period. Additionally, the user can specify a bitmask identifying the specific bandwidth types from the given source to track with the counter. Without ABMC enabled, monitoring will work in current mode without assignment option. Linux resctrl subsystem provides the interface to count maximum of two memory bandwidth events per group, from a combination of available total and local events. Keeping the current interface, users can enable a maximum of 2 ABMC counters per group. User will also have the option to enable only one counter to the group. If the system runs out of assignable ABMC counters, kernel will display an error. Users need to disable an already enabled counter to make space for new assignments. The feature can be detected via CPUID_Fn80000020_EBX_x00 bit 5. Bits Description 5 ABMC (Assignable Bandwidth Monitoring Counters) The feature details are documented in APM listed below [1]. [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming Publication # 24593 Revision 3.41 section 19.3.3.3 Assignable Bandwidth Monitoring (ABMC). Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537 Signed-off-by: Babu Moger Reviewed-by: Reinette Chatre --- Note: Checkpatch checks/warnings are ignored to maintain coding style. v10: No changes. v9: Took care of couple of minor merge conflicts. No other changes. v8: No changes. v7: Removed "" from feature flags. Not required anymore. https://lore.kernel.org/lkml/20240817145058.GCZsC40neU4wkPXeVR@fat_crat= e.local/ v6: Added Reinette's Reviewed-by. Moved the Checkpatch note below ---. v5: Minor rebase change and subject line update. v4: Changes because of rebase. Feature word 21 has few more additions now. Changed the text to "tracked by hardware" instead of active. v3: Change because of rebase. Actual patch did not change. v2: Added dependency on X86_FEATURE_BMEC. --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/cpuid-deps.c | 3 +++ arch/x86/kernel/cpu/scattered.c | 1 + 3 files changed, 5 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index f725ccc77b01..662c334662ba 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -479,6 +479,7 @@ #define X86_FEATURE_AMD_FAST_CPPC (21*32 + 5) /* Fast CPPC */ #define X86_FEATURE_AMD_HETEROGENEOUS_CORES (21*32 + 6) /* Heterogeneous C= ore Topology */ #define X86_FEATURE_AMD_WORKLOAD_CLASS (21*32 + 7) /* Workload Classificat= ion */ +#define X86_FEATURE_ABMC (21*32 + 8) /* Assignable Bandwidth Monitoring C= ounters */ =20 /* * BUG word(s) diff --git a/arch/x86/kernel/cpu/cpuid-deps.c b/arch/x86/kernel/cpu/cpuid-d= eps.c index 8bd84114c2d9..7e4d63b381d6 100644 --- a/arch/x86/kernel/cpu/cpuid-deps.c +++ b/arch/x86/kernel/cpu/cpuid-deps.c @@ -70,6 +70,9 @@ static const struct cpuid_dep cpuid_deps[] =3D { { X86_FEATURE_CQM_MBM_LOCAL, X86_FEATURE_CQM_LLC }, { X86_FEATURE_BMEC, X86_FEATURE_CQM_MBM_TOTAL }, { X86_FEATURE_BMEC, X86_FEATURE_CQM_MBM_LOCAL }, + { X86_FEATURE_ABMC, X86_FEATURE_CQM_MBM_TOTAL }, + { X86_FEATURE_ABMC, X86_FEATURE_CQM_MBM_LOCAL }, + { X86_FEATURE_ABMC, X86_FEATURE_BMEC }, { X86_FEATURE_AVX512_BF16, X86_FEATURE_AVX512VL }, { X86_FEATURE_AVX512_FP16, X86_FEATURE_AVX512BW }, { X86_FEATURE_ENQCMD, X86_FEATURE_XSAVES }, diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattere= d.c index 16f3ca30626a..3b72b72270f1 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -49,6 +49,7 @@ static const struct cpuid_bit cpuid_bits[] =3D { { X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 }, { X86_FEATURE_SMBA, CPUID_EBX, 2, 0x80000020, 0 }, { X86_FEATURE_BMEC, CPUID_EBX, 3, 0x80000020, 0 }, + { X86_FEATURE_ABMC, CPUID_EBX, 5, 0x80000020, 0 }, { X86_FEATURE_AMD_WORKLOAD_CLASS, CPUID_EAX, 22, 0x80000021, 0 }, { X86_FEATURE_PERFMON_V2, CPUID_EAX, 0, 0x80000022, 0 }, { X86_FEATURE_AMD_LBR_V2, CPUID_EAX, 1, 0x80000022, 0 }, --=20 2.34.1 From nobody Sun Dec 14 19:11:44 2025 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2066.outbound.protection.outlook.com [40.107.93.66]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 068BE1B395E; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Dec 2024 20:16:30.0213 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f2824fd5-de92-4665-901a-08dd1ae9dd6b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B074.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9027 Content-Type: text/plain; charset="utf-8" Add the command line option to enable or disable exposing the ABMC (Assignable Bandwidth Monitoring Counters) hardware feature to resctrl. Signed-off-by: Babu Moger Reviewed-by: Reinette Chatre --- v10: No changes. v9: No code changes. Added Reviewed-by. v8: Commit message update. v7: No changes v6: No changes v5: No changes v4: No changes v3: No changes v2: No changes --- Documentation/admin-guide/kernel-parameters.txt | 2 +- Documentation/arch/x86/resctrl.rst | 1 + arch/x86/kernel/cpu/resctrl/core.c | 2 ++ 3 files changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentatio= n/admin-guide/kernel-parameters.txt index 7d427d0a4a1a..f22d367290aa 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -5854,7 +5854,7 @@ rdt=3D [HW,X86,RDT] Turn on/off individual RDT features. List is: cmt, mbmtotal, mbmlocal, l3cat, l3cdp, l2cat, l2cdp, - mba, smba, bmec. + mba, smba, bmec, abmc. E.g. to turn on cmt and turn off mba use: rdt=3Dcmt,!mba =20 diff --git a/Documentation/arch/x86/resctrl.rst b/Documentation/arch/x86/re= sctrl.rst index a824affd741d..30586728a4cd 100644 --- a/Documentation/arch/x86/resctrl.rst +++ b/Documentation/arch/x86/resctrl.rst @@ -26,6 +26,7 @@ MBM (Memory Bandwidth Monitoring) "cqm_mbm_total", "cqm_= mbm_local" MBA (Memory Bandwidth Allocation) "mba" SMBA (Slow Memory Bandwidth Allocation) "" BMEC (Bandwidth Monitoring Event Configuration) "" +ABMC (Assignable Bandwidth Monitoring Counters) "" =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D =20 Historically, new features were made visible by default in /proc/cpuinfo. = This diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index 62f2c5bbe2c6..b3861f0e5857 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -809,6 +809,7 @@ enum { RDT_FLAG_MBA, RDT_FLAG_SMBA, RDT_FLAG_BMEC, + RDT_FLAG_ABMC, }; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Dec 2024 20:16:37.8748 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1d4b0982-1271-4c57-8854-08dd1ae9e217 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B073.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6180 Content-Type: text/plain; charset="utf-8" The cache allocation and memory bandwidth allocation feature properties are consolidated into struct resctrl_cache and struct resctrl_membw respectively. In preparation for more monitoring properties that will clobber the existing resource struct more, re-organize the monitoring specific properties to also be in a separate structure. Suggested-by: Reinette Chatre Signed-off-by: Babu Moger Reviewed-by: Reinette Chatre --- v10: No changes. v9: No changes. v8: Added Reviewed-by from Reinette. No other changes. v7: Added kernel doc for data structure. Minor text update. v6: Update commit message and update kernel doc for rdt_resource. v5: Commit message update. Also changes related to data structure updates does to SNC support. v4: New patch. --- arch/x86/kernel/cpu/resctrl/core.c | 4 ++-- arch/x86/kernel/cpu/resctrl/monitor.c | 18 +++++++++--------- arch/x86/kernel/cpu/resctrl/rdtgroup.c | 8 ++++---- include/linux/resctrl.h | 16 ++++++++++++---- 4 files changed, 27 insertions(+), 19 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index b3861f0e5857..ff4dc649e35c 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -124,7 +124,7 @@ u32 resctrl_arch_system_num_rmid_idx(void) struct rdt_resource *r =3D &rdt_resources_all[RDT_RESOURCE_L3].r_resctrl; =20 /* RMID are independent numbers for x86. num_rmid_idx =3D=3D num_rmid */ - return r->num_rmid; + return r->mon.num_rmid; } =20 /* @@ -625,7 +625,7 @@ static void domain_add_cpu_mon(int cpu, struct rdt_reso= urce *r) =20 arch_mon_domain_online(r, d); =20 - if (arch_domain_mbm_alloc(r->num_rmid, hw_dom)) { + if (arch_domain_mbm_alloc(r->mon.num_rmid, hw_dom)) { mon_domain_free(hw_dom); return; } diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/re= sctrl/monitor.c index daf2e8c03d86..ec2a237321dc 100644 --- a/arch/x86/kernel/cpu/resctrl/monitor.c +++ b/arch/x86/kernel/cpu/resctrl/monitor.c @@ -222,7 +222,7 @@ static int logical_rmid_to_physical_rmid(int cpu, int l= rmid) if (snc_nodes_per_l3_cache =3D=3D 1) return lrmid; =20 - return lrmid + (cpu_to_node(cpu) % snc_nodes_per_l3_cache) * r->num_rmid; + return lrmid + (cpu_to_node(cpu) % snc_nodes_per_l3_cache) * r->mon.num_r= mid; } =20 static int __rmid_read_phys(u32 prmid, enum resctrl_event_id eventid, u64 = *val) @@ -297,11 +297,11 @@ void resctrl_arch_reset_rmid_all(struct rdt_resource = *r, struct rdt_mon_domain * =20 if (is_mbm_total_enabled()) memset(hw_dom->arch_mbm_total, 0, - sizeof(*hw_dom->arch_mbm_total) * r->num_rmid); + sizeof(*hw_dom->arch_mbm_total) * r->mon.num_rmid); =20 if (is_mbm_local_enabled()) memset(hw_dom->arch_mbm_local, 0, - sizeof(*hw_dom->arch_mbm_local) * r->num_rmid); + sizeof(*hw_dom->arch_mbm_local) * r->mon.num_rmid); } =20 static u64 mbm_overflow_count(u64 prev_msr, u64 cur_msr, unsigned int widt= h) @@ -1083,14 +1083,14 @@ static struct mon_evt mbm_local_event =3D { */ static __init void l3_mon_evt_init(struct rdt_resource *r) { - INIT_LIST_HEAD(&r->evt_list); + INIT_LIST_HEAD(&r->mon.evt_list); =20 if (is_llc_occupancy_enabled()) - list_add_tail(&llc_occupancy_event.list, &r->evt_list); + list_add_tail(&llc_occupancy_event.list, &r->mon.evt_list); if (is_mbm_total_enabled()) - list_add_tail(&mbm_total_event.list, &r->evt_list); + list_add_tail(&mbm_total_event.list, &r->mon.evt_list); if (is_mbm_local_enabled()) - list_add_tail(&mbm_local_event.list, &r->evt_list); + list_add_tail(&mbm_local_event.list, &r->mon.evt_list); } =20 /* @@ -1187,7 +1187,7 @@ int __init rdt_get_mon_l3_config(struct rdt_resource = *r) =20 resctrl_rmid_realloc_limit =3D boot_cpu_data.x86_cache_size * 1024; hw_res->mon_scale =3D boot_cpu_data.x86_cache_occ_scale / snc_nodes_per_l= 3_cache; - r->num_rmid =3D (boot_cpu_data.x86_cache_max_rmid + 1) / snc_nodes_per_l3= _cache; + r->mon.num_rmid =3D (boot_cpu_data.x86_cache_max_rmid + 1) / snc_nodes_pe= r_l3_cache; hw_res->mbm_width =3D MBM_CNTR_WIDTH_BASE; =20 if (mbm_offset > 0 && mbm_offset <=3D MBM_CNTR_WIDTH_OFFSET_MAX) @@ -1202,7 +1202,7 @@ int __init rdt_get_mon_l3_config(struct rdt_resource = *r) * * For a 35MB LLC and 56 RMIDs, this is ~1.8% of the LLC. */ - threshold =3D resctrl_rmid_realloc_limit / r->num_rmid; + threshold =3D resctrl_rmid_realloc_limit / r->mon.num_rmid; =20 /* * Because num_rmid may not be a power of two, round the value diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index d906a1cd8491..1647ad9145ef 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1097,7 +1097,7 @@ static int rdt_num_rmids_show(struct kernfs_open_file= *of, { struct rdt_resource *r =3D of->kn->parent->priv; =20 - seq_printf(seq, "%d\n", r->num_rmid); + seq_printf(seq, "%d\n", r->mon.num_rmid); =20 return 0; } @@ -1108,7 +1108,7 @@ static int rdt_mon_features_show(struct kernfs_open_f= ile *of, struct rdt_resource *r =3D of->kn->parent->priv; struct mon_evt *mevt; =20 - list_for_each_entry(mevt, &r->evt_list, list) { + list_for_each_entry(mevt, &r->mon.evt_list, list) { seq_printf(seq, "%s\n", mevt->name); if (mevt->configurable) seq_printf(seq, "%s_config\n", mevt->name); @@ -3057,13 +3057,13 @@ static int mon_add_all_files(struct kernfs_node *kn= , struct rdt_mon_domain *d, struct mon_evt *mevt; int ret; =20 - if (WARN_ON(list_empty(&r->evt_list))) + if (WARN_ON(list_empty(&r->mon.evt_list))) return -EPERM; =20 priv.u.rid =3D r->rid; priv.u.domid =3D do_sum ? d->ci->id : d->hdr.id; priv.u.sum =3D do_sum; - list_for_each_entry(mevt, &r->evt_list, list) { + list_for_each_entry(mevt, &r->mon.evt_list, list) { priv.u.evtid =3D mevt->evtid; ret =3D mon_addfile(kn, mevt->name, priv.priv); if (ret) diff --git a/include/linux/resctrl.h b/include/linux/resctrl.h index d94abba1c716..3c2307c7c106 100644 --- a/include/linux/resctrl.h +++ b/include/linux/resctrl.h @@ -182,16 +182,26 @@ enum resctrl_scope { RESCTRL_L3_NODE, }; =20 +/** + * struct resctrl_mon - Monitoring related data of a resctrl resource + * @num_rmid: Number of RMIDs available + * @evt_list: List of monitoring events + */ +struct resctrl_mon { + int num_rmid; + struct list_head evt_list; +}; + /** * struct rdt_resource - attributes of a resctrl resource * @rid: The index of the resource * @alloc_capable: Is allocation available on this machine * @mon_capable: Is monitor feature available on this machine - * @num_rmid: Number of RMIDs available * @ctrl_scope: Scope of this resource for control functions * @mon_scope: Scope of this resource for monitor functions * @cache: Cache allocation related data * @membw: If the component has bandwidth controls, their properties. + * @mon: Monitoring related data. * @ctrl_domains: RCU list of all control domains for this resource * @mon_domains: RCU list of all monitor domains for this resource * @name: Name to use in "schemata" file. @@ -199,7 +209,6 @@ enum resctrl_scope { * @default_ctrl: Specifies default cache cbm or memory B/W percent. * @format_str: Per resource format string to show domain value * @parse_ctrlval: Per resource function pointer to parse control values - * @evt_list: List of monitoring events * @fflags: flags to choose base and info files * @cdp_capable: Is the CDP feature available on this resource */ @@ -207,11 +216,11 @@ struct rdt_resource { int rid; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Dec 2024 20:16:45.7403 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: eae7fc71-e834-4646-b4a0-08dd1ae9e6c7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B077.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB7457 Content-Type: text/plain; charset="utf-8" ABMC feature details are reported via CPUID Fn8000_0020_EBX_x5. Bits Description 15:0 MAX_ABMC Maximum Supported Assignable Bandwidth Monitoring Counter ID + 1 The feature details are documented in APM listed below [1]. [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming Publication # 24593 Revision 3.41 section 19.3.3.3 Assignable Bandwidth Monitoring (ABMC). Detect the feature and number of assignable monitoring counters supported. Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537 Signed-off-by: Babu Moger Reviewed-by: Reinette Chatre --- v10: No changes. v9: Added Reviewed-by tag. No code changes v8: Used GENMASK for the mask. v7: Removed WARN_ON for num_mbm_cntrs. Decided to dynamically allocate the bitmap. WARN_ON is not required anymore. Removed redundant comments. v6: Commit message update. Renamed abmc_capable to mbm_cntr_assignable. v5: Name change num_cntrs to num_mbm_cntrs. Moved abmc_capable to resctrl_mon. v4: Removed resctrl_arch_has_abmc(). Added all the code inline. We dont need to separate this as arch code. v3: Removed changes related to mon_features. Moved rdt_cpu_has to core.c and added new function resctrl_arch_has_abm= c. Also moved the fields mbm_assign_capable and mbm_assign_cntrs to rdt_resource. (James) v2: Changed the field name to mbm_assign_capable from abmc_capable. --- arch/x86/kernel/cpu/resctrl/monitor.c | 6 ++++++ include/linux/resctrl.h | 4 ++++ 2 files changed, 10 insertions(+) diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/re= sctrl/monitor.c index ec2a237321dc..36df69da99f2 100644 --- a/arch/x86/kernel/cpu/resctrl/monitor.c +++ b/arch/x86/kernel/cpu/resctrl/monitor.c @@ -1230,6 +1230,12 @@ int __init rdt_get_mon_l3_config(struct rdt_resource= *r) mbm_local_event.configurable =3D true; mbm_config_rftype_init("mbm_local_bytes_config"); } + + if (rdt_cpu_has(X86_FEATURE_ABMC)) { + r->mon.mbm_cntr_assignable =3D true; + cpuid_count(0x80000020, 5, &eax, &ebx, &ecx, &edx); + r->mon.num_mbm_cntrs =3D (ebx & GENMASK(15, 0)) + 1; + } } =20 l3_mon_evt_init(r); diff --git a/include/linux/resctrl.h b/include/linux/resctrl.h index 3c2307c7c106..511cfce8fc21 100644 --- a/include/linux/resctrl.h +++ b/include/linux/resctrl.h @@ -185,10 +185,14 @@ enum resctrl_scope { /** * struct resctrl_mon - Monitoring related data of a resctrl resource * @num_rmid: Number of RMIDs available + * @num_mbm_cntrs: Number of assignable monitoring counters + * @mbm_cntr_assignable:Is system capable of supporting monitor assignment? * @evt_list: List of monitoring events */ struct resctrl_mon { int num_rmid; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Dec 2024 20:16:53.5058 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 820607ed-e87d-4836-052e-08dd1ae9eb6b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B074.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4412 Content-Type: text/plain; charset="utf-8" thread_throttle_mode_init() and mbm_config_rftype_init() both initialize fflags for resctrl files. Adding new files will involve adding another function to initialize the fflags. This can be simplified by adding a new function resctrl_file_fflags_init() and passing the file name and flags to be initialized. Consolidate fflags initialization into resctrl_file_fflags_init() and remove thread_throttle_mode_init() and mbm_config_rftype_init(). Signed-off-by: Babu Moger Reviewed-by: Reinette Chatre --- v10: No changes. Tony added this patch in his series. Will remove it after it is merged. https://lore.kernel.org/lkml/20241122235832.27498-2-tony.luck@intel.co= m/ v9: No changes. v8: No changes. v7: No changes. v6: Added Reviewed-by from Reinette. v5: Commit message update. v4: Commit message update. v3: New patch to display ABMC capability. --- arch/x86/kernel/cpu/resctrl/core.c | 4 +++- arch/x86/kernel/cpu/resctrl/internal.h | 4 ++-- arch/x86/kernel/cpu/resctrl/monitor.c | 6 ++++-- arch/x86/kernel/cpu/resctrl/rdtgroup.c | 16 +++------------- 4 files changed, 12 insertions(+), 18 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index ff4dc649e35c..45f74d57de84 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -234,7 +234,9 @@ static __init bool __get_mem_config_intel(struct rdt_re= source *r) r->membw.throttle_mode =3D THREAD_THROTTLE_PER_THREAD; else r->membw.throttle_mode =3D THREAD_THROTTLE_MAX; - thread_throttle_mode_init(); + + resctrl_file_fflags_init("thread_throttle_mode", + RFTYPE_CTRL_INFO | RFTYPE_RES_MB); =20 r->alloc_capable =3D true; =20 diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index 16181b90159a..9dd1799adba3 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -647,8 +647,8 @@ void cqm_handle_limbo(struct work_struct *work); bool has_busy_rmid(struct rdt_mon_domain *d); void __check_limbo(struct rdt_mon_domain *d, bool force_free); void rdt_domain_reconfigure_cdp(struct rdt_resource *r); -void __init thread_throttle_mode_init(void); -void __init mbm_config_rftype_init(const char *config); +void __init resctrl_file_fflags_init(const char *config, + unsigned long fflags); void rdt_staged_configs_clear(void); bool closid_allocated(unsigned int closid); int resctrl_find_cleanest_closid(void); diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/re= sctrl/monitor.c index 36df69da99f2..80be91671dc1 100644 --- a/arch/x86/kernel/cpu/resctrl/monitor.c +++ b/arch/x86/kernel/cpu/resctrl/monitor.c @@ -1224,11 +1224,13 @@ int __init rdt_get_mon_l3_config(struct rdt_resourc= e *r) =20 if (rdt_cpu_has(X86_FEATURE_CQM_MBM_TOTAL)) { mbm_total_event.configurable =3D true; - mbm_config_rftype_init("mbm_total_bytes_config"); + resctrl_file_fflags_init("mbm_total_bytes_config", + RFTYPE_MON_INFO | RFTYPE_RES_CACHE); } if (rdt_cpu_has(X86_FEATURE_CQM_MBM_LOCAL)) { mbm_local_event.configurable =3D true; - mbm_config_rftype_init("mbm_local_bytes_config"); + resctrl_file_fflags_init("mbm_local_bytes_config", + RFTYPE_MON_INFO | RFTYPE_RES_CACHE); } =20 if (rdt_cpu_has(X86_FEATURE_ABMC)) { diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 1647ad9145ef..687d9d8d82a4 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -2020,24 +2020,14 @@ static struct rftype *rdtgroup_get_rftype_by_name(c= onst char *name) return NULL; } =20 -void __init thread_throttle_mode_init(void) -{ - struct rftype *rft; - - rft =3D rdtgroup_get_rftype_by_name("thread_throttle_mode"); - if (!rft) - return; - - rft->fflags =3D RFTYPE_CTRL_INFO | RFTYPE_RES_MB; -} - -void __init mbm_config_rftype_init(const char *config) +void __init resctrl_file_fflags_init(const char *config, + unsigned long fflags) { struct rftype *rft; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Dec 2024 20:17:01.3234 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cc1eb8ce-ee88-49b7-7fdf-08dd1ae9f011 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B075.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4415 Content-Type: text/plain; charset="utf-8" Add the functionality to enable/disable AMD ABMC feature. AMD ABMC feature is enabled by setting enabled bit(0) in MSR L3_QOS_EXT_CFG. When the state of ABMC is changed, the MSR needs to be updated on all the logical processors in the QOS Domain. Hardware counters will reset when ABMC state is changed. The ABMC feature details are documented in APM listed below [1]. [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming Publication # 24593 Revision 3.41 section 19.3.3.3 Assignable Bandwidth Monitoring (ABMC). Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537 Signed-off-by: Babu Moger Reviewed-by: Reinette Chatre --- v10: No changes. v9: Re-ordered the MSR and added Reviewed-by tag. v8: Commit message update and moved around the comments about L3_QOS_EXT_CFG to _resctrl_abmc_enable. v7: Renamed the function resctrl_arch_get_abmc_enabled() to resctrl_arch_mbm_cntr_assign_enabled= (). Merged resctrl_arch_mbm_cntr_assign_disable, resctrl_arch_mbm_cntr_assi= gn_disable and renamed to resctrl_arch_mbm_cntr_assign_set(). Moved the function definition to linux/resctrl.h. Passed the struct rdt_resource to these functions. Removed resctrl_arch_reset_rmid_all() from arch code. This will be done from the caller. v6: Renamed abmc_enabled to mbm_cntr_assign_enabled. Used msr_set_bit and msr_clear_bit for msr updates. Renamed resctrl_arch_abmc_enable() to resctrl_arch_mbm_cntr_assign_enab= le(). Renamed resctrl_arch_abmc_disable() to resctrl_arch_mbm_cntr_assign_dis= able(). Made _resctrl_abmc_enable to return void. v5: Renamed resctrl_abmc_enable to resctrl_arch_abmc_enable. Renamed resctrl_abmc_disable to resctrl_arch_abmc_disable. Introduced resctrl_arch_get_abmc_enabled to get abmc state from non-arch code. Renamed resctrl_abmc_set_all to _resctrl_abmc_enable(). Modified commit log to make it clear about AMD ABMC feature. v3: No changes. v2: Few text changes in commit message. --- arch/x86/include/asm/msr-index.h | 1 + arch/x86/kernel/cpu/resctrl/core.c | 5 ++++ arch/x86/kernel/cpu/resctrl/internal.h | 5 ++++ arch/x86/kernel/cpu/resctrl/rdtgroup.c | 36 ++++++++++++++++++++++++++ include/linux/resctrl.h | 3 +++ 5 files changed, 50 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-in= dex.h index 3ae84c3b8e6d..bdc95b7cd1b0 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -1194,6 +1194,7 @@ /* - AMD: */ #define MSR_IA32_MBA_BW_BASE 0xc0000200 #define MSR_IA32_SMBA_BW_BASE 0xc0000280 +#define MSR_IA32_L3_QOS_EXT_CFG 0xc00003ff #define MSR_IA32_EVT_CFG_BASE 0xc0000400 =20 /* AMD-V MSRs */ diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index 45f74d57de84..407a80454ae1 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -405,6 +405,11 @@ void rdt_ctrl_update(void *arg) hw_res->msr_update(m); } =20 +bool resctrl_arch_mbm_cntr_assign_enabled(struct rdt_resource *r) +{ + return resctrl_to_arch_res(r)->mbm_cntr_assign_enabled; +} + /* * rdt_find_domain - Search for a domain id in a resource domain list. * diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index 9dd1799adba3..c07a93da31cc 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -56,6 +56,9 @@ /* Max event bits supported */ #define MAX_EVT_CONFIG_BITS GENMASK(6, 0) =20 +/* Setting bit 0 in L3_QOS_EXT_CFG enables the ABMC feature. */ +#define ABMC_ENABLE_BIT 0 + /** * cpumask_any_housekeeping() - Choose any CPU in @mask, preferring those = that * aren't marked nohz_full @@ -477,6 +480,7 @@ struct rdt_parse_data { * @mbm_cfg_mask: Bandwidth sources that can be tracked when Bandwidth * Monitoring Event Configuration (BMEC) is supported. * @cdp_enabled: CDP state of this resource + * @mbm_cntr_assign_enabled: ABMC feature is enabled * * Members of this structure are either private to the architecture * e.g. mbm_width, or accessed via helpers that provide abstraction. e.g. @@ -491,6 +495,7 @@ struct rdt_hw_resource { unsigned int mbm_width; unsigned int mbm_cfg_mask; bool cdp_enabled; + bool mbm_cntr_assign_enabled; }; =20 static inline struct rdt_hw_resource *resctrl_to_arch_res(struct rdt_resou= rce *r) diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 687d9d8d82a4..d54c2701c09c 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -2402,6 +2402,42 @@ int resctrl_arch_set_cdp_enabled(enum resctrl_res_le= vel l, bool enable) return 0; } =20 +static void resctrl_abmc_set_one_amd(void *arg) +{ + bool *enable =3D arg; + + if (*enable) + msr_set_bit(MSR_IA32_L3_QOS_EXT_CFG, ABMC_ENABLE_BIT); + else + msr_clear_bit(MSR_IA32_L3_QOS_EXT_CFG, ABMC_ENABLE_BIT); +} + +/* + * Update L3_QOS_EXT_CFG MSR on all the CPUs associated with the monitor + * domain. + */ +static void _resctrl_abmc_enable(struct rdt_resource *r, bool enable) +{ + struct rdt_mon_domain *d; + + list_for_each_entry(d, &r->mon_domains, hdr.list) + on_each_cpu_mask(&d->hdr.cpu_mask, + resctrl_abmc_set_one_amd, &enable, 1); +} + +int resctrl_arch_mbm_cntr_assign_set(struct rdt_resource *r, bool enable) +{ + struct rdt_hw_resource *hw_res =3D resctrl_to_arch_res(r); + + if (r->mon.mbm_cntr_assignable && + hw_res->mbm_cntr_assign_enabled !=3D enable) { + _resctrl_abmc_enable(r, enable); + hw_res->mbm_cntr_assign_enabled =3D enable; + } + + return 0; +} + /* * We don't allow rdtgroup directories to be created anywhere * except the root directory. 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Thu, 12 Dec 2024 14:17:07 -0600 From: Babu Moger To: , , , , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v10 08/24] x86/resctrl: Introduce the interface to display monitor mode Date: Thu, 12 Dec 2024 14:15:11 -0600 Message-ID: <28399c9a82b771695181e8cb69d9c21847ff4c9c.1734034524.git.babu.moger@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B074:EE_|DM4PR12MB7623:EE_ X-MS-Office365-Filtering-Correlation-Id: 401a299f-efaa-4c34-6012-08dd1ae9f4c2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|1800799024|376014|7416014; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Dec 2024 20:17:09.1934 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 401a299f-efaa-4c34-6012-08dd1ae9f4c2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B074.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7623 Content-Type: text/plain; charset="utf-8" Introduce the interface file "mbm_assign_mode" to list monitor modes supported. The "mbm_cntr_assign" mode provides the option to assign a counter to an RMID, event pair and monitor the bandwidth as long as it is assigned. On AMD systems "mbm_cntr_assign" is backed by the ABMC (Assignable Bandwidth Monitoring Counters) hardware feature and is enabled by default. The "default" mode is the existing monitoring mode that works without the explicit counter assignment, instead relying on dynamic counter assignment by hardware that may result in hardware not dedicating a counter resulting in monitoring data reads returning "Unavailable". Provide an interface to display the monitor mode on the system. $ cat /sys/fs/resctrl/info/L3_MON/mbm_assign_mode [mbm_cntr_assign] default Signed-off-by: Babu Moger --- v10: Added few more text to user documentation clarify on the default mode. v9: Updated user documentation based on comments. v8: Commit message update. v7: Updated the descriptions/commit log in resctrl.rst to generic text. Thanks to James and Reinette. Rename mbm_mode to mbm_assign_mode. Introduced mutex lock in rdtgroup_mbm_mode_show(). v6: Added documentation for mbm_cntr_assign and legacy mode. Moved mbm_mode fflags initialization to static initialization. v5: Changed interface name to mbm_mode. It will be always available even if ABMC feature is not supported. Added description in resctrl.rst about ABMC mode. Fixed display abmc and legacy consistantly. v4: Fixed the checks for legacy and abmc mode. Default it ABMC. v3: New patch to display ABMC capability. --- Documentation/arch/x86/resctrl.rst | 33 ++++++++++++++++++++++++++ arch/x86/kernel/cpu/resctrl/rdtgroup.c | 31 ++++++++++++++++++++++++ 2 files changed, 64 insertions(+) diff --git a/Documentation/arch/x86/resctrl.rst b/Documentation/arch/x86/re= sctrl.rst index 30586728a4cd..1e4a1f615496 100644 --- a/Documentation/arch/x86/resctrl.rst +++ b/Documentation/arch/x86/resctrl.rst @@ -257,6 +257,39 @@ with the following files: # cat /sys/fs/resctrl/info/L3_MON/mbm_local_bytes_config 0=3D0x30;1=3D0x30;3=3D0x15;4=3D0x15 =20 +"mbm_assign_mode": + Reports the list of monitoring modes supported. The enclosed brackets + indicate which mode is enabled. + :: + + # cat /sys/fs/resctrl/info/L3_MON/mbm_assign_mode + [mbm_cntr_assign] + default + + "mbm_cntr_assign": + + In mbm_cntr_assign mode user-space is able to specify which of the + events in CTRL_MON or MON groups should have a counter assigned using the + "mbm_assign_control" file. The number of counters available is described + in the "num_mbm_cntrs" file. Changing the mode may cause all counters on + a resource to reset. + + The mode is useful on AMD platforms which support more CTRL_MON and MON + groups than hardware counters, meaning 'unassigned' events on CTRL_MON or + MON groups will report 'Unavailable'. + + AMD Platforms with ABMC (Assignable Bandwidth Monitoring Counters) feature + enable this mode by default so that counters remain assigned even when the + corresponding RMID is not in use by any processor. + + "default": + + In default mode, resctrl assumes there is a hardware counter for each + event within every CTRL_MON and MON group. On AMD platforms, it is + recommended to use mbm_cntr_assign mode if supported, because reading + "mbm_total_bytes" or "mbm_local_bytes" will report 'Unavailable' if + there is no counter associated with that event. + "max_threshold_occupancy": Read/write file provides the largest value (in bytes) at which a previously used LLC_occupancy diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index d54c2701c09c..f25ff1430014 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -845,6 +845,30 @@ static int rdtgroup_rmid_show(struct kernfs_open_file = *of, return ret; } =20 +static int rdtgroup_mbm_assign_mode_show(struct kernfs_open_file *of, + struct seq_file *s, void *v) +{ + struct rdt_resource *r =3D of->kn->parent->priv; + + mutex_lock(&rdtgroup_mutex); + + if (r->mon.mbm_cntr_assignable) { + if (resctrl_arch_mbm_cntr_assign_enabled(r)) { + seq_puts(s, "[mbm_cntr_assign]\n"); + seq_puts(s, "default\n"); + } else { + seq_puts(s, "mbm_cntr_assign\n"); + seq_puts(s, "[default]\n"); + } + } else { + seq_puts(s, "[default]\n"); + } + + mutex_unlock(&rdtgroup_mutex); + + return 0; +} + #ifdef CONFIG_PROC_CPU_RESCTRL =20 /* @@ -1901,6 +1925,13 @@ static struct rftype res_common_files[] =3D { .seq_show =3D mbm_local_bytes_config_show, .write =3D mbm_local_bytes_config_write, }, + { + .name =3D "mbm_assign_mode", + .mode =3D 0444, + .kf_ops =3D &rdtgroup_kf_single_ops, + .seq_show =3D rdtgroup_mbm_assign_mode_show, + .fflags =3D RFTYPE_MON_INFO, + }, { .name =3D "cpus", .mode =3D 0644, --=20 2.34.1 From nobody Sun Dec 14 19:11:44 2025 Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2069.outbound.protection.outlook.com [40.107.237.69]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2769D1D95A3; Thu, 12 Dec 2024 20:17:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Dec 2024 20:17:17.0752 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: da96ce8f-92e0-4dd4-07a8-08dd1ae9f975 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B071.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB8046 Content-Type: text/plain; charset="utf-8" The mbm_cntr_assign mode provides an option to the user to assign a counter to an RMID, event pair and monitor the bandwidth as long as the counter is assigned. Number of assignments depend on number of monitoring counters available. Provide the interface to display the number of monitoring counters supported. The interface file 'num_mbm_cntrs' is available when an architecture supports mbm_cntr_assign mode. Signed-off-by: Babu Moger --- v10: No changes. v9: Updated user document based on the comments. Will add a new file available_mbm_cntrs later in the series. v8: Commit message update and documentation update. v7: Minor commit log text changes. v6: No changes. v5: Changed the display name from num_cntrs to num_mbm_cntrs. Updated the commit message. Moved the patch after mbm_mode is introduced. v4: Changed the counter name to num_cntrs. And few text changes. v3: Changed the field name to mbm_assign_cntrs. v2: Changed the field name to mbm_assignable_counters from abmc_counter. --- --- Documentation/arch/x86/resctrl.rst | 12 ++++++++++++ arch/x86/kernel/cpu/resctrl/monitor.c | 1 + arch/x86/kernel/cpu/resctrl/rdtgroup.c | 16 ++++++++++++++++ 3 files changed, 29 insertions(+) diff --git a/Documentation/arch/x86/resctrl.rst b/Documentation/arch/x86/re= sctrl.rst index 1e4a1f615496..43a861adeada 100644 --- a/Documentation/arch/x86/resctrl.rst +++ b/Documentation/arch/x86/resctrl.rst @@ -290,6 +290,18 @@ with the following files: "mbm_total_bytes" or "mbm_local_bytes" will report 'Unavailable' if there is no counter associated with that event. =20 +"num_mbm_cntrs": + The number of monitoring counters available for assignment when the + architecture supports mbm_cntr_assign mode. + + The resctrl file system supports tracking up to two memory bandwidth + events per monitoring group: mbm_total_bytes and/or mbm_local_bytes. + Up to two counters can be assigned per monitoring group, one for each + memory bandwidth event. More monitoring groups can be tracked by + assigning one counter per monitoring group. However, doing so limits + memory bandwidth tracking to a single memory bandwidth event per + monitoring group. + "max_threshold_occupancy": Read/write file provides the largest value (in bytes) at which a previously used LLC_occupancy diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/re= sctrl/monitor.c index 80be91671dc1..c23e94fa6852 100644 --- a/arch/x86/kernel/cpu/resctrl/monitor.c +++ b/arch/x86/kernel/cpu/resctrl/monitor.c @@ -1237,6 +1237,7 @@ int __init rdt_get_mon_l3_config(struct rdt_resource = *r) r->mon.mbm_cntr_assignable =3D true; cpuid_count(0x80000020, 5, &eax, &ebx, &ecx, &edx); r->mon.num_mbm_cntrs =3D (ebx & GENMASK(15, 0)) + 1; + resctrl_file_fflags_init("num_mbm_cntrs", RFTYPE_MON_INFO); } } =20 diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index f25ff1430014..339bb0b09a82 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -869,6 +869,16 @@ static int rdtgroup_mbm_assign_mode_show(struct kernfs= _open_file *of, return 0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Dec 2024 20:17:25.1221 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 47e681d5-cabd-4bd0-e39b-08dd1ae9fe40 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B071.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB6981 Content-Type: text/plain; charset="utf-8" If the BMEC (Bandwidth Monitoring Event Configuration) feature is supported, the bandwidth events can be configured to track specific events. The event configuration is domain specific. ABMC (Assignable Bandwidth Monitoring Counters) feature needs event configuration information to assign a hardware counter to an RMID. Event configurations are not stored in resctrl but instead always read from or written to hardware directly when prompted by user space. Read the event configuration from the hardware during the domain initialization. Save the configuration value in struct rdt_hw_mon_domain, so it can be used for counter assignment. Signed-off-by: Babu Moger Reviewed-by: Reinette Chatre --- v10: Conflicts due to code displacement. Actual code didnt change. v9: Added Reviewed-by tag. No other changes. v8: Renamed resctrl_mbm_evt_config_init() to arch_mbm_evt_config_init() Minor commit message update. v7: Fixed initializing INVALID_CONFIG_VALUE to mbm_local_cfg in case of err= or. v6: Renamed resctrl_arch_mbm_evt_config -> resctrl_mbm_evt_config_init Initialized value to INVALID_CONFIG_VALUE if it is not configurable. Minor commit message update. v5: Exported mon_event_config_index_get. Renamed arch_domain_mbm_evt_config to resctrl_arch_mbm_evt_config. v4: Read the configuration information from the hardware to initialize. Added few commit messages. Fixed the tab spaces. v3: Minor changes related to rebase in mbm_config_write_domain. v2: No changes. --- arch/x86/kernel/cpu/resctrl/core.c | 2 ++ arch/x86/kernel/cpu/resctrl/internal.h | 9 +++++++++ arch/x86/kernel/cpu/resctrl/monitor.c | 26 ++++++++++++++++++++++++++ arch/x86/kernel/cpu/resctrl/rdtgroup.c | 4 +--- 4 files changed, 38 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index 407a80454ae1..136b081ed04b 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -632,6 +632,8 @@ static void domain_add_cpu_mon(int cpu, struct rdt_reso= urce *r) =20 arch_mon_domain_online(r, d); =20 + arch_mbm_evt_config_init(hw_dom); + if (arch_domain_mbm_alloc(r->mon.num_rmid, hw_dom)) { mon_domain_free(hw_dom); return; diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index c07a93da31cc..f864550ddd42 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -56,6 +56,9 @@ /* Max event bits supported */ #define MAX_EVT_CONFIG_BITS GENMASK(6, 0) =20 +#define INVALID_CONFIG_VALUE U32_MAX +#define INVALID_CONFIG_INDEX UINT_MAX + /* Setting bit 0 in L3_QOS_EXT_CFG enables the ABMC feature. */ #define ABMC_ENABLE_BIT 0 =20 @@ -401,6 +404,8 @@ struct rdt_hw_ctrl_domain { * @d_resctrl: Properties exposed to the resctrl file system * @arch_mbm_total: arch private state for MBM total bandwidth * @arch_mbm_local: arch private state for MBM local bandwidth + * @mbm_total_cfg: MBM total bandwidth configuration + * @mbm_local_cfg: MBM local bandwidth configuration * * Members of this structure are accessed via helpers that provide abstrac= tion. */ @@ -408,6 +413,8 @@ struct rdt_hw_mon_domain { struct rdt_mon_domain d_resctrl; struct arch_mbm_state *arch_mbm_total; struct arch_mbm_state *arch_mbm_local; + u32 mbm_total_cfg; + u32 mbm_local_cfg; }; =20 static inline struct rdt_hw_ctrl_domain *resctrl_to_arch_ctrl_dom(struct r= dt_ctrl_domain *r) @@ -657,5 +664,7 @@ void __init resctrl_file_fflags_init(const char *config, void rdt_staged_configs_clear(void); bool closid_allocated(unsigned int closid); int resctrl_find_cleanest_closid(void); +void arch_mbm_evt_config_init(struct rdt_hw_mon_domain *hw_dom); +unsigned int mon_event_config_index_get(u32 evtid); =20 #endif /* _ASM_X86_RESCTRL_INTERNAL_H */ diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/re= sctrl/monitor.c index c23e94fa6852..b07d60fabf1c 100644 --- a/arch/x86/kernel/cpu/resctrl/monitor.c +++ b/arch/x86/kernel/cpu/resctrl/monitor.c @@ -1248,6 +1248,32 @@ int __init rdt_get_mon_l3_config(struct rdt_resource= *r) return 0; } =20 +void arch_mbm_evt_config_init(struct rdt_hw_mon_domain *hw_dom) +{ + unsigned int index; + u64 msrval; + + /* + * Read the configuration registers QOS_EVT_CFG_n, where is + * the BMEC event number (EvtID). + */ + if (mbm_total_event.configurable) { + index =3D mon_event_config_index_get(QOS_L3_MBM_TOTAL_EVENT_ID); + rdmsrl(MSR_IA32_EVT_CFG_BASE + index, msrval); + hw_dom->mbm_total_cfg =3D msrval & MAX_EVT_CONFIG_BITS; + } else { + hw_dom->mbm_total_cfg =3D INVALID_CONFIG_VALUE; + } + + if (mbm_local_event.configurable) { + index =3D mon_event_config_index_get(QOS_L3_MBM_LOCAL_EVENT_ID); + rdmsrl(MSR_IA32_EVT_CFG_BASE + index, msrval); + hw_dom->mbm_local_cfg =3D msrval & MAX_EVT_CONFIG_BITS; + } else { + hw_dom->mbm_local_cfg =3D INVALID_CONFIG_VALUE; + } +} + void __exit rdt_put_mon_l3_config(void) { dom_data_exit(); diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 339bb0b09a82..541bd353c567 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1582,8 +1582,6 @@ struct mon_config_info { u32 mon_config; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Dec 2024 20:17:32.7295 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 769fcb8a-3e0e-40b3-af86-08dd1aea02c9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B075.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4074 Content-Type: text/plain; charset="utf-8" The event configuration is domain specific and initialized during domain initialization. The values are stored in struct rdt_hw_mon_domain. It is not required to read the configuration register every time user asks for it. Use the value stored in struct rdt_hw_mon_domain instead. Introduce resctrl_arch_mon_event_config_get() and resctrl_arch_mon_event_config_set() to get/set architecture domain specific mbm_total_cfg/mbm_local_cfg values. Signed-off-by: Babu Moger --- v10: Moved the mon_config_info structure definition to resctrl.h. v9: Removed QOS_L3_OCCUP_EVENT_ID switch case in resctrl_arch_mon_event_con= fig_set. Fixed a unnecessary space. v8: Renamed resctrl_arch_event_config_get() to resctrl_arch_mon_event_config_get(). resctrl_arch_event_config_set() to resctrl_arch_mon_event_config_set(). v7: Removed check if (val =3D=3D INVALID_CONFIG_VALUE) as resctrl_arch_even= t_config_get already prints warning. Kept the Event config value definitions as is. v6: Fixed inconstancy with types. Made all the types to u32 for config value. Removed few rdt_last_cmd_puts as it is not necessary. Removed unused config value definitions. Few more updates to commit message. v5: Introduced resctrl_arch_event_config_get and resctrl_arch_event_config_get() based on our discussion. https://lore.kernel.org/lkml/68e861f9-245d-4496-a72e-46fc57d19c62@amd.c= om/ v4: New patch. --- arch/x86/kernel/cpu/resctrl/rdtgroup.c | 105 +++++++++++++------------ include/linux/resctrl.h | 16 ++++ 2 files changed, 72 insertions(+), 49 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 541bd353c567..682f47e0beb1 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1577,10 +1577,51 @@ static int rdtgroup_size_show(struct kernfs_open_fi= le *of, return ret; } =20 -struct mon_config_info { - u32 evtid; - u32 mon_config; -}; +u32 resctrl_arch_mon_event_config_get(struct rdt_mon_domain *d, + enum resctrl_event_id eventid) +{ + struct rdt_hw_mon_domain *hw_dom =3D resctrl_to_arch_mon_dom(d); + + switch (eventid) { + case QOS_L3_OCCUP_EVENT_ID: + break; + case QOS_L3_MBM_TOTAL_EVENT_ID: + return hw_dom->mbm_total_cfg; + case QOS_L3_MBM_LOCAL_EVENT_ID: + return hw_dom->mbm_local_cfg; + } + + /* Never expect to get here */ + WARN_ON_ONCE(1); + + return INVALID_CONFIG_VALUE; +} + +void resctrl_arch_mon_event_config_set(void *info) +{ + struct mon_config_info *mon_info =3D info; + struct rdt_hw_mon_domain *hw_dom; + unsigned int index; + + index =3D mon_event_config_index_get(mon_info->evtid); + if (index =3D=3D INVALID_CONFIG_INDEX) + return; + + wrmsr(MSR_IA32_EVT_CFG_BASE + index, mon_info->mon_config, 0); + + hw_dom =3D resctrl_to_arch_mon_dom(mon_info->d); + + switch (mon_info->evtid) { + case QOS_L3_MBM_TOTAL_EVENT_ID: + hw_dom->mbm_total_cfg =3D mon_info->mon_config; + break; + case QOS_L3_MBM_LOCAL_EVENT_ID: + hw_dom->mbm_local_cfg =3D mon_info->mon_config; + break; + default: + break; + } +} =20 /** * mon_event_config_index_get - get the hardware index for the @@ -1604,33 +1645,11 @@ unsigned int mon_event_config_index_get(u32 evtid) } } =20 -static void mon_event_config_read(void *info) -{ - struct mon_config_info *mon_info =3D info; - unsigned int index; - u64 msrval; - - index =3D mon_event_config_index_get(mon_info->evtid); - if (index =3D=3D INVALID_CONFIG_INDEX) { - pr_warn_once("Invalid event id %d\n", mon_info->evtid); - return; - } - rdmsrl(MSR_IA32_EVT_CFG_BASE + index, msrval); - - /* Report only the valid event configuration bits */ - mon_info->mon_config =3D msrval & MAX_EVT_CONFIG_BITS; -} - -static void mondata_config_read(struct rdt_mon_domain *d, struct mon_confi= g_info *mon_info) -{ - smp_call_function_any(&d->hdr.cpu_mask, mon_event_config_read, mon_info, = 1); -} - static int mbm_config_show(struct seq_file *s, struct rdt_resource *r, u32= evtid) { - struct mon_config_info mon_info; struct rdt_mon_domain *dom; bool sep =3D false; + u32 val; =20 cpus_read_lock(); mutex_lock(&rdtgroup_mutex); @@ -1639,11 +1658,8 @@ static int mbm_config_show(struct seq_file *s, struc= t rdt_resource *r, u32 evtid if (sep) seq_puts(s, ";"); =20 - memset(&mon_info, 0, sizeof(struct mon_config_info)); - mon_info.evtid =3D evtid; - mondata_config_read(dom, &mon_info); - - seq_printf(s, "%d=3D0x%02x", dom->hdr.id, mon_info.mon_config); + val =3D resctrl_arch_mon_event_config_get(dom, evtid); + seq_printf(s, "%d=3D0x%02x", dom->hdr.id, val); sep =3D true; } seq_puts(s, "\n"); @@ -1674,33 +1690,23 @@ static int mbm_local_bytes_config_show(struct kernf= s_open_file *of, return 0; } =20 -static void mon_event_config_write(void *info) -{ - struct mon_config_info *mon_info =3D info; - unsigned int index; - - index =3D mon_event_config_index_get(mon_info->evtid); - if (index =3D=3D INVALID_CONFIG_INDEX) { - pr_warn_once("Invalid event id %d\n", mon_info->evtid); - return; - } - wrmsr(MSR_IA32_EVT_CFG_BASE + index, mon_info->mon_config, 0); -} =20 static void mbm_config_write_domain(struct rdt_resource *r, struct rdt_mon_domain *d, u32 evtid, u32 val) { struct mon_config_info mon_info =3D {0}; + u32 config_val; =20 /* - * Read the current config value first. If both are the same then + * Check the current config value first. If both are the same then * no need to write it again. */ - mon_info.evtid =3D evtid; - mondata_config_read(d, &mon_info); - if (mon_info.mon_config =3D=3D val) + config_val =3D resctrl_arch_mon_event_config_get(d, evtid); + if (config_val =3D=3D INVALID_CONFIG_VALUE || config_val =3D=3D val) return; =20 + mon_info.d =3D d; + mon_info.evtid =3D evtid; mon_info.mon_config =3D val; =20 /* @@ -1709,7 +1715,8 @@ static void mbm_config_write_domain(struct rdt_resour= ce *r, * are scoped at the domain level. Writing any of these MSRs * on one CPU is observed by all the CPUs in the domain. */ - smp_call_function_any(&d->hdr.cpu_mask, mon_event_config_write, + smp_call_function_any(&d->hdr.cpu_mask, + resctrl_arch_mon_event_config_set, &mon_info, 1); =20 /* diff --git a/include/linux/resctrl.h b/include/linux/resctrl.h index f11d6fdfd977..c8ab3d7a0dab 100644 --- a/include/linux/resctrl.h +++ b/include/linux/resctrl.h @@ -118,6 +118,18 @@ struct rdt_mon_domain { int cqm_work_cpu; }; =20 +/** + * struct mon_config_info - Monitoring event configuratiin details + * @d: Domain for the event + * @evtid: Event type + * @mon_config: Event configuration value + */ +struct mon_config_info { + struct rdt_mon_domain *d; + enum resctrl_event_id evtid; + u32 mon_config; +}; + /** * struct resctrl_cache - Cache allocation related data * @cbm_len: Length of the cache bit mask @@ -352,6 +364,10 @@ void resctrl_arch_reset_rmid(struct rdt_resource *r, s= truct rdt_mon_domain *d, */ void resctrl_arch_reset_rmid_all(struct rdt_resource *r, struct rdt_mon_do= main *d); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Dec 2024 20:17:42.5062 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0bf15d85-ae65-499e-7eca-08dd1aea089d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B074.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6594 Content-Type: text/plain; charset="utf-8" In mbm_assign_mode, the MBM counters are assigned/unassigned to an RMID, event pair in a resctrl group and monitor the bandwidth as long as it is assigned. Counters are assigned/unassigned at domain level and needs to be tracked at domain level. Add the mbm_assign_cntr_cfg data structure to struct rdt_ctrl_domain to manage and track MBM counter assignments at the domain level. Suggested-by: Peter Newman Signed-off-by: Babu Moger --- v10: Patch changed completely to handle the counters at domain level. https://lore.kernel.org/lkml/CALPaoCj+zWq1vkHVbXYP0znJbe6Ke3PXPWjtri5A= FgD9cQDCUg@mail.gmail.com/ Removed Reviewed-by tag. Did not see the need to add cntr_id in mbm_state structure. Not used i= n the code. v9: Added Reviewed-by tag. No other changes. v8: Minor commit message changes. v7: Added check mbm_cntr_assignable for allocating bitmap mbm_cntr_map v6: New patch to add domain level assignment. --- arch/x86/kernel/cpu/resctrl/rdtgroup.c | 11 +++++++++++ include/linux/resctrl.h | 12 ++++++++++++ 2 files changed, 23 insertions(+) diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 682f47e0beb1..1ee008a63d8b 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -4068,6 +4068,7 @@ static void __init rdtgroup_setup_default(void) =20 static void domain_destroy_mon_state(struct rdt_mon_domain *d) { + kfree(d->cntr_cfg); bitmap_free(d->rmid_busy_llc); kfree(d->mbm_total); kfree(d->mbm_local); @@ -4141,6 +4142,16 @@ static int domain_setup_mon_state(struct rdt_resourc= e *r, struct rdt_mon_domain return -ENOMEM; } } + if (is_mbm_enabled() && r->mon.mbm_cntr_assignable) { + tsize =3D sizeof(*d->cntr_cfg); + d->cntr_cfg =3D kcalloc(r->mon.num_mbm_cntrs, tsize, GFP_KERNEL); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Dec 2024 20:17:48.3700 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dca3d643-5637-4521-a02f-08dd1aea0c1e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B075.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB8148 Content-Type: text/plain; charset="utf-8" Provide the interface to display the number of monitoring counters available for assignment in each domain when mbm_cntr_assign is supported. Signed-off-by: Babu Moger --- v10: Patch changed to handle the counters at domain level. https://lore.kernel.org/lkml/CALPaoCj+zWq1vkHVbXYP0znJbe6Ke3PXPWjtri5A= FgD9cQDCUg@mail.gmail.com/ So, display logic also changed now. v9: New patch --- Documentation/arch/x86/resctrl.rst | 4 +++ arch/x86/kernel/cpu/resctrl/monitor.c | 1 + arch/x86/kernel/cpu/resctrl/rdtgroup.c | 47 ++++++++++++++++++++++++++ 3 files changed, 52 insertions(+) diff --git a/Documentation/arch/x86/resctrl.rst b/Documentation/arch/x86/re= sctrl.rst index 43a861adeada..c075fcee96b7 100644 --- a/Documentation/arch/x86/resctrl.rst +++ b/Documentation/arch/x86/resctrl.rst @@ -302,6 +302,10 @@ with the following files: memory bandwidth tracking to a single memory bandwidth event per monitoring group. =20 +"available_mbm_cntrs": + The number of monitoring counters available for assignment in each + domain when the architecture supports mbm_cntr_assign mode. + "max_threshold_occupancy": Read/write file provides the largest value (in bytes) at which a previously used LLC_occupancy diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/re= sctrl/monitor.c index b07d60fabf1c..f857af361af1 100644 --- a/arch/x86/kernel/cpu/resctrl/monitor.c +++ b/arch/x86/kernel/cpu/resctrl/monitor.c @@ -1238,6 +1238,7 @@ int __init rdt_get_mon_l3_config(struct rdt_resource = *r) cpuid_count(0x80000020, 5, &eax, &ebx, &ecx, &edx); r->mon.num_mbm_cntrs =3D (ebx & GENMASK(15, 0)) + 1; resctrl_file_fflags_init("num_mbm_cntrs", RFTYPE_MON_INFO); + resctrl_file_fflags_init("available_mbm_cntrs", RFTYPE_MON_INFO); } } =20 diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 1ee008a63d8b..72518e0ec2ec 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -879,6 +879,47 @@ static int rdtgroup_num_mbm_cntrs_show(struct kernfs_o= pen_file *of, return 0; } =20 +static int rdtgroup_available_mbm_cntrs_show(struct kernfs_open_file *of, + struct seq_file *s, void *v) +{ + struct rdt_resource *r =3D of->kn->parent->priv; + struct rdt_mon_domain *dom; + bool sep =3D false; + u32 cntrs, i; + int ret =3D 0; + + cpus_read_lock(); + mutex_lock(&rdtgroup_mutex); + + if (!resctrl_arch_mbm_cntr_assign_enabled(r)) { + rdt_last_cmd_puts("mbm_cntr_assign mode is not enabled\n"); + ret =3D -EINVAL; + goto unlock_cntrs_show; + } + + + list_for_each_entry(dom, &r->mon_domains, hdr.list) { + if (sep) + seq_puts(s, ";"); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Dec 2024 20:17:56.1512 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 251f1640-e918-41df-8f54-08dd1aea10bf X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B075.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8217 The ABMC feature provides an option to the user to assign a hardware counter to an RMID, event pair and monitor the bandwidth as long as the counter is assigned. The bandwidth events will be tracked by the hardware until the user changes the configuration. Each resctrl group can configure maximum two counters, one for total event and one for local event. The ABMC feature implements an MSR L3_QOS_ABMC_CFG (C000_03FDh). Configuration is done by setting the counter id, bandwidth source (RMID) and bandwidth configuration supported by BMEC (Bandwidth Monitoring Event Configuration). Attempts to read or write the MSR when ABMC is not enabled will result in a #GP(0) exception. Introduce the data structures and definitions for MSR L3_QOS_ABMC_CFG (0xC000_03FDh): =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Bits Mnemonic Description Access Reset Type Value =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D 63 CfgEn Configuration Enable R/W 0 62 CtrEn Enable/disable counting R/W 0 61:53 =E2=80=93 Reserved MBZ 0 52:48 CtrID Counter Identifier R/W 0 47 IsCOS BwSrc field is a CLOSID R/W 0 (not an RMID) 46:44 =E2=80=93 Reserved MBZ 0 43:32 BwSrc Bandwidth Source R/W 0 (RMID or CLOSID) 31:0 BwType Bandwidth configuration R/W 0 to track for this counter =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D The feature details are documented in the APM listed below [1]. [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming Publication # 24593 Revision 3.41 section 19.3.3.3 Assignable Bandwidth Monitoring (ABMC). Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537 Signed-off-by: Babu Moger Reviewed-by: Reinette Chatre --- v10: No changes. v9: Removed the references of L3_QOS_ABMC_DSC. Text changes about configuration in kernel doc. v8: Update the configuration notes in kernel_doc. Few commit message update. v7: Removed the reference of L3_QOS_ABMC_DSC as it is not used anymore. Moved the configuration notes to kernel_doc. Adjusted the tabs for l3_qos_abmc_cfg and checkpatch seems happy. v6: Removed all the fs related changes. Added note on CfgEn,CtrEn. Removed the definitions which are not used. Removed cntr_id initialization. v5: Moved assignment flags here (path 10/19 of v4). Added MON_CNTR_UNSET definition to initialize cntr_id's. More details in commit log. Renamed few fields in l3_qos_abmc_cfg for readability. v4: Added more descriptions. Changed the name abmc_ctr_id to ctr_id. Added L3_QOS_ABMC_DSC. Used for reading the configuration. v3: No changes. v2: No changes. --- arch/x86/include/asm/msr-index.h | 1 + arch/x86/kernel/cpu/resctrl/internal.h | 35 ++++++++++++++++++++++++++ 2 files changed, 36 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-in= dex.h index bdc95b7cd1b0..d7dec2326cd8 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -1194,6 +1194,7 @@ /* - AMD: */ #define MSR_IA32_MBA_BW_BASE 0xc0000200 #define MSR_IA32_SMBA_BW_BASE 0xc0000280 +#define MSR_IA32_L3_QOS_ABMC_CFG 0xc00003fd #define MSR_IA32_L3_QOS_EXT_CFG 0xc00003ff #define MSR_IA32_EVT_CFG_BASE 0xc0000400 =20 diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index f864550ddd42..35bcf0e5ba7e 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -602,6 +602,41 @@ union cpuid_0x10_x_edx { unsigned int full; }; =20 +/* + * ABMC counters are configured by writing to L3_QOS_ABMC_CFG. + * @bw_type : Bandwidth configuration (supported by BMEC) + * tracked by the @cntr_id. + * @bw_src : Bandwidth source (RMID or CLOSID). + * @reserved1 : Reserved. + * @is_clos : @bw_src field is a CLOSID (not an RMID). + * @cntr_id : Counter identifier. + * @reserved : Reserved. + * @cntr_en : Counting enable bit. + * @cfg_en : Configuration enable bit. + * + * Configuration and counting: + * Counter can be configured across multiple writes to MSR. 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Counter @cntr_id is reset when the + * configuration is applied. + * @cfg_en =3D 1, @cntr_en =3D 0 : Apply @cntr_id configuration but do not + * count events. + * @cfg_en =3D 1, @cntr_en =3D 1 : Apply @cntr_id configuration and start + * counting events. + */ +union l3_qos_abmc_cfg { + struct { + unsigned long bw_type :32, + bw_src :12, + reserved1: 3, + is_clos : 1, + cntr_id : 5, + reserved : 9, + cntr_en : 1, + cfg_en : 1; + } split; + unsigned long full; +}; + void rdt_last_cmd_clear(void); void rdt_last_cmd_puts(const char *s); __printf(1, 2) --=20 2.34.1 From nobody Sun Dec 14 19:11:44 2025 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2081.outbound.protection.outlook.com [40.107.244.81]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3DE6D1D79A0; Thu, 12 Dec 2024 20:18:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.244.81 ARC-Seal: i=2; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Dec 2024 20:18:04.0683 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 60795b34-a04c-4205-ff3e-08dd1aea1579 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B077.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7150 Content-Type: text/plain; charset="utf-8" The ABMC feature provides an option to the user to assign a hardware counter to an RMID, event pair and monitor the bandwidth as long as it is assigned. The assigned RMID will be tracked by the hardware until the user unassigns it manually. Configure the counters by writing to the L3_QOS_ABMC_CFG MSR and specifying the counter ID, bandwidth source (RMID), and bandwidth event configuration. Provide the interface to assign the counter ids to RMID. The feature details are documented in the APM listed below [1]. [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming Publication # 24593 Revision 3.41 section 19.3.3.3 Assignable Bandwidth Monitoring (ABMC). Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537 Signed-off-by: Babu Moger --- v10: Added call resctrl_arch_reset_rmid() to reset the RMID in the domain inside IPI call. SMP and non-SMP call support is not required in resctrl_arch_config_cn= tr with new domain specific assign approach/data structure. Commit message update. v9: Removed the code to reset the architectural state. It will done in another patch. v8: Rename resctrl_arch_assign_cntr to resctrl_arch_config_cntr. v7: Separated arch and fs functions. This patch only has arch implementatio= n. Added struct rdt_resource to the interface resctrl_arch_assign_cntr. Rename rdtgroup_abmc_cfg() to resctrl_abmc_config_one_amd(). v6: Removed mbm_cntr_alloc() from this patch to keep fs and arch code separate. Added code to update the counter assignment at domain level. v5: Few name changes to match cntr_id. Changed the function names to rdtgroup_assign_cntr resctr_arch_assign_cntr More comments on commit log. Added function summary. v4: Commit message update. User bitmap APIs where applicable. Changed the interfaces considering MPAM(arm). Added domain specific assignment. v3: Removed the static from the prototype of rdtgroup_assign_abmc. The function is not called directly from user anymore. These changes are related to global assignment interface. v2: Minor text changes in commit message. --- arch/x86/kernel/cpu/resctrl/internal.h | 3 ++ arch/x86/kernel/cpu/resctrl/rdtgroup.c | 58 ++++++++++++++++++++++++++ 2 files changed, 61 insertions(+) diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index 35bcf0e5ba7e..849bcfe4ea5b 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -701,5 +701,8 @@ bool closid_allocated(unsigned int closid); int resctrl_find_cleanest_closid(void); void arch_mbm_evt_config_init(struct rdt_hw_mon_domain *hw_dom); unsigned int mon_event_config_index_get(u32 evtid); +int resctrl_arch_config_cntr(struct rdt_resource *r, struct rdt_mon_domain= *d, + enum resctrl_event_id evtid, u32 rmid, u32 closid, + u32 cntr_id, bool assign); =20 #endif /* _ASM_X86_RESCTRL_INTERNAL_H */ diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 72518e0ec2ec..e895d2415f22 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1686,6 +1686,34 @@ unsigned int mon_event_config_index_get(u32 evtid) } } =20 +struct cntr_config { + struct rdt_resource *r; + struct rdt_mon_domain *d; + enum resctrl_event_id evtid; + u32 rmid; + u32 closid; + u32 cntr_id; + u32 val; + bool assign; +}; + +static void resctrl_abmc_config_one_amd(void *info) +{ + struct cntr_config *config =3D info; + union l3_qos_abmc_cfg abmc_cfg =3D { 0 }; + + abmc_cfg.split.cfg_en =3D 1; + abmc_cfg.split.cntr_en =3D config->assign ? 1 : 0; + abmc_cfg.split.cntr_id =3D config->cntr_id; + abmc_cfg.split.bw_src =3D config->rmid; + abmc_cfg.split.bw_type =3D config->val; + + wrmsrl(MSR_IA32_L3_QOS_ABMC_CFG, abmc_cfg.full); + + resctrl_arch_reset_rmid(config->r, config->d, config->closid, + config->rmid, config->evtid); +} + static int mbm_config_show(struct seq_file *s, struct rdt_resource *r, u32= evtid) { struct rdt_mon_domain *dom; @@ -1869,6 +1897,36 @@ static ssize_t mbm_local_bytes_config_write(struct k= ernfs_open_file *of, return ret ?: nbytes; } =20 +/* + * Send an IPI to the domain to assign the counter to RMID, event pair. + */ +int resctrl_arch_config_cntr(struct rdt_resource *r, struct rdt_mon_domain= *d, + enum resctrl_event_id evtid, u32 rmid, u32 closid, + u32 cntr_id, bool assign) +{ + struct rdt_hw_mon_domain *hw_dom =3D resctrl_to_arch_mon_dom(d); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Dec 2024 20:18:11.9506 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 08f2ed62-a3b0-46ae-5c7e-08dd1aea1a2a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B076.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYXPR12MB9388 Content-Type: text/plain; charset="utf-8" The mbm_cntr_assign mode offers several counters that can be assigned to an RMID, event pair and monitor the bandwidth as long as it is assigned. Counters are managed at the domain level. Introduce the interface to allocate/free/assign the counters. If the user requests assignments across all domains, some domains may fail if they run out of counters. Ensure assignments continue in other domains wherever possible. Signed-off-by: Babu Moger --- v10: Patch changed completely. Counters are managed at the domain based on the discussion. https://lore.kernel.org/lkml/CALPaoCj+zWq1vkHVbXYP0znJbe6Ke3PXPWjtri5A= FgD9cQDCUg@mail.gmail.com/ Reset non-architectural MBM state. Commit message update. v9: Introduced new function resctrl_config_cntr to assign the counter, upda= te the bitmap and reset the architectural state. Taken care of error handling(freeing the counter) when assignment fails. Moved mbm_cntr_assigned_to_domain here as it used in this patch. Minor text changes. v8: Renamed rdtgroup_assign_cntr() to rdtgroup_assign_cntr_event(). Added the code to return the error if rdtgroup_assign_cntr_event fails. Moved definition of MBM_EVENT_ARRAY_INDEX to resctrl/internal.h. Updated typo in the comments. v7: New patch. Moved all the FS code here. Merged rdtgroup_assign_cntr and rdtgroup_alloc_cntr. Adde new #define MBM_EVENT_ARRAY_INDEX. --- arch/x86/kernel/cpu/resctrl/internal.h | 5 +- arch/x86/kernel/cpu/resctrl/monitor.c | 4 +- arch/x86/kernel/cpu/resctrl/rdtgroup.c | 110 +++++++++++++++++++++++++ 3 files changed, 116 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index 849bcfe4ea5b..70d2577fc377 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -704,5 +704,8 @@ unsigned int mon_event_config_index_get(u32 evtid); int resctrl_arch_config_cntr(struct rdt_resource *r, struct rdt_mon_domain= *d, enum resctrl_event_id evtid, u32 rmid, u32 closid, u32 cntr_id, bool assign); - +int rdtgroup_assign_cntr_event(struct rdt_resource *r, struct rdtgroup *rd= tgrp, + struct rdt_mon_domain *d, enum resctrl_event_id evtid); +struct mbm_state *get_mbm_state(struct rdt_mon_domain *d, u32 closid, + u32 rmid, enum resctrl_event_id evtid); #endif /* _ASM_X86_RESCTRL_INTERNAL_H */ diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/re= sctrl/monitor.c index f857af361af1..8823cd97ff1f 100644 --- a/arch/x86/kernel/cpu/resctrl/monitor.c +++ b/arch/x86/kernel/cpu/resctrl/monitor.c @@ -575,8 +575,8 @@ void free_rmid(u32 closid, u32 rmid) list_add_tail(&entry->list, &rmid_free_lru); } =20 -static struct mbm_state *get_mbm_state(struct rdt_mon_domain *d, u32 closi= d, - u32 rmid, enum resctrl_event_id evtid) +struct mbm_state *get_mbm_state(struct rdt_mon_domain *d, u32 closid, + u32 rmid, enum resctrl_event_id evtid) { u32 idx =3D resctrl_arch_rmid_idx_encode(closid, rmid); =20 diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index e895d2415f22..1c8694a68cf4 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1927,6 +1927,116 @@ int resctrl_arch_config_cntr(struct rdt_resource *r= , struct rdt_mon_domain *d, return 0; } =20 +/* + * Configure the counter for the event, RMID pair for the domain. + */ +static int resctrl_config_cntr(struct rdt_resource *r, struct rdt_mon_doma= in *d, + enum resctrl_event_id evtid, u32 rmid, u32 closid, + u32 cntr_id, bool assign) +{ + struct mbm_state *m; + int ret; + + ret =3D resctrl_arch_config_cntr(r, d, evtid, rmid, closid, cntr_id, assi= gn); + if (ret) + return ret; + + m =3D get_mbm_state(d, closid, rmid, evtid); + if (m) + memset(m, 0, sizeof(struct mbm_state)); + + return ret; +} + +static bool mbm_cntr_assigned(struct rdt_resource *r, struct rdt_mon_domai= n *d, + struct rdtgroup *rdtgrp, enum resctrl_event_id evtid) +{ + int cntr_id; + + for (cntr_id =3D 0; cntr_id < r->mon.num_mbm_cntrs; cntr_id++) { + if (d->cntr_cfg[cntr_id].rdtgrp =3D=3D rdtgrp && + d->cntr_cfg[cntr_id].evtid =3D=3D evtid) + return true; + } + + return false; +} + +static int mbm_cntr_alloc(struct rdt_resource *r, struct rdt_mon_domain *d, + struct rdtgroup *rdtgrp, enum resctrl_event_id evtid) +{ + int cntr_id; + + for (cntr_id =3D 0; cntr_id < r->mon.num_mbm_cntrs; cntr_id++) { + if (!d->cntr_cfg[cntr_id].rdtgrp) { + d->cntr_cfg[cntr_id].rdtgrp =3D rdtgrp; + d->cntr_cfg[cntr_id].evtid =3D evtid; + return cntr_id; + } + } + + return -EINVAL; +} + +static void mbm_cntr_free(struct rdt_resource *r, struct rdt_mon_domain *d, + struct rdtgroup *rdtgrp, enum resctrl_event_id evtid) +{ + int cntr_id; + + for (cntr_id =3D 0; cntr_id < r->mon.num_mbm_cntrs; cntr_id++) { + if (d->cntr_cfg[cntr_id].rdtgrp =3D=3D rdtgrp && + d->cntr_cfg[cntr_id].evtid =3D=3D evtid) + memset(&d->cntr_cfg[cntr_id], 0, sizeof(struct mbm_cntr_cfg)); + } +} + +/* + * Assign a hardware counter to event @evtid of group @rdtgrp. + * Counter will be assigned to all the domains if rdt_mon_domain is NULL + * else the counter will be assigned to specific domain. + */ +int rdtgroup_assign_cntr_event(struct rdt_resource *r, struct rdtgroup *rd= tgrp, + struct rdt_mon_domain *d, enum resctrl_event_id evtid) +{ + int cntr_id, ret =3D 0; + + if (!d) { + list_for_each_entry(d, &r->mon_domains, hdr.list) { + if (mbm_cntr_assigned(r, d, rdtgrp, evtid)) + continue; + + cntr_id =3D mbm_cntr_alloc(r, d, rdtgrp, evtid); + if (cntr_id < 0) { + rdt_last_cmd_puts("Domain Out of MBM assignable counters\n"); + continue; + } + + ret =3D resctrl_config_cntr(r, d, evtid, rdtgrp->mon.rmid, + rdtgrp->closid, cntr_id, true); + if (ret) + goto out_done_assign; + } + } else { + if (mbm_cntr_assigned(r, d, rdtgrp, evtid)) + goto out_done_assign; + + cntr_id =3D mbm_cntr_alloc(r, d, rdtgrp, evtid); + if (cntr_id < 0) { + rdt_last_cmd_puts("Domain Out of MBM assignable counters\n"); + goto out_done_assign; + } + + ret =3D resctrl_config_cntr(r, d, evtid, rdtgrp->mon.rmid, + rdtgrp->closid, cntr_id, true); + } + +out_done_assign: + if (ret) + mbm_cntr_free(r, d, rdtgrp, evtid); + + return ret; +} + /* rdtgroup information files for one cache resource. */ static struct rftype res_common_files[] =3D { { --=20 2.34.1 From nobody Sun Dec 14 19:11:44 2025 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2076.outbound.protection.outlook.com [40.107.93.76]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E1F1F1D88C7; Thu, 12 Dec 2024 20:18:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.93.76 ARC-Seal: i=2; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Dec 2024 20:18:21.4011 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: da1dec82-faf8-4ada-61ec-08dd1aea1fcc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B075.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6052 Content-Type: text/plain; charset="utf-8" The mbm_cntr_assign mode provides a limited number of hardware counters that can be assigned to an RMID, event pair to monitor bandwidth while assigned. If all counters are in use, the kernel will show an error message: "Out of MBM assignable counters" when a new assignment is requested. To make space for a new assignment, users must unassign an already assigned counter. Introduce an interface that allows for the unassignment of counter IDs from the domain. Signed-off-by: Babu Moger --- v10: Patch changed again. Counters are managed at the domain based on the discussion. https://lore.kernel.org/lkml/CALPaoCj+zWq1vkHVbXYP0znJbe6Ke3PXPWjtri5A= FgD9cQDCUg@mail.gmail.com/ commit message update. v9: Changes related to addition of new function resctrl_config_cntr(). The removed rdtgroup_mbm_cntr_is_assigned() as it was introduced already. Text changes to take care comments. v8: Renamed rdtgroup_mbm_cntr_is_assigned to mbm_cntr_assigned_to_domain Added return error handling in resctrl_arch_config_cntr(). v7: Merged rdtgroup_unassign_cntr and rdtgroup_free_cntr functions. Renamed rdtgroup_mbm_cntr_test() to rdtgroup_mbm_cntr_is_assigned(). Reworded the commit log little bit. v6: Removed mbm_cntr_free from this patch. Added counter test in all the domains and free if it is not assigned to any domains. v5: Few name changes to match cntr_id. Changed the function names to rdtgroup_unassign_cntr More comments on commit log. v4: Added domain specific unassign feature. Few name changes. v3: Removed the static from the prototype of rdtgroup_unassign_abmc. The function is not called directly from user anymore. These changes are related to global assignment interface. v2: No changes. --- arch/x86/kernel/cpu/resctrl/internal.h | 2 + arch/x86/kernel/cpu/resctrl/rdtgroup.c | 52 ++++++++++++++++++++++++++ 2 files changed, 54 insertions(+) diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index 70d2577fc377..f858098dbe4b 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -706,6 +706,8 @@ int resctrl_arch_config_cntr(struct rdt_resource *r, st= ruct rdt_mon_domain *d, u32 cntr_id, bool assign); int rdtgroup_assign_cntr_event(struct rdt_resource *r, struct rdtgroup *rd= tgrp, struct rdt_mon_domain *d, enum resctrl_event_id evtid); +int rdtgroup_unassign_cntr_event(struct rdt_resource *r, struct rdtgroup *= rdtgrp, + struct rdt_mon_domain *d, enum resctrl_event_id evtid); struct mbm_state *get_mbm_state(struct rdt_mon_domain *d, u32 closid, u32 rmid, enum resctrl_event_id evtid); #endif /* _ASM_X86_RESCTRL_INTERNAL_H */ diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 1c8694a68cf4..a71a8389b649 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1990,6 +1990,20 @@ static void mbm_cntr_free(struct rdt_resource *r, st= ruct rdt_mon_domain *d, } } =20 +static int mbm_cntr_get(struct rdt_resource *r, struct rdt_mon_domain *d, + struct rdtgroup *rdtgrp, enum resctrl_event_id evtid) +{ + int cntr_id; + + for (cntr_id =3D 0; cntr_id < r->mon.num_mbm_cntrs; cntr_id++) { + if (d->cntr_cfg[cntr_id].rdtgrp =3D=3D rdtgrp && + d->cntr_cfg[cntr_id].evtid =3D=3D evtid) + return cntr_id; + } + + return -EINVAL; +} + /* * Assign a hardware counter to event @evtid of group @rdtgrp. * Counter will be assigned to all the domains if rdt_mon_domain is NULL @@ -2037,6 +2051,44 @@ int rdtgroup_assign_cntr_event(struct rdt_resource *= r, struct rdtgroup *rdtgrp, return ret; } =20 +/* + * Unassign a hardware counter associated with @evtid from the domain and + * the group. Unassign the counters from all the domains if rdt_mon_domain + * is NULL else unassign from the specific domain. + */ +int rdtgroup_unassign_cntr_event(struct rdt_resource *r, struct rdtgroup *= rdtgrp, + struct rdt_mon_domain *d, enum resctrl_event_id evtid) +{ + int cntr_id, ret =3D 0; + + if (!d) { + list_for_each_entry(d, &r->mon_domains, hdr.list) { + if (!mbm_cntr_assigned(r, d, rdtgrp, evtid)) + continue; + + cntr_id =3D mbm_cntr_get(r, d, rdtgrp, evtid); + + ret =3D resctrl_config_cntr(r, d, evtid, rdtgrp->mon.rmid, + rdtgrp->closid, cntr_id, false); + if (!ret) + mbm_cntr_free(r, d, rdtgrp, evtid); + } + } else { + if (!mbm_cntr_assigned(r, d, rdtgrp, evtid)) + goto out_done_unassign; + + cntr_id =3D mbm_cntr_get(r, d, rdtgrp, evtid); + + ret =3D resctrl_config_cntr(r, d, evtid, rdtgrp->mon.rmid, + rdtgrp->closid, cntr_id, false); + if (!ret) + mbm_cntr_free(r, d, rdtgrp, evtid); + } + +out_done_unassign: + return ret; +} + /* rdtgroup information files for one cache resource. */ static struct rftype res_common_files[] =3D { { --=20 2.34.1 From nobody Sun Dec 14 19:11:44 2025 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2063.outbound.protection.outlook.com [40.107.94.63]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 384AE1DE4D9; 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Thu, 12 Dec 2024 14:18:25 -0600 From: Babu Moger To: , , , , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v10 18/24] x86/resctrl: Auto assign/unassign counters when mbm_cntr_assign is enabled Date: Thu, 12 Dec 2024 14:15:21 -0600 Message-ID: <35e1b0915fe08bb0ef093e23ca3d520fc6aa32ab.1734034524.git.babu.moger@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B074:EE_|MN6PR12MB8566:EE_ X-MS-Office365-Filtering-Correlation-Id: da5bbdd9-597a-4006-9aa5-08dd1aea23ab X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|7416014|82310400026; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Dec 2024 20:18:27.8971 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: da5bbdd9-597a-4006-9aa5-08dd1aea23ab X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B074.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN6PR12MB8566 Content-Type: text/plain; charset="utf-8" Assign/unassign counters on resctrl group creation/deletion. Two counters are required per group, one for MBM total event and one for MBM local event. There are a limited number of counters available for assignment. If these counters are exhausted, the kernel will display the error message: "Out of MBM assignable counters". However, it is not necessary to fail the creation of a group due to assignment failures. Users have the flexibility to modify the assignments at a later time. Signed-off-by: Babu Moger --- v10: Assigned the counter before exposing the event files. Moved the call rdtgroup_assign_cntrs() inside mkdir_rdt_prepare_rmid_al= loc(). This is called both CNTR_MON and MON group creation. Call mbm_cntr_reset() when unmounted to clear all the assignments. Taken care of few other feedback comments. v9: Changed rdtgroup_assign_cntrs() and rdtgroup_unassign_cntrs() to return= void. Updated couple of rdtgroup_unassign_cntrs() calls properly. Updated function comments. v8: Renamed rdtgroup_assign_grp to rdtgroup_assign_cntrs. Renamed rdtgroup_unassign_grp to rdtgroup_unassign_cntrs. Fixed the problem with unassigning the child MON groups of CTRL_MON gro= up. v7: Reworded the commit message. Removed the reference of ABMC with mbm_cntr_assign. Renamed the function rdtgroup_assign_cntrs to rdtgroup_assign_grp. v6: Removed the redundant comments on all the calls of rdtgroup_assign_cntrs. Updated the commit message. Dropped printing error message on every call of rdtgroup_assign_cntrs. v5: Removed the code to enable/disable ABMC during the mount. That will be another patch. Added arch callers to get the arch specific data. Renamed fuctions to match the other abmc function. Added code comments for assignment failures. v4: Few name changes based on the upstream discussion. Commit message update. v3: This is a new patch. Patch addresses the upstream comment to enable ABMC feature by default if the feature is available. --- arch/x86/kernel/cpu/resctrl/rdtgroup.c | 81 +++++++++++++++++++++++++- 1 file changed, 79 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index a71a8389b649..5acae525881a 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -920,6 +920,25 @@ static int rdtgroup_available_mbm_cntrs_show(struct ke= rnfs_open_file *of, return ret; } =20 +static void mbm_cntr_reset(struct rdt_resource *r) +{ + struct rdt_mon_domain *dom; + + /* + * Hardware counters will reset after switching the monitor mode. + * Reset the architectural state so that reading of hardware + * counter is not considered as an overflow in the next update. + * Also reset the domain counter bitmap. + */ + if (is_mbm_enabled() && r->mon.mbm_cntr_assignable) { + list_for_each_entry(dom, &r->mon_domains, hdr.list) { + memset(dom->cntr_cfg, 0, + sizeof(*dom->cntr_cfg) * r->mon.num_mbm_cntrs); + resctrl_arch_reset_rmid_all(r, dom); + } + } +} + #ifdef CONFIG_PROC_CPU_RESCTRL =20 /* @@ -2969,6 +2988,46 @@ static void schemata_list_destroy(void) } } =20 +/* + * Called when a new group is created. If "mbm_cntr_assign" mode is enable= d, + * counters are automatically assigned. Each group can accommodate two cou= nters: + * one for the total event and one for the local event. Assignments may fa= il + * due to the limited number of counters. However, it is not necessary to = fail + * the group creation and thus no failure is returned. Users have the opti= on + * to modify the counter assignments after the group has been created. + */ +static void rdtgroup_assign_cntrs(struct rdtgroup *rdtgrp) +{ + struct rdt_resource *r =3D &rdt_resources_all[RDT_RESOURCE_L3].r_resctrl; + + if (!resctrl_arch_mbm_cntr_assign_enabled(r)) + return; + + if (is_mbm_total_enabled()) + rdtgroup_assign_cntr_event(r, rdtgrp, NULL, QOS_L3_MBM_TOTAL_EVENT_ID); + + if (is_mbm_local_enabled()) + rdtgroup_assign_cntr_event(r, rdtgrp, NULL, QOS_L3_MBM_LOCAL_EVENT_ID); +} + +/* + * Called when a group is deleted. Counters are unassigned if it was in + * assigned state. + */ +static void rdtgroup_unassign_cntrs(struct rdtgroup *rdtgrp) +{ + struct rdt_resource *r =3D &rdt_resources_all[RDT_RESOURCE_L3].r_resctrl; + + if (!resctrl_arch_mbm_cntr_assign_enabled(r)) + return; + + if (is_mbm_total_enabled()) + rdtgroup_unassign_cntr_event(r, rdtgrp, NULL, QOS_L3_MBM_TOTAL_EVENT_ID); + + if (is_mbm_local_enabled()) + rdtgroup_unassign_cntr_event(r, rdtgrp, NULL, QOS_L3_MBM_LOCAL_EVENT_ID); +} + static int rdt_get_tree(struct fs_context *fc) { struct rdt_fs_context *ctx =3D rdt_fc2context(fc); @@ -3023,6 +3082,8 @@ static int rdt_get_tree(struct fs_context *fc) if (ret < 0) goto out_info; =20 + rdtgroup_assign_cntrs(&rdtgroup_default); + ret =3D mkdir_mondata_all(rdtgroup_default.kn, &rdtgroup_default, &kn_mondata); if (ret < 0) @@ -3058,8 +3119,10 @@ static int rdt_get_tree(struct fs_context *fc) out_psl: rdt_pseudo_lock_release(); out_mondata: - if (resctrl_arch_mon_capable()) + if (resctrl_arch_mon_capable()) { kernfs_remove(kn_mondata); + rdtgroup_unassign_cntrs(&rdtgroup_default); + } out_mongrp: if (resctrl_arch_mon_capable()) kernfs_remove(kn_mongrp); @@ -3238,6 +3301,7 @@ static void free_all_child_rdtgrp(struct rdtgroup *rd= tgrp) =20 head =3D &rdtgrp->mon.crdtgrp_list; list_for_each_entry_safe(sentry, stmp, head, mon.crdtgrp_list) { + rdtgroup_unassign_cntrs(sentry); free_rmid(sentry->closid, sentry->mon.rmid); list_del(&sentry->mon.crdtgrp_list); =20 @@ -3278,6 +3342,8 @@ static void rmdir_all_sub(void) cpumask_or(&rdtgroup_default.cpu_mask, &rdtgroup_default.cpu_mask, &rdtgrp->cpu_mask); =20 + rdtgroup_unassign_cntrs(rdtgrp); + free_rmid(rdtgrp->closid, rdtgrp->mon.rmid); =20 kernfs_remove(rdtgrp->kn); @@ -3309,6 +3375,8 @@ static void rdt_kill_sb(struct super_block *sb) for_each_alloc_capable_rdt_resource(r) reset_all_ctrls(r); rmdir_all_sub(); + rdtgroup_unassign_cntrs(&rdtgroup_default); + mbm_cntr_reset(&rdt_resources_all[RDT_RESOURCE_L3].r_resctrl); rdt_pseudo_lock_release(); rdtgroup_default.mode =3D RDT_MODE_SHAREABLE; schemata_list_destroy(); @@ -3772,6 +3840,8 @@ static int mkdir_rdt_prepare_rmid_alloc(struct rdtgro= up *rdtgrp) } rdtgrp->mon.rmid =3D ret; =20 + rdtgroup_assign_cntrs(rdtgrp); + ret =3D mkdir_mondata_all(rdtgrp->kn, rdtgrp, &rdtgrp->mon.mon_data_kn); if (ret) { rdt_last_cmd_puts("kernfs subdir error\n"); @@ -3784,8 +3854,10 @@ static int mkdir_rdt_prepare_rmid_alloc(struct rdtgr= oup *rdtgrp) =20 static void mkdir_rdt_prepare_rmid_free(struct rdtgroup *rgrp) { - if (resctrl_arch_mon_capable()) + if (resctrl_arch_mon_capable()) { + rdtgroup_unassign_cntrs(rgrp); free_rmid(rgrp->closid, rgrp->mon.rmid); + } } =20 static int mkdir_rdt_prepare(struct kernfs_node *parent_kn, @@ -4044,6 +4116,9 @@ static int rdtgroup_rmdir_mon(struct rdtgroup *rdtgrp= , cpumask_var_t tmpmask) update_closid_rmid(tmpmask, NULL); =20 rdtgrp->flags =3D RDT_DELETED; + + rdtgroup_unassign_cntrs(rdtgrp); + free_rmid(rdtgrp->closid, rdtgrp->mon.rmid); =20 /* @@ -4090,6 +4165,8 @@ static int rdtgroup_rmdir_ctrl(struct rdtgroup *rdtgr= p, cpumask_var_t tmpmask) cpumask_or(tmpmask, tmpmask, &rdtgrp->cpu_mask); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Dec 2024 20:18:35.3495 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a0b6a51d-2ad2-4548-bf17-08dd1aea281c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B077.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB8345 Content-Type: text/plain; charset="utf-8" In mbm_cntr_assign mode, the hardware counter should be assigned to read the MBM events. Report 'Unassigned' in case the user attempts to read the events without assigning the counter. Signed-off-by: Babu Moger --- v10: Moved the code to check the assign state inside mon_event_read(). Fixed few text comments. v9: Used is_mbm_event() to check the event type. Minor user documentation update. v8: Used MBM_EVENT_ARRAY_INDEX to get the index for the MBM event. Documentation update to make the text generic. v7: Moved the documentation under "mon_data". Updated the text little bit. v6: Added more explaination in the resctrl.rst Added checks to detect "Unassigned" before reading RMID. v5: New patch. --- Documentation/arch/x86/resctrl.rst | 10 ++++++++++ arch/x86/kernel/cpu/resctrl/ctrlmondata.c | 8 ++++++++ arch/x86/kernel/cpu/resctrl/internal.h | 2 ++ arch/x86/kernel/cpu/resctrl/rdtgroup.c | 4 ++-- 4 files changed, 22 insertions(+), 2 deletions(-) diff --git a/Documentation/arch/x86/resctrl.rst b/Documentation/arch/x86/re= sctrl.rst index c075fcee96b7..3ec14c314606 100644 --- a/Documentation/arch/x86/resctrl.rst +++ b/Documentation/arch/x86/resctrl.rst @@ -430,6 +430,16 @@ When monitoring is enabled all MON groups will also co= ntain: for the L3 cache they occupy). These are named "mon_sub_L3_YY" where "YY" is the node number. =20 + When supported the mbm_cntr_assign mode allows users to assign a + counter to mon_hw_id, event pair enabling bandwidth monitoring for + as long as the counter remains assigned. The hardware will continue + tracking the assigned mon_hw_id until the user manually unassigns + it, ensuring that counters are not reset during this period. With + a limited number of counters, the system may run out of assignable + counters. In that case, MBM event counters will return 'Unassigned' + when the event is read. Users must manually assign a counter to read + the events. + "mon_hw_id": Available only with debug option. The identifier used by hardware for the monitor group. On x86 this is the RMID. diff --git a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c b/arch/x86/kernel/cp= u/resctrl/ctrlmondata.c index 200d89a64027..8e265a86e524 100644 --- a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c +++ b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c @@ -527,6 +527,12 @@ void mon_event_read(struct rmid_read *rr, struct rdt_r= esource *r, /* When picking a CPU from cpu_mask, ensure it can't race with cpuhp */ lockdep_assert_cpus_held(); =20 + if (resctrl_arch_mbm_cntr_assign_enabled(r) && is_mbm_event(evtid) && + !mbm_cntr_assigned(r, d, rdtgrp, evtid)) { + rr->err =3D -ENOENT; + return; + } + /* * Setup the parameters to pass to mon_event_count() to read the data. */ @@ -618,6 +624,8 @@ int rdtgroup_mondata_show(struct seq_file *m, void *arg) seq_puts(m, "Error\n"); else if (rr.err =3D=3D -EINVAL) seq_puts(m, "Unavailable\n"); + else if (rr.err =3D=3D -ENOENT) + seq_puts(m, "Unassigned\n"); else seq_printf(m, "%llu\n", rr.val); =20 diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index f858098dbe4b..bb3213a7993e 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -710,4 +710,6 @@ int rdtgroup_unassign_cntr_event(struct rdt_resource *r= , struct rdtgroup *rdtgrp struct rdt_mon_domain *d, enum resctrl_event_id evtid); struct mbm_state *get_mbm_state(struct rdt_mon_domain *d, u32 closid, u32 rmid, enum resctrl_event_id evtid); +bool mbm_cntr_assigned(struct rdt_resource *r, struct rdt_mon_domain *d, + struct rdtgroup *rdtgrp, enum resctrl_event_id evtid); #endif /* _ASM_X86_RESCTRL_INTERNAL_H */ diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 5acae525881a..8d00b1689a80 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1967,8 +1967,8 @@ static int resctrl_config_cntr(struct rdt_resource *r= , struct rdt_mon_domain *d, return ret; } =20 -static bool mbm_cntr_assigned(struct rdt_resource *r, struct rdt_mon_domai= n *d, - struct rdtgroup *rdtgrp, enum resctrl_event_id evtid) +bool mbm_cntr_assigned(struct rdt_resource *r, struct rdt_mon_domain *d, + struct rdtgroup *rdtgrp, enum resctrl_event_id evtid) { int cntr_id; =20 --=20 2.34.1 From nobody Sun Dec 14 19:11:44 2025 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2086.outbound.protection.outlook.com [40.107.223.86]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8ACB61D5AC0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Dec 2024 20:18:43.2936 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ed12f373-6ff8-4d4e-ed61-08dd1aea2cd8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B072.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB7752 Content-Type: text/plain; charset="utf-8" Introduce interface to switch between mbm_cntr_assign and default modes. $ cat /sys/fs/resctrl/info/L3_MON/mbm_assign_mode [mbm_cntr_assign] default To enable the "mbm_cntr_assign" mode: $ echo "mbm_cntr_assign" > /sys/fs/resctrl/info/L3_MON/mbm_assign_mode To enable the default monitoring mode: $ echo "default" > /sys/fs/resctrl/info/L3_MON/mbm_assign_mode MBM event counters will reset when mbm_assign_mode is changed. Signed-off-by: Babu Moger --- v10: The call mbm_cntr_reset() has been moved to earlier patch. Minor documentation update. v9: Fixed extra spaces in user documentation. Fixed problem changing the mode to mbm_cntr_assign mode when it is not supported. Added extra checks to detect if systems supports it. Used the rdtgroup_cntr_id_init to initialize cntr_id. v8: Reset the internal counters after mbm_cntr_assign mode is changed. Renamed rdtgroup_mbm_cntr_reset() to mbm_cntr_reset() Updated the documentation to make text generic. v7: Changed the interface name to mbm_assign_mode. Removed the references of ABMC. Added the changes to reset global and domain bitmaps. Added the changes to reset rmid. v6: Changed the mode name to mbm_cntr_assign. Moved all the FS related code here. Added changes to reset mbm_cntr_map and resctrl group counters. v5: Change log and mode description text correction. v4: Minor commit text changes. Keep the default to ABMC when supported. Fixed comments to reflect changed interface "mbm_mode". v3: New patch to address the review comments from upstream. --- Documentation/arch/x86/resctrl.rst | 15 ++++++++ arch/x86/kernel/cpu/resctrl/rdtgroup.c | 50 +++++++++++++++++++++++++- 2 files changed, 64 insertions(+), 1 deletion(-) diff --git a/Documentation/arch/x86/resctrl.rst b/Documentation/arch/x86/re= sctrl.rst index 3ec14c314606..d3a8a34cf629 100644 --- a/Documentation/arch/x86/resctrl.rst +++ b/Documentation/arch/x86/resctrl.rst @@ -290,6 +290,21 @@ with the following files: "mbm_total_bytes" or "mbm_local_bytes" will report 'Unavailable' if there is no counter associated with that event. =20 + * To enable "mbm_cntr_assign" mode: + :: + + # echo "mbm_cntr_assign" > /sys/fs/resctrl/info/L3_MON/mbm_assign_mode + + * To enable default monitoring mode: + :: + + # echo "default" > /sys/fs/resctrl/info/L3_MON/mbm_assign_mode + + The MBM events (mbm_total_bytes and/or mbm_local_bytes) associated with + counters may reset when "mbm_assign_mode" is changed. Moving to + mbm_cntr_assign mode require users to assign the counters to the events. + Otherwise, the MBM event counters will return "Unassigned" when read. + "num_mbm_cntrs": The number of monitoring counters available for assignment when the architecture supports mbm_cntr_assign mode. diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 8d00b1689a80..eea534cce3d0 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -939,6 +939,53 @@ static void mbm_cntr_reset(struct rdt_resource *r) } } =20 +static ssize_t rdtgroup_mbm_assign_mode_write(struct kernfs_open_file *of, + char *buf, size_t nbytes, loff_t off) +{ + struct rdt_resource *r =3D of->kn->parent->priv; + int ret =3D 0; + bool enable; + + /* Valid input requires a trailing newline */ + if (nbytes =3D=3D 0 || buf[nbytes - 1] !=3D '\n') + return -EINVAL; + + buf[nbytes - 1] =3D '\0'; + + cpus_read_lock(); + mutex_lock(&rdtgroup_mutex); + + rdt_last_cmd_clear(); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Dec 2024 20:18:51.0143 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a3266a27-c9aa-402a-ff9b-08dd1aea3172 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B073.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB8175 Content-Type: text/plain; charset="utf-8" Configure mbm_cntr_assign on AMD. 'mbm_cntr_assign' mode in AMD is ABMC (Assignable Bandwidth Monitoring Counters). It is enabled by default when supported on the system. Ensure that the ABMC is updated on all logical processors in the resctrl domain. Signed-off-by: Babu Moger --- v10: Commit text in imperative tone. v9: Minor code change due to merge. Actual code did not change. v8: Renamed resctrl_arch_mbm_cntr_assign_configure to resctrl_arch_mbm_cntr_assign_set_one. Adde r->mon_capable check. Commit message update. v7: Introduced resctrl_arch_mbm_cntr_assign_configure() to configure. Moved the default settings to rdt_get_mon_l3_config(). It should be done before the hotplug handler is called. It cannot be done at rdtgroup_init(). v6: Keeping the default enablement in arch init code for now. This may need some discussion. Renamed resctrl_arch_configure_abmc to resctrl_arch_mbm_cntr_assign_co= nfigure. v5: New patch to enable ABMC by default. --- arch/x86/kernel/cpu/resctrl/internal.h | 1 + arch/x86/kernel/cpu/resctrl/monitor.c | 1 + arch/x86/kernel/cpu/resctrl/rdtgroup.c | 11 +++++++++++ 3 files changed, 13 insertions(+) diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index bb3213a7993e..1ca51f68a523 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -712,4 +712,5 @@ struct mbm_state *get_mbm_state(struct rdt_mon_domain *= d, u32 closid, u32 rmid, enum resctrl_event_id evtid); bool mbm_cntr_assigned(struct rdt_resource *r, struct rdt_mon_domain *d, struct rdtgroup *rdtgrp, enum resctrl_event_id evtid); +void resctrl_arch_mbm_cntr_assign_set_one(struct rdt_resource *r); #endif /* _ASM_X86_RESCTRL_INTERNAL_H */ diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/re= sctrl/monitor.c index 8823cd97ff1f..845636a205bf 100644 --- a/arch/x86/kernel/cpu/resctrl/monitor.c +++ b/arch/x86/kernel/cpu/resctrl/monitor.c @@ -1237,6 +1237,7 @@ int __init rdt_get_mon_l3_config(struct rdt_resource = *r) r->mon.mbm_cntr_assignable =3D true; cpuid_count(0x80000020, 5, &eax, &ebx, &ecx, &edx); r->mon.num_mbm_cntrs =3D (ebx & GENMASK(15, 0)) + 1; + hw_res->mbm_cntr_assign_enabled =3D true; resctrl_file_fflags_init("num_mbm_cntrs", RFTYPE_MON_INFO); resctrl_file_fflags_init("available_mbm_cntrs", RFTYPE_MON_INFO); } diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index eea534cce3d0..65b3556978ad 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -2824,6 +2824,13 @@ int resctrl_arch_mbm_cntr_assign_set(struct rdt_reso= urce *r, bool enable) return 0; } =20 +void resctrl_arch_mbm_cntr_assign_set_one(struct rdt_resource *r) +{ + struct rdt_hw_resource *hw_res =3D resctrl_to_arch_res(r); + + resctrl_abmc_set_one_amd(&hw_res->mbm_cntr_assign_enabled); +} + /* * We don't allow rdtgroup directories to be created anywhere * except the root directory. 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Dec 2024 20:18:58.9656 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0eb0431b-c2dd-4571-46f7-08dd1aea3630 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B072.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8754 Content-Type: text/plain; charset="utf-8" Resctrl provides option to configure events by writing to the interfaces /sys/fs/resctrl/info/L3_MON/mbm_total_bytes_config or /sys/fs/resctrl/info/L3_MON/mbm_local_bytes_config when BMEC (Bandwidth Monitoring Event Configuration) is supported. Whenever the event configuration is updated, MBM assignments must be revised across all monitor groups within the impacted domains. Signed-off-by: Babu Moger --- v10: Code changed completely with domain specific counter assignment. Rewrite the commit message. Added few more code comments. v9: Again patch changed completely based on the comment. https://lore.kernel.org/lkml/03b278b5-6c15-4d09-9ab7-3317e84a409e@intel= .com/ Introduced resctrl_mon_event_config_set to handle IPI. But sending another IPI inside IPI causes problem. Kernel reports SMP warning. So, introduced resctrl_arch_update_cntr() to send the command = directly. v8: Patch changed completely. Updated the assignment on same IPI as the event is updated. Could not do the way we discussed in the thread. https://lore.kernel.org/lkml/f77737ac-d3f6-3e4b-3565-564f79c86ca8@amd.c= om/ Needed to figure out event type to update the configuration. v7: New patch to update the assignments. Missed it earlier. --- arch/x86/kernel/cpu/resctrl/rdtgroup.c | 67 ++++++++++++++++++++++---- include/linux/resctrl.h | 4 +- 2 files changed, 61 insertions(+), 10 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 65b3556978ad..6b5c886b7e99 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1704,26 +1704,26 @@ u32 resctrl_arch_mon_event_config_get(struct rdt_mo= n_domain *d, return INVALID_CONFIG_VALUE; } =20 -void resctrl_arch_mon_event_config_set(void *info) +void resctrl_arch_mon_event_config_set(struct rdt_mon_domain *d, + enum resctrl_event_id eventid, u32 val) { - struct mon_config_info *mon_info =3D info; struct rdt_hw_mon_domain *hw_dom; unsigned int index; =20 - index =3D mon_event_config_index_get(mon_info->evtid); + index =3D mon_event_config_index_get(eventid); if (index =3D=3D INVALID_CONFIG_INDEX) return; =20 - wrmsr(MSR_IA32_EVT_CFG_BASE + index, mon_info->mon_config, 0); + wrmsr(MSR_IA32_EVT_CFG_BASE + index, val, 0); =20 - hw_dom =3D resctrl_to_arch_mon_dom(mon_info->d); + hw_dom =3D resctrl_to_arch_mon_dom(d); =20 - switch (mon_info->evtid) { + switch (eventid) { case QOS_L3_MBM_TOTAL_EVENT_ID: - hw_dom->mbm_total_cfg =3D mon_info->mon_config; + hw_dom->mbm_total_cfg =3D val; break; case QOS_L3_MBM_LOCAL_EVENT_ID: - hw_dom->mbm_local_cfg =3D mon_info->mon_config; + hw_dom->mbm_local_cfg =3D val; break; default: break; @@ -1825,6 +1825,54 @@ static int mbm_local_bytes_config_show(struct kernfs= _open_file *of, return 0; } =20 +/* + * Review the cntr_cfg domain configuration. If a matching assignment is f= ound, + * update the counter assignment accordingly. This is within the IPI Conte= xt, + * so call resctrl_abmc_config_one_amd directly. + */ +static void resctrl_arch_update_cntr(struct rdt_resource *r, struct rdt_mo= n_domain *d, + enum resctrl_event_id evtid, u32 val) +{ + struct cntr_config config; + struct rdtgroup *rdtgrp; + struct mbm_state *m; + u32 cntr_id; + + for (cntr_id =3D 0; cntr_id < r->mon.num_mbm_cntrs; cntr_id++) { + rdtgrp =3D d->cntr_cfg[cntr_id].rdtgrp; + if (rdtgrp && d->cntr_cfg[cntr_id].evtid =3D=3D evtid) { + memset(&config, 0, sizeof(struct cntr_config)); + config.r =3D r; + config.d =3D d; + config.evtid =3D evtid; + config.rmid =3D rdtgrp->mon.rmid; + config.closid =3D rdtgrp->closid; + config.cntr_id =3D cntr_id; + config.val =3D val; + config.assign =3D 1; + + resctrl_abmc_config_one_amd(&config); + + m =3D get_mbm_state(d, rdtgrp->closid, rdtgrp->mon.rmid, evtid); + if (m) + memset(m, 0, sizeof(struct mbm_state)); + } + } +} + +static void resctrl_mon_event_config_set(void *info) +{ + struct mon_config_info *mon_info =3D info; + struct rdt_mon_domain *d =3D mon_info->d; + struct rdt_resource *r =3D mon_info->r; + + resctrl_arch_mon_event_config_set(d, mon_info->evtid, mon_info->mon_confi= g); + + /* Check if assignments needs to be updated */ + if (resctrl_arch_mbm_cntr_assign_enabled(r)) + resctrl_arch_update_cntr(r, d, mon_info->evtid, + mon_info->mon_config); +} =20 static void mbm_config_write_domain(struct rdt_resource *r, struct rdt_mon_domain *d, u32 evtid, u32 val) @@ -1840,6 +1888,7 @@ static void mbm_config_write_domain(struct rdt_resour= ce *r, if (config_val =3D=3D INVALID_CONFIG_VALUE || config_val =3D=3D val) return; =20 + mon_info.r =3D r; mon_info.d =3D d; mon_info.evtid =3D evtid; mon_info.mon_config =3D val; @@ -1851,7 +1900,7 @@ static void mbm_config_write_domain(struct rdt_resour= ce *r, * on one CPU is observed by all the CPUs in the domain. */ smp_call_function_any(&d->hdr.cpu_mask, - resctrl_arch_mon_event_config_set, + resctrl_mon_event_config_set, &mon_info, 1); =20 /* diff --git a/include/linux/resctrl.h b/include/linux/resctrl.h index 03c67d9156f3..2bf461179680 100644 --- a/include/linux/resctrl.h +++ b/include/linux/resctrl.h @@ -137,6 +137,7 @@ struct rdt_mon_domain { * @mon_config: Event configuration value */ struct mon_config_info { + struct rdt_resource *r; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Dec 2024 20:19:06.7870 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b092d480-b7a4-40f1-b897-08dd1aea3ad9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B077.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7141 Content-Type: text/plain; charset="utf-8" Provide the interface to list the assignment states of all the resctrl groups in mbm_cntr_assign mode. Example: $ mount -t resctrl resctrl /sys/fs/resctrl/ $ cat /sys/fs/resctrl/info/L3_MON/mbm_assign_control //0=3Dtl;1=3Dtl; List follows the following format: "//=3D" Format for specific type of groups: - Default CTRL_MON group: "//=3D" - Non-default CTRL_MON group: "//=3D" - Child MON group of default CTRL_MON group: "//=3D" - Child MON group of non-default CTRL_MON group: "//=3D" Flags can be one of the following: t MBM total event is assigned l MBM local event is assigned tl Both total and local MBM events are assigned _ None of the MBM events are assigned Signed-off-by: Babu Moger --- v10: Changes mostly due to domain specific counter assignment. v9: Minor parameter update in resctrl_mbm_event_assigned(). v8: Moved resctrl_mbm_event_assigned() in here as it is first used here. Moved rdt_last_cmd_clear() before making any call. Updated the commit log. Corrected the doc format. v7: Renamed the interface name from 'mbm_control' to 'mbm_assign_control' to match 'mbm_assign_mode'. Removed Arch references from FS code. Added rdt_last_cmd_clear() before the command processing. Added rdtgroup_mutex before all the calls. Removed references of ABMC from FS code. v6: The domain specific assignment can be determined looking at mbm_cntr_ma= p. Removed rdtgroup_abmc_dom_cfg() and rdtgroup_abmc_dom_state(). Removed the switch statement for the domain_state detection. Determined the flags incremently. Removed special handling of default group while printing.. v5: Replaced "assignment flags" with "flags". Changes related to mon structure. Changes related renaming the interface from mbm_assign_control to mbm_control. v4: Added functionality to query domain specific assigment in. rdtgroup_abmc_dom_state(). v3: New patch. Addresses the feedback to provide the global assignment interface. https://lore.kernel.org/lkml/c73f444b-83a1-4e9a-95d3-54c5165ee782@intel= .com/ --- Documentation/arch/x86/resctrl.rst | 44 ++++++++++++++++ arch/x86/kernel/cpu/resctrl/monitor.c | 1 + arch/x86/kernel/cpu/resctrl/rdtgroup.c | 71 ++++++++++++++++++++++++++ 3 files changed, 116 insertions(+) diff --git a/Documentation/arch/x86/resctrl.rst b/Documentation/arch/x86/re= sctrl.rst index d3a8a34cf629..9ae2b8f335dd 100644 --- a/Documentation/arch/x86/resctrl.rst +++ b/Documentation/arch/x86/resctrl.rst @@ -321,6 +321,50 @@ with the following files: The number of monitoring counters available for assignment in each domain when the architecture supports mbm_cntr_assign mode. =20 +"mbm_assign_control": + Reports the resctrl group and monitor status of each group. + + List follows the following format: + "//=3D" + + Format for specific type of groups: + + * Default CTRL_MON group: + "//=3D" + + * Non-default CTRL_MON group: + "//=3D" + + * Child MON group of default CTRL_MON group: + "//=3D" + + * Child MON group of non-default CTRL_MON group: + "//=3D" + + Flags can be one of the following: + :: + + t MBM total event is assigned. + l MBM local event is assigned. + tl Both MBM total and local events are assigned. + _ None of the MBM events are assigned. + + Examples: + :: + + # mkdir /sys/fs/resctrl/mon_groups/child_default_mon_grp + # mkdir /sys/fs/resctrl/non_default_ctrl_mon_grp + # mkdir /sys/fs/resctrl/non_default_ctrl_mon_grp/mon_groups/child_non_de= fault_mon_grp + + # cat /sys/fs/resctrl/info/L3_MON/mbm_assign_control + non_default_ctrl_mon_grp//0=3Dtl;1=3Dtl; + non_default_ctrl_mon_grp/child_non_default_mon_grp/0=3Dtl;1=3Dtl; + //0=3Dtl;1=3Dtl; + /child_default_mon_grp/0=3Dtl;1=3Dtl; + + There are four resctrl groups. All the groups have total and local MBM ev= ents + assigned on domain 0 and 1. + "max_threshold_occupancy": Read/write file provides the largest value (in bytes) at which a previously used LLC_occupancy diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/re= sctrl/monitor.c index 845636a205bf..3bb4313df92e 100644 --- a/arch/x86/kernel/cpu/resctrl/monitor.c +++ b/arch/x86/kernel/cpu/resctrl/monitor.c @@ -1240,6 +1240,7 @@ int __init rdt_get_mon_l3_config(struct rdt_resource = *r) hw_res->mbm_cntr_assign_enabled =3D true; resctrl_file_fflags_init("num_mbm_cntrs", RFTYPE_MON_INFO); resctrl_file_fflags_init("available_mbm_cntrs", RFTYPE_MON_INFO); + resctrl_file_fflags_init("mbm_assign_control", RFTYPE_MON_INFO); } } =20 diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 6b5c886b7e99..70bf590ded8a 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -986,6 +986,71 @@ static ssize_t rdtgroup_mbm_assign_mode_write(struct k= ernfs_open_file *of, return ret ?: nbytes; } =20 +static char *rdtgroup_mon_state_to_str(struct rdt_resource *r, + struct rdt_mon_domain *d, + struct rdtgroup *rdtgrp, char *str) +{ + char *tmp =3D str; + + /* Query the total and local event flags for the domain */ + if (mbm_cntr_assigned(r, d, rdtgrp, QOS_L3_MBM_TOTAL_EVENT_ID)) + *tmp++ =3D 't'; + + if (mbm_cntr_assigned(r, d, rdtgrp, QOS_L3_MBM_LOCAL_EVENT_ID)) + *tmp++ =3D 'l'; + + if (tmp =3D=3D str) + *tmp++ =3D '_'; + + *tmp =3D '\0'; + return str; +} + +static int rdtgroup_mbm_assign_control_show(struct kernfs_open_file *of, + struct seq_file *s, void *v) +{ + struct rdt_resource *r =3D of->kn->parent->priv; + struct rdt_mon_domain *dom; + struct rdtgroup *rdtg; + char str[10]; + + cpus_read_lock(); + mutex_lock(&rdtgroup_mutex); + rdt_last_cmd_clear(); + + if (!resctrl_arch_mbm_cntr_assign_enabled(r)) { + rdt_last_cmd_puts("mbm_cntr_assign mode is not enabled\n"); + mutex_unlock(&rdtgroup_mutex); + cpus_read_unlock(); + return -EINVAL; + } + + list_for_each_entry(rdtg, &rdt_all_groups, rdtgroup_list) { + struct rdtgroup *crg; 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Thu, 12 Dec 2024 14:19:12 -0600 From: Babu Moger To: , , , , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v10 24/24] x86/resctrl: Introduce interface to modify assignment states of the groups Date: Thu, 12 Dec 2024 14:15:27 -0600 Message-ID: <2da72f1a57beb1f3de5cb2bdeda2269bdade8c76.1734034524.git.babu.moger@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B074:EE_|CH2PR12MB9520:EE_ X-MS-Office365-Filtering-Correlation-Id: 96071d37-bcac-4360-237b-08dd1aea3f89 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|36860700013|82310400026; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Dec 2024 20:19:14.6475 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 96071d37-bcac-4360-237b-08dd1aea3f89 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B074.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB9520 Introduce the interface to assign MBM events in mbm_cntr_assign mode. Events can be enabled or disabled by writing to file /sys/fs/resctrl/info/L3_MON/mbm_assign_control Format is similar to the list format with addition of opcode for the assignment operation. "//" Format for specific type of groups: * Default CTRL_MON group: "//" * Non-default CTRL_MON group: "//" * Child MON group of default CTRL_MON group: "//" * Child MON group of non-default CTRL_MON group: "//" Domain_id '*' will apply the flags on all the domains. Opcode can be one of the following: =3D Update the assignment to match the flags + Assign a new MBM event without impacting existing assignments. - Unassign a MBM event from currently assigned events. Assignment flags can be one of the following: t MBM total event l MBM local event tl Both total and local MBM events _ None of the MBM events. Valid only with '=3D' opcode. This flag cannot be combined with other flags. Signed-off-by: Babu Moger --- v10: Fixed the issue with finding the domain in multiple iterations. Printed error message with domain information when assign fails. Changed the variables to unsigned for processing assign state. Taken care of few format corrections. v9: Fixed handling special case '//0=3D' and '//". Removed extra strstr() call. Added generic failure text when assignment operation fails. Corrected user documentation format texts. v8: Moved unassign as the first action during the assign modification. Assign none "_" takes priority. Cannot be mixed with other flags. Updated the documentation and .rst file format. htmldoc looks ok. v7: Simplified the parsing (strsep(&token, "//") in rdtgroup_mbm_assign_con= trol_write(). Added mutex lock in rdtgroup_mbm_assign_control_write() while processin= g. Renamed rdtgroup_find_grp to rdtgroup_find_grp_by_name. Fixed rdtgroup_str_to_mon_state to return error for invalid flags. Simplified the calls rdtgroup_assign_cntr by merging few functions earl= ier. Removed ABMC reference in FS code. Reinette commented about handling the combination of flags like 'lt_' a= nd '_lt'. Not sure if we need to change the behaviour here. Processed them sequen= cially right now. Users have the liberty to pass the flags. Restricting it might be a pro= blem later. v6: Added support assign all if domain id is '*' Fixed the allocation of counter id if it not assigned already. v5: Interface name changed from mbm_assign_control to mbm_control. Fixed opcode and flags combination. '=3D_" is valid. "-_" amd "+_" is not valid. Minor message update. Renamed the function with prefix - rdtgroup_. Corrected few documentation mistakes. Rebase related changes after SNC support. v4: Added domain specific assignments. Fixed the opcode parsing. v3: New patch. Addresses the feedback to provide the global assignment interface. --- Documentation/arch/x86/resctrl.rst | 116 +++++++++++- arch/x86/kernel/cpu/resctrl/internal.h | 10 + arch/x86/kernel/cpu/resctrl/rdtgroup.c | 241 ++++++++++++++++++++++++- 3 files changed, 365 insertions(+), 2 deletions(-) diff --git a/Documentation/arch/x86/resctrl.rst b/Documentation/arch/x86/re= sctrl.rst index 9ae2b8f335dd..3bb7c11df59d 100644 --- a/Documentation/arch/x86/resctrl.rst +++ b/Documentation/arch/x86/resctrl.rst @@ -347,7 +347,8 @@ with the following files: t MBM total event is assigned. l MBM local event is assigned. tl Both MBM total and local events are assigned. - _ None of the MBM events are assigned. + _ None of the MBM events are assigned. Only works with opcode '=3D' for= write + and cannot be combined with other flags. =20 Examples: :: @@ -365,6 +366,119 @@ with the following files: There are four resctrl groups. All the groups have total and local MBM ev= ents assigned on domain 0 and 1. =20 + Assignment state can be updated by writing to "mbm_assign_control". + + Format is similar to the list format with addition of opcode for the + assignment operation. + + "//" + + Format for each type of group: + + * Default CTRL_MON group: + "//" + + * Non-default CTRL_MON group: + "//" + + * Child MON group of default CTRL_MON group: + "//" + + * Child MON group of non-default CTRL_MON group: + "//" + + Domain_id '*' will apply the flags to all the domains. + + Opcode can be one of the following: + :: + + =3D Update the assignment to match the MBM event. + + Assign a new MBM event without impacting existing assignments. + - Unassign a MBM event from currently assigned events. + + Examples: + Initial group status: + :: + + # cat /sys/fs/resctrl/info/L3_MON/mbm_assign_control + non_default_ctrl_mon_grp//0=3Dtl;1=3Dtl; + non_default_ctrl_mon_grp/child_non_default_mon_grp/0=3Dtl;1=3Dtl; + //0=3Dtl;1=3Dtl; + /child_default_mon_grp/0=3Dtl;1=3Dtl; + + To update the default group to assign only total MBM event on domain 0: + :: + + # echo "//0=3Dt" > /sys/fs/resctrl/info/L3_MON/mbm_assign_control + + Assignment status after the update: + :: + + # cat /sys/fs/resctrl/info/L3_MON/mbm_assign_control + non_default_ctrl_mon_grp//0=3Dtl;1=3Dtl; + non_default_ctrl_mon_grp/child_non_default_mon_grp/0=3Dtl;1=3Dtl; + //0=3Dt;1=3Dtl; + /child_default_mon_grp/0=3Dtl;1=3Dtl; + + To update the MON group child_default_mon_grp to remove total MBM event o= n domain 1: + :: + + # echo "/child_default_mon_grp/1-t" > /sys/fs/resctrl/info/L3_MON/mbm_a= ssign_control + + Assignment status after the update: + :: + + # cat /sys/fs/resctrl/info/L3_MON/mbm_assign_control + non_default_ctrl_mon_grp//0=3Dtl;1=3Dtl; + non_default_ctrl_mon_grp/child_non_default_mon_grp/0=3Dtl;1=3Dtl; + //0=3Dt;1=3Dtl; + /child_default_mon_grp/0=3Dtl;1=3Dl; + + To update the MON group non_default_ctrl_mon_grp/child_non_default_mon_gr= p to unassign + both local and total MBM events on domain 1: + :: + + # echo "non_default_ctrl_mon_grp/child_non_default_mon_grp/1=3D_" > + /sys/fs/resctrl/info/L3_MON/mbm_assign_control + + Assignment status after the update: + :: + + # cat /sys/fs/resctrl/info/L3_MON/mbm_assign_control + non_default_ctrl_mon_grp//0=3Dtl;1=3Dtl; + non_default_ctrl_mon_grp/child_non_default_mon_grp/0=3Dtl;1=3D_; + //0=3Dt;1=3Dtl; + /child_default_mon_grp/0=3Dtl;1=3Dl; + + To update the default group to add a local MBM event domain 0: + :: + + # echo "//0+l" > /sys/fs/resctrl/info/L3_MON/mbm_assign_control + + Assignment status after the update: + :: + + # cat /sys/fs/resctrl/info/L3_MON/mbm_assign_control + non_default_ctrl_mon_grp//0=3Dtl;1=3Dtl; + non_default_ctrl_mon_grp/child_non_default_mon_grp/0=3Dtl;1=3D_; + //0=3Dtl;1=3Dtl; + /child_default_mon_grp/0=3Dtl;1=3Dl; + + To update the non default CTRL_MON group non_default_ctrl_mon_grp to unas= sign all the + MBM events on all the domains: + :: + + # echo "non_default_ctrl_mon_grp//*=3D_" > /sys/fs/resctrl/info/L3_MON/= mbm_assign_control + + Assignment status after the update: + :: + + # cat /sys/fs/resctrl/info/L3_MON/mbm_assign_control + non_default_ctrl_mon_grp//0=3D_;1=3D_; + non_default_ctrl_mon_grp/child_non_default_mon_grp/0=3Dtl;1=3D_; + //0=3Dtl;1=3Dtl; + /child_default_mon_grp/0=3Dtl;1=3Dl; + "max_threshold_occupancy": Read/write file provides the largest value (in bytes) at which a previously used LLC_occupancy diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index 1ca51f68a523..f433e31a5e87 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -62,6 +62,16 @@ /* Setting bit 0 in L3_QOS_EXT_CFG enables the ABMC feature. */ #define ABMC_ENABLE_BIT 0 =20 +/* + * Assignment flags for mbm_cntr_assign mode + */ +enum { + ASSIGN_NONE =3D 0, + ASSIGN_TOTAL =3D BIT(QOS_L3_MBM_TOTAL_EVENT_ID), + ASSIGN_LOCAL =3D BIT(QOS_L3_MBM_LOCAL_EVENT_ID), + ASSIGN_INVALID, +}; + /** * cpumask_any_housekeeping() - Choose any CPU in @mask, preferring those = that * aren't marked nohz_full diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 70bf590ded8a..61a552974f13 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1051,6 +1051,244 @@ static int rdtgroup_mbm_assign_control_show(struct = kernfs_open_file *of, return 0; } =20 +static unsigned int rdtgroup_str_to_mon_state(char *flag) +{ + unsigned int i, mon_state =3D ASSIGN_NONE; + + if (!strlen(flag)) + return ASSIGN_INVALID; + + for (i =3D 0; i < strlen(flag); i++) { + switch (*(flag + i)) { + case 't': + mon_state |=3D ASSIGN_TOTAL; + break; + case 'l': + mon_state |=3D ASSIGN_LOCAL; + break; + case '_': + return ASSIGN_NONE; + default: + return ASSIGN_INVALID; + } + } + + return mon_state; +} + +static struct rdtgroup *rdtgroup_find_grp_by_name(enum rdt_group_type rtyp= e, + char *p_grp, char *c_grp) +{ + struct rdtgroup *rdtg, *crg; + + if (rtype =3D=3D RDTCTRL_GROUP && *p_grp =3D=3D '\0') { + return &rdtgroup_default; + } else if (rtype =3D=3D RDTCTRL_GROUP) { + list_for_each_entry(rdtg, &rdt_all_groups, rdtgroup_list) + if (!strcmp(p_grp, rdtg->kn->name)) + return rdtg; + } else if (rtype =3D=3D RDTMON_GROUP) { + list_for_each_entry(rdtg, &rdt_all_groups, rdtgroup_list) { + if (!strcmp(p_grp, rdtg->kn->name)) { + list_for_each_entry(crg, &rdtg->mon.crdtgrp_list, + mon.crdtgrp_list) { + if (!strcmp(c_grp, crg->kn->name)) + return crg; + } + } + } + } + + return NULL; +} + +static int rdtgroup_process_flags(struct rdt_resource *r, + enum rdt_group_type rtype, + char *p_grp, char *c_grp, char *tok) +{ + unsigned int op, mon_state, assign_state, unassign_state; + char *dom_str, *id_str, *op_str; + struct rdt_mon_domain *d; + struct rdtgroup *rdtgrp; + unsigned long dom_id; + char domain[10]; + bool found; + int ret; + + rdtgrp =3D rdtgroup_find_grp_by_name(rtype, p_grp, c_grp); + + if (!rdtgrp) { + rdt_last_cmd_puts("Not a valid resctrl group\n"); + return -EINVAL; + } + +next: + if (!tok || tok[0] =3D=3D '\0') + return 0; + + /* Start processing the strings for each domain */ + dom_str =3D strim(strsep(&tok, ";")); + + op_str =3D strpbrk(dom_str, "=3D+-"); + + if (op_str) { + op =3D *op_str; + } else { + rdt_last_cmd_puts("Missing operation =3D, +, - character\n"); + return -EINVAL; + } + + id_str =3D strsep(&dom_str, "=3D+-"); + + /* Check for domain id '*' which means all domains */ + if (id_str && *id_str =3D=3D '*') { + d =3D NULL; + goto check_state; + } else if (!id_str || kstrtoul(id_str, 10, &dom_id)) { + rdt_last_cmd_puts("Missing domain id\n"); + return -EINVAL; + } + + /* Verify if the dom_id is valid */ + found =3D false; + list_for_each_entry(d, &r->mon_domains, hdr.list) { + if (d->hdr.id =3D=3D dom_id) { + found =3D true; + break; + } + } + + if (!found) { + rdt_last_cmd_printf("Invalid domain id %ld\n", dom_id); + return -EINVAL; + } + +check_state: + mon_state =3D rdtgroup_str_to_mon_state(dom_str); + + if (mon_state =3D=3D ASSIGN_INVALID) { + rdt_last_cmd_puts("Invalid assign flag\n"); + goto out_fail; + } + + assign_state =3D 0; + unassign_state =3D 0; + + switch (op) { + case '+': + if (mon_state =3D=3D ASSIGN_NONE) { + rdt_last_cmd_puts("Invalid assign opcode\n"); + goto out_fail; + } + assign_state =3D mon_state; + break; + case '-': + if (mon_state =3D=3D ASSIGN_NONE) { + rdt_last_cmd_puts("Invalid assign opcode\n"); + goto out_fail; + } + unassign_state =3D mon_state; + break; + case '=3D': + assign_state =3D mon_state; + unassign_state =3D (ASSIGN_TOTAL | ASSIGN_LOCAL) & ~assign_state; + break; + default: + break; + } + + if (unassign_state & ASSIGN_TOTAL) { + ret =3D rdtgroup_unassign_cntr_event(r, rdtgrp, d, QOS_L3_MBM_TOTAL_EVEN= T_ID); + if (ret) + goto out_fail; + } + + if (unassign_state & ASSIGN_LOCAL) { + ret =3D rdtgroup_unassign_cntr_event(r, rdtgrp, d, QOS_L3_MBM_LOCAL_EVEN= T_ID); + if (ret) + goto out_fail; + } + + if (assign_state & ASSIGN_TOTAL) { + ret =3D rdtgroup_assign_cntr_event(r, rdtgrp, d, QOS_L3_MBM_TOTAL_EVENT_= ID); + if (ret) + goto out_fail; + } + + if (assign_state & ASSIGN_LOCAL) { + ret =3D rdtgroup_assign_cntr_event(r, rdtgrp, d, QOS_L3_MBM_LOCAL_EVENT_= ID); + if (ret) + goto out_fail; + } + + goto next; + +out_fail: + sprintf(domain, d ? "%ld" : "*", dom_id); + + rdt_last_cmd_printf("Assign operation '%s%c%s' failed on the group %s/%s/= \n", + domain, op, dom_str, p_grp, c_grp); + + return -EINVAL; +} + +static ssize_t rdtgroup_mbm_assign_control_write(struct kernfs_open_file *= of, + char *buf, size_t nbytes, loff_t off) +{ + struct rdt_resource *r =3D of->kn->parent->priv; + char *token, *cmon_grp, *mon_grp; + enum rdt_group_type rtype; + int ret; + + /* Valid input requires a trailing newline */ + if (nbytes =3D=3D 0 || buf[nbytes - 1] !=3D '\n') + return -EINVAL; + + buf[nbytes - 1] =3D '\0'; + + cpus_read_lock(); + mutex_lock(&rdtgroup_mutex); + + rdt_last_cmd_clear(); + + if (!resctrl_arch_mbm_cntr_assign_enabled(r)) { + rdt_last_cmd_puts("mbm_cntr_assign mode is not enabled\n"); + mutex_unlock(&rdtgroup_mutex); + cpus_read_unlock(); + return -EINVAL; + } + + while ((token =3D strsep(&buf, "\n")) !=3D NULL) { + /* + * The write command follows the following format: + * =E2=80=9C//=E2= =80=9D + * Extract the CTRL_MON group. + */ + cmon_grp =3D strsep(&token, "/"); + + /* + * Extract the MON_GROUP. + * strsep returns empty string for contiguous delimiters. + * Empty mon_grp here means it is a RDTCTRL_GROUP. + */ + mon_grp =3D strsep(&token, "/"); + + if (*mon_grp =3D=3D '\0') + rtype =3D RDTCTRL_GROUP; + else + rtype =3D RDTMON_GROUP; + + ret =3D rdtgroup_process_flags(r, rtype, cmon_grp, mon_grp, token); + if (ret) + break; + } + + mutex_unlock(&rdtgroup_mutex); + cpus_read_unlock(); + + return ret ?: nbytes; +} + #ifdef CONFIG_PROC_CPU_RESCTRL =20 /* @@ -2383,9 +2621,10 @@ static struct rftype res_common_files[] =3D { }, { .name =3D "mbm_assign_control", - .mode =3D 0444, + .mode =3D 0644, .kf_ops =3D &rdtgroup_kf_single_ops, .seq_show =3D rdtgroup_mbm_assign_control_show, + .write =3D rdtgroup_mbm_assign_control_write, }, { .name =3D "mbm_assign_mode", --=20 2.34.1