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Signed-off-by: Marcelo Schmitt --- .../bindings/iio/adc/adi,ad4000.yaml | 115 +++++++++++++++++- 1 file changed, 114 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4000.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad4000.yaml index e413a9d8d2a2..35049071a9de 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad4000.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4000.yaml @@ -19,6 +19,21 @@ description: | https://www.analog.com/media/en/technical-documentation/data-sheets/ad= 4020-4021-4022.pdf https://www.analog.com/media/en/technical-documentation/data-sheets/ad= aq4001.pdf https://www.analog.com/media/en/technical-documentation/data-sheets/ad= aq4003.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/ad= 7685.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/ad= 7686.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/ad= 7687.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/ad= 7688.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/ad= 7690.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/ad= 7691.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/ad= 7693.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/ad= 7694.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/ad= 7942.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/ad= 7946.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/ad= 7980.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/ad= 7982.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/ad= 7983.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/ad= 7984.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/ad= 7988-1_7988-5.pdf =20 $ref: /schemas/spi/spi-peripheral-props.yaml# =20 @@ -63,6 +78,38 @@ properties: =20 - const: adi,adaq4003 =20 + - const: adi,ad7946 + - items: + - enum: + - adi,ad7942 + - const: adi,ad7946 + + - const: adi,ad7983 + - items: + - enum: + - adi,ad7980 + - adi,ad7988-5 + - adi,ad7686 + - adi,ad7685 + - adi,ad7694 + - adi,ad7988-1 + - const: adi,ad7983 + + - const: adi,ad7688 + - items: + - enum: + - adi,ad7693 + - adi,ad7687 + - const: adi,ad7688 + + - const: adi,ad7984 + - items: + - enum: + - adi,ad7982 + - adi,ad7690 + - adi,ad7691 + - const: adi,ad7984 + reg: maxItems: 1 =20 @@ -129,10 +176,76 @@ required: - compatible - reg - vdd-supply - - vio-supply - ref-supply =20 allOf: + # AD7694 doesn't have a VIO pin + - if: + properties: + compatible: + contains: + enum: + - adi,ad4000 + - adi,ad4001 + - adi,ad4002 + - adi,ad4003 + - adi,ad4004 + - adi,ad4005 + - adi,ad4006 + - adi,ad4007 + - adi,ad4008 + - adi,ad4010 + - adi,ad4011 + - adi,ad4020 + - adi,ad4021 + - adi,ad4022 + - adi,adaq4001 + - adi,adaq4003 + - adi,ad7685 + - adi,ad7686 + - adi,ad7687 + - adi,ad7688 + - adi,ad7690 + - adi,ad7691 + - adi,ad7693 + - adi,ad7942 + - adi,ad7946 + - adi,ad7980 + - adi,ad7982 + - adi,ad7983 + - adi,ad7984 + - adi,ad7988-1 + - adi,ad7988-5 + then: + required: + - vio-supply + # Single-channel PulSAR devices have SDI either tied to VIO, GND, or hos= t CS. + - if: + properties: + compatible: + contains: + enum: + - adi,ad7685 + - adi,ad7686 + - adi,ad7687 + - adi,ad7688 + - adi,ad7690 + - adi,ad7691 + - adi,ad7693 + - adi,ad7694 + - adi,ad7942 + - adi,ad7946 + - adi,ad7980 + - adi,ad7982 + - adi,ad7983 + - adi,ad7984 + - adi,ad7988-1 + - adi,ad7988-5 + then: + properties: + adi,sdi-pin: + enum: [ high, low, cs ] + default: high # The configuration register can only be accessed if SDI is connected to= MOSI - if: required: --=20 2.45.2 From nobody Sat Nov 23 02:21:32 2024 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1048F374CC; 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charset="utf-8" The ADC data is pushed to the IIO buffer along with timestamp but no timestamp channel was provided to retried the time data. Add a timestamp channel to provide sample capture time. Signed-off-by: Marcelo Schmitt Reviewed-by: David Lechner --- I was about to reply to the patches the other week but waited thinking I would be able to test them on time. My initial intent was to provide timestamps for ADC readings, but I didn't realize an IIO timestamp channel would be needed (silly me). David, do you want a Suggested-by tag in this one? drivers/iio/adc/ad4000.c | 98 +++++++++++++++++++++++----------------- 1 file changed, 56 insertions(+), 42 deletions(-) diff --git a/drivers/iio/adc/ad4000.c b/drivers/iio/adc/ad4000.c index b3b82535f5c1..21731c4d31ee 100644 --- a/drivers/iio/adc/ad4000.c +++ b/drivers/iio/adc/ad4000.c @@ -49,6 +49,7 @@ .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) | \ BIT(IIO_CHAN_INFO_SCALE), \ .info_mask_separate_available =3D _reg_access ? BIT(IIO_CHAN_INFO_SCALE) = : 0,\ + .scan_index =3D 0, \ .scan_type =3D { \ .sign =3D _sign, \ .realbits =3D _real_bits, \ @@ -62,6 +63,12 @@ __AD4000_DIFF_CHANNEL((_sign), (_real_bits), \ ((_real_bits) > 16 ? 32 : 16), (_reg_access)) =20 +#define AD4000_DIFF_CHANNELS(_sign, _real_bits, _reg_access) \ +{ \ + AD4000_DIFF_CHANNEL(_sign, _real_bits, _reg_access), \ + IIO_CHAN_SOFT_TIMESTAMP(1) \ +} + #define __AD4000_PSEUDO_DIFF_CHANNEL(_sign, _real_bits, _storage_bits, _re= g_access)\ { \ .type =3D IIO_VOLTAGE, \ @@ -71,6 +78,7 @@ BIT(IIO_CHAN_INFO_SCALE) | \ BIT(IIO_CHAN_INFO_OFFSET), \ .info_mask_separate_available =3D _reg_access ? BIT(IIO_CHAN_INFO_SCALE) = : 0,\ + .scan_index =3D 0, \ .scan_type =3D { \ .sign =3D _sign, \ .realbits =3D _real_bits, \ @@ -84,6 +92,12 @@ __AD4000_PSEUDO_DIFF_CHANNEL((_sign), (_real_bits), \ ((_real_bits) > 16 ? 32 : 16), (_reg_access)) =20 +#define AD4000_PSEUDO_DIFF_CHANNELS(_sign, _real_bits, _reg_access) \ +{ \ + AD4000_PSEUDO_DIFF_CHANNEL(_sign, _real_bits, _reg_access), \ + IIO_CHAN_SOFT_TIMESTAMP(1) \ +} + static const char * const ad4000_power_supplies[] =3D { "vdd", "vio" }; @@ -110,106 +124,106 @@ static const int ad4000_gains[] =3D { =20 struct ad4000_chip_info { const char *dev_name; - struct iio_chan_spec chan_spec; - struct iio_chan_spec reg_access_chan_spec; + struct iio_chan_spec chan_spec[2]; + struct iio_chan_spec reg_access_chan_spec[2]; bool has_hardware_gain; }; =20 static const struct ad4000_chip_info ad4000_chip_info =3D { .dev_name =3D "ad4000", - .chan_spec =3D AD4000_PSEUDO_DIFF_CHANNEL('u', 16, 0), - .reg_access_chan_spec =3D AD4000_PSEUDO_DIFF_CHANNEL('u', 16, 1), + .chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 0), + .reg_access_chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 1), }; =20 static const struct ad4000_chip_info ad4001_chip_info =3D { .dev_name =3D "ad4001", - .chan_spec =3D AD4000_DIFF_CHANNEL('s', 16, 0), - .reg_access_chan_spec =3D AD4000_DIFF_CHANNEL('s', 16, 1), + .chan_spec =3D AD4000_DIFF_CHANNELS('s', 16, 0), + .reg_access_chan_spec =3D AD4000_DIFF_CHANNELS('s', 16, 1), }; =20 static const struct ad4000_chip_info ad4002_chip_info =3D { .dev_name =3D "ad4002", - .chan_spec =3D AD4000_PSEUDO_DIFF_CHANNEL('u', 18, 0), - .reg_access_chan_spec =3D AD4000_PSEUDO_DIFF_CHANNEL('u', 18, 1), + .chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 18, 0), + .reg_access_chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 18, 1), }; =20 static const struct ad4000_chip_info ad4003_chip_info =3D { .dev_name =3D "ad4003", - .chan_spec =3D AD4000_DIFF_CHANNEL('s', 18, 0), - .reg_access_chan_spec =3D AD4000_DIFF_CHANNEL('s', 18, 1), + .chan_spec =3D AD4000_DIFF_CHANNELS('s', 18, 0), + .reg_access_chan_spec =3D AD4000_DIFF_CHANNELS('s', 18, 1), }; =20 static const struct ad4000_chip_info ad4004_chip_info =3D { .dev_name =3D "ad4004", - .chan_spec =3D AD4000_PSEUDO_DIFF_CHANNEL('u', 16, 0), - .reg_access_chan_spec =3D AD4000_PSEUDO_DIFF_CHANNEL('u', 16, 1), + .chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 0), + .reg_access_chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 1), }; =20 static const struct ad4000_chip_info ad4005_chip_info =3D { .dev_name =3D "ad4005", - .chan_spec =3D AD4000_DIFF_CHANNEL('s', 16, 0), - .reg_access_chan_spec =3D AD4000_DIFF_CHANNEL('s', 16, 1), + .chan_spec =3D AD4000_DIFF_CHANNELS('s', 16, 0), + .reg_access_chan_spec =3D AD4000_DIFF_CHANNELS('s', 16, 1), }; =20 static const struct ad4000_chip_info ad4006_chip_info =3D { .dev_name =3D "ad4006", - .chan_spec =3D AD4000_PSEUDO_DIFF_CHANNEL('u', 18, 0), - .reg_access_chan_spec =3D AD4000_PSEUDO_DIFF_CHANNEL('u', 18, 1), + .chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 18, 0), + .reg_access_chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 18, 1), }; =20 static const struct ad4000_chip_info ad4007_chip_info =3D { .dev_name =3D "ad4007", - .chan_spec =3D AD4000_DIFF_CHANNEL('s', 18, 0), - .reg_access_chan_spec =3D AD4000_DIFF_CHANNEL('s', 18, 1), + .chan_spec =3D AD4000_DIFF_CHANNELS('s', 18, 0), + .reg_access_chan_spec =3D AD4000_DIFF_CHANNELS('s', 18, 1), }; =20 static const struct ad4000_chip_info ad4008_chip_info =3D { .dev_name =3D "ad4008", - .chan_spec =3D AD4000_PSEUDO_DIFF_CHANNEL('u', 16, 0), - .reg_access_chan_spec =3D AD4000_PSEUDO_DIFF_CHANNEL('u', 16, 1), + .chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 0), + .reg_access_chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 1), }; =20 static const struct ad4000_chip_info ad4010_chip_info =3D { .dev_name =3D "ad4010", - .chan_spec =3D AD4000_PSEUDO_DIFF_CHANNEL('u', 18, 0), - .reg_access_chan_spec =3D AD4000_PSEUDO_DIFF_CHANNEL('u', 18, 1), + .chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 18, 0), + .reg_access_chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 18, 1), }; =20 static const struct ad4000_chip_info ad4011_chip_info =3D { .dev_name =3D "ad4011", - .chan_spec =3D AD4000_DIFF_CHANNEL('s', 18, 0), - .reg_access_chan_spec =3D AD4000_DIFF_CHANNEL('s', 18, 1), + .chan_spec =3D AD4000_DIFF_CHANNELS('s', 18, 0), + .reg_access_chan_spec =3D AD4000_DIFF_CHANNELS('s', 18, 1), }; =20 static const struct ad4000_chip_info ad4020_chip_info =3D { .dev_name =3D "ad4020", - .chan_spec =3D AD4000_DIFF_CHANNEL('s', 20, 0), - .reg_access_chan_spec =3D AD4000_DIFF_CHANNEL('s', 20, 1), + .chan_spec =3D AD4000_DIFF_CHANNELS('s', 20, 0), + .reg_access_chan_spec =3D AD4000_DIFF_CHANNELS('s', 20, 1), }; =20 static const struct ad4000_chip_info ad4021_chip_info =3D { .dev_name =3D "ad4021", - .chan_spec =3D AD4000_DIFF_CHANNEL('s', 20, 0), - .reg_access_chan_spec =3D AD4000_DIFF_CHANNEL('s', 20, 1), + .chan_spec =3D AD4000_DIFF_CHANNELS('s', 20, 0), + .reg_access_chan_spec =3D AD4000_DIFF_CHANNELS('s', 20, 1), }; =20 static const struct ad4000_chip_info ad4022_chip_info =3D { .dev_name =3D "ad4022", - .chan_spec =3D AD4000_DIFF_CHANNEL('s', 20, 0), - .reg_access_chan_spec =3D AD4000_DIFF_CHANNEL('s', 20, 1), + .chan_spec =3D AD4000_DIFF_CHANNELS('s', 20, 0), + .reg_access_chan_spec =3D AD4000_DIFF_CHANNELS('s', 20, 1), }; =20 static const struct ad4000_chip_info adaq4001_chip_info =3D { .dev_name =3D "adaq4001", - .chan_spec =3D AD4000_DIFF_CHANNEL('s', 16, 0), - .reg_access_chan_spec =3D AD4000_DIFF_CHANNEL('s', 16, 1), + .chan_spec =3D AD4000_DIFF_CHANNELS('s', 16, 0), + .reg_access_chan_spec =3D AD4000_DIFF_CHANNELS('s', 16, 1), .has_hardware_gain =3D true, }; =20 static const struct ad4000_chip_info adaq4003_chip_info =3D { .dev_name =3D "adaq4003", - .chan_spec =3D AD4000_DIFF_CHANNEL('s', 18, 0), - .reg_access_chan_spec =3D AD4000_DIFF_CHANNEL('s', 18, 1), + .chan_spec =3D AD4000_DIFF_CHANNELS('s', 18, 0), + .reg_access_chan_spec =3D AD4000_DIFF_CHANNELS('s', 18, 1), .has_hardware_gain =3D true, }; =20 @@ -591,7 +605,7 @@ static int ad4000_probe(struct spi_device *spi) switch (st->sdi_pin) { case AD4000_SDI_MOSI: indio_dev->info =3D &ad4000_reg_access_info; - indio_dev->channels =3D &chip->reg_access_chan_spec; + indio_dev->channels =3D chip->reg_access_chan_spec; =20 /* * In "3-wire mode", the ADC SDI line must be kept high when @@ -603,7 +617,7 @@ static int ad4000_probe(struct spi_device *spi) if (ret < 0) return ret; =20 - ret =3D ad4000_prepare_3wire_mode_message(st, indio_dev->channels); + ret =3D ad4000_prepare_3wire_mode_message(st, &indio_dev->channels[0]); if (ret) return ret; =20 @@ -614,16 +628,16 @@ static int ad4000_probe(struct spi_device *spi) break; case AD4000_SDI_VIO: indio_dev->info =3D &ad4000_info; - indio_dev->channels =3D &chip->chan_spec; - ret =3D ad4000_prepare_3wire_mode_message(st, indio_dev->channels); + indio_dev->channels =3D chip->chan_spec; + ret =3D ad4000_prepare_3wire_mode_message(st, &indio_dev->channels[0]); if (ret) return ret; =20 break; case AD4000_SDI_CS: indio_dev->info =3D &ad4000_info; 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charset="utf-8" The SPI transfers for AD4020, AD4021, and AD4022 have slightly different timing specifications. Use device specific timing constraints to set SPI transfer parameters. Signed-off-by: Marcelo Schmitt --- drivers/iio/adc/ad4000.c | 50 ++++++++++++++++++++++++++++++++-------- 1 file changed, 41 insertions(+), 9 deletions(-) diff --git a/drivers/iio/adc/ad4000.c b/drivers/iio/adc/ad4000.c index 21731c4d31ee..68ac77494263 100644 --- a/drivers/iio/adc/ad4000.c +++ b/drivers/iio/adc/ad4000.c @@ -35,10 +35,6 @@ =20 #define AD4000_SCALE_OPTIONS 2 =20 -#define AD4000_TQUIET1_NS 190 -#define AD4000_TQUIET2_NS 60 -#define AD4000_TCONV_NS 320 - #define __AD4000_DIFF_CHANNEL(_sign, _real_bits, _storage_bits, _reg_acces= s) \ { \ .type =3D IIO_VOLTAGE, \ @@ -122,10 +118,30 @@ static const int ad4000_gains[] =3D { 454, 909, 1000, 1900, }; =20 +struct ad4000_time_spec { + int t_conv_ns; + int t_quiet2_ns; +}; + +/* + * Same timing specifications for all of AD4000, AD4001, ..., AD4008, AD40= 10, + * ADAQ4001, and ADAQ4003. + */ +static const struct ad4000_time_spec ad4000_t_spec =3D { + .t_conv_ns =3D 320, + .t_quiet2_ns =3D 60, +}; + +static const struct ad4000_time_spec ad4020_t_spec =3D { + .t_conv_ns =3D 350, + .t_quiet2_ns =3D 60, +}; + struct ad4000_chip_info { const char *dev_name; struct iio_chan_spec chan_spec[2]; struct iio_chan_spec reg_access_chan_spec[2]; + const struct ad4000_time_spec *time_spec; bool has_hardware_gain; }; =20 @@ -133,90 +149,105 @@ static const struct ad4000_chip_info ad4000_chip_inf= o =3D { .dev_name =3D "ad4000", .chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 0), .reg_access_chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 1), + .time_spec =3D &ad4000_t_spec, }; =20 static const struct ad4000_chip_info ad4001_chip_info =3D { .dev_name =3D "ad4001", .chan_spec =3D AD4000_DIFF_CHANNELS('s', 16, 0), .reg_access_chan_spec =3D AD4000_DIFF_CHANNELS('s', 16, 1), + .time_spec =3D &ad4000_t_spec, }; =20 static const struct ad4000_chip_info ad4002_chip_info =3D { .dev_name =3D "ad4002", .chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 18, 0), .reg_access_chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 18, 1), + .time_spec =3D &ad4000_t_spec, }; =20 static const struct ad4000_chip_info ad4003_chip_info =3D { .dev_name =3D "ad4003", .chan_spec =3D AD4000_DIFF_CHANNELS('s', 18, 0), .reg_access_chan_spec =3D AD4000_DIFF_CHANNELS('s', 18, 1), + .time_spec =3D &ad4000_t_spec, }; =20 static const struct ad4000_chip_info ad4004_chip_info =3D { .dev_name =3D "ad4004", .chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 0), .reg_access_chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 1), + .time_spec =3D &ad4000_t_spec, }; =20 static const struct ad4000_chip_info ad4005_chip_info =3D { .dev_name =3D "ad4005", .chan_spec =3D AD4000_DIFF_CHANNELS('s', 16, 0), .reg_access_chan_spec =3D AD4000_DIFF_CHANNELS('s', 16, 1), + .time_spec =3D &ad4000_t_spec, }; =20 static const struct ad4000_chip_info ad4006_chip_info =3D { .dev_name =3D "ad4006", .chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 18, 0), .reg_access_chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 18, 1), + .time_spec =3D &ad4000_t_spec, }; =20 static const struct ad4000_chip_info ad4007_chip_info =3D { .dev_name =3D "ad4007", .chan_spec =3D AD4000_DIFF_CHANNELS('s', 18, 0), .reg_access_chan_spec =3D AD4000_DIFF_CHANNELS('s', 18, 1), + .time_spec =3D &ad4000_t_spec, }; =20 static const struct ad4000_chip_info ad4008_chip_info =3D { .dev_name =3D "ad4008", .chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 0), .reg_access_chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 1), + .time_spec =3D &ad4000_t_spec, }; =20 static const struct ad4000_chip_info ad4010_chip_info =3D { .dev_name =3D "ad4010", .chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 18, 0), .reg_access_chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 18, 1), + .time_spec =3D &ad4000_t_spec, }; =20 static const struct ad4000_chip_info ad4011_chip_info =3D { .dev_name =3D "ad4011", .chan_spec =3D AD4000_DIFF_CHANNELS('s', 18, 0), .reg_access_chan_spec =3D AD4000_DIFF_CHANNELS('s', 18, 1), + .time_spec =3D &ad4000_t_spec, }; =20 static const struct ad4000_chip_info ad4020_chip_info =3D { .dev_name =3D "ad4020", .chan_spec =3D AD4000_DIFF_CHANNELS('s', 20, 0), .reg_access_chan_spec =3D AD4000_DIFF_CHANNELS('s', 20, 1), + .time_spec =3D &ad4020_t_spec, }; =20 static const struct ad4000_chip_info ad4021_chip_info =3D { .dev_name =3D "ad4021", .chan_spec =3D AD4000_DIFF_CHANNELS('s', 20, 0), .reg_access_chan_spec =3D AD4000_DIFF_CHANNELS('s', 20, 1), + .time_spec =3D &ad4020_t_spec, }; =20 static const struct ad4000_chip_info ad4022_chip_info =3D { .dev_name =3D "ad4022", .chan_spec =3D AD4000_DIFF_CHANNELS('s', 20, 0), .reg_access_chan_spec =3D AD4000_DIFF_CHANNELS('s', 20, 1), + .time_spec =3D &ad4020_t_spec, }; =20 static const struct ad4000_chip_info adaq4001_chip_info =3D { .dev_name =3D "adaq4001", .chan_spec =3D AD4000_DIFF_CHANNELS('s', 16, 0), .reg_access_chan_spec =3D AD4000_DIFF_CHANNELS('s', 16, 1), + .time_spec =3D &ad4000_t_spec, .has_hardware_gain =3D true, }; =20 @@ -224,6 +255,7 @@ static const struct ad4000_chip_info adaq4003_chip_info= =3D { .dev_name =3D "adaq4003", .chan_spec =3D AD4000_DIFF_CHANNELS('s', 18, 0), .reg_access_chan_spec =3D AD4000_DIFF_CHANNELS('s', 18, 1), + .time_spec =3D &ad4000_t_spec, .has_hardware_gain =3D true, }; =20 @@ -238,6 +270,7 @@ struct ad4000_state { bool span_comp; u16 gain_milli; int scale_tbl[AD4000_SCALE_OPTIONS][2]; + const struct ad4000_time_spec *time_spec; =20 /* * DMA (thus cache coherency maintenance) requires the transfer buffers @@ -502,16 +535,15 @@ static const struct iio_info ad4000_info =3D { static int ad4000_prepare_3wire_mode_message(struct ad4000_state *st, const struct iio_chan_spec *chan) { - unsigned int cnv_pulse_time =3D AD4000_TCONV_NS; struct spi_transfer *xfers =3D st->xfers; =20 xfers[0].cs_change =3D 1; - xfers[0].cs_change_delay.value =3D cnv_pulse_time; + xfers[0].cs_change_delay.value =3D st->time_spec->t_conv_ns; xfers[0].cs_change_delay.unit =3D SPI_DELAY_UNIT_NSECS; =20 xfers[1].rx_buf =3D &st->scan.data; xfers[1].len =3D BITS_TO_BYTES(chan->scan_type.storagebits); - xfers[1].delay.value =3D AD4000_TQUIET2_NS; + xfers[1].delay.value =3D st->time_spec->t_quiet2_ns; xfers[1].delay.unit =3D SPI_DELAY_UNIT_NSECS; =20 spi_message_init_with_transfers(&st->msg, st->xfers, 2); @@ -529,7 +561,6 @@ static int ad4000_prepare_3wire_mode_message(struct ad4= 000_state *st, static int ad4000_prepare_4wire_mode_message(struct ad4000_state *st, const struct iio_chan_spec *chan) { - unsigned int cnv_to_sdi_time =3D AD4000_TCONV_NS; struct spi_transfer *xfers =3D st->xfers; =20 /* @@ -537,7 +568,7 @@ static int ad4000_prepare_4wire_mode_message(struct ad4= 000_state *st, * going low. */ xfers[0].cs_off =3D 1; - xfers[0].delay.value =3D cnv_to_sdi_time; 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Thu, 14 Nov 2024 18:51:45 -0500 Received: from ASHBMBX9.ad.analog.com (10.64.17.10) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Thu, 14 Nov 2024 18:51:44 -0500 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Thu, 14 Nov 2024 18:51:44 -0500 Received: from work.ad.analog.com (HYB-hERzalRezfV.ad.analog.com [10.65.205.9]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 4AENpXo9028835; Thu, 14 Nov 2024 18:51:36 -0500 From: Marcelo Schmitt To: , , , , , , , CC: , , Subject: [PATCH 4/4] iio: adc: ad4000: Add support for PulSAR devices Date: Thu, 14 Nov 2024 20:51:32 -0300 Message-ID: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-GUID: E1zX0BbgcLVAHPwlwrZ_4n7k_dZU1XQD X-Proofpoint-ORIG-GUID: E1zX0BbgcLVAHPwlwrZ_4n7k_dZU1XQD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 mlxscore=0 malwarescore=0 bulkscore=0 priorityscore=1501 adultscore=0 mlxlogscore=999 phishscore=0 suspectscore=0 lowpriorityscore=0 impostorscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411140189 Content-Type: text/plain; charset="utf-8" The AD4000 series and the single-channel PulSAR series of devices have similar SPI transfer specifications and wiring configurations. Single-channel PulSAR devices are slower than AD4000, and don't have a configuration register. That taken into account, single-channel PulSARs can be supported by the ad4000 driver without any increase in code complexity. Signed-off-by: Marcelo Schmitt Reviewed-by: David Lechner --- drivers/iio/adc/ad4000.c | 163 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 163 insertions(+) diff --git a/drivers/iio/adc/ad4000.c b/drivers/iio/adc/ad4000.c index 68ac77494263..8e31b42534f5 100644 --- a/drivers/iio/adc/ad4000.c +++ b/drivers/iio/adc/ad4000.c @@ -137,6 +137,41 @@ static const struct ad4000_time_spec ad4020_t_spec =3D= { .t_quiet2_ns =3D 60, }; =20 +/* AD7983, AD7984 */ +static const struct ad4000_time_spec ad7983_t_spec =3D { + .t_conv_ns =3D 500, +}; + +/* AD7980, AD7982 */ +static const struct ad4000_time_spec ad7980_t_spec =3D { + .t_conv_ns =3D 800, +}; + +/* AD7946, AD7686, AD7688, AD7988-5, AD7693 */ +static const struct ad4000_time_spec ad7686_t_spec =3D { + .t_conv_ns =3D 1600, +}; + +/* AD7690 */ +static const struct ad4000_time_spec ad7690_t_spec =3D { + .t_conv_ns =3D 2100, +}; + +/* AD7942, AD7685, AD7687, AD7694 */ +static const struct ad4000_time_spec ad7687_t_spec =3D { + .t_conv_ns =3D 3200, +}; + +/* AD7691 */ +static const struct ad4000_time_spec ad7691_t_spec =3D { + .t_conv_ns =3D 3700, +}; + +/* AD7988-1 */ +static const struct ad4000_time_spec ad7988_1_t_spec =3D { + .t_conv_ns =3D 9500, +}; + struct ad4000_chip_info { const char *dev_name; struct iio_chan_spec chan_spec[2]; @@ -259,6 +294,102 @@ static const struct ad4000_chip_info adaq4003_chip_in= fo =3D { .has_hardware_gain =3D true, }; =20 +static const struct ad4000_chip_info ad7685_chip_info =3D { + .dev_name =3D "ad7685", + .chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 0), + .time_spec =3D &ad7687_t_spec, +}; + +static const struct ad4000_chip_info ad7686_chip_info =3D { + .dev_name =3D "ad7686", + .chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 0), + .time_spec =3D &ad7686_t_spec, +}; + +static const struct ad4000_chip_info ad7687_chip_info =3D { + .dev_name =3D "ad7687", + .chan_spec =3D AD4000_DIFF_CHANNELS('s', 16, 0), + .time_spec =3D &ad7687_t_spec, +}; + +static const struct ad4000_chip_info ad7688_chip_info =3D { + .dev_name =3D "ad7688", + .chan_spec =3D AD4000_DIFF_CHANNELS('s', 16, 0), + .time_spec =3D &ad7686_t_spec, +}; + +static const struct ad4000_chip_info ad7690_chip_info =3D { + .dev_name =3D "ad7690", + .chan_spec =3D AD4000_DIFF_CHANNELS('s', 18, 0), + .time_spec =3D &ad7690_t_spec, +}; + +static const struct ad4000_chip_info ad7691_chip_info =3D { + .dev_name =3D "ad7691", + .chan_spec =3D AD4000_DIFF_CHANNELS('s', 18, 0), + .time_spec =3D &ad7691_t_spec, +}; + +static const struct ad4000_chip_info ad7693_chip_info =3D { + .dev_name =3D "ad7693", + .chan_spec =3D AD4000_DIFF_CHANNELS('s', 16, 0), + .time_spec =3D &ad7686_t_spec, +}; + +static const struct ad4000_chip_info ad7694_chip_info =3D { + .dev_name =3D "ad7694", + .chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 0), + .time_spec =3D &ad7687_t_spec, +}; + +static const struct ad4000_chip_info ad7942_chip_info =3D { + .dev_name =3D "ad7942", + .chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 14, 0), + .time_spec =3D &ad7687_t_spec, +}; + +static const struct ad4000_chip_info ad7946_chip_info =3D { + .dev_name =3D "ad7946", + .chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 14, 0), + .time_spec =3D &ad7686_t_spec, +}; + +static const struct ad4000_chip_info ad7980_chip_info =3D { + .dev_name =3D "ad7980", + .chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 0), + .time_spec =3D &ad7980_t_spec, +}; + +static const struct ad4000_chip_info ad7982_chip_info =3D { + .dev_name =3D "ad7982", + .chan_spec =3D AD4000_DIFF_CHANNELS('s', 18, 0), + .time_spec =3D &ad7980_t_spec, +}; + +static const struct ad4000_chip_info ad7983_chip_info =3D { + .dev_name =3D "ad7983", + .chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 0), + .time_spec =3D &ad7983_t_spec, +}; + +static const struct ad4000_chip_info ad7984_chip_info =3D { + .dev_name =3D "ad7984", + .chan_spec =3D AD4000_DIFF_CHANNELS('s', 18, 0), + .time_spec =3D &ad7983_t_spec, +}; + +static const struct ad4000_chip_info ad7988_1_chip_info =3D { + .dev_name =3D "ad7988-1", + .chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 0), + .time_spec =3D &ad7988_1_t_spec, +}; + +static const struct ad4000_chip_info ad7988_5_chip_info =3D { + .dev_name =3D "ad7988-5", + .chan_spec =3D AD4000_PSEUDO_DIFF_CHANNELS('u', 16, 0), + .time_spec =3D &ad7686_t_spec, +}; + struct ad4000_state { struct spi_device *spi; struct gpio_desc *cnv_gpio; @@ -732,6 +863,22 @@ static const struct spi_device_id ad4000_id[] =3D { { "ad4022", (kernel_ulong_t)&ad4022_chip_info }, { "adaq4001", (kernel_ulong_t)&adaq4001_chip_info }, { "adaq4003", (kernel_ulong_t)&adaq4003_chip_info }, + { "ad7685", (kernel_ulong_t)&ad7685_chip_info }, + { "ad7686", (kernel_ulong_t)&ad7686_chip_info }, + { "ad7687", (kernel_ulong_t)&ad7687_chip_info }, + { "ad7688", (kernel_ulong_t)&ad7688_chip_info }, + { "ad7690", (kernel_ulong_t)&ad7690_chip_info }, + { "ad7691", (kernel_ulong_t)&ad7691_chip_info }, + { "ad7693", (kernel_ulong_t)&ad7693_chip_info }, + { "ad7694", (kernel_ulong_t)&ad7694_chip_info }, + { "ad7942", (kernel_ulong_t)&ad7942_chip_info }, + { "ad7946", (kernel_ulong_t)&ad7946_chip_info }, + { "ad7980", (kernel_ulong_t)&ad7980_chip_info }, + { "ad7982", (kernel_ulong_t)&ad7982_chip_info }, + { "ad7983", (kernel_ulong_t)&ad7983_chip_info }, + { "ad7984", (kernel_ulong_t)&ad7984_chip_info }, + { "ad7988-1", (kernel_ulong_t)&ad7988_1_chip_info }, + { "ad7988-5", (kernel_ulong_t)&ad7988_5_chip_info }, { } }; MODULE_DEVICE_TABLE(spi, ad4000_id); @@ -753,6 +900,22 @@ static const struct of_device_id ad4000_of_match[] =3D= { { .compatible =3D "adi,ad4022", .data =3D &ad4022_chip_info }, { .compatible =3D "adi,adaq4001", .data =3D &adaq4001_chip_info }, { .compatible =3D "adi,adaq4003", .data =3D &adaq4003_chip_info }, + { .compatible =3D "adi,ad7685", .data =3D &ad7685_chip_info }, + { .compatible =3D "adi,ad7686", .data =3D &ad7686_chip_info }, + { .compatible =3D "adi,ad7687", .data =3D &ad7687_chip_info }, + { .compatible =3D "adi,ad7688", .data =3D &ad7688_chip_info }, + { .compatible =3D "adi,ad7690", .data =3D &ad7690_chip_info }, + { .compatible =3D "adi,ad7691", .data =3D &ad7691_chip_info }, + { .compatible =3D "adi,ad7693", .data =3D &ad7693_chip_info }, + { .compatible =3D "adi,ad7694", .data =3D &ad7694_chip_info }, + { .compatible =3D "adi,ad7942", .data =3D &ad7942_chip_info }, + { .compatible =3D "adi,ad7946", .data =3D &ad7946_chip_info }, + { .compatible =3D "adi,ad7980", .data =3D &ad7980_chip_info }, + { .compatible =3D "adi,ad7982", .data =3D &ad7982_chip_info }, + { .compatible =3D "adi,ad7983", .data =3D &ad7983_chip_info }, + { .compatible =3D "adi,ad7984", .data =3D &ad7984_chip_info }, + { .compatible =3D "adi,ad7988-1", .data =3D &ad7988_1_chip_info }, + { .compatible =3D "adi,ad7988-5", .data =3D &ad7988_5_chip_info }, { } }; MODULE_DEVICE_TABLE(of, ad4000_of_match); --=20 2.45.2