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Fri, 8 Nov 2024 21:48:55 -0800 From: Nicolin Chen To: , , , CC: , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH RFCv1 1/7] genirq/msi: Allow preset IOVA in struct msi_desc for MSI doorbell address Date: Fri, 8 Nov 2024 21:48:46 -0800 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A102:EE_|BL3PR12MB6475:EE_ X-MS-Office365-Filtering-Correlation-Id: 1f5d5392-9d74-41d5-4c0a-08dd008235ea X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|376014|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?t/S9K0XP4NZ0tg1+bxB+qfMa9SC0pV7WHw1QHoPygbgdTHgg3p7RzN5Pa6M1?= =?us-ascii?Q?YqXoRwFRlyAYZ85gPdxplb1oQmzoeydmoPbInJWXEPUOYgKiG7KEC8C6OjUm?= =?us-ascii?Q?dGEgrD5MT77Rsslxks782kTRGitx1vv0JxjNDYu4lytP9guzv6yC1g9LUIPR?= =?us-ascii?Q?0shtj9d3HmUGKKaOJhinu3AKwZn48J++zDxjh6+L58Sgl1JWtvV4QBy9m3bM?= =?us-ascii?Q?RUZYhnqawjUyiIMXNJk15gMyl43wVBgWNyuJhCz+tTmqpyqo/idCGQSBJwSW?= =?us-ascii?Q?wFKAvXFDjL+P33YSBxXDYBKpbg+lWdfxF6MHFCOSvznpM1GkMz+neEq2fnlO?= =?us-ascii?Q?Mep+0wUqELkWY5P9OsvFCSemDzm2Ujx7J6GSNOrbJJTsAtNhA/xHxtHxPmNk?= =?us-ascii?Q?sa0NLUhyBbAHppRf5Qjmqg7m/D1wAHfZ7uUvSwqKQuAxC0E4JQi9q+evY9un?= =?us-ascii?Q?S7otiEDiAm7VKeFXAAd2mzeyNeUh0zmxFQplTpWXQMc2fGdkAYagkd7D3j7B?= =?us-ascii?Q?dnyqhoTX6SJodapG998cI9PVzhEsyAHp0zxoW4Jk3X0aBM5LeJKWPRguHniM?= =?us-ascii?Q?nw8wySpWSd0hBH0LD1eUVLn4onJhok5w6boAvH4GTwN8BZ5qe9ueypTD8RDz?= =?us-ascii?Q?/a9jIms44gw0nQNKAXYtjhs5fzbRTo5ySer4+M74F/WCWkBaZsQQEB0UV9xN?= =?us-ascii?Q?ixH+BLt9cB1UqxklH2VLWIZiB6htP0RCDLex02zilyJv6kuFw3LnXEPMCuxf?= =?us-ascii?Q?2HFudNbEM04g/+XgHD4wKCmHl3kkjkS2HcKLfkME60EiVaKQzQKxZNkVzahd?= =?us-ascii?Q?19R5DSOSe9L2x7sfAPR6wNNU8ZAYGiPxY7e4NjvM8i4Lezp+yA05Yg0fbpNo?= =?us-ascii?Q?F0CS2AWmk+czNM4ywOBa2RsR0alV26f+dMU7XsnFrArwajyjC7n5vdbds4w/?= =?us-ascii?Q?e7OJp45TOjLbFI6axyqRAn0GVS1IEeY82hsxX28PuF2eM+xeV82TI2Ytm8Et?= =?us-ascii?Q?gBEhh9ePMzsYcp1Wh2WpA8X38AQqoSX9MBg2SXMcVEZ30l9t2daTP8hSVX0Y?= =?us-ascii?Q?VVV19XZMrHwgunky/Y5KB8Ptbj0Qnzukieh1iNc/fT9oS7zQY483Q/to69Tz?= =?us-ascii?Q?4rkHNzQvhSJ76RKeixaxgloPzMBWCg0E7vR6AmWjNMQMBQg0KILfVqCaRWT2?= =?us-ascii?Q?YlWT2S1XuXZm50rfD2Dm53bCXm2VSQtNlrQm6q07fmsslwyT4Ot3iJPv5H0t?= =?us-ascii?Q?ws+47sAVcMfFbaLEU2+zN8EA8Njy39xyR+TuwHOG/M8O5ynxgjU2cjNIgkaV?= =?us-ascii?Q?IyDVnNlN2cSiPXVBFA2AwydoMJkzrY0wcGIO7tpyDtzNzaATWz4/CQqjNS8a?= =?us-ascii?Q?7Bcchh+EBsY4mHC2ewxWjjDT15rYmvoeqHdtic0lVSBGZS9pzA=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(7416014)(376014)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Nov 2024 05:49:00.4743 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1f5d5392-9d74-41d5-4c0a-08dd008235ea X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A102.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6475 Content-Type: text/plain; charset="utf-8" Currently, the IOVA and its mapping (to physical doorbell address) is done by the dma-iommu via the iommu_cookie in the struct msi_desc, which is the structure used by three parties: genirq, irqchip and dma-iommu. However, when dealing with a nested translation on ARM64, the MSI doorbell address is behind the SMMU (IOMMU on ARM64), thus HW needs to be programed with the stage-1 IOVA, i.e. guest-level IOVA, rather than asking dma-iommu to allocate one. To support a guest-programmable pathway, first we need to make sure struct msi_desc will allow a preset IOVA v.s. using iommu_cookie. Add an msi_iova to the structure and init its value to PHYS_ADDR_MAX. And provide a helper for drivers to get the msi_iova out of an msi_desc object. A following patch will change msi_setup_msi_descs and msix_setup_msi_descs to call msi_domain_insert_msi_desc and finish the actual value forwarding. Signed-off-by: Nicolin Chen --- include/linux/msi.h | 11 +++++++++++ kernel/irq/msi.c | 6 ++++++ 2 files changed, 17 insertions(+) diff --git a/include/linux/msi.h b/include/linux/msi.h index b10093c4d00e..873094743065 100644 --- a/include/linux/msi.h +++ b/include/linux/msi.h @@ -185,6 +185,7 @@ struct msi_desc { struct irq_affinity_desc *affinity; #ifdef CONFIG_IRQ_MSI_IOMMU const void *iommu_cookie; + dma_addr_t msi_iova; #endif #ifdef CONFIG_SYSFS struct device_attribute *sysfs_attrs; @@ -296,6 +297,11 @@ static inline void msi_desc_set_iommu_cookie(struct ms= i_desc *desc, { desc->iommu_cookie =3D iommu_cookie; } + +static inline dma_addr_t msi_desc_get_iova(struct msi_desc *desc) +{ + return desc->msi_iova; +} #else static inline const void *msi_desc_get_iommu_cookie(struct msi_desc *desc) { @@ -306,6 +312,11 @@ static inline void msi_desc_set_iommu_cookie(struct ms= i_desc *desc, const void *iommu_cookie) { } + +static inline dma_addr_t msi_desc_get_iova(struct msi_desc *desc) +{ + return PHYS_ADDR_MAX; +} #endif =20 int msi_domain_insert_msi_desc(struct device *dev, unsigned int domid, diff --git a/kernel/irq/msi.c b/kernel/irq/msi.c index 3a24d6b5f559..f3159ec0f036 100644 --- a/kernel/irq/msi.c +++ b/kernel/irq/msi.c @@ -81,6 +81,9 @@ static struct msi_desc *msi_alloc_desc(struct device *dev= , int nvec, =20 desc->dev =3D dev; desc->nvec_used =3D nvec; +#ifdef CONFIG_IRQ_MSI_IOMMU + desc->msi_iova =3D PHYS_ADDR_MAX; +#endif if (affinity) { desc->affinity =3D kmemdup_array(affinity, nvec, sizeof(*desc->affinity)= , GFP_KERNEL); if (!desc->affinity) { @@ -158,6 +161,9 @@ int msi_domain_insert_msi_desc(struct device *dev, unsi= gned int domid, =20 /* Copy type specific data to the new descriptor. */ desc->pci =3D init_desc->pci; +#ifdef CONFIG_IRQ_MSI_IOMMU + desc->msi_iova =3D init_desc->msi_iova; +#endif =20 return msi_insert_desc(dev, desc, domid, init_desc->msi_index); } --=20 2.43.0 From nobody Sat Nov 23 23:06:59 2024 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2069.outbound.protection.outlook.com [40.107.92.69]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 795CC145B03; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Nov 2024 05:49:04.6618 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 06986a8a-70ad-459e-1c8e-08dd00823862 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A102.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7936 Content-Type: text/plain; charset="utf-8" Now struct msi_desc can carry a preset IOVA for MSI doorbell address. This is typically preset by user space when engaging a 2-stage translation. So, use the preset IOVA instead of kernel-level IOVA allocations in dma-iommu. Signed-off-by: Nicolin Chen --- drivers/irqchip/irq-gic-v3-its.c | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-= its.c index ab597e74ba08..bc1768576546 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -1723,6 +1723,8 @@ static u64 its_irq_get_msi_base(struct its_device *it= s_dev) static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *ms= g) { struct its_device *its_dev =3D irq_data_get_irq_chip_data(d); + struct msi_desc *desc =3D irq_data_get_msi_desc(d); + dma_addr_t iova =3D msi_desc_get_iova(desc); struct its_node *its; u64 addr; =20 @@ -1733,7 +1735,13 @@ static void its_irq_compose_msi_msg(struct irq_data = *d, struct msi_msg *msg) msg->address_hi =3D upper_32_bits(addr); msg->data =3D its_get_event_id(d); =20 - iommu_dma_compose_msi_msg(irq_data_get_msi_desc(d), msg); + /* Bypass iommu_dma_compose_msi_msg if msi_iova is preset */ + if (iova =3D=3D PHYS_ADDR_MAX) { + iommu_dma_compose_msi_msg(desc, msg); + } else { + msg->address_lo =3D lower_32_bits(iova); + msg->address_hi =3D upper_32_bits(iova); + } } =20 static int its_irq_set_irqchip_state(struct irq_data *d, @@ -3570,6 +3578,7 @@ static int its_irq_domain_alloc(struct irq_domain *do= main, unsigned int virq, { msi_alloc_info_t *info =3D args; struct its_device *its_dev =3D info->scratchpad[0].ptr; + dma_addr_t iova =3D msi_desc_get_iova(info->desc); struct its_node *its =3D its_dev->its; struct irq_data *irqd; irq_hw_number_t hwirq; @@ -3580,9 +3589,13 @@ static int its_irq_domain_alloc(struct irq_domain *d= omain, unsigned int virq, if (err) return err; =20 - err =3D iommu_dma_prepare_msi(info->desc, its->get_msi_base(its_dev)); - if (err) - return err; + /* Bypass iommu_dma_prepare_msi if msi_iova is preset */ + if (iova =3D=3D PHYS_ADDR_MAX) { + err =3D iommu_dma_prepare_msi(info->desc, + its->get_msi_base(its_dev)); + if (err) + return err; + } =20 for (i =3D 0; i < nr_irqs; i++) { err =3D its_irq_gic_domain_alloc(domain, virq + i, hwirq + i); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Nov 2024 05:49:00.3675 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 11d964e9-49a7-44e8-c6a8-08dd008235bf X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE9.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4390 Content-Type: text/plain; charset="utf-8" msi_setup_msi_descs and msix_setup_msi_descs are the two callers of genirq helper msi_domain_insert_msi_desc that is now ready for a preset msi_iova. So, do the same in these two callers. Note MSIx supports multiple entries, so use struct msix_entry to pass msi_iova in. Signed-off-by: Nicolin Chen --- include/linux/pci.h | 1 + drivers/pci/msi/msi.c | 18 ++++++++++++++---- 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/include/linux/pci.h b/include/linux/pci.h index 573b4c4c2be6..68ebb9d42f7f 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1652,6 +1652,7 @@ int pci_set_vga_state(struct pci_dev *pdev, bool deco= de, struct msix_entry { u32 vector; /* Kernel uses to write allocated vector */ u16 entry; /* Driver uses to specify entry, OS writes */ + u64 iova; /* Kernel uses to override doorbell address */ }; =20 #ifdef CONFIG_PCI_MSI diff --git a/drivers/pci/msi/msi.c b/drivers/pci/msi/msi.c index 3a45879d85db..95caa81d3421 100644 --- a/drivers/pci/msi/msi.c +++ b/drivers/pci/msi/msi.c @@ -282,7 +282,7 @@ static void pci_msi_set_enable(struct pci_dev *dev, int= enable) pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); } =20 -static int msi_setup_msi_desc(struct pci_dev *dev, int nvec, +static int msi_setup_msi_desc(struct pci_dev *dev, int nvec, dma_addr_t io= va, struct irq_affinity_desc *masks) { struct msi_desc desc; @@ -312,6 +312,10 @@ static int msi_setup_msi_desc(struct pci_dev *dev, int= nvec, else desc.pci.mask_pos =3D dev->msi_cap + PCI_MSI_MASK_32; =20 +#ifdef CONFIG_IRQ_MSI_IOMMU + desc.msi_iova =3D iova; +#endif + /* Save the initial mask status */ if (desc.pci.msi_attrib.can_mask) pci_read_config_dword(dev, desc.pci.mask_pos, &desc.pci.msi_mask); @@ -349,7 +353,7 @@ static int msi_verify_entries(struct pci_dev *dev) * which could have been allocated. */ static int msi_capability_init(struct pci_dev *dev, int nvec, - struct irq_affinity *affd) + struct irq_affinity *affd, dma_addr_t iova) { struct irq_affinity_desc *masks =3D NULL; struct msi_desc *entry, desc; @@ -370,7 +374,7 @@ static int msi_capability_init(struct pci_dev *dev, int= nvec, masks =3D irq_create_affinity_masks(nvec, affd); =20 msi_lock_descs(&dev->dev); - ret =3D msi_setup_msi_desc(dev, nvec, masks); + ret =3D msi_setup_msi_desc(dev, nvec, iova, masks); if (ret) goto fail; =20 @@ -456,7 +460,7 @@ int __pci_enable_msi_range(struct pci_dev *dev, int min= vec, int maxvec, return -ENOSPC; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Nov 2024 05:49:08.6351 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1a22acb9-c352-4df2-63ca-08dd00823ac0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A104.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB8372 Content-Type: text/plain; charset="utf-8" The previous patch passes in the msi_iova to msi_capability_init, so this allows its caller to do the same. Signed-off-by: Nicolin Chen --- drivers/pci/msi/msi.h | 3 ++- drivers/pci/msi/api.c | 6 ++++-- drivers/pci/msi/msi.c | 4 ++-- 3 files changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/pci/msi/msi.h b/drivers/pci/msi/msi.h index ee53cf079f4e..8009d69bf9a5 100644 --- a/drivers/pci/msi/msi.h +++ b/drivers/pci/msi/msi.h @@ -93,7 +93,8 @@ extern int pci_msi_enable; void pci_msi_shutdown(struct pci_dev *dev); void pci_msix_shutdown(struct pci_dev *dev); void pci_free_msi_irqs(struct pci_dev *dev); -int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec, st= ruct irq_affinity *affd); +int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec, + struct irq_affinity *affd, dma_addr_t iova); int __pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entrie= s, int minvec, int maxvec, struct irq_affinity *affd, int flags); void __pci_restore_msi_state(struct pci_dev *dev); diff --git a/drivers/pci/msi/api.c b/drivers/pci/msi/api.c index b956ce591f96..99ade7f69cd4 100644 --- a/drivers/pci/msi/api.c +++ b/drivers/pci/msi/api.c @@ -29,7 +29,8 @@ */ int pci_enable_msi(struct pci_dev *dev) { - int rc =3D __pci_enable_msi_range(dev, 1, 1, NULL); + int rc =3D __pci_enable_msi_range(dev, 1, 1, NULL, + PHYS_ADDR_MAX); if (rc < 0) return rc; return 0; @@ -274,7 +275,8 @@ int pci_alloc_irq_vectors_affinity(struct pci_dev *dev,= unsigned int min_vecs, } =20 if (flags & PCI_IRQ_MSI) { - nvecs =3D __pci_enable_msi_range(dev, min_vecs, max_vecs, affd); + nvecs =3D __pci_enable_msi_range(dev, min_vecs, max_vecs, + affd, PHYS_ADDR_MAX); if (nvecs > 0) return nvecs; } diff --git a/drivers/pci/msi/msi.c b/drivers/pci/msi/msi.c index 95caa81d3421..25da0435c674 100644 --- a/drivers/pci/msi/msi.c +++ b/drivers/pci/msi/msi.c @@ -417,7 +417,7 @@ static int msi_capability_init(struct pci_dev *dev, int= nvec, } =20 int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec, - struct irq_affinity *affd) + struct irq_affinity *affd, dma_addr_t iova) { int nvec; int rc; @@ -460,7 +460,7 @@ int __pci_enable_msi_range(struct pci_dev *dev, int min= vec, int maxvec, return -ENOSPC; } =20 - rc =3D msi_capability_init(dev, nvec, affd, PHYS_ADDR_MAX); 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Fri, 8 Nov 2024 21:49:01 -0800 From: Nicolin Chen To: , , , CC: , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH RFCv1 5/7] PCI/MSI: Extract a common __pci_alloc_irq_vectors function Date: Fri, 8 Nov 2024 21:48:50 -0800 Message-ID: <0c09c2b1cef3eb085a2f4fd33105eb18aed2b611.1731130093.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A104:EE_|SN7PR12MB8103:EE_ X-MS-Office365-Filtering-Correlation-Id: a84e2032-2e31-45be-a94f-08dd00823d2e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|1800799024|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?jU6MCsoweLdVtWf3F1s+Vge4zLy4yxylCa+JsSdnVT62SYTR8w9DNhU03YB0?= =?us-ascii?Q?BGf6pSFaRxtxiqHSJGjLQeAWbFyzL+aKAUWU3OHU6tySbixiFFxMVyQb03wN?= =?us-ascii?Q?P3ZU7TXrIIWQEtM/Cj2yzxPTxdeqUZBfO1tHgtk4iMTVA7DM/Ryve3WVH6mO?= =?us-ascii?Q?NgewTRKkiRUNV2UTcZBeTkwq3ee7/Pf0b0lWc6aP/xQ75TETGoAnpOEhIfER?= =?us-ascii?Q?fbTenYdhanqo0ZTMftVIqr4D2mctFh/aag4LO1x/vtR/XKAmLYMDUCXEC4hv?= =?us-ascii?Q?3njMMJvTfn8mA0RX7/QgFsX3vfMEg/R9IakQP2pstJIZmWzppPKDtqgix7cb?= =?us-ascii?Q?oHsQgmVAn/iKFN+SHeCT64hNAwjM+KdLkwWt1yfJkr4pENYoe5UQm67M7AvP?= =?us-ascii?Q?u0HT/+yagE0vaMBhnwQ0VBZOuJm2kIBpuyjwFeTAjswKThCvIcs6wxV2p+GV?= =?us-ascii?Q?HIYojQ7zAjjgchF+jHJCJ+aHwSsCAGtcE4UXsbrh1gdfLkSWyG3N4hbspaJJ?= =?us-ascii?Q?J1AHkmutq6eFeA63+qve6lR91VLpIODqjDrdxtVTHvAQxfhj3T+jH8ug4NXq?= =?us-ascii?Q?ggV6ufAv/bZ0IjF4CzLWkm1DBAitOg6AjAOqz8ufx5Bw4YejD9N65iM9cqCE?= =?us-ascii?Q?guP0rJWCt3eTcvziJDCjDA67jUlck2nRK5ZSb78FJm07lWvE5XhqmPNWEmoO?= =?us-ascii?Q?c6w6XobJXoLkBqxDPVg1sp518xbeGYzjFxcv9aDqyih9lb4QhkE2zCJAcT5e?= =?us-ascii?Q?md71kS+rHQRBduig0Sm5MrKJ4nwAkXBw8IDBmG6BamuEm87j0ei2D++my7uE?= =?us-ascii?Q?1PpdlIgLwPjX194kHWqbGQ2an/awDuKCE0rE+M6hDUbYTBbswd+iGhD0ycPj?= =?us-ascii?Q?wQKEdHYCv6YUuNl312MaQ9SIJpM+nHAKs97RdLtYcyeaAsYg92UAklNj4M+3?= =?us-ascii?Q?WnEstexyfFVJxzloAu0Rha8qfy5aDQxhf7w8v/n06/k3oui06Y2cF8dWs2RD?= =?us-ascii?Q?YF9z+g/WkG4Bfx5iqhS6yAkIzN+2qz7xYevXk2rXjztDZLxRnNRertLd/on6?= =?us-ascii?Q?kALPJoUbiv1k8wiO0ghMMMZwp6BfmwJP5plkHz0mQeunmUaHafaAKncu7qaq?= =?us-ascii?Q?pGYIZ8Ss9rCPkTg8V+Cgnf/Mw2TakP7W/ddTr0TWL3Xi3LfTwUVkKe5hKOT5?= =?us-ascii?Q?ak5BFge14w2ZB5ohdhs5sWhDwfZOYYwhlK+ExHNMuz7AcoeO/JpZkF0lgqP/?= =?us-ascii?Q?1NaKygJlje8YN/8Dg6pd3YKSeeTaWcPJcIeYqJ3MRBFVztujxqBpE0hTAPIW?= =?us-ascii?Q?oks5s5ZganaEl++b0u+FLjI3Fn6Gmi5/Gt4t3ndjvxge9hAtiu7ZBA8nVS6E?= =?us-ascii?Q?iGsX3AHIRalxALHDx5MRHw/Nq2WMA6wVwSLqBDXr9PgxVIDwsw=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(376014)(1800799024)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Nov 2024 05:49:12.6663 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a84e2032-2e31-45be-a94f-08dd00823d2e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A104.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB8103 Content-Type: text/plain; charset="utf-8" Extract a common function from the existing callers, to prepare for a new helper that provides an array of msi_iovas. Also, extract the msi_iova(s) from the array and pass in properly down to __pci_enable_msi/msix_range(). Signed-off-by: Nicolin Chen --- drivers/pci/msi/api.c | 113 ++++++++++++++++++++++++++---------------- 1 file changed, 70 insertions(+), 43 deletions(-) diff --git a/drivers/pci/msi/api.c b/drivers/pci/msi/api.c index 99ade7f69cd4..dff3d7350b38 100644 --- a/drivers/pci/msi/api.c +++ b/drivers/pci/msi/api.c @@ -204,6 +204,72 @@ void pci_disable_msix(struct pci_dev *dev) } EXPORT_SYMBOL(pci_disable_msix); =20 +static int __pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_v= ecs, + unsigned int max_vecs, unsigned int flags, + struct irq_affinity *affd, + dma_addr_t *msi_iovas) +{ + struct irq_affinity msi_default_affd =3D {0}; + int nvecs =3D -ENOSPC; + + if (flags & PCI_IRQ_AFFINITY) { + if (!affd) + affd =3D &msi_default_affd; + } else { + if (WARN_ON(affd)) + affd =3D NULL; + } + + if (flags & PCI_IRQ_MSIX) { + struct msix_entry *entries =3D NULL; + + if (msi_iovas) { + int count =3D max_vecs - min_vecs + 1; + int i; + + entries =3D kcalloc(max_vecs - min_vecs + 1, + sizeof(*entries), GFP_KERNEL); + if (!entries) + return -ENOMEM; + for (i =3D 0; i < count; i++) { + entries[i].entry =3D i; + entries[i].iova =3D msi_iovas[i]; + } + } + + nvecs =3D __pci_enable_msix_range(dev, entries, min_vecs, + max_vecs, affd, flags); + kfree(entries); + if (nvecs > 0) + return nvecs; + } + + if (flags & PCI_IRQ_MSI) { + nvecs =3D __pci_enable_msi_range(dev, min_vecs, max_vecs, affd, + msi_iovas ? *msi_iovas : + PHYS_ADDR_MAX); + if (nvecs > 0) + return nvecs; + } + + /* use INTx IRQ if allowed */ + if (flags & PCI_IRQ_INTX) { + if (min_vecs =3D=3D 1 && dev->irq) { + /* + * Invoke the affinity spreading logic to ensure that + * the device driver can adjust queue configuration + * for the single interrupt case. + */ + if (affd) + irq_create_affinity_masks(1, affd); + pci_intx(dev, 1); + return 1; + } + } + + return nvecs; +} + /** * pci_alloc_irq_vectors() - Allocate multiple device interrupt vectors * @dev: the PCI device to operate on @@ -235,8 +301,8 @@ EXPORT_SYMBOL(pci_disable_msix); int pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, unsigned int max_vecs, unsigned int flags) { - return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, - flags, NULL); + return __pci_alloc_irq_vectors(dev, min_vecs, max_vecs, + flags, NULL, NULL); } EXPORT_SYMBOL(pci_alloc_irq_vectors); =20 @@ -256,47 +322,8 @@ int pci_alloc_irq_vectors_affinity(struct pci_dev *dev= , unsigned int min_vecs, unsigned int max_vecs, unsigned int flags, struct irq_affinity *affd) { - struct irq_affinity msi_default_affd =3D {0}; - int nvecs =3D -ENOSPC; - - if (flags & PCI_IRQ_AFFINITY) { - if (!affd) - affd =3D &msi_default_affd; - } else { - if (WARN_ON(affd)) - affd =3D NULL; - } - - if (flags & PCI_IRQ_MSIX) { - nvecs =3D __pci_enable_msix_range(dev, NULL, min_vecs, max_vecs, - affd, flags); - if (nvecs > 0) - return nvecs; - } - - if (flags & PCI_IRQ_MSI) { - nvecs =3D __pci_enable_msi_range(dev, min_vecs, max_vecs, - affd, PHYS_ADDR_MAX); - if (nvecs > 0) - return nvecs; - } - - /* use INTx IRQ if allowed */ - if (flags & PCI_IRQ_INTX) { - if (min_vecs =3D=3D 1 && dev->irq) { - /* - * Invoke the affinity spreading logic to ensure that - * the device driver can adjust queue configuration - * for the single interrupt case. - */ - if (affd) - irq_create_affinity_masks(1, affd); - pci_intx(dev, 1); - return 1; - } - } - - return nvecs; + return __pci_alloc_irq_vectors(dev, min_vecs, max_vecs, + flags, affd, NULL); } EXPORT_SYMBOL(pci_alloc_irq_vectors_affinity); =20 --=20 2.43.0 From nobody Sat Nov 23 23:06:59 2024 Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2055.outbound.protection.outlook.com [40.107.237.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 52BBE146017; Sat, 9 Nov 2024 05:49:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.237.55 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731131354; cv=fail; b=GOx3GhLYNNDDeuD1MEl49BYM8648/DZYb1uLwqWZ7iOOQOB2HTEplaEElZxWti29Ziy/ieffCwXOQcG9cO41vzFofv/iTipRcltR4q8FBXu284GzmGIaTafpjmpjwK1afhQOgNhbJI/gFpSA/aeJV/ngkWE/bID7K3pXA8madKY= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Nov 2024 05:49:05.5258 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 81d2d01d-8d46-48b0-deda-08dd008238d2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE8.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM3PR12MB9413 Content-Type: text/plain; charset="utf-8" Now, the common __pci_alloc_irq_vectors() accepts an array of msi_iovas, which is a list of preset IOVAs for MSI doorbell addresses. Add a helper that would pass in a list. A following patch will call this to forward msi_iovas from user space. Signed-off-by: Nicolin Chen --- include/linux/pci.h | 17 +++++++++++++++++ drivers/pci/msi/api.c | 21 +++++++++++++++++++++ 2 files changed, 38 insertions(+) diff --git a/include/linux/pci.h b/include/linux/pci.h index 68ebb9d42f7f..6423bee3b207 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1678,6 +1678,9 @@ int pci_alloc_irq_vectors(struct pci_dev *dev, unsign= ed int min_vecs, int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_v= ecs, unsigned int max_vecs, unsigned int flags, struct irq_affinity *affd); +int pci_alloc_irq_vectors_iovas(struct pci_dev *dev, unsigned int min_vecs, + unsigned int max_vecs, unsigned int flags, + dma_addr_t *msi_iovas); =20 bool pci_msix_can_alloc_dyn(struct pci_dev *dev); struct msi_map pci_msix_alloc_irq_at(struct pci_dev *dev, unsigned int ind= ex, @@ -1714,6 +1717,13 @@ pci_alloc_irq_vectors_affinity(struct pci_dev *dev, = unsigned int min_vecs, return -ENOSPC; } static inline int +pci_alloc_irq_vectors_iovas(struct pci_dev *dev, unsigned int min_vecs, + unsigned int max_vecs, unsigned int flags, + dma_addr_t *msi_iovas) + + return -ENOSPC; /* No support if !CONFIG_PCI_MSI */ +} +static inline int pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, unsigned int max_vecs, unsigned int flags) { @@ -2068,6 +2078,13 @@ pci_alloc_irq_vectors_affinity(struct pci_dev *dev, = unsigned int min_vecs, return -ENOSPC; } static inline int +pci_alloc_irq_vectors_iovas(struct pci_dev *dev, unsigned int min_vecs, + unsigned int max_vecs, unsigned int flags, + dma_addr_t *msi_iovas) +{ + return -ENOSPC; +} +static inline int pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, unsigned int max_vecs, unsigned int flags) { diff --git a/drivers/pci/msi/api.c b/drivers/pci/msi/api.c index dff3d7350b38..4e90ef8f571c 100644 --- a/drivers/pci/msi/api.c +++ b/drivers/pci/msi/api.c @@ -327,6 +327,27 @@ int pci_alloc_irq_vectors_affinity(struct pci_dev *dev= , unsigned int min_vecs, } EXPORT_SYMBOL(pci_alloc_irq_vectors_affinity); =20 +/** + * pci_alloc_irq_vectors_iovas() - Allocate multiple device interrupt + * vectors with preset msi_iovas + * @dev: the PCI device to operate on + * @min_vecs: minimum required number of vectors (must be >=3D 1) + * @max_vecs: maximum desired number of vectors + * @flags: allocation flags, as in pci_alloc_irq_vectors() + * @msi_iovas: list of IOVAs for MSI between [min_vecs, max_vecs] + * + * Same as pci_alloc_irq_vectors(), but with the extra @msi_iovas paramete= r. + * Check that function docs, and &struct irq_affinity, for more details. + */ +int pci_alloc_irq_vectors_iovas(struct pci_dev *dev, unsigned int min_vecs, + unsigned int max_vecs, unsigned int flags, + dma_addr_t *msi_iovas) +{ + return __pci_alloc_irq_vectors(dev, min_vecs, max_vecs, + flags, NULL, msi_iovas); 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Fri, 8 Nov 2024 21:49:04 -0800 From: Nicolin Chen To: , , , CC: , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH RFCv1 7/7] vfio/pci: Allow preset MSI IOVAs via VFIO_IRQ_SET_ACTION_PREPARE Date: Fri, 8 Nov 2024 21:48:52 -0800 Message-ID: <07623edc330420376e235607285a0f56b54787f2.1731130093.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A104:EE_|DM6PR12MB4451:EE_ X-MS-Office365-Filtering-Correlation-Id: 898678ff-363d-4644-f709-08dd00823ee2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|7416014|376014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?4RGZzPd0VzgeAZB96EogBoPROCYecdCFNJKjuqpVSdZIWrM21uOMeRDfslRi?= =?us-ascii?Q?HxHgaKIDQyhuTpCOfy6lyng/pa3h6lj1fnDdDY+szsz/zqocJx8we8mMTB1G?= =?us-ascii?Q?UMS9f3G/iRx6SBQl34QV+lTNkUne/iKNPTzJ8wi44SZSS1UW5ulRe3v5E6LW?= =?us-ascii?Q?jgfMmhAVTQ+Yxmj9cZV4xPG6T+GWlS6pu3GgjqQ1HLWPJ+an+cvhnSt5zAv3?= =?us-ascii?Q?X44rvYhZJserliTGicLU13mkZS6G6qF9G6uyG5xqnrArXAniW+5nAYirVpq9?= =?us-ascii?Q?z5hyvhgN7VkioNevU4GA7UyZTHAUpI9tiCAmkz3KQjx5g0cpEI7z4xOpgaEp?= =?us-ascii?Q?YIK61SI8XLHhzy7/hOZflcgpxJcCgiPmLkO6MK59C7Xm83xqsdQWbETlYO27?= =?us-ascii?Q?v01Uqw24yz4kgHDHu9nGh0gYQiR6Rc07Dq23qgI4AikTLHpRH5hD6mGwY92I?= =?us-ascii?Q?u7SkP8rvEAs/HRPUcf1i63r4zJ1Rhnu2EPJV1tX8rxDrofbdhcpUIyx8xXR+?= =?us-ascii?Q?pOAUmK0ulE3QUjOCgtUu3spKxHpb4LtBk9QPwxZk4uDDdGq7Bj98wAxmBcpK?= =?us-ascii?Q?sex3FOlO02ZxN7UoUy0NI7vFGZt7V8BVW2X0nzkh2NvGYenqkQgqtd+Q9i1v?= =?us-ascii?Q?25hzDOl4neLHZk0NGPipSLQfPz3blqodfGcHnhYyBpgM2IrHnDX3eEeXsO3P?= =?us-ascii?Q?RAbEHlNVe8pJmVu3tx3Oi9dFEc0zIPbKRw3xd+gp+wKUeJygnu00sfrWo/ef?= =?us-ascii?Q?98jTWMnTmeVIXXB1Yia1XjjS4vi4SkobnS3KHLVYN1BCz3WT9M5SQbjX7KOq?= =?us-ascii?Q?Avm/66MeWcptuvNsWtIIOOL6DL14u5dYiSGsk04r1MPJMrNEktTkgTUdUEuh?= =?us-ascii?Q?3svwpgJJ3PmEVRVnxowSWt9r3/pJB4JRt7oTCQV5765TWn/qr48lay59LkUq?= =?us-ascii?Q?xza2kJvlROc5jglpIAeoG+Wp+svBz0wESY0dM/kSV9MuXpupCxKU1IwWY0WA?= =?us-ascii?Q?7AA/s7yC2MuCi+CZ3iVHBFKwO4swZIqODUClajQY4rU3eCoXKbQjV6bC+e3Y?= =?us-ascii?Q?z73MT2oFMP3YGkPLbaD4J3AyTv2ycdexADB86Pz2JXB5u4hHpNK8CQ+ZiAfP?= =?us-ascii?Q?WEbpwsEIpw+z5M50Ww5tHnEoII+FqLfQX8Ju7MU3Sgpin2yxlmACfljDSZsQ?= =?us-ascii?Q?VWNRIk8eCy5wSvMabhk5L8Tix3anxvzw7I9WfCP416JezQrWtXVj0+ZON7g3?= =?us-ascii?Q?lz4vJadC5kvH5+v5ybSIlW8i+hM+av2WVy/xtiljdP+L4CF/xHe/9mvOmXCZ?= =?us-ascii?Q?wEpe7ubCBarhqE9CQsFYIXw6r5M0jzayiW9iLoZG5fxzve04tTXzH98jYM0+?= =?us-ascii?Q?EMq8RbePLR3jT5oKcdJeep6oGZ2rDqf32aZCk7cIpA7HMgqiHQ=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(7416014)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Nov 2024 05:49:15.5882 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 898678ff-363d-4644-f709-08dd00823ee2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A104.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4451 Content-Type: text/plain; charset="utf-8" Add a new VFIO_IRQ_SET_ACTION_PREPARE to set VFIO_IRQ_SET_DATA_MSI_IOVA, giving user space an interface to forward to kernel the stage-1 IOVA (of a 2-stage translation: IOVA->IPA->PA) for an MSI doorbell address, since the ITS hardware needs to be programmed with the top level IOVA address, in order to work with the IOMMU on ARM64. Signed-off-by: Nicolin Chen --- include/linux/vfio_pci_core.h | 1 + include/uapi/linux/vfio.h | 8 ++++-- drivers/vfio/pci/vfio_pci_intrs.c | 41 ++++++++++++++++++++++++++++++- drivers/vfio/vfio_main.c | 3 +++ 4 files changed, 50 insertions(+), 3 deletions(-) diff --git a/include/linux/vfio_pci_core.h b/include/linux/vfio_pci_core.h index fbb472dd99b3..08027b8331f0 100644 --- a/include/linux/vfio_pci_core.h +++ b/include/linux/vfio_pci_core.h @@ -63,6 +63,7 @@ struct vfio_pci_core_device { int irq_type; int num_regions; struct vfio_pci_region *region; + dma_addr_t *msi_iovas; u8 msi_qmax; u8 msix_bar; u16 msix_size; diff --git a/include/uapi/linux/vfio.h b/include/uapi/linux/vfio.h index 2b68e6cdf190..d6be351abcde 100644 --- a/include/uapi/linux/vfio.h +++ b/include/uapi/linux/vfio.h @@ -590,6 +590,8 @@ struct vfio_irq_set { #define VFIO_IRQ_SET_ACTION_MASK (1 << 3) /* Mask interrupt */ #define VFIO_IRQ_SET_ACTION_UNMASK (1 << 4) /* Unmask interrupt */ #define VFIO_IRQ_SET_ACTION_TRIGGER (1 << 5) /* Trigger interrupt */ +#define VFIO_IRQ_SET_DATA_MSI_IOVA (1 << 6) /* Data is MSI IOVA (u64) */ +#define VFIO_IRQ_SET_ACTION_PREPARE (1 << 7) /* Prepare interrupt */ __u32 index; __u32 start; __u32 count; @@ -599,10 +601,12 @@ struct vfio_irq_set { =20 #define VFIO_IRQ_SET_DATA_TYPE_MASK (VFIO_IRQ_SET_DATA_NONE | \ VFIO_IRQ_SET_DATA_BOOL | \ - VFIO_IRQ_SET_DATA_EVENTFD) + VFIO_IRQ_SET_DATA_EVENTFD | \ + VFIO_IRQ_SET_DATA_MSI_IOVA) #define VFIO_IRQ_SET_ACTION_TYPE_MASK (VFIO_IRQ_SET_ACTION_MASK | \ VFIO_IRQ_SET_ACTION_UNMASK | \ - VFIO_IRQ_SET_ACTION_TRIGGER) + VFIO_IRQ_SET_ACTION_TRIGGER | \ + VFIO_IRQ_SET_ACTION_PREPARE) /** * VFIO_DEVICE_RESET - _IO(VFIO_TYPE, VFIO_BASE + 11) * diff --git a/drivers/vfio/pci/vfio_pci_intrs.c b/drivers/vfio/pci/vfio_pci_= intrs.c index 8382c5834335..18bcdc5b1ef5 100644 --- a/drivers/vfio/pci/vfio_pci_intrs.c +++ b/drivers/vfio/pci/vfio_pci_intrs.c @@ -383,7 +383,7 @@ static int vfio_msi_enable(struct vfio_pci_core_device = *vdev, int nvec, bool msi =20 /* return the number of supported vectors if we can't get all: */ cmd =3D vfio_pci_memory_lock_and_enable(vdev); - ret =3D pci_alloc_irq_vectors(pdev, 1, nvec, flag); + ret =3D pci_alloc_irq_vectors_iovas(pdev, 1, nvec, flag, vdev->msi_iovas); if (ret < nvec) { if (ret > 0) pci_free_irq_vectors(pdev); @@ -685,6 +685,9 @@ static int vfio_pci_set_msi_trigger(struct vfio_pci_cor= e_device *vdev, =20 if (irq_is(vdev, index) && !count && (flags & VFIO_IRQ_SET_DATA_NONE)) { vfio_msi_disable(vdev, msix); + /* FIXME we need a better cleanup routine */ + kfree(vdev->msi_iovas); + vdev->msi_iovas =3D NULL; return 0; } =20 @@ -728,6 +731,39 @@ static int vfio_pci_set_msi_trigger(struct vfio_pci_co= re_device *vdev, return 0; } =20 +static int vfio_pci_set_msi_prepare(struct vfio_pci_core_device *vdev, + unsigned index, unsigned start, + unsigned count, uint32_t flags, void *data) +{ + uint64_t *iovas =3D data; + unsigned int i; + + if (!(irq_is(vdev, index) || is_irq_none(vdev))) + return -EINVAL; + + if (flags & VFIO_IRQ_SET_DATA_NONE) { + if (!count) + return -EINVAL; + /* FIXME support partial unset */ + kfree(vdev->msi_iovas); + vdev->msi_iovas =3D NULL; + return 0; + } + + if (!(flags & VFIO_IRQ_SET_DATA_MSI_IOVA)) + return -EOPNOTSUPP; + if (!IS_ENABLED(CONFIG_IRQ_MSI_IOMMU)) + return -EOPNOTSUPP; + if (!vdev->msi_iovas) + vdev->msi_iovas =3D kcalloc(count, sizeof(dma_addr_t), GFP_KERNEL); + if (!vdev->msi_iovas) + return -ENOMEM; + for (i =3D 0; i < count; i++) + vdev->msi_iovas[i] =3D iovas[i]; + + return 0; +} + static int vfio_pci_set_ctx_trigger_single(struct eventfd_ctx **ctx, unsigned int count, uint32_t flags, void *data) @@ -837,6 +873,9 @@ int vfio_pci_set_irqs_ioctl(struct vfio_pci_core_device= *vdev, uint32_t flags, case VFIO_IRQ_SET_ACTION_TRIGGER: func =3D vfio_pci_set_msi_trigger; break; + case VFIO_IRQ_SET_ACTION_PREPARE: + func =3D vfio_pci_set_msi_prepare; + break; } break; case VFIO_PCI_ERR_IRQ_INDEX: diff --git a/drivers/vfio/vfio_main.c b/drivers/vfio/vfio_main.c index a5a62d9d963f..61211c082a64 100644 --- a/drivers/vfio/vfio_main.c +++ b/drivers/vfio/vfio_main.c @@ -1554,6 +1554,9 @@ int vfio_set_irqs_validate_and_prepare(struct vfio_ir= q_set *hdr, int num_irqs, case VFIO_IRQ_SET_DATA_EVENTFD: size =3D sizeof(int32_t); break; + case VFIO_IRQ_SET_DATA_MSI_IOVA: + size =3D sizeof(uint64_t); + break; default: return -EINVAL; } --=20 2.43.0