From nobody Mon Nov 25 11:55:00 2024 Received: from mail-pl1-f180.google.com (mail-pl1-f180.google.com [209.85.214.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6E4561B815; Mon, 28 Oct 2024 03:07:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730084878; cv=none; b=ZDhhbvKsm3VcA3kxqL/GJlC0OF5hFrp89MSysGezreYpBX48zicCRi0+VSs1V23BoGCd/nkgDA166ZBHIsPgJFMZ4XZSmQ5+PLW41HcUbKPbKGHpG+QmqYRWkG4ELj6XDTxMVVSa2EaR2eRI6YglGx43zOXGTc4ndibH4Hfj0dQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730084878; c=relaxed/simple; bh=yAvB6cVpIwKDppgU1iwS2RXsmxheZHy7TvtAMdpmMko=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=i/YablZXOaPOW2MGCid3k0EtnLbbrT0saWNuWHKkuubFLxPE6ic71qvvZ6Im542d99WJAYRzGGNKgK+1+D/J9mlbeLcEl/lY5WDDt5WUmdMTkweGHcRBcC9wOxHvVz8zzHd/KNKqJwiuomVkhg586B0c3jgFlC/p8M60vLws03E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=kyNn9ae3; arc=none smtp.client-ip=209.85.214.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="kyNn9ae3" Received: by mail-pl1-f180.google.com with SMTP id d9443c01a7336-207115e3056so30929505ad.2; Sun, 27 Oct 2024 20:07:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730084873; x=1730689673; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bdryZOMhxiW4npFPYp0MqfeoyxH5M3xaITVAKSd/8NQ=; b=kyNn9ae3fLHQ4dvTz/NSSK9Gj52mHprOeYP3/hKSzoTczsBxfxZn3TY+jXvIyI3U+/ dGgJEncf99AAW9jHPuUxcDOhsbURb/DrJ0e8wFlTrquktBLCZ6OZPqhi4ZYq/maPcLAh BpoxfPdRTD1L4dgxWJY4p1ufe+9EWIPMX//5PjSR36Wso1nMNqXlxunjretgsijV0UCb fmxkL1L37Ylp94/tG57Er1UxfFRJnVAOfEM4Sq4hujO/+pMbUTafMfTuRWLVJDYxTsTZ m+qeR02mKCMIrf/ViCF/DkdBq7Xtewm0bD5vx2UUyhLQZSN2RU7OJkQeZmEXLEEpGhTV IkVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730084873; x=1730689673; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bdryZOMhxiW4npFPYp0MqfeoyxH5M3xaITVAKSd/8NQ=; b=mrS5WUV1GvY6QjT/x5eXXxa9cTeSrBiJ52GAoB7B70T7CIGCQN8V5HwoPpoHcAdcTg UxhhK9GAgS2fJsP0QZKHXi5XK9IeJvPgPlRE2nGAvd3WjHOzNTkPO0yBz4Cb9GT/ChQz h1saRX3JWkdgSNoKPWFGdigpliOfYJ4U5Hksn5JCQoCDGt4aJMrP1debifp1zc1ZwcHA V9kGDlh2bkr9We3uZOUir4YGBsHIU8siOmVwXoH2HSLjesqohki4tx9/9RB4WsNFAlnY Iq4x50NTKTm0OJppeqIIrIIyQOWIxso8wdGFTIvS4jed7B6QWdjTsVxaZdoN/3TMGOHA KJHw== X-Forwarded-Encrypted: i=1; AJvYcCWC5lHuZ17F0TwMG7KJTrrpyM81yj55slUKwnWnM3lFcl57CyFiWIvovcr4cyrhjAWZg0VnSMs20H/6V5A=@vger.kernel.org X-Gm-Message-State: AOJu0YzWrxd3BYK5Ncg/lXaE+tRcCjYhQ/IfG6G1/zbOZYLg8i7SEYMV 6EOVSNfQkSI4vE5pjQUw1HvPQrnfTlmGooKvoGblRnxYQ/nfanCFrojx/g== X-Google-Smtp-Source: AGHT+IFzRZ9DjbmuVYzFvvjNuJbQo3a8bYII8XSWuhLrssuP3J41UOuOfUhtXNULlz5ic8lf2rKqrA== X-Received: by 2002:a17:903:228b:b0:20b:fd73:32bb with SMTP id d9443c01a7336-210c6872da0mr90208335ad.2.1730084872647; Sun, 27 Oct 2024 20:07:52 -0700 (PDT) Received: from localhost.localdomain ([129.146.253.192]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-210bbf6d327sm41414155ad.67.2024.10.27.20.07.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Oct 2024 20:07:52 -0700 (PDT) From: Furong Xu <0x1207@gmail.com> To: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Vladimir Oltean , Andrew Lunn , Simon Horman , andrew+netdev@lunn.ch, Alexandre Torgue , Jose Abreu , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , xfr@outlook.com, Furong Xu <0x1207@gmail.com> Subject: [PATCH net-next v5 1/6] net: stmmac: Introduce separate files for FPE implementation Date: Mon, 28 Oct 2024 11:07:24 +0800 Message-Id: <458bba8b76c65a3f24fd8df6780d386bb88791ab.1730084449.git.0x1207@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" By moving FPE related code info separate files, FPE implementation becomes a separate module initially. No functional change intended. Signed-off-by: Furong Xu <0x1207@gmail.com> Reviewed-by: Simon Horman Reviewed-by: Vladimir Oltean --- drivers/net/ethernet/stmicro/stmmac/Makefile | 2 +- .../net/ethernet/stmicro/stmmac/dwmac4_core.c | 1 + drivers/net/ethernet/stmicro/stmmac/dwmac5.c | 150 -------- drivers/net/ethernet/stmicro/stmmac/dwmac5.h | 26 -- .../net/ethernet/stmicro/stmmac/dwxgmac2.h | 2 - .../ethernet/stmicro/stmmac/dwxgmac2_core.c | 27 +- drivers/net/ethernet/stmicro/stmmac/stmmac.h | 10 - .../ethernet/stmicro/stmmac/stmmac_ethtool.c | 2 +- .../net/ethernet/stmicro/stmmac/stmmac_fpe.c | 354 ++++++++++++++++++ .../net/ethernet/stmicro/stmmac/stmmac_fpe.h | 45 +++ .../net/ethernet/stmicro/stmmac/stmmac_main.c | 149 +------- 11 files changed, 405 insertions(+), 363 deletions(-) create mode 100644 drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.c create mode 100644 drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.h diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/eth= ernet/stmicro/stmmac/Makefile index c2f0e91f6bf8..7e46dca90628 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Makefile +++ b/drivers/net/ethernet/stmicro/stmmac/Makefile @@ -6,7 +6,7 @@ stmmac-objs:=3D stmmac_main.o stmmac_ethtool.o stmmac_mdio.= o ring_mode.o \ mmc_core.o stmmac_hwtstamp.o stmmac_ptp.o dwmac4_descs.o \ dwmac4_dma.o dwmac4_lib.o dwmac4_core.o dwmac5.o hwif.o \ stmmac_tc.o dwxgmac2_core.o dwxgmac2_dma.o dwxgmac2_descs.o \ - stmmac_xdp.o stmmac_est.o \ + stmmac_xdp.o stmmac_est.o stmmac_fpe.o \ $(stmmac-y) =20 stmmac-$(CONFIG_STMMAC_SELFTESTS) +=3D stmmac_selftests.o diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c b/drivers/ne= t/ethernet/stmicro/stmmac/dwmac4_core.c index e65a65666cc1..4d217926820a 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c @@ -16,6 +16,7 @@ #include #include #include "stmmac.h" +#include "stmmac_fpe.h" #include "stmmac_pcs.h" #include "dwmac4.h" #include "dwmac5.h" diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac5.c b/drivers/net/eth= ernet/stmicro/stmmac/dwmac5.c index 08add508db84..1c431b918719 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac5.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac5.c @@ -572,153 +572,3 @@ int dwmac5_flex_pps_config(void __iomem *ioaddr, int = index, writel(val, ioaddr + MAC_PPS_CONTROL); return 0; } - -void dwmac5_fpe_configure(void __iomem *ioaddr, struct stmmac_fpe_cfg *cfg, - u32 num_txq, u32 num_rxq, - bool tx_enable, bool pmac_enable) -{ - u32 value; - - if (tx_enable) { - cfg->fpe_csr =3D EFPE; - value =3D readl(ioaddr + GMAC_RXQ_CTRL1); - value &=3D ~GMAC_RXQCTRL_FPRQ; - value |=3D (num_rxq - 1) << GMAC_RXQCTRL_FPRQ_SHIFT; - writel(value, ioaddr + GMAC_RXQ_CTRL1); - } else { - cfg->fpe_csr =3D 0; - } - writel(cfg->fpe_csr, ioaddr + MAC_FPE_CTRL_STS); - - value =3D readl(ioaddr + GMAC_INT_EN); - - if (pmac_enable) { - if (!(value & GMAC_INT_FPE_EN)) { - /* Dummy read to clear any pending masked interrupts */ - readl(ioaddr + MAC_FPE_CTRL_STS); - - value |=3D GMAC_INT_FPE_EN; - } - } else { - value &=3D ~GMAC_INT_FPE_EN; - } - - writel(value, ioaddr + GMAC_INT_EN); -} - -int dwmac5_fpe_irq_status(void __iomem *ioaddr, struct net_device *dev) -{ - u32 value; - int status; - - status =3D FPE_EVENT_UNKNOWN; - - /* Reads from the MAC_FPE_CTRL_STS register should only be performed - * here, since the status flags of MAC_FPE_CTRL_STS are "clear on read" - */ - value =3D readl(ioaddr + MAC_FPE_CTRL_STS); - - if (value & TRSP) { - status |=3D FPE_EVENT_TRSP; - netdev_dbg(dev, "FPE: Respond mPacket is transmitted\n"); - } - - if (value & TVER) { - status |=3D FPE_EVENT_TVER; - netdev_dbg(dev, "FPE: Verify mPacket is transmitted\n"); - } - - if (value & RRSP) { - status |=3D FPE_EVENT_RRSP; - netdev_dbg(dev, "FPE: Respond mPacket is received\n"); - } - - if (value & RVER) { - status |=3D FPE_EVENT_RVER; - netdev_dbg(dev, "FPE: Verify mPacket is received\n"); - } - - return status; -} - -void dwmac5_fpe_send_mpacket(void __iomem *ioaddr, struct stmmac_fpe_cfg *= cfg, - enum stmmac_mpacket_type type) -{ - u32 value =3D cfg->fpe_csr; - - if (type =3D=3D MPACKET_VERIFY) - value |=3D SVER; - else if (type =3D=3D MPACKET_RESPONSE) - value |=3D SRSP; - - writel(value, ioaddr + MAC_FPE_CTRL_STS); -} - -int dwmac5_fpe_get_add_frag_size(const void __iomem *ioaddr) -{ - return FIELD_GET(DWMAC5_ADD_FRAG_SZ, readl(ioaddr + MTL_FPE_CTRL_STS)); -} - -void dwmac5_fpe_set_add_frag_size(void __iomem *ioaddr, u32 add_frag_size) -{ - u32 value; - - value =3D readl(ioaddr + MTL_FPE_CTRL_STS); - writel(u32_replace_bits(value, add_frag_size, DWMAC5_ADD_FRAG_SZ), - ioaddr + MTL_FPE_CTRL_STS); -} - -#define ALG_ERR_MSG "TX algorithm SP is not suitable for one-to-many mappi= ng" -#define WEIGHT_ERR_MSG "TXQ weight %u differs across other TXQs in TC: [%u= ]" - -int dwmac5_fpe_map_preemption_class(struct net_device *ndev, - struct netlink_ext_ack *extack, u32 pclass) -{ - u32 val, offset, count, queue_weight, preemptible_txqs =3D 0; - struct stmmac_priv *priv =3D netdev_priv(ndev); - u32 num_tc =3D ndev->num_tc; - - if (!pclass) - goto update_mapping; - - /* DWMAC CORE4+ can not program TC:TXQ mapping to hardware. - * - * Synopsys Databook: - * "The number of Tx DMA channels is equal to the number of Tx queues, - * and is direct one-to-one mapping." - */ - for (u32 tc =3D 0; tc < num_tc; tc++) { - count =3D ndev->tc_to_txq[tc].count; - offset =3D ndev->tc_to_txq[tc].offset; - - if (pclass & BIT(tc)) - preemptible_txqs |=3D GENMASK(offset + count - 1, offset); - - /* This is 1:1 mapping, go to next TC */ - if (count =3D=3D 1) - continue; - - if (priv->plat->tx_sched_algorithm =3D=3D MTL_TX_ALGORITHM_SP) { - NL_SET_ERR_MSG_MOD(extack, ALG_ERR_MSG); - return -EINVAL; - } - - queue_weight =3D priv->plat->tx_queues_cfg[offset].weight; - - for (u32 i =3D 1; i < count; i++) { - if (priv->plat->tx_queues_cfg[offset + i].weight !=3D - queue_weight) { - NL_SET_ERR_MSG_FMT_MOD(extack, WEIGHT_ERR_MSG, - queue_weight, tc); - return -EINVAL; - } - } - } - -update_mapping: - val =3D readl(priv->ioaddr + MTL_FPE_CTRL_STS); - writel(u32_replace_bits(val, preemptible_txqs, DWMAC5_PREEMPTION_CLASS), - priv->ioaddr + MTL_FPE_CTRL_STS); - - return 0; -} diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac5.h b/drivers/net/eth= ernet/stmicro/stmmac/dwmac5.h index 6c6eb6790e83..00b151b3b688 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac5.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac5.h @@ -11,15 +11,6 @@ #define PRTYEN BIT(1) #define TMOUTEN BIT(0) =20 -#define MAC_FPE_CTRL_STS 0x00000234 -#define TRSP BIT(19) -#define TVER BIT(18) -#define RRSP BIT(17) -#define RVER BIT(16) -#define SRSP BIT(2) -#define SVER BIT(1) -#define EFPE BIT(0) - #define MAC_PPS_CONTROL 0x00000b70 #define PPS_MAXIDX(x) ((((x) + 1) * 8) - 1) #define PPS_MINIDX(x) ((x) * 8) @@ -39,12 +30,6 @@ #define MAC_PPSx_INTERVAL(x) (0x00000b88 + ((x) * 0x10)) #define MAC_PPSx_WIDTH(x) (0x00000b8c + ((x) * 0x10)) =20 -#define MTL_FPE_CTRL_STS 0x00000c90 -/* Preemption Classification */ -#define DWMAC5_PREEMPTION_CLASS GENMASK(15, 8) -/* Additional Fragment Size of preempted frames */ -#define DWMAC5_ADD_FRAG_SZ GENMASK(1, 0) - #define MTL_RXP_CONTROL_STATUS 0x00000ca0 #define RXPI BIT(31) #define NPE GENMASK(23, 16) @@ -108,16 +93,5 @@ int dwmac5_rxp_config(void __iomem *ioaddr, struct stmm= ac_tc_entry *entries, int dwmac5_flex_pps_config(void __iomem *ioaddr, int index, struct stmmac_pps_cfg *cfg, bool enable, u32 sub_second_inc, u32 systime_flags); -void dwmac5_fpe_configure(void __iomem *ioaddr, struct stmmac_fpe_cfg *cfg, - u32 num_txq, u32 num_rxq, - bool tx_enable, bool pmac_enable); -void dwmac5_fpe_send_mpacket(void __iomem *ioaddr, - struct stmmac_fpe_cfg *cfg, - enum stmmac_mpacket_type type); -int dwmac5_fpe_irq_status(void __iomem *ioaddr, struct net_device *dev); -int dwmac5_fpe_get_add_frag_size(const void __iomem *ioaddr); -void dwmac5_fpe_set_add_frag_size(void __iomem *ioaddr, u32 add_frag_size); -int dwmac5_fpe_map_preemption_class(struct net_device *ndev, - struct netlink_ext_ack *extack, u32 pclass); =20 #endif /* __DWMAC5_H__ */ diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h b/drivers/net/e= thernet/stmicro/stmmac/dwxgmac2.h index 6a2c7d22df1e..917796293c26 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h @@ -193,8 +193,6 @@ #define XGMAC_MDIO_ADDR 0x00000200 #define XGMAC_MDIO_DATA 0x00000204 #define XGMAC_MDIO_C22P 0x00000220 -#define XGMAC_FPE_CTRL_STS 0x00000280 -#define XGMAC_EFPE BIT(0) #define XGMAC_ADDRx_HIGH(x) (0x00000300 + (x) * 0x8) #define XGMAC_ADDR_MAX 32 #define XGMAC_AE BIT(31) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c b/drivers/= net/ethernet/stmicro/stmmac/dwxgmac2_core.c index f519d43738b0..111ba5a524ed 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c @@ -8,6 +8,7 @@ #include #include #include "stmmac.h" +#include "stmmac_fpe.h" #include "stmmac_ptp.h" #include "dwxlgmac2.h" #include "dwxgmac2.h" @@ -1504,32 +1505,6 @@ static void dwxgmac2_set_arp_offload(struct mac_devi= ce_info *hw, bool en, writel(value, ioaddr + XGMAC_RX_CONFIG); } =20 -static void dwxgmac3_fpe_configure(void __iomem *ioaddr, - struct stmmac_fpe_cfg *cfg, - u32 num_txq, u32 num_rxq, - bool tx_enable, bool pmac_enable) -{ - u32 value; - - if (!tx_enable) { - value =3D readl(ioaddr + XGMAC_FPE_CTRL_STS); - - value &=3D ~XGMAC_EFPE; - - writel(value, ioaddr + XGMAC_FPE_CTRL_STS); - return; - } - - value =3D readl(ioaddr + XGMAC_RXQ_CTRL1); - value &=3D ~XGMAC_RQ; - value |=3D (num_rxq - 1) << XGMAC_RQ_SHIFT; - writel(value, ioaddr + XGMAC_RXQ_CTRL1); - - value =3D readl(ioaddr + XGMAC_FPE_CTRL_STS); - value |=3D XGMAC_EFPE; - writel(value, ioaddr + XGMAC_FPE_CTRL_STS); -} - const struct stmmac_ops dwxgmac210_ops =3D { .core_init =3D dwxgmac2_core_init, .set_mac =3D dwxgmac2_set_mac, diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac.h b/drivers/net/eth= ernet/stmicro/stmmac/stmmac.h index ea135203ff2e..816b979e72cc 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac.h +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac.h @@ -146,15 +146,6 @@ struct stmmac_channel { u32 index; }; =20 -/* FPE link-partner hand-shaking mPacket type */ -enum stmmac_mpacket_type { - MPACKET_VERIFY =3D 0, - MPACKET_RESPONSE =3D 1, -}; - -#define STMMAC_FPE_MM_MAX_VERIFY_RETRIES 3 -#define STMMAC_FPE_MM_MAX_VERIFY_TIME_MS 128 - struct stmmac_fpe_cfg { /* Serialize access to MAC Merge state between ethtool requests * and link state updates. @@ -420,7 +411,6 @@ bool stmmac_eee_init(struct stmmac_priv *priv); int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt); int stmmac_reinit_ringparam(struct net_device *dev, u32 rx_size, u32 tx_si= ze); int stmmac_bus_clks_config(struct stmmac_priv *priv, bool enabled); -void stmmac_fpe_apply(struct stmmac_priv *priv); =20 static inline bool stmmac_xdp_is_enabled(struct stmmac_priv *priv) { diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c b/drivers= /net/ethernet/stmicro/stmmac/stmmac_ethtool.c index 2a37592a6281..2792a4c6cbcd 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c @@ -17,9 +17,9 @@ #include =20 #include "stmmac.h" +#include "stmmac_fpe.h" #include "dwmac_dma.h" #include "dwxgmac2.h" -#include "dwmac5.h" =20 #define REG_SPACE_SIZE 0x1060 #define GMAC4_REG_SPACE_SIZE 0x116C diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.c b/drivers/net= /ethernet/stmicro/stmmac/stmmac_fpe.c new file mode 100644 index 000000000000..0a90e8f0df29 --- /dev/null +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.c @@ -0,0 +1,354 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2024 Furong Xu <0x1207@gmail.com> + * stmmac FPE(802.3 Qbu) handling + */ +#include "stmmac.h" +#include "stmmac_fpe.h" +#include "dwmac4.h" +#include "dwmac5.h" +#include "dwxgmac2.h" + +#define MAC_FPE_CTRL_STS 0x00000234 +#define TRSP BIT(19) +#define TVER BIT(18) +#define RRSP BIT(17) +#define RVER BIT(16) +#define SRSP BIT(2) +#define SVER BIT(1) +#define EFPE BIT(0) + +#define MTL_FPE_CTRL_STS 0x00000c90 +/* Preemption Classification */ +#define DWMAC5_PREEMPTION_CLASS GENMASK(15, 8) +/* Additional Fragment Size of preempted frames */ +#define DWMAC5_ADD_FRAG_SZ GENMASK(1, 0) + +#define XGMAC_FPE_CTRL_STS 0x00000280 +#define XGMAC_EFPE BIT(0) + +void stmmac_fpe_link_state_handle(struct stmmac_priv *priv, bool is_up) +{ + struct stmmac_fpe_cfg *fpe_cfg =3D &priv->fpe_cfg; + unsigned long flags; + + timer_shutdown_sync(&fpe_cfg->verify_timer); + + spin_lock_irqsave(&fpe_cfg->lock, flags); + + if (is_up && fpe_cfg->pmac_enabled) { + /* VERIFY process requires pmac enabled when NIC comes up */ + stmmac_fpe_configure(priv, priv->ioaddr, fpe_cfg, + priv->plat->tx_queues_to_use, + priv->plat->rx_queues_to_use, + false, true); + + /* New link =3D> maybe new partner =3D> new verification process */ + stmmac_fpe_apply(priv); + } else { + /* No link =3D> turn off EFPE */ + stmmac_fpe_configure(priv, priv->ioaddr, fpe_cfg, + priv->plat->tx_queues_to_use, + priv->plat->rx_queues_to_use, + false, false); + } + + spin_unlock_irqrestore(&fpe_cfg->lock, flags); +} + +void stmmac_fpe_event_status(struct stmmac_priv *priv, int status) +{ + struct stmmac_fpe_cfg *fpe_cfg =3D &priv->fpe_cfg; + + /* This is interrupt context, just spin_lock() */ + spin_lock(&fpe_cfg->lock); + + if (!fpe_cfg->pmac_enabled || status =3D=3D FPE_EVENT_UNKNOWN) + goto unlock_out; + + /* LP has sent verify mPacket */ + if ((status & FPE_EVENT_RVER) =3D=3D FPE_EVENT_RVER) + stmmac_fpe_send_mpacket(priv, priv->ioaddr, fpe_cfg, + MPACKET_RESPONSE); + + /* Local has sent verify mPacket */ + if ((status & FPE_EVENT_TVER) =3D=3D FPE_EVENT_TVER && + fpe_cfg->status !=3D ETHTOOL_MM_VERIFY_STATUS_SUCCEEDED) + fpe_cfg->status =3D ETHTOOL_MM_VERIFY_STATUS_VERIFYING; + + /* LP has sent response mPacket */ + if ((status & FPE_EVENT_RRSP) =3D=3D FPE_EVENT_RRSP && + fpe_cfg->status =3D=3D ETHTOOL_MM_VERIFY_STATUS_VERIFYING) + fpe_cfg->status =3D ETHTOOL_MM_VERIFY_STATUS_SUCCEEDED; + +unlock_out: + spin_unlock(&fpe_cfg->lock); +} + +/** + * stmmac_fpe_verify_timer - Timer for MAC Merge verification + * @t: timer_list struct containing private info + * + * Verify the MAC Merge capability in the local TX direction, by + * transmitting Verify mPackets up to 3 times. Wait until link + * partner responds with a Response mPacket, otherwise fail. + */ +static void stmmac_fpe_verify_timer(struct timer_list *t) +{ + struct stmmac_fpe_cfg *fpe_cfg =3D from_timer(fpe_cfg, t, verify_timer); + struct stmmac_priv *priv =3D container_of(fpe_cfg, struct stmmac_priv, + fpe_cfg); + unsigned long flags; + bool rearm =3D false; + + spin_lock_irqsave(&fpe_cfg->lock, flags); + + switch (fpe_cfg->status) { + case ETHTOOL_MM_VERIFY_STATUS_INITIAL: + case ETHTOOL_MM_VERIFY_STATUS_VERIFYING: + if (fpe_cfg->verify_retries !=3D 0) { + stmmac_fpe_send_mpacket(priv, priv->ioaddr, + fpe_cfg, MPACKET_VERIFY); + rearm =3D true; + } else { + fpe_cfg->status =3D ETHTOOL_MM_VERIFY_STATUS_FAILED; + } + + fpe_cfg->verify_retries--; + break; + + case ETHTOOL_MM_VERIFY_STATUS_SUCCEEDED: + stmmac_fpe_configure(priv, priv->ioaddr, fpe_cfg, + priv->plat->tx_queues_to_use, + priv->plat->rx_queues_to_use, + true, true); + break; + + default: + break; + } + + if (rearm) { + mod_timer(&fpe_cfg->verify_timer, + jiffies + msecs_to_jiffies(fpe_cfg->verify_time)); + } + + spin_unlock_irqrestore(&fpe_cfg->lock, flags); +} + +static void stmmac_fpe_verify_timer_arm(struct stmmac_fpe_cfg *fpe_cfg) +{ + if (fpe_cfg->pmac_enabled && fpe_cfg->tx_enabled && + fpe_cfg->verify_enabled && + fpe_cfg->status !=3D ETHTOOL_MM_VERIFY_STATUS_FAILED && + fpe_cfg->status !=3D ETHTOOL_MM_VERIFY_STATUS_SUCCEEDED) { + timer_setup(&fpe_cfg->verify_timer, stmmac_fpe_verify_timer, 0); + mod_timer(&fpe_cfg->verify_timer, jiffies); + } +} + +void stmmac_fpe_init(struct stmmac_priv *priv) +{ + priv->fpe_cfg.verify_retries =3D STMMAC_FPE_MM_MAX_VERIFY_RETRIES; + priv->fpe_cfg.verify_time =3D STMMAC_FPE_MM_MAX_VERIFY_TIME_MS; + priv->fpe_cfg.status =3D ETHTOOL_MM_VERIFY_STATUS_DISABLED; + timer_setup(&priv->fpe_cfg.verify_timer, stmmac_fpe_verify_timer, 0); + spin_lock_init(&priv->fpe_cfg.lock); +} + +void stmmac_fpe_apply(struct stmmac_priv *priv) +{ + struct stmmac_fpe_cfg *fpe_cfg =3D &priv->fpe_cfg; + + /* If verification is disabled, configure FPE right away. + * Otherwise let the timer code do it. + */ + if (!fpe_cfg->verify_enabled) { + stmmac_fpe_configure(priv, priv->ioaddr, fpe_cfg, + priv->plat->tx_queues_to_use, + priv->plat->rx_queues_to_use, + fpe_cfg->tx_enabled, + fpe_cfg->pmac_enabled); + } else { + fpe_cfg->status =3D ETHTOOL_MM_VERIFY_STATUS_INITIAL; + fpe_cfg->verify_retries =3D STMMAC_FPE_MM_MAX_VERIFY_RETRIES; + + if (netif_running(priv->dev)) + stmmac_fpe_verify_timer_arm(fpe_cfg); + } +} + +void dwmac5_fpe_configure(void __iomem *ioaddr, struct stmmac_fpe_cfg *cfg, + u32 num_txq, u32 num_rxq, + bool tx_enable, bool pmac_enable) +{ + u32 value; + + if (tx_enable) { + cfg->fpe_csr =3D EFPE; + value =3D readl(ioaddr + GMAC_RXQ_CTRL1); + value &=3D ~GMAC_RXQCTRL_FPRQ; + value |=3D (num_rxq - 1) << GMAC_RXQCTRL_FPRQ_SHIFT; + writel(value, ioaddr + GMAC_RXQ_CTRL1); + } else { + cfg->fpe_csr =3D 0; + } + writel(cfg->fpe_csr, ioaddr + MAC_FPE_CTRL_STS); + + value =3D readl(ioaddr + GMAC_INT_EN); + + if (pmac_enable) { + if (!(value & GMAC_INT_FPE_EN)) { + /* Dummy read to clear any pending masked interrupts */ + readl(ioaddr + MAC_FPE_CTRL_STS); + + value |=3D GMAC_INT_FPE_EN; + } + } else { + value &=3D ~GMAC_INT_FPE_EN; + } + + writel(value, ioaddr + GMAC_INT_EN); +} + +int dwmac5_fpe_irq_status(void __iomem *ioaddr, struct net_device *dev) +{ + u32 value; + int status; + + status =3D FPE_EVENT_UNKNOWN; + + /* Reads from the MAC_FPE_CTRL_STS register should only be performed + * here, since the status flags of MAC_FPE_CTRL_STS are "clear on read" + */ + value =3D readl(ioaddr + MAC_FPE_CTRL_STS); + + if (value & TRSP) { + status |=3D FPE_EVENT_TRSP; + netdev_dbg(dev, "FPE: Respond mPacket is transmitted\n"); + } + + if (value & TVER) { + status |=3D FPE_EVENT_TVER; + netdev_dbg(dev, "FPE: Verify mPacket is transmitted\n"); + } + + if (value & RRSP) { + status |=3D FPE_EVENT_RRSP; + netdev_dbg(dev, "FPE: Respond mPacket is received\n"); + } + + if (value & RVER) { + status |=3D FPE_EVENT_RVER; + netdev_dbg(dev, "FPE: Verify mPacket is received\n"); + } + + return status; +} + +void dwmac5_fpe_send_mpacket(void __iomem *ioaddr, struct stmmac_fpe_cfg *= cfg, + enum stmmac_mpacket_type type) +{ + u32 value =3D cfg->fpe_csr; + + if (type =3D=3D MPACKET_VERIFY) + value |=3D SVER; + else if (type =3D=3D MPACKET_RESPONSE) + value |=3D SRSP; + + writel(value, ioaddr + MAC_FPE_CTRL_STS); +} + +int dwmac5_fpe_get_add_frag_size(const void __iomem *ioaddr) +{ + return FIELD_GET(DWMAC5_ADD_FRAG_SZ, readl(ioaddr + MTL_FPE_CTRL_STS)); +} + +void dwmac5_fpe_set_add_frag_size(void __iomem *ioaddr, u32 add_frag_size) +{ + u32 value; + + value =3D readl(ioaddr + MTL_FPE_CTRL_STS); + writel(u32_replace_bits(value, add_frag_size, DWMAC5_ADD_FRAG_SZ), + ioaddr + MTL_FPE_CTRL_STS); +} + +#define ALG_ERR_MSG "TX algorithm SP is not suitable for one-to-many mappi= ng" +#define WEIGHT_ERR_MSG "TXQ weight %u differs across other TXQs in TC: [%u= ]" + +int dwmac5_fpe_map_preemption_class(struct net_device *ndev, + struct netlink_ext_ack *extack, u32 pclass) +{ + u32 val, offset, count, queue_weight, preemptible_txqs =3D 0; + struct stmmac_priv *priv =3D netdev_priv(ndev); + u32 num_tc =3D ndev->num_tc; + + if (!pclass) + goto update_mapping; + + /* DWMAC CORE4+ can not program TC:TXQ mapping to hardware. + * + * Synopsys Databook: + * "The number of Tx DMA channels is equal to the number of Tx queues, + * and is direct one-to-one mapping." + */ + for (u32 tc =3D 0; tc < num_tc; tc++) { + count =3D ndev->tc_to_txq[tc].count; + offset =3D ndev->tc_to_txq[tc].offset; + + if (pclass & BIT(tc)) + preemptible_txqs |=3D GENMASK(offset + count - 1, offset); + + /* This is 1:1 mapping, go to next TC */ + if (count =3D=3D 1) + continue; + + if (priv->plat->tx_sched_algorithm =3D=3D MTL_TX_ALGORITHM_SP) { + NL_SET_ERR_MSG_MOD(extack, ALG_ERR_MSG); + return -EINVAL; + } + + queue_weight =3D priv->plat->tx_queues_cfg[offset].weight; + + for (u32 i =3D 1; i < count; i++) { + if (priv->plat->tx_queues_cfg[offset + i].weight !=3D + queue_weight) { + NL_SET_ERR_MSG_FMT_MOD(extack, WEIGHT_ERR_MSG, + queue_weight, tc); + return -EINVAL; + } + } + } + +update_mapping: + val =3D readl(priv->ioaddr + MTL_FPE_CTRL_STS); + writel(u32_replace_bits(val, preemptible_txqs, DWMAC5_PREEMPTION_CLASS), + priv->ioaddr + MTL_FPE_CTRL_STS); + + return 0; +} + +void dwxgmac3_fpe_configure(void __iomem *ioaddr, struct stmmac_fpe_cfg *c= fg, + u32 num_txq, u32 num_rxq, + bool tx_enable, bool pmac_enable) +{ + u32 value; + + if (!tx_enable) { + value =3D readl(ioaddr + XGMAC_FPE_CTRL_STS); + + value &=3D ~XGMAC_EFPE; + + writel(value, ioaddr + XGMAC_FPE_CTRL_STS); + return; + } + + value =3D readl(ioaddr + XGMAC_RXQ_CTRL1); + value &=3D ~XGMAC_RQ; + value |=3D (num_rxq - 1) << XGMAC_RQ_SHIFT; + writel(value, ioaddr + XGMAC_RXQ_CTRL1); + + value =3D readl(ioaddr + XGMAC_FPE_CTRL_STS); + value |=3D XGMAC_EFPE; + writel(value, ioaddr + XGMAC_FPE_CTRL_STS); +} diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.h b/drivers/net= /ethernet/stmicro/stmmac/stmmac_fpe.h new file mode 100644 index 000000000000..25725fd5182f --- /dev/null +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2024 Furong Xu <0x1207@gmail.com> + * stmmac FPE(802.3 Qbu) handling + */ +#ifndef _STMMAC_FPE_H_ +#define _STMMAC_FPE_H_ + +#include +#include + +#define STMMAC_FPE_MM_MAX_VERIFY_RETRIES 3 +#define STMMAC_FPE_MM_MAX_VERIFY_TIME_MS 128 + +/* FPE link-partner hand-shaking mPacket type */ +enum stmmac_mpacket_type { + MPACKET_VERIFY =3D 0, + MPACKET_RESPONSE =3D 1, +}; + +struct stmmac_priv; +struct stmmac_fpe_cfg; + +void stmmac_fpe_link_state_handle(struct stmmac_priv *priv, bool is_up); +void stmmac_fpe_event_status(struct stmmac_priv *priv, int status); +void stmmac_fpe_init(struct stmmac_priv *priv); +void stmmac_fpe_apply(struct stmmac_priv *priv); + +void dwmac5_fpe_configure(void __iomem *ioaddr, struct stmmac_fpe_cfg *cfg, + u32 num_txq, u32 num_rxq, + bool tx_enable, bool pmac_enable); +void dwmac5_fpe_send_mpacket(void __iomem *ioaddr, + struct stmmac_fpe_cfg *cfg, + enum stmmac_mpacket_type type); +int dwmac5_fpe_irq_status(void __iomem *ioaddr, struct net_device *dev); +int dwmac5_fpe_get_add_frag_size(const void __iomem *ioaddr); +void dwmac5_fpe_set_add_frag_size(void __iomem *ioaddr, u32 add_frag_size); +int dwmac5_fpe_map_preemption_class(struct net_device *ndev, + struct netlink_ext_ack *extack, u32 pclass); + +void dwxgmac3_fpe_configure(void __iomem *ioaddr, struct stmmac_fpe_cfg *c= fg, + u32 num_txq, u32 num_rxq, + bool tx_enable, bool pmac_enable); + +#endif diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/ne= t/ethernet/stmicro/stmmac/stmmac_main.c index d3895d7eecfc..ab547430a717 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -43,6 +43,7 @@ #include #include #include "stmmac_ptp.h" +#include "stmmac_fpe.h" #include "stmmac.h" #include "stmmac_xdp.h" #include @@ -966,35 +967,6 @@ static void stmmac_mac_config(struct phylink_config *c= onfig, unsigned int mode, /* Nothing to do, xpcs_config() handles everything */ } =20 -static void stmmac_fpe_link_state_handle(struct stmmac_priv *priv, bool is= _up) -{ - struct stmmac_fpe_cfg *fpe_cfg =3D &priv->fpe_cfg; - unsigned long flags; - - timer_shutdown_sync(&fpe_cfg->verify_timer); - - spin_lock_irqsave(&fpe_cfg->lock, flags); - - if (is_up && fpe_cfg->pmac_enabled) { - /* VERIFY process requires pmac enabled when NIC comes up */ - stmmac_fpe_configure(priv, priv->ioaddr, fpe_cfg, - priv->plat->tx_queues_to_use, - priv->plat->rx_queues_to_use, - false, true); - - /* New link =3D> maybe new partner =3D> new verification process */ - stmmac_fpe_apply(priv); - } else { - /* No link =3D> turn off EFPE */ - stmmac_fpe_configure(priv, priv->ioaddr, fpe_cfg, - priv->plat->tx_queues_to_use, - priv->plat->rx_queues_to_use, - false, false); - } - - spin_unlock_irqrestore(&fpe_cfg->lock, flags); -} - static void stmmac_mac_link_down(struct phylink_config *config, unsigned int mode, phy_interface_t interface) { @@ -5953,35 +5925,6 @@ static int stmmac_set_features(struct net_device *ne= tdev, return 0; } =20 -static void stmmac_fpe_event_status(struct stmmac_priv *priv, int status) -{ - struct stmmac_fpe_cfg *fpe_cfg =3D &priv->fpe_cfg; - - /* This is interrupt context, just spin_lock() */ - spin_lock(&fpe_cfg->lock); - - if (!fpe_cfg->pmac_enabled || status =3D=3D FPE_EVENT_UNKNOWN) - goto unlock_out; - - /* LP has sent verify mPacket */ - if ((status & FPE_EVENT_RVER) =3D=3D FPE_EVENT_RVER) - stmmac_fpe_send_mpacket(priv, priv->ioaddr, fpe_cfg, - MPACKET_RESPONSE); - - /* Local has sent verify mPacket */ - if ((status & FPE_EVENT_TVER) =3D=3D FPE_EVENT_TVER && - fpe_cfg->status !=3D ETHTOOL_MM_VERIFY_STATUS_SUCCEEDED) - fpe_cfg->status =3D ETHTOOL_MM_VERIFY_STATUS_VERIFYING; - - /* LP has sent response mPacket */ - if ((status & FPE_EVENT_RRSP) =3D=3D FPE_EVENT_RRSP && - fpe_cfg->status =3D=3D ETHTOOL_MM_VERIFY_STATUS_VERIFYING) - fpe_cfg->status =3D ETHTOOL_MM_VERIFY_STATUS_SUCCEEDED; - -unlock_out: - spin_unlock(&fpe_cfg->lock); -} - static void stmmac_common_interrupt(struct stmmac_priv *priv) { u32 rx_cnt =3D priv->plat->rx_queues_to_use; @@ -7337,90 +7280,6 @@ int stmmac_reinit_ringparam(struct net_device *dev, = u32 rx_size, u32 tx_size) return ret; } =20 -/** - * stmmac_fpe_verify_timer - Timer for MAC Merge verification - * @t: timer_list struct containing private info - * - * Verify the MAC Merge capability in the local TX direction, by - * transmitting Verify mPackets up to 3 times. Wait until link - * partner responds with a Response mPacket, otherwise fail. - */ -static void stmmac_fpe_verify_timer(struct timer_list *t) -{ - struct stmmac_fpe_cfg *fpe_cfg =3D from_timer(fpe_cfg, t, verify_timer); - struct stmmac_priv *priv =3D container_of(fpe_cfg, struct stmmac_priv, - fpe_cfg); - unsigned long flags; - bool rearm =3D false; - - spin_lock_irqsave(&fpe_cfg->lock, flags); - - switch (fpe_cfg->status) { - case ETHTOOL_MM_VERIFY_STATUS_INITIAL: - case ETHTOOL_MM_VERIFY_STATUS_VERIFYING: - if (fpe_cfg->verify_retries !=3D 0) { - stmmac_fpe_send_mpacket(priv, priv->ioaddr, - fpe_cfg, MPACKET_VERIFY); - rearm =3D true; - } else { - fpe_cfg->status =3D ETHTOOL_MM_VERIFY_STATUS_FAILED; - } - - fpe_cfg->verify_retries--; - break; - - case ETHTOOL_MM_VERIFY_STATUS_SUCCEEDED: - stmmac_fpe_configure(priv, priv->ioaddr, fpe_cfg, - priv->plat->tx_queues_to_use, - priv->plat->rx_queues_to_use, - true, true); - break; - - default: - break; - } - - if (rearm) { - mod_timer(&fpe_cfg->verify_timer, - jiffies + msecs_to_jiffies(fpe_cfg->verify_time)); - } - - spin_unlock_irqrestore(&fpe_cfg->lock, flags); -} - -static void stmmac_fpe_verify_timer_arm(struct stmmac_fpe_cfg *fpe_cfg) -{ - if (fpe_cfg->pmac_enabled && fpe_cfg->tx_enabled && - fpe_cfg->verify_enabled && - fpe_cfg->status !=3D ETHTOOL_MM_VERIFY_STATUS_FAILED && - fpe_cfg->status !=3D ETHTOOL_MM_VERIFY_STATUS_SUCCEEDED) { - timer_setup(&fpe_cfg->verify_timer, stmmac_fpe_verify_timer, 0); - mod_timer(&fpe_cfg->verify_timer, jiffies); - } -} - -void stmmac_fpe_apply(struct stmmac_priv *priv) -{ - struct stmmac_fpe_cfg *fpe_cfg =3D &priv->fpe_cfg; - - /* If verification is disabled, configure FPE right away. - * Otherwise let the timer code do it. - */ - if (!fpe_cfg->verify_enabled) { - stmmac_fpe_configure(priv, priv->ioaddr, fpe_cfg, - priv->plat->tx_queues_to_use, - priv->plat->rx_queues_to_use, - fpe_cfg->tx_enabled, - fpe_cfg->pmac_enabled); - } else { - fpe_cfg->status =3D ETHTOOL_MM_VERIFY_STATUS_INITIAL; - fpe_cfg->verify_retries =3D STMMAC_FPE_MM_MAX_VERIFY_RETRIES; - - if (netif_running(priv->dev)) - stmmac_fpe_verify_timer_arm(fpe_cfg); - } -} - static int stmmac_xdp_rx_timestamp(const struct xdp_md *_ctx, u64 *timesta= mp) { const struct stmmac_xdp_buff *ctx =3D (void *)_ctx; @@ -7699,11 +7558,7 @@ int stmmac_dvr_probe(struct device *device, =20 mutex_init(&priv->lock); =20 - priv->fpe_cfg.verify_retries =3D STMMAC_FPE_MM_MAX_VERIFY_RETRIES; - priv->fpe_cfg.verify_time =3D STMMAC_FPE_MM_MAX_VERIFY_TIME_MS; - priv->fpe_cfg.status =3D ETHTOOL_MM_VERIFY_STATUS_DISABLED; - timer_setup(&priv->fpe_cfg.verify_timer, stmmac_fpe_verify_timer, 0); - spin_lock_init(&priv->fpe_cfg.lock); + stmmac_fpe_init(priv); =20 /* If a specific clk_csr value is passed from the platform * this means that the CSR Clock Range selection cannot be --=20 2.34.1 From nobody Mon Nov 25 11:55:00 2024 Received: from mail-pl1-f179.google.com (mail-pl1-f179.google.com [209.85.214.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 98CE6189913; Mon, 28 Oct 2024 03:07:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.179 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730084882; cv=none; b=bNPUZ6NJYhLUJEf29ZwtO3ozRGHXl02OMZA/qN0Le+OgOp/o7MTz6I0AqDw5hkvAowEAoUfZ0nHtLYkpXhQiNnfGKenGqr+qk0dahuoQ0w8hrqwSi1u19jQwAkpbQEKL2MuPFXquJZX46cOKDzhOL/u1tB+3k0C7gnryV8baRGE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730084882; c=relaxed/simple; bh=BuUgnL7h54rr2A/6ZDugxxWbzzOBYluHx6W8EmCTMgM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Ofy/W4wsiaDo51w1whsh9qKP6gtakyX0uEaanMdjEVRCZVhqSlcbrN0Jt+1H1nTIj8NG8yz5+fxFNrpEwsjY20GEVflbjwr3mNuInxvS93cSSsSOWzxXPXmcYhsdnn4X2WOIRaBBIMEBXClDABxlxuET67tH7FcQNuTw+K0hy7I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=TYJAUaKi; arc=none smtp.client-ip=209.85.214.179 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="TYJAUaKi" Received: by mail-pl1-f179.google.com with SMTP id d9443c01a7336-20cb89a4e4cso25072235ad.3; Sun, 27 Oct 2024 20:07:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730084878; x=1730689678; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ikOu3ozG9IaIbT4Vvh+Yk7rtkItRuerAPcX78kzIHYo=; b=TYJAUaKiRStF0XHS52kL7qZa+fY/WWezzeolbrMQB+jvDwXtSocpZs3tpzkAvk2GB1 7GtU+wuDrgVhvsqKLbEG9Oof8qAZ9Uwhwmi1xQxq1bFLJCE4v+GxR25hC0cHLtqB3iHe Z4WNyIyEy/CrXcKvGSdciRC/agtctK24uAIWpmSuudW7J27Yc4e3yfTVUoRBo3oAmTPz a496e5QqdSV4CU6akP3VHpESrk17PbiWVRqoGMkmxXPGSaFCgutyyZh65hgFa5dBArmE e6i7c2JsXBKS3/r600tDwYYj161CeGSNXis8Q5jTRhVND3m2V3P5gFDVJpIoolj9Qov8 2iYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730084878; x=1730689678; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ikOu3ozG9IaIbT4Vvh+Yk7rtkItRuerAPcX78kzIHYo=; b=v/QpK2k5xztwuecRl3VXAnOIdSHYkmBzUQ/kB6E+9fXuMFBve1NWnLBQzl2a31/62k fg27WOxcnKZ0Vw6QqMzbAJiLmdRVeBIJblOhBWMAhYYpdvXIa5SzDtsuY/m4zKc23hW+ r+KinKqOw+vbb3L34pahi6HttXb99w3uUhOvPnmGpx4w9fXj5Etm34tuCcwHtYN3w4RM 4o3DbSq3PA7iP1e6D8rPIOE0hhKg1ckDCsPq3PjRDwdBQ4LUS7E3bZawRJkW2mRIu/lG VOphNYBFVpsYCgDrR8PFj17bTPEcUL5h9ExT/DCLDz1l2lTjJMAI8ZQaW4xIChVXvWH4 yUfg== X-Forwarded-Encrypted: i=1; AJvYcCWMSDx/AuRWQB5klFkrtmCRQaOAWXTk8qL9HxqdZ1O1LOU+MCzfpAnQP3BU1Cl0q0eRwX6nupaZmZsS9k4=@vger.kernel.org X-Gm-Message-State: AOJu0YyCFUBEBibfneiSSuwA8wrfxS3YNrRewh1GXEPVycJWsUSTOO+V c0Q1aRk/d8WpHgnhWmIBW/TbvKsDCPMfaw/+RfUDdC5mr1PEGs4wP8QDpA== X-Google-Smtp-Source: AGHT+IHwr/E7cBYsiB558FY3+bsvh8hsMzFGb5XTNbqOwkYTfBo87w7Uxt5s4u5jzdfrHQvKeWlXig== X-Received: by 2002:a17:903:2445:b0:20c:bcd8:5ccb with SMTP id d9443c01a7336-210c6c0610amr106464195ad.30.1730084877928; Sun, 27 Oct 2024 20:07:57 -0700 (PDT) Received: from localhost.localdomain ([129.146.253.192]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-210bbf6d327sm41414155ad.67.2024.10.27.20.07.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Oct 2024 20:07:57 -0700 (PDT) From: Furong Xu <0x1207@gmail.com> To: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Vladimir Oltean , Andrew Lunn , Simon Horman , andrew+netdev@lunn.ch, Alexandre Torgue , Jose Abreu , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , xfr@outlook.com, Furong Xu <0x1207@gmail.com> Subject: [PATCH net-next v5 2/6] net: stmmac: Rework macro definitions for gmac4 and xgmac Date: Mon, 28 Oct 2024 11:07:25 +0800 Message-Id: <26f690d4f719ce09126aabfe86e4c9443c1ea530.1730084449.git.0x1207@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Rename and add macro definitions to better reuse them in common code. Signed-off-by: Furong Xu <0x1207@gmail.com> Reviewed-by: Simon Horman --- .../net/ethernet/stmicro/stmmac/stmmac_fpe.c | 77 ++++++++++--------- 1 file changed, 39 insertions(+), 38 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.c b/drivers/net= /ethernet/stmicro/stmmac/stmmac_fpe.c index 0a90e8f0df29..70ea475046f0 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.c @@ -9,23 +9,23 @@ #include "dwmac5.h" #include "dwxgmac2.h" =20 -#define MAC_FPE_CTRL_STS 0x00000234 -#define TRSP BIT(19) -#define TVER BIT(18) -#define RRSP BIT(17) -#define RVER BIT(16) -#define SRSP BIT(2) -#define SVER BIT(1) -#define EFPE BIT(0) - -#define MTL_FPE_CTRL_STS 0x00000c90 +#define GMAC5_MAC_FPE_CTRL_STS 0x00000234 +#define XGMAC_MAC_FPE_CTRL_STS 0x00000280 + +#define GMAC5_MTL_FPE_CTRL_STS 0x00000c90 +#define XGMAC_MTL_FPE_CTRL_STS 0x00001090 /* Preemption Classification */ -#define DWMAC5_PREEMPTION_CLASS GENMASK(15, 8) +#define FPE_MTL_PREEMPTION_CLASS GENMASK(15, 8) /* Additional Fragment Size of preempted frames */ -#define DWMAC5_ADD_FRAG_SZ GENMASK(1, 0) +#define FPE_MTL_ADD_FRAG_SZ GENMASK(1, 0) =20 -#define XGMAC_FPE_CTRL_STS 0x00000280 -#define XGMAC_EFPE BIT(0) +#define STMMAC_MAC_FPE_CTRL_STS_TRSP BIT(19) +#define STMMAC_MAC_FPE_CTRL_STS_TVER BIT(18) +#define STMMAC_MAC_FPE_CTRL_STS_RRSP BIT(17) +#define STMMAC_MAC_FPE_CTRL_STS_RVER BIT(16) +#define STMMAC_MAC_FPE_CTRL_STS_SRSP BIT(2) +#define STMMAC_MAC_FPE_CTRL_STS_SVER BIT(1) +#define STMMAC_MAC_FPE_CTRL_STS_EFPE BIT(0) =20 void stmmac_fpe_link_state_handle(struct stmmac_priv *priv, bool is_up) { @@ -185,7 +185,7 @@ void dwmac5_fpe_configure(void __iomem *ioaddr, struct = stmmac_fpe_cfg *cfg, u32 value; =20 if (tx_enable) { - cfg->fpe_csr =3D EFPE; + cfg->fpe_csr =3D STMMAC_MAC_FPE_CTRL_STS_EFPE; value =3D readl(ioaddr + GMAC_RXQ_CTRL1); value &=3D ~GMAC_RXQCTRL_FPRQ; value |=3D (num_rxq - 1) << GMAC_RXQCTRL_FPRQ_SHIFT; @@ -193,14 +193,14 @@ void dwmac5_fpe_configure(void __iomem *ioaddr, struc= t stmmac_fpe_cfg *cfg, } else { cfg->fpe_csr =3D 0; } - writel(cfg->fpe_csr, ioaddr + MAC_FPE_CTRL_STS); + writel(cfg->fpe_csr, ioaddr + GMAC5_MAC_FPE_CTRL_STS); =20 value =3D readl(ioaddr + GMAC_INT_EN); =20 if (pmac_enable) { if (!(value & GMAC_INT_FPE_EN)) { /* Dummy read to clear any pending masked interrupts */ - readl(ioaddr + MAC_FPE_CTRL_STS); + readl(ioaddr + GMAC5_MAC_FPE_CTRL_STS); =20 value |=3D GMAC_INT_FPE_EN; } @@ -221,24 +221,24 @@ int dwmac5_fpe_irq_status(void __iomem *ioaddr, struc= t net_device *dev) /* Reads from the MAC_FPE_CTRL_STS register should only be performed * here, since the status flags of MAC_FPE_CTRL_STS are "clear on read" */ - value =3D readl(ioaddr + MAC_FPE_CTRL_STS); + value =3D readl(ioaddr + GMAC5_MAC_FPE_CTRL_STS); =20 - if (value & TRSP) { + if (value & STMMAC_MAC_FPE_CTRL_STS_TRSP) { status |=3D FPE_EVENT_TRSP; netdev_dbg(dev, "FPE: Respond mPacket is transmitted\n"); } =20 - if (value & TVER) { + if (value & STMMAC_MAC_FPE_CTRL_STS_TVER) { status |=3D FPE_EVENT_TVER; netdev_dbg(dev, "FPE: Verify mPacket is transmitted\n"); } =20 - if (value & RRSP) { + if (value & STMMAC_MAC_FPE_CTRL_STS_RRSP) { status |=3D FPE_EVENT_RRSP; netdev_dbg(dev, "FPE: Respond mPacket is received\n"); } =20 - if (value & RVER) { + if (value & STMMAC_MAC_FPE_CTRL_STS_RVER) { status |=3D FPE_EVENT_RVER; netdev_dbg(dev, "FPE: Verify mPacket is received\n"); } @@ -252,25 +252,26 @@ void dwmac5_fpe_send_mpacket(void __iomem *ioaddr, st= ruct stmmac_fpe_cfg *cfg, u32 value =3D cfg->fpe_csr; =20 if (type =3D=3D MPACKET_VERIFY) - value |=3D SVER; + value |=3D STMMAC_MAC_FPE_CTRL_STS_SVER; else if (type =3D=3D MPACKET_RESPONSE) - value |=3D SRSP; + value |=3D STMMAC_MAC_FPE_CTRL_STS_SRSP; =20 - writel(value, ioaddr + MAC_FPE_CTRL_STS); + writel(value, ioaddr + GMAC5_MAC_FPE_CTRL_STS); } =20 int dwmac5_fpe_get_add_frag_size(const void __iomem *ioaddr) { - return FIELD_GET(DWMAC5_ADD_FRAG_SZ, readl(ioaddr + MTL_FPE_CTRL_STS)); + return FIELD_GET(FPE_MTL_ADD_FRAG_SZ, + readl(ioaddr + GMAC5_MTL_FPE_CTRL_STS)); } =20 void dwmac5_fpe_set_add_frag_size(void __iomem *ioaddr, u32 add_frag_size) { u32 value; =20 - value =3D readl(ioaddr + MTL_FPE_CTRL_STS); - writel(u32_replace_bits(value, add_frag_size, DWMAC5_ADD_FRAG_SZ), - ioaddr + MTL_FPE_CTRL_STS); + value =3D readl(ioaddr + GMAC5_MTL_FPE_CTRL_STS); + writel(u32_replace_bits(value, add_frag_size, FPE_MTL_ADD_FRAG_SZ), + ioaddr + GMAC5_MTL_FPE_CTRL_STS); } =20 #define ALG_ERR_MSG "TX algorithm SP is not suitable for one-to-many mappi= ng" @@ -321,9 +322,9 @@ int dwmac5_fpe_map_preemption_class(struct net_device *= ndev, } =20 update_mapping: - val =3D readl(priv->ioaddr + MTL_FPE_CTRL_STS); - writel(u32_replace_bits(val, preemptible_txqs, DWMAC5_PREEMPTION_CLASS), - priv->ioaddr + MTL_FPE_CTRL_STS); + val =3D readl(priv->ioaddr + GMAC5_MTL_FPE_CTRL_STS); + writel(u32_replace_bits(val, preemptible_txqs, FPE_MTL_PREEMPTION_CLASS), + priv->ioaddr + GMAC5_MTL_FPE_CTRL_STS); =20 return 0; } @@ -335,11 +336,11 @@ void dwxgmac3_fpe_configure(void __iomem *ioaddr, str= uct stmmac_fpe_cfg *cfg, u32 value; =20 if (!tx_enable) { - value =3D readl(ioaddr + XGMAC_FPE_CTRL_STS); + value =3D readl(ioaddr + XGMAC_MAC_FPE_CTRL_STS); =20 - value &=3D ~XGMAC_EFPE; + value &=3D ~STMMAC_MAC_FPE_CTRL_STS_EFPE; =20 - writel(value, ioaddr + XGMAC_FPE_CTRL_STS); + writel(value, ioaddr + XGMAC_MAC_FPE_CTRL_STS); return; } =20 @@ -348,7 +349,7 @@ void dwxgmac3_fpe_configure(void __iomem *ioaddr, struc= t stmmac_fpe_cfg *cfg, value |=3D (num_rxq - 1) << XGMAC_RQ_SHIFT; writel(value, ioaddr + XGMAC_RXQ_CTRL1); =20 - value =3D readl(ioaddr + XGMAC_FPE_CTRL_STS); - value |=3D XGMAC_EFPE; - writel(value, ioaddr + XGMAC_FPE_CTRL_STS); + value =3D readl(ioaddr + XGMAC_MAC_FPE_CTRL_STS); + value |=3D STMMAC_MAC_FPE_CTRL_STS_EFPE; + writel(value, ioaddr + XGMAC_MAC_FPE_CTRL_STS); } --=20 2.34.1 From nobody Mon Nov 25 11:55:00 2024 Received: from mail-pl1-f173.google.com (mail-pl1-f173.google.com [209.85.214.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5B8A318B492; Mon, 28 Oct 2024 03:08:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730084888; cv=none; b=qLwJzmT4Ewq5Ga9GrkXGohbgFJU1SOgMupXHVgsCRZsT6rp280UXGrxUDdsUi7FvomPrWnLx9YoJpa64gYTQuKq8nyGrJN9Onn0xjJiXOUkD4zF6kq8z8xVS8LRuqRcEjJokIZe9XVYG1ZYty2VD2QcBuY3GxMERUAEKLvjI2Wg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730084888; c=relaxed/simple; bh=4FuFXmGdpcrWL9nmgpXm6mjHQjqJJDYkSIN90saIM/o=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=aHCydk379DRTqJnVz5Buh8c81mesvRtgDKT1MkWwT40TtkIGcNhGoNUp6LvS3NCbD+7TDL21md5zSa64J5RZtqcbm3wIqsTCPofja4A/i5+mqnQ7oMVfp47r5hQxueq7RXa8U17kN1G5vNIgdzvlaPliB+0QPTUnKfkmEyb2qF4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=VGEmhsmL; arc=none smtp.client-ip=209.85.214.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="VGEmhsmL" Received: by mail-pl1-f173.google.com with SMTP id d9443c01a7336-20c70abba48so28511805ad.0; Sun, 27 Oct 2024 20:08:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730084884; x=1730689684; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GF1P9udSI/gLWtn1mmYkA2V46/mIuZf8t2FJy3p7Fjs=; b=VGEmhsmLrWWUNNar4CUSnQuvBcHDs/LNWrFVMlW7xMipSnlGPUmwDDJRRowz31ZnAn 7U3AhoabohZQaR93hrC16jM3SsCxlS4TKrFYjZBnr+WXs/SQN02tb/KNZeXjcN9M5aoN WdlQK4MHy/5HdG5qpO7HRug5EQ3wkgGyUyPsEE9q7c4u41o596AjOCLuBaGW5fEfkkhO PANMarrf+wdYI9GL1WB+8qcUoxN4quXoFKZk/Dd+OJVhYv5j8twWraexBsn6xAocKwjw trPEaPJd26ZvB6+ln7N2fA2hZa62HzaW6azia24WNcqMbNs5n/ydclAQv4f+0GxodnW7 Lawg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730084884; x=1730689684; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GF1P9udSI/gLWtn1mmYkA2V46/mIuZf8t2FJy3p7Fjs=; b=cfpZ2asAauWx1T3NHTEgu3EE3vAss/cN/GQU30Z8Z8CkrkgH90CTmMBrEu/Yu6dORg laqql59yRcaxkepSknW4KYHH/HKRh1CdKUliHJ/L32x7Sn+fkz0RzeZvMqKaxqJFd1pv /xTTm1Na1zhkVaUWIq4uQXGRYOISmV/3aqHyRi4ihfDPvjtFL7bDPm131Eb+rh8FwHHy ACQ64//BRI0EQmCfwSUdXZ9DAkHTr8R7SvUApYt7PTvfrPq5wMPTLx4ZE7n1+syQ0c5Z MDF8dsdirsY0+ljbvaJXmZnKc0GrorsorhKKSsY6aRpJYR0W1iQC6A//6J13p07ooqgd lx4A== X-Forwarded-Encrypted: i=1; AJvYcCVo9JiIvqVcnJd0dcpAK+uKyXy6QjY2DaEdxwuHRsPsTWe2dFvKcl9JFC+0OhNNEHQoJOTvvnhTQYsfcFg=@vger.kernel.org X-Gm-Message-State: AOJu0YzpRyroBEw06rA5BKoM/vycE7ig6LBziTVXpRutitmuX7M/6qqJ UIeasluJ0rouXknlROafupi94peAgQIowlHydR0M4fQCjsKBiWNppJvGug== X-Google-Smtp-Source: AGHT+IHmPJfyslMRdyn85Gv6um9R+ZvzNVSaAXKI4RBRTkmXqNbMkkJXV2P+8spKtq7bMKLcSj182Q== X-Received: by 2002:a17:902:f549:b0:20c:e4c3:27a3 with SMTP id d9443c01a7336-210c6c758a2mr99852125ad.43.1730084883474; Sun, 27 Oct 2024 20:08:03 -0700 (PDT) Received: from localhost.localdomain ([129.146.253.192]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-210bbf6d327sm41414155ad.67.2024.10.27.20.07.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Oct 2024 20:08:03 -0700 (PDT) From: Furong Xu <0x1207@gmail.com> To: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Vladimir Oltean , Andrew Lunn , Simon Horman , andrew+netdev@lunn.ch, Alexandre Torgue , Jose Abreu , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , xfr@outlook.com, Furong Xu <0x1207@gmail.com> Subject: [PATCH net-next v5 3/6] net: stmmac: Refactor FPE functions to generic version Date: Mon, 28 Oct 2024 11:07:26 +0800 Message-Id: <0f13217c5f7a543121286f13b389b5800bde1730.1730084449.git.0x1207@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" FPE implementation for DWMAC4 and DWXGMAC differs only for: 1) Offset address of MAC_FPE_CTRL_STS and MTL_FPE_CTRL_STS 2) FPRQ(Frame Preemption Residue Queue) field in MAC_RxQ_Ctrl1 3) Bit offset of Frame Preemption Interrupt Enable Refactor FPE functions to avoid code duplication. Signed-off-by: Furong Xu <0x1207@gmail.com> --- drivers/net/ethernet/stmicro/stmmac/dwmac4.h | 1 - .../net/ethernet/stmicro/stmmac/dwmac4_core.c | 10 -- .../net/ethernet/stmicro/stmmac/dwxgmac2.h | 2 +- .../ethernet/stmicro/stmmac/dwxgmac2_core.c | 2 - drivers/net/ethernet/stmicro/stmmac/hwif.c | 7 + drivers/net/ethernet/stmicro/stmmac/hwif.h | 20 +-- drivers/net/ethernet/stmicro/stmmac/stmmac.h | 1 + .../ethernet/stmicro/stmmac/stmmac_ethtool.c | 4 +- .../net/ethernet/stmicro/stmmac/stmmac_fpe.c | 144 ++++++++++-------- .../net/ethernet/stmicro/stmmac/stmmac_fpe.h | 20 +-- .../net/ethernet/stmicro/stmmac/stmmac_main.c | 8 +- 11 files changed, 101 insertions(+), 118 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h b/drivers/net/eth= ernet/stmicro/stmmac/dwmac4.h index 28fff6cab812..0c050324997a 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h @@ -69,7 +69,6 @@ #define GMAC_RXQCTRL_TACPQE BIT(21) #define GMAC_RXQCTRL_TACPQE_SHIFT 21 #define GMAC_RXQCTRL_FPRQ GENMASK(26, 24) -#define GMAC_RXQCTRL_FPRQ_SHIFT 24 =20 /* MAC Packet Filtering */ #define GMAC_PACKET_FILTER_PR BIT(0) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c b/drivers/ne= t/ethernet/stmicro/stmmac/dwmac4_core.c index 4d217926820a..c25781874aa7 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c @@ -1262,11 +1262,6 @@ const struct stmmac_ops dwmac410_ops =3D { .set_arp_offload =3D dwmac4_set_arp_offload, .config_l3_filter =3D dwmac4_config_l3_filter, .config_l4_filter =3D dwmac4_config_l4_filter, - .fpe_configure =3D dwmac5_fpe_configure, - .fpe_send_mpacket =3D dwmac5_fpe_send_mpacket, - .fpe_irq_status =3D dwmac5_fpe_irq_status, - .fpe_get_add_frag_size =3D dwmac5_fpe_get_add_frag_size, - .fpe_set_add_frag_size =3D dwmac5_fpe_set_add_frag_size, .fpe_map_preemption_class =3D dwmac5_fpe_map_preemption_class, .add_hw_vlan_rx_fltr =3D dwmac4_add_hw_vlan_rx_fltr, .del_hw_vlan_rx_fltr =3D dwmac4_del_hw_vlan_rx_fltr, @@ -1317,11 +1312,6 @@ const struct stmmac_ops dwmac510_ops =3D { .set_arp_offload =3D dwmac4_set_arp_offload, .config_l3_filter =3D dwmac4_config_l3_filter, .config_l4_filter =3D dwmac4_config_l4_filter, - .fpe_configure =3D dwmac5_fpe_configure, - .fpe_send_mpacket =3D dwmac5_fpe_send_mpacket, - .fpe_irq_status =3D dwmac5_fpe_irq_status, - .fpe_get_add_frag_size =3D dwmac5_fpe_get_add_frag_size, - .fpe_set_add_frag_size =3D dwmac5_fpe_set_add_frag_size, .fpe_map_preemption_class =3D dwmac5_fpe_map_preemption_class, .add_hw_vlan_rx_fltr =3D dwmac4_add_hw_vlan_rx_fltr, .del_hw_vlan_rx_fltr =3D dwmac4_del_hw_vlan_rx_fltr, diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h b/drivers/net/e= thernet/stmicro/stmmac/dwxgmac2.h index 917796293c26..efd47db05dbc 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h @@ -85,7 +85,6 @@ #define XGMAC_MCBCQ GENMASK(11, 8) #define XGMAC_MCBCQ_SHIFT 8 #define XGMAC_RQ GENMASK(7, 4) -#define XGMAC_RQ_SHIFT 4 #define XGMAC_UPQ GENMASK(3, 0) #define XGMAC_UPQ_SHIFT 0 #define XGMAC_RXQ_CTRL2 0x000000a8 @@ -96,6 +95,7 @@ #define XGMAC_LPIIS BIT(5) #define XGMAC_PMTIS BIT(4) #define XGMAC_INT_EN 0x000000b4 +#define XGMAC_FPEIE BIT(15) #define XGMAC_TSIE BIT(12) #define XGMAC_LPIIE BIT(5) #define XGMAC_PMTIE BIT(4) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c b/drivers/= net/ethernet/stmicro/stmmac/dwxgmac2_core.c index 111ba5a524ed..de6ffda31a80 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c @@ -1545,7 +1545,6 @@ const struct stmmac_ops dwxgmac210_ops =3D { .config_l3_filter =3D dwxgmac2_config_l3_filter, .config_l4_filter =3D dwxgmac2_config_l4_filter, .set_arp_offload =3D dwxgmac2_set_arp_offload, - .fpe_configure =3D dwxgmac3_fpe_configure, }; =20 static void dwxlgmac2_rx_queue_enable(struct mac_device_info *hw, u8 mode, @@ -1602,7 +1601,6 @@ const struct stmmac_ops dwxlgmac2_ops =3D { .config_l3_filter =3D dwxgmac2_config_l3_filter, .config_l4_filter =3D dwxgmac2_config_l4_filter, .set_arp_offload =3D dwxgmac2_set_arp_offload, - .fpe_configure =3D dwxgmac3_fpe_configure, }; =20 int dwxgmac2_setup(struct stmmac_priv *priv) diff --git a/drivers/net/ethernet/stmicro/stmmac/hwif.c b/drivers/net/ether= net/stmicro/stmmac/hwif.c index 88cce28b2f98..cfc50289aed6 100644 --- a/drivers/net/ethernet/stmicro/stmmac/hwif.c +++ b/drivers/net/ethernet/stmicro/stmmac/hwif.c @@ -6,6 +6,7 @@ =20 #include "common.h" #include "stmmac.h" +#include "stmmac_fpe.h" #include "stmmac_ptp.h" #include "stmmac_est.h" =20 @@ -185,6 +186,7 @@ static const struct stmmac_hwif_entry { .ptp_off =3D PTP_GMAC4_OFFSET, .mmc_off =3D MMC_GMAC4_OFFSET, .est_off =3D EST_GMAC4_OFFSET, + .fpe_reg =3D &dwmac5_fpe_reg, }, .desc =3D &dwmac4_desc_ops, .dma =3D &dwmac4_dma_ops, @@ -205,6 +207,7 @@ static const struct stmmac_hwif_entry { .ptp_off =3D PTP_GMAC4_OFFSET, .mmc_off =3D MMC_GMAC4_OFFSET, .est_off =3D EST_GMAC4_OFFSET, + .fpe_reg =3D &dwmac5_fpe_reg, }, .desc =3D &dwmac4_desc_ops, .dma =3D &dwmac410_dma_ops, @@ -225,6 +228,7 @@ static const struct stmmac_hwif_entry { .ptp_off =3D PTP_GMAC4_OFFSET, .mmc_off =3D MMC_GMAC4_OFFSET, .est_off =3D EST_GMAC4_OFFSET, + .fpe_reg =3D &dwmac5_fpe_reg, }, .desc =3D &dwmac4_desc_ops, .dma =3D &dwmac410_dma_ops, @@ -246,6 +250,7 @@ static const struct stmmac_hwif_entry { .ptp_off =3D PTP_XGMAC_OFFSET, .mmc_off =3D MMC_XGMAC_OFFSET, .est_off =3D EST_XGMAC_OFFSET, + .fpe_reg =3D &dwxgmac3_fpe_reg, }, .desc =3D &dwxgmac210_desc_ops, .dma =3D &dwxgmac210_dma_ops, @@ -267,6 +272,7 @@ static const struct stmmac_hwif_entry { .ptp_off =3D PTP_XGMAC_OFFSET, .mmc_off =3D MMC_XGMAC_OFFSET, .est_off =3D EST_XGMAC_OFFSET, + .fpe_reg =3D &dwxgmac3_fpe_reg, }, .desc =3D &dwxgmac210_desc_ops, .dma =3D &dwxgmac210_dma_ops, @@ -353,6 +359,7 @@ int stmmac_hwif_init(struct stmmac_priv *priv) mac->est =3D mac->est ? : entry->est; =20 priv->hw =3D mac; + priv->fpe_cfg.reg =3D entry->regs.fpe_reg; priv->ptpaddr =3D priv->ioaddr + entry->regs.ptp_off; priv->mmcaddr =3D priv->ioaddr + entry->regs.mmc_off; if (entry->est) diff --git a/drivers/net/ethernet/stmicro/stmmac/hwif.h b/drivers/net/ether= net/stmicro/stmmac/hwif.h index d5a9f01ecac5..64f8ed67dcc4 100644 --- a/drivers/net/ethernet/stmicro/stmmac/hwif.h +++ b/drivers/net/ethernet/stmicro/stmmac/hwif.h @@ -420,15 +420,6 @@ struct stmmac_ops { bool en, bool udp, bool sa, bool inv, u32 match); void (*set_arp_offload)(struct mac_device_info *hw, bool en, u32 addr); - void (*fpe_configure)(void __iomem *ioaddr, struct stmmac_fpe_cfg *cfg, - u32 num_txq, u32 num_rxq, - bool tx_enable, bool pmac_enable); - void (*fpe_send_mpacket)(void __iomem *ioaddr, - struct stmmac_fpe_cfg *cfg, - enum stmmac_mpacket_type type); - int (*fpe_irq_status)(void __iomem *ioaddr, struct net_device *dev); - int (*fpe_get_add_frag_size)(const void __iomem *ioaddr); - void (*fpe_set_add_frag_size)(void __iomem *ioaddr, u32 add_frag_size); int (*fpe_map_preemption_class)(struct net_device *ndev, struct netlink_ext_ack *extack, u32 pclass); @@ -530,16 +521,6 @@ struct stmmac_ops { stmmac_do_callback(__priv, mac, config_l4_filter, __args) #define stmmac_set_arp_offload(__priv, __args...) \ stmmac_do_void_callback(__priv, mac, set_arp_offload, __args) -#define stmmac_fpe_configure(__priv, __args...) \ - stmmac_do_void_callback(__priv, mac, fpe_configure, __args) -#define stmmac_fpe_send_mpacket(__priv, __args...) \ - stmmac_do_void_callback(__priv, mac, fpe_send_mpacket, __args) -#define stmmac_fpe_irq_status(__priv, __args...) \ - stmmac_do_callback(__priv, mac, fpe_irq_status, __args) -#define stmmac_fpe_get_add_frag_size(__priv, __args...) \ - stmmac_do_callback(__priv, mac, fpe_get_add_frag_size, __args) -#define stmmac_fpe_set_add_frag_size(__priv, __args...) \ - stmmac_do_void_callback(__priv, mac, fpe_set_add_frag_size, __args) #define stmmac_fpe_map_preemption_class(__priv, __args...) \ stmmac_do_void_callback(__priv, mac, fpe_map_preemption_class, __args) =20 @@ -678,6 +659,7 @@ struct stmmac_est_ops { stmmac_do_void_callback(__priv, est, irq_status, __args) =20 struct stmmac_regs_off { + const struct stmmac_fpe_reg *fpe_reg; u32 ptp_off; u32 mmc_off; u32 est_off; diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac.h b/drivers/net/eth= ernet/stmicro/stmmac/stmmac.h index 816b979e72cc..1d86439b8a14 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac.h +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac.h @@ -152,6 +152,7 @@ struct stmmac_fpe_cfg { */ spinlock_t lock; =20 + const struct stmmac_fpe_reg *reg; u32 fpe_csr; /* MAC_FPE_CTRL_STS reg cache */ =20 enum ethtool_mm_verify_status status; diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c b/drivers= /net/ethernet/stmicro/stmmac/stmmac_ethtool.c index 2792a4c6cbcd..f2783f7c46f3 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c @@ -1294,7 +1294,7 @@ static int stmmac_get_mm(struct net_device *ndev, else state->tx_active =3D false; =20 - frag_size =3D stmmac_fpe_get_add_frag_size(priv, priv->ioaddr); + frag_size =3D stmmac_fpe_get_add_frag_size(priv); state->tx_min_frag_size =3D ethtool_mm_frag_size_add_to_min(frag_size); =20 spin_unlock_irqrestore(&priv->fpe_cfg.lock, flags); @@ -1329,7 +1329,7 @@ static int stmmac_set_mm(struct net_device *ndev, str= uct ethtool_mm_cfg *cfg, if (!cfg->verify_enabled) fpe_cfg->status =3D ETHTOOL_MM_VERIFY_STATUS_DISABLED; =20 - stmmac_fpe_set_add_frag_size(priv, priv->ioaddr, frag_size); + stmmac_fpe_set_add_frag_size(priv, frag_size); stmmac_fpe_apply(priv); =20 spin_unlock_irqrestore(&fpe_cfg->lock, flags); diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.c b/drivers/net= /ethernet/stmicro/stmmac/stmmac_fpe.c index 70ea475046f0..05a0e1a22155 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.c @@ -27,19 +27,30 @@ #define STMMAC_MAC_FPE_CTRL_STS_SVER BIT(1) #define STMMAC_MAC_FPE_CTRL_STS_EFPE BIT(0) =20 +struct stmmac_fpe_reg { + const u32 mac_fpe_reg; /* offset of MAC_FPE_CTRL_STS */ + const u32 mtl_fpe_reg; /* offset of MTL_FPE_CTRL_STS */ + const u32 rxq_ctrl1_reg; /* offset of MAC_RxQ_Ctrl1 */ + const u32 fprq_mask; /* Frame Preemption Residue Queue */ + const u32 int_en_reg; /* offset of MAC_Interrupt_Enable */ + const u32 int_en_bit; /* Frame Preemption Interrupt Enable */ +}; + void stmmac_fpe_link_state_handle(struct stmmac_priv *priv, bool is_up) { struct stmmac_fpe_cfg *fpe_cfg =3D &priv->fpe_cfg; unsigned long flags; =20 + if (!priv->dma_cap.fpesel) + return; + timer_shutdown_sync(&fpe_cfg->verify_timer); =20 spin_lock_irqsave(&fpe_cfg->lock, flags); =20 if (is_up && fpe_cfg->pmac_enabled) { /* VERIFY process requires pmac enabled when NIC comes up */ - stmmac_fpe_configure(priv, priv->ioaddr, fpe_cfg, - priv->plat->tx_queues_to_use, + stmmac_fpe_configure(priv, priv->plat->tx_queues_to_use, priv->plat->rx_queues_to_use, false, true); =20 @@ -47,8 +58,7 @@ void stmmac_fpe_link_state_handle(struct stmmac_priv *pri= v, bool is_up) stmmac_fpe_apply(priv); } else { /* No link =3D> turn off EFPE */ - stmmac_fpe_configure(priv, priv->ioaddr, fpe_cfg, - priv->plat->tx_queues_to_use, + stmmac_fpe_configure(priv, priv->plat->tx_queues_to_use, priv->plat->rx_queues_to_use, false, false); } @@ -56,7 +66,7 @@ void stmmac_fpe_link_state_handle(struct stmmac_priv *pri= v, bool is_up) spin_unlock_irqrestore(&fpe_cfg->lock, flags); } =20 -void stmmac_fpe_event_status(struct stmmac_priv *priv, int status) +static void stmmac_fpe_event_status(struct stmmac_priv *priv, int status) { struct stmmac_fpe_cfg *fpe_cfg =3D &priv->fpe_cfg; =20 @@ -68,8 +78,7 @@ void stmmac_fpe_event_status(struct stmmac_priv *priv, in= t status) =20 /* LP has sent verify mPacket */ if ((status & FPE_EVENT_RVER) =3D=3D FPE_EVENT_RVER) - stmmac_fpe_send_mpacket(priv, priv->ioaddr, fpe_cfg, - MPACKET_RESPONSE); + stmmac_fpe_send_mpacket(priv, MPACKET_RESPONSE); =20 /* Local has sent verify mPacket */ if ((status & FPE_EVENT_TVER) =3D=3D FPE_EVENT_TVER && @@ -107,8 +116,7 @@ static void stmmac_fpe_verify_timer(struct timer_list *= t) case ETHTOOL_MM_VERIFY_STATUS_INITIAL: case ETHTOOL_MM_VERIFY_STATUS_VERIFYING: if (fpe_cfg->verify_retries !=3D 0) { - stmmac_fpe_send_mpacket(priv, priv->ioaddr, - fpe_cfg, MPACKET_VERIFY); + stmmac_fpe_send_mpacket(priv, MPACKET_VERIFY); rearm =3D true; } else { fpe_cfg->status =3D ETHTOOL_MM_VERIFY_STATUS_FAILED; @@ -118,8 +126,7 @@ static void stmmac_fpe_verify_timer(struct timer_list *= t) break; =20 case ETHTOOL_MM_VERIFY_STATUS_SUCCEEDED: - stmmac_fpe_configure(priv, priv->ioaddr, fpe_cfg, - priv->plat->tx_queues_to_use, + stmmac_fpe_configure(priv, priv->plat->tx_queues_to_use, priv->plat->rx_queues_to_use, true, true); break; @@ -154,6 +161,11 @@ void stmmac_fpe_init(struct stmmac_priv *priv) priv->fpe_cfg.status =3D ETHTOOL_MM_VERIFY_STATUS_DISABLED; timer_setup(&priv->fpe_cfg.verify_timer, stmmac_fpe_verify_timer, 0); spin_lock_init(&priv->fpe_cfg.lock); + + if (priv->dma_cap.fpesel && !priv->fpe_cfg.reg) { + dev_warn(priv->device, "FPE on this MAC is not supported by driver, forc= e disable it.\n"); + priv->dma_cap.fpesel =3D 0; + } } =20 void stmmac_fpe_apply(struct stmmac_priv *priv) @@ -164,8 +176,7 @@ void stmmac_fpe_apply(struct stmmac_priv *priv) * Otherwise let the timer code do it. */ if (!fpe_cfg->verify_enabled) { - stmmac_fpe_configure(priv, priv->ioaddr, fpe_cfg, - priv->plat->tx_queues_to_use, + stmmac_fpe_configure(priv, priv->plat->tx_queues_to_use, priv->plat->rx_queues_to_use, fpe_cfg->tx_enabled, fpe_cfg->pmac_enabled); @@ -178,50 +189,54 @@ void stmmac_fpe_apply(struct stmmac_priv *priv) } } =20 -void dwmac5_fpe_configure(void __iomem *ioaddr, struct stmmac_fpe_cfg *cfg, - u32 num_txq, u32 num_rxq, +void stmmac_fpe_configure(struct stmmac_priv *priv, u32 num_txq, u32 num_r= xq, bool tx_enable, bool pmac_enable) { + struct stmmac_fpe_cfg *cfg =3D &priv->fpe_cfg; + const struct stmmac_fpe_reg *reg =3D cfg->reg; + void __iomem *ioaddr =3D priv->ioaddr; u32 value; =20 if (tx_enable) { cfg->fpe_csr =3D STMMAC_MAC_FPE_CTRL_STS_EFPE; - value =3D readl(ioaddr + GMAC_RXQ_CTRL1); - value &=3D ~GMAC_RXQCTRL_FPRQ; - value |=3D (num_rxq - 1) << GMAC_RXQCTRL_FPRQ_SHIFT; - writel(value, ioaddr + GMAC_RXQ_CTRL1); + value =3D readl(ioaddr + reg->rxq_ctrl1_reg); + value &=3D ~reg->fprq_mask; + /* Keep this SHIFT, FIELD_PREP() expects a constant mask :-/ */ + value |=3D (num_rxq - 1) << __ffs(reg->fprq_mask); + writel(value, ioaddr + reg->rxq_ctrl1_reg); } else { cfg->fpe_csr =3D 0; } - writel(cfg->fpe_csr, ioaddr + GMAC5_MAC_FPE_CTRL_STS); + writel(cfg->fpe_csr, ioaddr + reg->mac_fpe_reg); =20 - value =3D readl(ioaddr + GMAC_INT_EN); + value =3D readl(ioaddr + reg->int_en_reg); =20 if (pmac_enable) { - if (!(value & GMAC_INT_FPE_EN)) { + if (!(value & reg->int_en_bit)) { /* Dummy read to clear any pending masked interrupts */ - readl(ioaddr + GMAC5_MAC_FPE_CTRL_STS); + readl(ioaddr + reg->mac_fpe_reg); =20 - value |=3D GMAC_INT_FPE_EN; + value |=3D reg->int_en_bit; } } else { - value &=3D ~GMAC_INT_FPE_EN; + value &=3D ~reg->int_en_bit; } =20 - writel(value, ioaddr + GMAC_INT_EN); + writel(value, ioaddr + reg->int_en_reg); } =20 -int dwmac5_fpe_irq_status(void __iomem *ioaddr, struct net_device *dev) +void stmmac_fpe_irq_status(struct stmmac_priv *priv) { + const struct stmmac_fpe_reg *reg =3D priv->fpe_cfg.reg; + void __iomem *ioaddr =3D priv->ioaddr; + struct net_device *dev =3D priv->dev; + int status =3D FPE_EVENT_UNKNOWN; u32 value; - int status; - - status =3D FPE_EVENT_UNKNOWN; =20 /* Reads from the MAC_FPE_CTRL_STS register should only be performed * here, since the status flags of MAC_FPE_CTRL_STS are "clear on read" */ - value =3D readl(ioaddr + GMAC5_MAC_FPE_CTRL_STS); + value =3D readl(ioaddr + reg->mac_fpe_reg); =20 if (value & STMMAC_MAC_FPE_CTRL_STS_TRSP) { status |=3D FPE_EVENT_TRSP; @@ -243,35 +258,41 @@ int dwmac5_fpe_irq_status(void __iomem *ioaddr, struc= t net_device *dev) netdev_dbg(dev, "FPE: Verify mPacket is received\n"); } =20 - return status; + stmmac_fpe_event_status(priv, status); } =20 -void dwmac5_fpe_send_mpacket(void __iomem *ioaddr, struct stmmac_fpe_cfg *= cfg, +void stmmac_fpe_send_mpacket(struct stmmac_priv *priv, enum stmmac_mpacket_type type) { - u32 value =3D cfg->fpe_csr; + const struct stmmac_fpe_reg *reg =3D priv->fpe_cfg.reg; + void __iomem *ioaddr =3D priv->ioaddr; + u32 value =3D priv->fpe_cfg.fpe_csr; =20 if (type =3D=3D MPACKET_VERIFY) value |=3D STMMAC_MAC_FPE_CTRL_STS_SVER; else if (type =3D=3D MPACKET_RESPONSE) value |=3D STMMAC_MAC_FPE_CTRL_STS_SRSP; =20 - writel(value, ioaddr + GMAC5_MAC_FPE_CTRL_STS); + writel(value, ioaddr + reg->mac_fpe_reg); } =20 -int dwmac5_fpe_get_add_frag_size(const void __iomem *ioaddr) +int stmmac_fpe_get_add_frag_size(struct stmmac_priv *priv) { - return FIELD_GET(FPE_MTL_ADD_FRAG_SZ, - readl(ioaddr + GMAC5_MTL_FPE_CTRL_STS)); + const struct stmmac_fpe_reg *reg =3D priv->fpe_cfg.reg; + void __iomem *ioaddr =3D priv->ioaddr; + + return FIELD_GET(FPE_MTL_ADD_FRAG_SZ, readl(ioaddr + reg->mtl_fpe_reg)); } =20 -void dwmac5_fpe_set_add_frag_size(void __iomem *ioaddr, u32 add_frag_size) +void stmmac_fpe_set_add_frag_size(struct stmmac_priv *priv, u32 add_frag_s= ize) { + const struct stmmac_fpe_reg *reg =3D priv->fpe_cfg.reg; + void __iomem *ioaddr =3D priv->ioaddr; u32 value; =20 - value =3D readl(ioaddr + GMAC5_MTL_FPE_CTRL_STS); + value =3D readl(ioaddr + reg->mtl_fpe_reg); writel(u32_replace_bits(value, add_frag_size, FPE_MTL_ADD_FRAG_SZ), - ioaddr + GMAC5_MTL_FPE_CTRL_STS); + ioaddr + reg->mtl_fpe_reg); } =20 #define ALG_ERR_MSG "TX algorithm SP is not suitable for one-to-many mappi= ng" @@ -329,27 +350,20 @@ int dwmac5_fpe_map_preemption_class(struct net_device= *ndev, return 0; } =20 -void dwxgmac3_fpe_configure(void __iomem *ioaddr, struct stmmac_fpe_cfg *c= fg, - u32 num_txq, u32 num_rxq, - bool tx_enable, bool pmac_enable) -{ - u32 value; - - if (!tx_enable) { - value =3D readl(ioaddr + XGMAC_MAC_FPE_CTRL_STS); - - value &=3D ~STMMAC_MAC_FPE_CTRL_STS_EFPE; - - writel(value, ioaddr + XGMAC_MAC_FPE_CTRL_STS); - return; - } - - value =3D readl(ioaddr + XGMAC_RXQ_CTRL1); - value &=3D ~XGMAC_RQ; - value |=3D (num_rxq - 1) << XGMAC_RQ_SHIFT; - writel(value, ioaddr + XGMAC_RXQ_CTRL1); - - value =3D readl(ioaddr + XGMAC_MAC_FPE_CTRL_STS); - value |=3D STMMAC_MAC_FPE_CTRL_STS_EFPE; - writel(value, ioaddr + XGMAC_MAC_FPE_CTRL_STS); -} +const struct stmmac_fpe_reg dwmac5_fpe_reg =3D { + .mac_fpe_reg =3D GMAC5_MAC_FPE_CTRL_STS, + .mtl_fpe_reg =3D GMAC5_MTL_FPE_CTRL_STS, + .rxq_ctrl1_reg =3D GMAC_RXQ_CTRL1, + .fprq_mask =3D GMAC_RXQCTRL_FPRQ, + .int_en_reg =3D GMAC_INT_EN, + .int_en_bit =3D GMAC_INT_FPE_EN, +}; + +const struct stmmac_fpe_reg dwxgmac3_fpe_reg =3D { + .mac_fpe_reg =3D XGMAC_MAC_FPE_CTRL_STS, + .mtl_fpe_reg =3D XGMAC_MTL_FPE_CTRL_STS, + .rxq_ctrl1_reg =3D XGMAC_RXQ_CTRL1, + .fprq_mask =3D XGMAC_RQ, + .int_en_reg =3D XGMAC_INT_EN, + .int_en_bit =3D XGMAC_FPEIE, +}; diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.h b/drivers/net= /ethernet/stmicro/stmmac/stmmac_fpe.h index 25725fd5182f..0b601a9fd805 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.h +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.h @@ -22,24 +22,20 @@ struct stmmac_priv; struct stmmac_fpe_cfg; =20 void stmmac_fpe_link_state_handle(struct stmmac_priv *priv, bool is_up); -void stmmac_fpe_event_status(struct stmmac_priv *priv, int status); void stmmac_fpe_init(struct stmmac_priv *priv); void stmmac_fpe_apply(struct stmmac_priv *priv); - -void dwmac5_fpe_configure(void __iomem *ioaddr, struct stmmac_fpe_cfg *cfg, - u32 num_txq, u32 num_rxq, +void stmmac_fpe_configure(struct stmmac_priv *priv, u32 num_txq, u32 num_r= xq, bool tx_enable, bool pmac_enable); -void dwmac5_fpe_send_mpacket(void __iomem *ioaddr, - struct stmmac_fpe_cfg *cfg, +void stmmac_fpe_send_mpacket(struct stmmac_priv *priv, enum stmmac_mpacket_type type); -int dwmac5_fpe_irq_status(void __iomem *ioaddr, struct net_device *dev); -int dwmac5_fpe_get_add_frag_size(const void __iomem *ioaddr); -void dwmac5_fpe_set_add_frag_size(void __iomem *ioaddr, u32 add_frag_size); +void stmmac_fpe_irq_status(struct stmmac_priv *priv); +int stmmac_fpe_get_add_frag_size(struct stmmac_priv *priv); +void stmmac_fpe_set_add_frag_size(struct stmmac_priv *priv, u32 add_frag_s= ize); + int dwmac5_fpe_map_preemption_class(struct net_device *ndev, struct netlink_ext_ack *extack, u32 pclass); =20 -void dwxgmac3_fpe_configure(void __iomem *ioaddr, struct stmmac_fpe_cfg *c= fg, - u32 num_txq, u32 num_rxq, - bool tx_enable, bool pmac_enable); +extern const struct stmmac_fpe_reg dwmac5_fpe_reg; +extern const struct stmmac_fpe_reg dwxgmac3_fpe_reg; =20 #endif diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/ne= t/ethernet/stmicro/stmmac/stmmac_main.c index ab547430a717..9fcf2df099ec 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -5943,12 +5943,8 @@ static void stmmac_common_interrupt(struct stmmac_pr= iv *priv) stmmac_est_irq_status(priv, priv, priv->dev, &priv->xstats, tx_cnt); =20 - if (priv->dma_cap.fpesel) { - int status =3D stmmac_fpe_irq_status(priv, priv->ioaddr, - priv->dev); - - stmmac_fpe_event_status(priv, status); - } + if (priv->dma_cap.fpesel) + stmmac_fpe_irq_status(priv); =20 /* To handle GMAC own interrupts */ if ((priv->plat->has_gmac) || xmac) { --=20 2.34.1 From nobody Mon Nov 25 11:55:00 2024 Received: from mail-pf1-f172.google.com (mail-pf1-f172.google.com [209.85.210.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BB45318C02D; Mon, 28 Oct 2024 03:08:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730084891; cv=none; b=mZhXK6PT3uDbjOqm5yl6AFG4YAsBbLY9a/196PzACAgd6ooXSlZ3he1B5G+iPV6ZpcQLGnHupoLi3mTSWZT8XEEJ+eqWZhW3BZK8i0QfgkiGZbRq/SaHBU1v8tNaP1h6qbBZYGTlBNcVP5xI32bfSheZs3vVPYhO+yMUuCdqKWE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730084891; c=relaxed/simple; bh=IludlujJ838qPT7HOL2bUhqb4Mv6PhSa9aKeKQxdUXQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=BRCoSJ8qzefxgRmT0/V156bkYdMh4Hmi4zPwti7C2529g9Xg2faM4sbBtM3rUJY4gyyBgL2AtFFe99B4N3llTHn09caRWhuc20iOLGYs//Ix+8zLVEbAx0edLmC3UlJ+4b9xwmR8/5n9LPuqt8kiKH7JmVC4v70eZmqOXKvaOPA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=cuvu5+HG; arc=none smtp.client-ip=209.85.210.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="cuvu5+HG" Received: by mail-pf1-f172.google.com with SMTP id d2e1a72fcca58-7204dff188eso2332291b3a.1; Sun, 27 Oct 2024 20:08:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730084889; x=1730689689; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Kn52y9HQNLKC2nRbhsI1WecpIBp46gjHfUlvO0bwqrs=; b=cuvu5+HG7VOAQHgEgl0It3YmRws5cCYMCQA3sywnNPc538gXQkh1C7Si9o4zhRSgvf /XyM1Ewixgck7Zle1//O3ryq49dOZO09T1e4vFieVLi8EwX4RWt4HzDFgLU96oW8iHJ7 l7dHnXDmy7l/wqry2Vwym+jrfwcypQQniLkfptElCWnWyFx3jJxTwuvy7Wh+PXtMM/3d JCuAtfMjxXBVVInewk+T/Pic9Mmq56rOXolAxSVfPJa/lJwV2ns+BEuaULfvbNMUZS+L vmufjPIdKtRLaVc5+QzFXFq79DvVMH0HRJdWfl/F/LGL0BkIGHpCo83RzNbsC85Xbe4B 08uQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730084889; x=1730689689; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Kn52y9HQNLKC2nRbhsI1WecpIBp46gjHfUlvO0bwqrs=; b=oizNqIhXrYLjRPZR6UeafgExYtTu5M1lG4cFnQmxQs8M5U5/voBz+8bSLqAK9a/mGy 4L/sjHVUU6Ee5wsgEePBPkTJh2DqvOnfN9vwfZdzhYl7KyHdfO34O9OCvBaGp4M2N8zO Qip7cmwRfyURr67pJDmCctms8rYbxOWG9Xlco+JKLJ0y5sjuycYvwM0ivFdy/D1In0af DRMk1vsnLd8x1nZPbrtyfmWm5WsEftPqz2c6Y8PIA4XwvLUn3xP1oKSdzRMmlDaLQlHV 1xRulgTXX9y0i7Rzfvmjnar95yYcoY1JXdlvLAPUtXFRkvSxdZJqYKvZ0iAQyZnojBMX 36zw== X-Forwarded-Encrypted: i=1; AJvYcCUatLspfkygdldyD+K8kAoe2V64DSPhQOAHExEn+OaoW7s6Mnv7ZvC3DB6/0JlzZqrLeQyDTGvPB/MRkxs=@vger.kernel.org X-Gm-Message-State: AOJu0YzCo8p1Da3uNtb2Jpn2QZb1gGrpx/ZvDY68k60av1T5zT/F1YZl VpgKh4bg8qfdbyhKmjmrUyrgTIphzg+pUqhrIAtcJD2I4KhFe3uRPRpZPA== X-Google-Smtp-Source: AGHT+IFEzrmGRpALAGVKconvFr3R884KqP941Fdm7RrIlzyHNj9gSTRob3wsZU6po/99rAkn3RP7Sg== X-Received: by 2002:a05:6a20:b58b:b0:1d9:d04:586d with SMTP id adf61e73a8af0-1d9a8533e06mr9963979637.38.1730084888563; Sun, 27 Oct 2024 20:08:08 -0700 (PDT) Received: from localhost.localdomain ([129.146.253.192]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-210bbf6d327sm41414155ad.67.2024.10.27.20.08.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Oct 2024 20:08:08 -0700 (PDT) From: Furong Xu <0x1207@gmail.com> To: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Vladimir Oltean , Andrew Lunn , Simon Horman , andrew+netdev@lunn.ch, Alexandre Torgue , Jose Abreu , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , xfr@outlook.com, Furong Xu <0x1207@gmail.com> Subject: [PATCH net-next v5 4/6] net: stmmac: xgmac: Rename XGMAC_RQ to XGMAC_FPRQ Date: Mon, 28 Oct 2024 11:07:27 +0800 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Synopsys XGMAC Databook defines MAC_RxQ_Ctrl1 register: RQ: Frame Preemption Residue Queue XGMAC_FPRQ is more readable and more consistent with GMAC4. Signed-off-by: Furong Xu <0x1207@gmail.com> Reviewed-by: Simon Horman --- drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h | 2 +- drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h b/drivers/net/e= thernet/stmicro/stmmac/dwxgmac2.h index efd47db05dbc..a04a79003692 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h @@ -84,7 +84,7 @@ #define XGMAC_MCBCQEN BIT(15) #define XGMAC_MCBCQ GENMASK(11, 8) #define XGMAC_MCBCQ_SHIFT 8 -#define XGMAC_RQ GENMASK(7, 4) +#define XGMAC_FPRQ GENMASK(7, 4) #define XGMAC_UPQ GENMASK(3, 0) #define XGMAC_UPQ_SHIFT 0 #define XGMAC_RXQ_CTRL2 0x000000a8 diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.c b/drivers/net= /ethernet/stmicro/stmmac/stmmac_fpe.c index 05a0e1a22155..ce5dc896f9d8 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.c @@ -363,7 +363,7 @@ const struct stmmac_fpe_reg dwxgmac3_fpe_reg =3D { .mac_fpe_reg =3D XGMAC_MAC_FPE_CTRL_STS, .mtl_fpe_reg =3D XGMAC_MTL_FPE_CTRL_STS, .rxq_ctrl1_reg =3D XGMAC_RXQ_CTRL1, - .fprq_mask =3D XGMAC_RQ, + .fprq_mask =3D XGMAC_FPRQ, .int_en_reg =3D XGMAC_INT_EN, .int_en_bit =3D XGMAC_FPEIE, }; --=20 2.34.1 From nobody Mon Nov 25 11:55:00 2024 Received: from mail-pl1-f180.google.com (mail-pl1-f180.google.com [209.85.214.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5749A18801A; Mon, 28 Oct 2024 03:08:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730084897; cv=none; b=SBsrACSYl+17Ysis6bPpzBwW8kWfmrc/9JgVrHeNA1T3AUvGSraLZ75SJOZAItN8xoOJHZm0ZqsN5iTYfXzq6QckPvJIP8rnwewL9z4VqREZFLIqJxK/qxH5CrkXyu9/XQ68Nfwuk4lBdRAWUf6pbga1nR+y3q8NeU4ixSzP8wU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730084897; c=relaxed/simple; bh=RfgT38CL6eHGwS7VJQtfvK/CHnRaILysqwErw0w3nZE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=bdw9RJ6e2nhbIEFpRX1DGY+ixr4BQY1sTTCfUTQzq92mdYD+0QQr7wVLStaSSb3U0fTELEWIzcwHoopkZuYq/DsjUc+CMhSCCFveqH75lnggWzjXz+3QoaDMer0wEx4XnRSiQDRgKa7tk2HKXfZmrPANq79LU17BJw3OpJTB3vw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=PZDI3U57; arc=none smtp.client-ip=209.85.214.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="PZDI3U57" Received: by mail-pl1-f180.google.com with SMTP id d9443c01a7336-20c805a0753so35856315ad.0; Sun, 27 Oct 2024 20:08:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730084894; x=1730689694; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3IK0+tz6UgrWkk3eQKtuPkyttD+TXu0biBXSgNcL1KU=; b=PZDI3U57GFo2qCagCqHQDwp0FoZGghyMWVQKn2yM8DBhHjwkzkfXs3GdfMItmmVBbU OuxX/ZQlWNodaOM0VCEz1YW3zEh7dYioXyLnkMgwyNqoILSkAICCqiaEqd3OdB8d2y2W vuauNvyggO6ee+ITz1Vgx5Pd4sbtCgBgifVJAzXQPSfDGnP/kAvMQwM7AH/MdeWkXS9W BXysNcI681gSuUyKPCjZoMRZNlQF6uzZFEJ/Jm+RMzZzczq8+WnXVYcDMUS+6y9aCGpC illL+6aiZIwFJ4nRutM273lNKQQ0l/h4m8BtpLn2JIZ3cL17ZrDdpdlq9Yw4l6JaSbbp cW9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730084894; x=1730689694; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3IK0+tz6UgrWkk3eQKtuPkyttD+TXu0biBXSgNcL1KU=; b=N9YFUev0AD3DcEyGrOvJ1WW97buJqIDnY9F36PkjKaHNTvcj8tIkUrcRYW0dSW4rRJ 3dTVxQFojt8IKdWG9LyO56Z2OEt6PZeC9viDP61D5MM3BZZVW0WA66ee6pXG2MIb2BPc I/OXt6KdKVqpV8n/8qgYkqOr6u+2vqcufcIC8btgIeluTd/0Z0UdunU75dnG5de4GSW7 C0NB5GaklVLnTY+WCD0nN0+bwiBsxBKk+Q9FV5tzeR5OrqEllfYDEI7AbuJhMviUkict clk8fC4uN/HxLKG+cYVSWK3BkGN7VS4fhWgJgKfSir0hAU83gsZWJUh3LQZ/nv2+MW4p zmXg== X-Forwarded-Encrypted: i=1; AJvYcCUqpBINhadnEhzsVAYp4L1eUKRwggMJfIi1sMZ9AYtjHoE44fqKvj0nKKfZrDsdl4FBBS+qUCpnH6u6GcI=@vger.kernel.org X-Gm-Message-State: AOJu0YwotTDEZfQiktjR98DqhjGX4BXminALWi7mQcSsSm3S4LGrcCvb wALbloBfoCbiMTr8Rg+N/T0YdTgY+LegW23Cr80u3Xo1xeeEcvzLKM7XYA== X-Google-Smtp-Source: AGHT+IE1LfTy77L+XgqKFk08IJORYTgfKR/xYxHxwpKcRnPD2X0/L4nVVPTJb2xMm9Vl7axWq/7AFQ== X-Received: by 2002:a17:902:cf0a:b0:20c:9d79:cf85 with SMTP id d9443c01a7336-210c6c932ecmr92308935ad.54.1730084894044; Sun, 27 Oct 2024 20:08:14 -0700 (PDT) Received: from localhost.localdomain ([129.146.253.192]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-210bbf6d327sm41414155ad.67.2024.10.27.20.08.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Oct 2024 20:08:13 -0700 (PDT) From: Furong Xu <0x1207@gmail.com> To: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Vladimir Oltean , Andrew Lunn , Simon Horman , andrew+netdev@lunn.ch, Alexandre Torgue , Jose Abreu , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , xfr@outlook.com, Furong Xu <0x1207@gmail.com> Subject: [PATCH net-next v5 5/6] net: stmmac: xgmac: Complete FPE support Date: Mon, 28 Oct 2024 11:07:28 +0800 Message-Id: <3126dce1a85138a7760096fc15c580a5c6bbf5c9.1730084449.git.0x1207@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Implement the necessary fpe_map_preemption_class callback for xgmac. Signed-off-by: Furong Xu <0x1207@gmail.com> --- .../ethernet/stmicro/stmmac/dwxgmac2_core.c | 2 + .../net/ethernet/stmicro/stmmac/stmmac_fpe.c | 43 +++++++++++++++++++ .../net/ethernet/stmicro/stmmac/stmmac_fpe.h | 3 ++ 3 files changed, 48 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c b/drivers/= net/ethernet/stmicro/stmmac/dwxgmac2_core.c index de6ffda31a80..9a60a6e8f633 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c @@ -1545,6 +1545,7 @@ const struct stmmac_ops dwxgmac210_ops =3D { .config_l3_filter =3D dwxgmac2_config_l3_filter, .config_l4_filter =3D dwxgmac2_config_l4_filter, .set_arp_offload =3D dwxgmac2_set_arp_offload, + .fpe_map_preemption_class =3D dwxgmac3_fpe_map_preemption_class, }; =20 static void dwxlgmac2_rx_queue_enable(struct mac_device_info *hw, u8 mode, @@ -1601,6 +1602,7 @@ const struct stmmac_ops dwxlgmac2_ops =3D { .config_l3_filter =3D dwxgmac2_config_l3_filter, .config_l4_filter =3D dwxgmac2_config_l4_filter, .set_arp_offload =3D dwxgmac2_set_arp_offload, + .fpe_map_preemption_class =3D dwxgmac3_fpe_map_preemption_class, }; =20 int dwxgmac2_setup(struct stmmac_priv *priv) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.c b/drivers/net= /ethernet/stmicro/stmmac/stmmac_fpe.c index ce5dc896f9d8..541fe6ce87f7 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.c @@ -350,6 +350,49 @@ int dwmac5_fpe_map_preemption_class(struct net_device = *ndev, return 0; } =20 +int dwxgmac3_fpe_map_preemption_class(struct net_device *ndev, + struct netlink_ext_ack *extack, u32 pclass) +{ + u32 val, offset, count, preemptible_txqs =3D 0; + struct stmmac_priv *priv =3D netdev_priv(ndev); + u32 num_tc =3D ndev->num_tc; + + if (!num_tc) { + /* Restore default TC:Queue mapping */ + for (u32 i =3D 0; i < priv->plat->tx_queues_to_use; i++) { + val =3D readl(priv->ioaddr + XGMAC_MTL_TXQ_OPMODE(i)); + writel(u32_replace_bits(val, i, XGMAC_Q2TCMAP), + priv->ioaddr + XGMAC_MTL_TXQ_OPMODE(i)); + } + } + + /* Synopsys Databook: + * "All Queues within a traffic class are selected in a round robin + * fashion (when packets are available) when the traffic class is + * selected by the scheduler for packet transmission. This is true for + * any of the scheduling algorithms." + */ + for (u32 tc =3D 0; tc < num_tc; tc++) { + count =3D ndev->tc_to_txq[tc].count; + offset =3D ndev->tc_to_txq[tc].offset; + + if (pclass & BIT(tc)) + preemptible_txqs |=3D GENMASK(offset + count - 1, offset); + + for (u32 i =3D 0; i < count; i++) { + val =3D readl(priv->ioaddr + XGMAC_MTL_TXQ_OPMODE(offset + i)); + writel(u32_replace_bits(val, tc, XGMAC_Q2TCMAP), + priv->ioaddr + XGMAC_MTL_TXQ_OPMODE(offset + i)); + } + } + + val =3D readl(priv->ioaddr + XGMAC_MTL_FPE_CTRL_STS); + writel(u32_replace_bits(val, preemptible_txqs, FPE_MTL_PREEMPTION_CLASS), + priv->ioaddr + XGMAC_MTL_FPE_CTRL_STS); + + return 0; +} + const struct stmmac_fpe_reg dwmac5_fpe_reg =3D { .mac_fpe_reg =3D GMAC5_MAC_FPE_CTRL_STS, .mtl_fpe_reg =3D GMAC5_MTL_FPE_CTRL_STS, diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.h b/drivers/net= /ethernet/stmicro/stmmac/stmmac_fpe.h index 0b601a9fd805..ea18ea738da6 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.h +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.h @@ -34,6 +34,9 @@ void stmmac_fpe_set_add_frag_size(struct stmmac_priv *pri= v, u32 add_frag_size); =20 int dwmac5_fpe_map_preemption_class(struct net_device *ndev, struct netlink_ext_ack *extack, u32 pclass); +int dwxgmac3_fpe_map_preemption_class(struct net_device *ndev, + struct netlink_ext_ack *extack, + u32 pclass); =20 extern const struct stmmac_fpe_reg dwmac5_fpe_reg; extern const struct stmmac_fpe_reg dwxgmac3_fpe_reg; --=20 2.34.1 From nobody Mon Nov 25 11:55:00 2024 Received: from mail-pl1-f172.google.com (mail-pl1-f172.google.com [209.85.214.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7675818D649; Mon, 28 Oct 2024 03:08:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730084902; cv=none; b=jVLIYXkNzMREbZVFqu/UoG/1OfH7QlPgFGWjKMczteDDoYIvZ5ISpZvV9CFeBoR+e98oh3M5Ikvvq9g8r8xx/cW08JNs9TlhCX+NBb3Gyi825Z71EU/acxKKDS2Za+Y3MQCiiMaKp2GS4PKCzfccxEgvRrow+qIhX88efuntBbY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730084902; c=relaxed/simple; bh=udSu0PifOzRa5GkWP7sFryWEU4fALlPs0aaNg1SJDJs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=d+i5dShclg689gTtMfBUSW9iRSfyL1cPXUTNUmzSMle01iHRzbcC5xBW850Zx/RSZ9XT++ckd/w9Eja5ukSJA8L2UuL/7jTlRxhFoQKHN86JRcR4DU+mV7IzZva/NMlB8sHuKAoNZLDnU3X9TykG3tV99xLcKWtv+kB04rjxxM8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=M/eS6jln; arc=none smtp.client-ip=209.85.214.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="M/eS6jln" Received: by mail-pl1-f172.google.com with SMTP id d9443c01a7336-20cbb1cf324so32127935ad.0; Sun, 27 Oct 2024 20:08:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1730084899; x=1730689699; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XZgSPrHkP+5PHa4TM3CPdf/GMcXQ4aZTX0bTblaWKZw=; b=M/eS6jlnau4rNaTBJJZ0IM4GCJzH8W8ETBEanJxx54h3xCIV5rX3ANh0zDaZwrj2SO 0AoFs9zWmHXz/nNI8okrdgHf2a5EgKg1JoeuijcuF6ZGsFN4WZv75l9HRMDCcGz17TAk nLZGb8HCMW/BRnFk4KRc711rzqpMi7v2CK7WvZcQY1kMywp2/a3Sty0l5eBuPZK7YyBi SDLvfOXhLAo0Y9JVU/ZfM6RC/SXWWuKSngwyNCqGJDRpsHT9S3xt4EfYMFDrehSbOn1E 48RYosM2g8QgIwZFflEt32UX9Pf4W4738jrwWzYR0vOKAqtxoM1N2YgOVeYgCPJrLm6l o2ow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730084899; x=1730689699; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XZgSPrHkP+5PHa4TM3CPdf/GMcXQ4aZTX0bTblaWKZw=; b=pQh5OSGAgsfjXl5+wY9fgDVWtnrH57MXxOG8G01TrhJ9/ltQx6Rg0E2a1qEXYB9CK0 c7/nDhkjqNAvBBSqcHhBj0jxiMeNTGgQSXp2ydyN2fw/P975HbMdI3jWIVbUj8vdoi5C Xc3aNZic4+vLdKwDjGLhpRIV5zGaVLi1p/VDzPxvIxk3yWLeBEFUHFpFn8Giyn326aL4 z8p8poiomKK3sE2DrSoTmD7FsMPwJQ0i9JNK0T73WZMIM5z5A5FmCAdNAUydwXntIO1E MbFaQCOg4eTM7QNPyYj74e5UX9OSFm9NS+4IFT34ORvVqlL0CPbxAhL7OgjUtjxxlIFl ABmw== X-Forwarded-Encrypted: i=1; AJvYcCVHsznSNyki5PcYvMNy3vAvy2HuCt0TCMkZaXZ9aPIsFPfgKnjSu3YB19SuZN9Ca8FqKvqMvWMLXPYpT3A=@vger.kernel.org X-Gm-Message-State: AOJu0YxX53zWp9JhNeOjDAcqPCwRdJknZmBHkj6trP7qZ2aaqM+mKwVL Ppdj2IpXrYOwcxuxAkSuOVVVOR/cjznEmsETef2dQTzUUh50uu+pD+QNAA== X-Google-Smtp-Source: AGHT+IFchisKXMXu4T+iCy7SrFqbq7c/JyULflLF19QqNcWyjDqPmVKAegFzkUP62qdTFlLz5UXVQQ== X-Received: by 2002:a17:902:f607:b0:20b:ab4b:544a with SMTP id d9443c01a7336-210c6c6d591mr113535035ad.43.1730084899264; Sun, 27 Oct 2024 20:08:19 -0700 (PDT) Received: from localhost.localdomain ([129.146.253.192]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-210bbf6d327sm41414155ad.67.2024.10.27.20.08.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Oct 2024 20:08:18 -0700 (PDT) From: Furong Xu <0x1207@gmail.com> To: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Vladimir Oltean , Andrew Lunn , Simon Horman , andrew+netdev@lunn.ch, Alexandre Torgue , Jose Abreu , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , xfr@outlook.com, Furong Xu <0x1207@gmail.com> Subject: [PATCH net-next v5 6/6] net: stmmac: xgmac: Enable FPE for tc-mqprio/tc-taprio Date: Mon, 28 Oct 2024 11:07:29 +0800 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The FPE on XGMAC is ready, it is time to update dwxgmac_tc_ops to let user configure FPE via tc-mqprio/tc-taprio. Signed-off-by: Furong Xu <0x1207@gmail.com> --- drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c b/drivers/net/= ethernet/stmicro/stmmac/stmmac_tc.c index 75ad2da1a37f..6a79e6a111ed 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c @@ -1290,8 +1290,8 @@ const struct stmmac_tc_ops dwxgmac_tc_ops =3D { .setup_cls_u32 =3D tc_setup_cls_u32, .setup_cbs =3D tc_setup_cbs, .setup_cls =3D tc_setup_cls, - .setup_taprio =3D tc_setup_taprio_without_fpe, + .setup_taprio =3D tc_setup_taprio, .setup_etf =3D tc_setup_etf, .query_caps =3D tc_query_caps, - .setup_mqprio =3D tc_setup_mqprio_unimplemented, + .setup_mqprio =3D tc_setup_dwmac510_mqprio, }; --=20 2.34.1